C9716J

C9716J 100 MHz Clock Generator with SSCG and Power Management for Mobile Application Preliminary Product Features • • • • • • • • • • Supplies: 2 Ref clocks 2 Host (CPU) clocks 1 free running and 5 PCI Clocks 1 48MHz fixed clock 1 48 or 24 MHz fixed clock Separate supply pins for mixed (3.3/2.5V) voltage application. 100 or 66 MHz CPU clock operation -1.5% Spread Spectrum modulation for reducing EMI Rich Power Management Functions. 28-pin SSOP & TSSOP packages for minimum board space. Frequency Table SEL 100/66# 0 1 CPU Clock 66.66 MHz 100.00 MHz PCI Clock 33.33 MHz 33.33 MHz Block Diagram SEL48# Pin Configuration REF2 VDDR XIN XOUT OSC SS# REF1 SEL48# PLL 48-24M 48-24M/TS# VDDC SEL100/66# CS# PD# PS# SS# PLL CPU (1,2) PCI_F VDDP VSS XIN XOUT PCI_F PCI1 PCI2 VSS VDDP PCI3 PCI4 PCI5 VDDF 48M 48-24/TS# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VDDR REF/SEL48# REF1/SS# VDDC CPU1 CPU2 VSS VSS PS# VDD CS# PD# SEL100/66# VSS PCI (1:3) INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035 TEL: 408-263-6300 ext. 275 FAX 408-263-6571 Rev. 1.0 4/28/2000 Page 1 of 12 C9716J 100 MHz Clock Generator with SSCG and Power Management for Mobile Application Preliminary Pin Description PIN No. 2 Pin Name XIN PWR VDD I/O I TYPE XTAL4 Description On-chip reference oscillator input pin. Requires either an external parallel resonant crystal (nominally 14.318 MHz) or externally generated reference signal O-chip reference oscillator output pin. Drives an external parallel resonant crystal (14.318 MHz) when an externally generated reference signal is used. 3.3 volt power supply for core logic. Clock outputs. CPU frequency table specified on page 1. Powers down device when LOW When signal is LOW, stops CPU clocks in low state. Frequency select input pins. See frequency select table on page 1. NO INTERNAL PULLUP RESISTOR IS PROVIDED BY DEVICE 2.5V power for CPU and Host clock outputs. Free running PCI clock 3.3V. Does not stop when PS# is at a logic LOW level PCI output clocks. See frequency table of page 1. When signal is LOW, stops all PCI clocks in low state. 3.3 Volt power supply pins for free running PCI clock output buffer. Fixed 48 MHz clock. Power up selectable 48 or 24 MHz clock. If strapped LOW at powerup causes the devices outputs to be tri-stated until the next power up sequence occurs. At power up this pin determines if the device’s spread spectrum modulation feature is enabled or disabled. After power up this pin becomes a reference clock output. A 0 (logic low) enables SSCG and a 1 (logic high) disables SSCG. At power up this pin determine the frequency of the clock at pin 14. If it is LOW, the clock will be 48 MHz, if HIGH the clock will be 24 MHz. After power up this pin will become a reference clock output. Power for fixed clock output buffer. Ground pins for device. Power for Reference Oscillator output buffer. 3 XOUT VDD O XTAL4 19 23, 24 17 18 16 VDD CPU (1,2) PD# CS# SEL100/66# VDDC - P O I I I PWR C100S INP3U INP3U INP3 25 4 5,6,9, 10,11 20 8 13 14 VDDC PCI_F PCI(1:5) PS# VDDP 48M 48-24M/TS# VDDP VDDP VDDF VDDF P O O I P O I/O PWR P100S P100S INP3U PWR U48 U48BU 26 REF1/SS# VDDR I/O U48BU 27 REF2/SEL48 # VDDR I/O U48BU 12 1, 7, 15, 21, 22 28 VDDF VSS VDDR - P P P PWR PWR PWR Notes 1. INP3U pins have internal pullup resistors that will guarantee to a logic1 (high) level if no connection is made to the device’s pin. INP3 pins do not contain this function and must be electrically connected to VDD or VSS by external circuitry to ensure a valid logic 1 or 0 is sensed. INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035 TEL: 408-263-6300 ext. 275 FAX 408-263-6571 Rev. 1.0 4/28/2000 Page 2 of 12 C9716J 100 MHz Clock Generator with SSCG and Power Management for Mobile Application Preliminary Frequency Selection Table Descriptions All Outputs Tri-State 66 MHz 100 MHz Test Mode 48-24M/TS# at Power UP 0 1 1 0 SEL 66/100 0 0 1 1 Outputs CPU PCI Hi-Z 66.66 MHz 100.00 MHz 7.16 MHz Hi-Z 33.33 MHz 33.33 MHz 2.38 MHz 48M Hi-Z 48 MHz 48 MHz 7.16 MHz 48/24M Hi-Z 24/48 MHz 24/48 MHz 7.16/3.58 MHz Power Management Functions PS# X 1 0 CS# X 0 1 PD# 0 1 X CPU LOW LOW ON 48M LOW ON ON PCI LOW ON LOW PCI_F LOW ON ON VCOs OFF ON ON CS# is an input clock synthesizer. It is used to turn off the CPU clocks for low power operation. CS# is asserted asynchronously by the external clock control logic with the rising edge of free running PCI clock (and hence CPU Clock) and must be internally synchronized to the external PCI_F output. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks must always be stopped in a low state and started in such a manner as to guarantee that the high pulse width is a full pulse. CPU clock on latency need to be 2 or 3 CPU clocks periods in time and CPU clock off latency needs to be 2 or 3 CPU clocks periods in time. INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035 TEL: 408-263-6300 ext. 275 FAX 408-263-6571 Rev. 1.0 4/28/2000 Page 3 of 12 C9716J 100 MHz Clock Generator with SSCG and Power Management for Mobile Application Preliminary Power Management Timing CPU CS# CPU STOP TIMING CPU PCI REF 48M PD# POWER DOWN TIMING PCI PS# PCI STOP TIMING The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is an asynchronous active low input. This signal needs to be synchronized internal to the device prior to powering down the clock synthesizer. PD# is an asynchronous function for powering up the system. Internal clocks are not running after the device is put in power down. When PD# is active low, all clocks need to be driven to a low value and held prior to turning off the VCO’s and the Crystal. The power-up latency needs to be less than 3 mS. The power down latency should be as short as possible but conforming to the sequence requirements shown below. AS# and CS# are considered to be don’t cares during the power down operations. INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035 TEL: 408-263-6300 ext. 275 FAX 408-263-6571 Rev. 1.0 4/28/2000 Page 4 of 12 C9716J 100 MHz Clock Generator with SSCG and Power Management for Mobile Application Preliminary Power Management Timing Signal CS# PD# Signal State 0 (disabled) 1 (enabled) 1 (cold start/normal operation) Latency No. of rising edges of free running PCI CLOCK (PCIF) 1 1 3 mS 0 (power down) 1 NOTES: 1. Clock on/off latency is defined in the number of rising edges of free running PCI CLOCK between the clock disable goes low/high to the first valid clock comes out of the device. Spectrum Spread Clocking Non -Spread Reduction Spread Spectrum Analysis INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035 TEL: 408-263-6300 ext. 275 FAX 408-263-6571 Rev. 1.0 4/28/2000 Page 5 of 12 C9716J 100 MHz Clock Generator with SSCG and Power Management for Mobile Application Preliminary Spectrum Spreading Selection Table Min (MHz) 98.51285 65.6649 Center (MHz) 99.2634 66.166 Max (MHz) 100.01397 66.667 CPU Frequency 100.00 66.66 % OF FREQUENCY SPREADING 1.5% (-1.5% + 0%) 1.5% (1.5% + 0%) MODE Down Spread Down Spread Test and Measurement Condition Out Put Buffer Test Point Specified Test Load Condition CL Clock Output Wave form 3.3 V Clocking Interface PCI ( 1:5) , 48-24M, REF(1,2) tHKP Duty Cycle 3.3 V 2.4 V 1.5 V 0.4 V 0.0 V tprise tpfall 2.5 V 2.0 V 1.25 V 0.4 V 0.0 V tprise tpfall 2.5 V Clocking Interface CPU (1,2) tHKP Duty Cycle INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST. MILPITAS, CA 95035 TEL: 408-263-6300 ext. 275 FAX 408-263-6571 Rev. 1.0 4/28/2000 Page 6 of 12 C9716J 100 MHz Clock Generator with SSCG and Power Management for Mobile Application Preliminary Absolute Maximum Ratings Voltage Relative to VSS: Voltage Relative to VDD: Storage Temperature: Operating Temperature: Maximum Power Supply: -0.3V 0.3V 0ºC to + 125ºC 0ºC to +70ºC 7V This device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. For proper operation, Vin should be constrained to the range: VSS