CC2420SK

SmartRF ® CC2420 CC2420 2.4 GHz IEEE 802.15.4 / ZigBee-ready RF Transceiver Applications • • • • 2.4 GHz IEEE 802.15.4 systems ZigBee systems Home/building automation Industrial Control • • • Wireless sensor networks PC peripherals Consumer Electronics Product Description The CC2420 is a true single-chip 2.4 GHz IEEE 802.15.4 compliant RF transceiver designed for low-power and low-voltage wireless applications. CC2420 includes a digital direct sequence spread spectrum baseband modem providing a spreading gain of 9 dB and an effective data rate of 250 kbps. The CC2420 is a low-cost, highly integrated solution for robust wireless communication in the 2.4 GHz unlicensed ISM band. It complies with worldwide regulations covered by ETSI EN 300 328 and EN 300 440 class 2 (Europe), FCC CFR47 Part 15 (US) and ARIB STD-T66 (Japan). The CC2420 provides extensive hardware support for packet handling, data buffering, burst transmissions, data encryption, data authentication, clear channel assessment, link quality indication and packet timing information. These features reduce the load on the host controller and allow CC2420 to interface low-cost microcontrollers. The configuration interface and transmit / receive FIFOs of CC2420 are accessed via an SPI interface. In a typical application CC2420 will be used together with a microcontroller and a few external passive components. CC2420 is based on Chipcon’s SmartRF®03 technology in 0.18 µm CMOS. Key Features • True single-chip 2.4 GHz IEEE 802.15.4 compliant RF transceiver with baseband modem and MAC support DSSS baseband modem with 2 MChips/s and 250 kbps effective data rate. Suitable for both RFD and FFD operation Low current consumption (RX: 19.7 mA, TX: 17.4 mA) Low supply voltage (2.1 – 3.6 V) with integrated voltage regulator Low supply voltage (1.6 – 2.0 V) with external voltage regulator • • • • • • • • • • • • Programmable output power No external RF switch / filter needed I/Q low-IF receiver I/Q direct upconversion transmitter Very few external components 128(RX) + 128(TX) byte data buffering Digital RSSI / LQI support Hardware MAC encryption (AES-128) Battery monitor QLP-48 package, 7x7 mm Complies with ETSI EN 300 328, EN 300 440 class 2, FCC CFR-47 part 15 and ARIB STD-T66 Powerful and flexible development tools available • • • • • Chipcon AS SmartRF® CC2420 Preliminary Datasheet (rev 1.2), 2004-06-09 Page 1 of 87 SmartRF ® CC2420 Table of contents Abbreviations _____________________________________________________________________ 5 References _______________________________________________________________________ 6 Features _________________________________________________________________________ 7 Absolute Maximum Ratings _________________________________________________________ 8 Operating Conditions ______________________________________________________________ 8 Electrical Specifications ____________________________________________________________ 9 Pin Assignment __________________________________________________________________ 14 Circuit Description _______________________________________________________________ 16 Application Circuit _______________________________________________________________ 18 Input / output matching ___________________________________________________________ 18 Bias resistor ____________________________________________________________________ 18 Crystal ________________________________________________________________________ 18 Voltage regulator ________________________________________________________________ 18 Power supply decoupling and filtering _______________________________________________ 18 IEEE 802.15.4 Modulation Format __________________________________________________ 22 Configuration Overview ___________________________________________________________ 23 Evaluation Software ______________________________________________________________ 24 4-wire Serial Configuration and Data Interface ________________________________________ 25 Register access _________________________________________________________________ 25 Status byte _____________________________________________________________________ 26 Command strobes _______________________________________________________________ 27 RAM access ____________________________________________________________________ 27 FIFO access ____________________________________________________________________ 29 Multiple SPI access ______________________________________________________________ 29 Microcontroller Interface and Pin Description ________________________________________ 30 Configuration interface ___________________________________________________________ 30 Receive mode __________________________________________________________________ 31 RXFIFO overflow _______________________________________________________________ 31 Transmit mode __________________________________________________________________ 33 General control and status pins _____________________________________________________ 33 Demodulator, Symbol Synchroniser and Data Decision _________________________________ 33 Frame Format ___________________________________________________________________ 34 Synchronisation header ___________________________________________________________ 34 Length field ____________________________________________________________________ 35 MAC protocol data unit ___________________________________________________________ 35 Frame check sequence ____________________________________________________________ 36 RF Data Buffering ________________________________________________________________ 37 Buffered transmit mode ___________________________________________________________ 37 Buffered receive mode ___________________________________________________________ 38 Un-buffered, serial mode __________________________________________________________ 38 Address Recognition ______________________________________________________________ 39 Acknowledge Frames _____________________________________________________________ 40 Radio control state machine ________________________________________________________ 42 MAC Security Operations (Encryption and Authentication) _____________________________ 44 Chipcon AS SmartRF® CC2420 Preliminary Datasheet (rev 1.2), 2004-06-09 Page 2 of 87 SmartRF ® CC2420 Keys __________________________________________________________________________ 44 Nonce / counter _________________________________________________________________ 44 Stand-alone encryption ___________________________________________________________ 45 In-line security operations _________________________________________________________ 45 CTR mode encryption / decryption __________________________________________________ 46 CBC-MAC_____________________________________________________________________ 46 CCM _________________________________________________________________________ 46 Timing ________________________________________________________________________ 47 Linear IF and AGC Settings________________________________________________________ 47 RSSI / Energy Detection ___________________________________________________________ 47 Link Quality Indication ___________________________________________________________ 48 Clear Channel Assessment _________________________________________________________ 49 Frequency and Channel Programming _______________________________________________ 49 VCO and PLL Self-Calibration _____________________________________________________ 50 VCO _________________________________________________________________________ 50 PLL self-calibration ______________________________________________________________ 50 Output Power Programming _______________________________________________________ 50 Voltage Regulator ________________________________________________________________ 50 Battery Monitor __________________________________________________________________ 51 Crystal Oscillator ________________________________________________________________ 52 Input / Output Matching __________________________________________________________ 53 Transmitter Test Modes ___________________________________________________________ 54 Unmodulated carrier _____________________________________________________________ 54 Modulated spectrum _____________________________________________________________ 55 System Considerations and Guidelines _______________________________________________ 56 Frequency hopping and multi-channel systems_________________________________________ 56 Data burst transmissions __________________________________________________________ 56 Crystal accuracy and drift _________________________________________________________ 56 Communication robustness ________________________________________________________ 56 Communication security __________________________________________________________ 56 Low cost systems________________________________________________________________ 57 Battery operated systems __________________________________________________________ 57 BER / PER measurements _________________________________________________________ 57 PCB Layout Recommendations _____________________________________________________ 58 Antenna Considerations ___________________________________________________________ 58 Configuration Registers ___________________________________________________________ 60 Test Output Signals _______________________________________________________________ 80 Package Description (QLP 48) ______________________________________________________ 82 Recommended layout for package (QLP 48) __________________________________________ 83 Package thermal properties ________________________________________________________ 83 Soldering information ____________________________________________________________ 83 Plastic tube specification __________________________________________________________ 84 Carrier tape and reel specification ___________________________________________________ 84 Ordering Information _____________________________________________________________ 84 General Information ______________________________________________________________ 85 Document History _______________________________________________________________ 85 Product Status Definitions _________________________________________________________ 86 Chipcon AS SmartRF® CC2420 Preliminary Datasheet (rev 1.2), 2004-06-09 Page 3 of 87 SmartRF ® CC2420 Disclaimer _____________________________________________________________________ 86 Trademarks ____________________________________________________________________ 86 Life Support Policy ______________________________________________________________ 86 Address Information ______________________________________________________________ 87 Chipcon AS SmartRF® CC2420 Preliminary Datasheet (rev 1.2), 2004-06-09 Page 4 of 87 SmartRF ® CC2420 Abbreviations ADC AES AGC ARIB BER CBC-MAC CCA CCM CFR CSMA-CA CTR CW DAC DSSS ESD ESR EVM FCC FCF FIFO FFCTRL HSSD IEEE IF ISM ITU-T I/O I/Q kbps LNA LO LQI LSB MAC MFR MHR MIC MPDU MSDU NA NC O-QPSK PA PCB PER PHY PHR PLL PSDU QLP RAM RBW RF RSSI Analogue to Digital Converter Advanced Encryption Standard Automatic Gain Control Association of Radio Industries and Businesses Bit Error Rate Cipher Block Chaining Message Authentication Code Clear Cannel Assessment Counter mode + CBC-MAC Code of Federal Regulations Carrier Sense Multiple Access with Collision Avoidance Counter mode (encryption) Continuous Wave Digital to Analogue Converter Direct Sequence Spread Spectrum Electro Static Discharge Equivalent Series Resistance Error Vector Magnitude Federal Communications Commission Frame Control Field First In First Out FIFO and Frame Control High Speed Serial Debug Institute of Electrical and Electronics Engineers Intermediate Frequency Industrial, Scientific and Medical International Telecommunication Union – Telecommunication Standardization Sector Input / Output In-phase / Quadrature-phase kilo bits per second Low-Noise Amplifier Local Oscillator Link Quality Indication Least Significant Bit / Byte Medium Access Control MAC Footer MAC Header Message Integrity Code MAC Protocol Data Unit MAC Service Data Unit Not Available Not Connected Offset - Quadrature Phase Shift Keying Power Amplifier Printed Circuit Board Packet Error Rate Physical Layer PHY Header Phase Locked Loop PHY Service Data Unit Quad Leadless Package Random Access Memory Resolution BandWidth Radio Frequency Receive Signal Strength Indicator Chipcon AS SmartRF® CC2420 Preliminary Datasheet (rev 1.2), 2004-06-09 Page 5 of 87 SmartRF ® CC2420 RX SHR SPI TBD T/R TX VCO VGA Receive Synchronisation Header Serial Peripheral Interface To Be Decided / To Be Defined Transmit / Receive Transmit Voltage Controlled Oscillator Variable Gain Amplifier References [1] IEEE std. 802.15.4 - 2003: Wireless Medium Access Control (MAC) and Physical Layer (PHY) specifications for Low Rate Wireless Personal Area Networks (LR-WPANs) http://standards.ieee.org/getieee802/download/802.15.4-2003.pdf [2] NIST FIPS Pub 197: Advanced Encryption Standard (AES), Federal Information Processing Standards Publication 197, US Department of Commerce/N.I.S.T., November 26, 2001. Available from the NIST website. http://csrc.nist.gov/publications/fips/fips197/fips-197.pdf [3] R. Housley, D. Whiting, N. Ferguson, Counter with CBC-MAC (CCM), submitted to NIST, June 3, 2002. Available from the NIST website. http://csrc.nist.gov/CryptoToolkit/modes/proposedmodes/ProposedModesPa ge.html Chipcon AS SmartRF® CC2420 Preliminary Datasheet (rev 1.2), 2004-06-09 Page 6 of 87 SmartRF ® CC2420 Features • 2400 – 2483.5 MHz RF Transceiver • Direct Sequence Spread Spectrum (DSSS) transceiver • 250 kbps data rate, 2 MChip/s chip rate • O-QPSK with half sine pulse shaping modulation • Very low current consumption (RX: 19.7 mA, TX: 17.4 mA) • High sensitivity (-94 dBm) • High adjacent channel rejection (39 dB) • High alternate channel rejection (55 dB) • On-chip VCO, LNA and PA • Low supply voltage (2.1 – 3.6 V) with on-chip voltage regulator • Programmable output power • I/Q low-IF soft decision receiver • I/Q direct up-conversion transmitter Separate transmit and receive FIFOs • 128 byte transmit data FIFO • 128 byte receive data FIFO Very few external components • Only reference crystal and a minimised number of passives • No external filters needed Easy configuration interface • 4-wire SPI interface • Serial clock up to 10 MHz • • • 802.15.4 MAC hardware support: • Automatic preamble generator • Synchronisation word insertion/detection • CRC-16 computation and checking over the MAC payload • Clear Channel Assessment • Energy detection / digital RSSI • Link Quality Indication • Full automatic MAC security (CTR, CBC-MAC, CCM) 802.15.4 MAC hardware security: • Automated security operations within the receive and transmit FIFOs. • CTR mode encryption / decryption • CBC-MAC authentication • CCM encryption / decryption and authentication • Stand-alone AES encryption Development tools available • Fully equipped development kit • Demonstration board reference design with microcontroller code • Easy-to-use software for generating the CC2420 configuration data Small size QLP-48 package, 7 x 7 mm Complies with EN 300 328, EN 300 440 class 2, FCC CFR47 part 15 and ARIB STD-T66 • • • • • Chipcon AS SmartRF® CC2420 Preliminary Datasheet (rev 1.2), 2004-06-09 Page 7 of 87 SmartRF ® CC2420 Absolute Maximum Ratings Parameter Supply voltage for on-chip voltage regulator, VREG_IN pin 43. Supply voltage (VDDIO) for digital I/Os, DVDD3.3, pin 25. Supply voltage (VDD) on AVDD_VCO, DVDD1.8, etc (pin no 1, 2, 3, 4, 10, 14, 15, 17, 18, 20, 26, 35, 37, 44 and 48) Voltage on any digital I/O pin, (pin no. 21, 27-34 and 41) Voltage on any other pin, (pin no. 6, 7, 8, 11, 12, 13, 16, 36, 38, 39, 40, 45, 46 and 47) Input RF level Storage temperature range Reflow solder temperature − 50 Min. -0.3 -0.3 − 0.3 Max. 3.6 3.6 2.0 Units V V V Condition -0.3 -0.3 VDDIO+0.3, max 3.6 VDD+0.3, max 2.0 10 150 260 V V dBm °C °C T = 10 s The absolute maximum ratings given above should under no circumstances be violated. Stress exceeding one or more of the limiting values may cause permanent damage to the device. Caution! ESD sensitive device. Precaution should be used when handling the device in order to prevent permanent damage. Operating Conditions Parameter Supply voltage for on-chip voltage regulator, VREG_IN pin 43. Supply voltage (VDDIO) for digital I/Os, DVDD3.3, pin 25 . Supply voltage (VDD) on AVDD_VCO, DVDD1.8, etc (pin no 1, 2, 3, 4, 10, 14, 15, 17, 18, 20, 26, 35, 37, 44 and 48) Operating ambient temperature range Min. 2.1 1.6 Typ. Max. 3.6 3.6 Units V V The digital I/O voltage (DVDD3.3 pin) must match the external interfacing circuit (e.g. microcontroller). The typical application uses regulated 1.8 V supply generated by the on-chip voltage regulator. Condition 1.6 1.8 2.0 V − 40 85 °C Chipcon AS SmartRF® CC2420 Preliminary Datasheet (rev 1.2), 2004-06-09 Page 8 of 87 SmartRF ® CC2420 Electrical Specifications Measured on CC2420 Evaluation Module, Tc = 27 °C, DVDD3.3 and VREG_IN = 3.3 V, internal voltage regulator used if nothing else stated. Parameter Overall RF Frequency Range 2400 2483.5 MHz Programmable in 1 MHz steps, 5 MHz steps for compliance with [1] Min. Typ. Max. Unit Condition / Note Transmit Section Transmit bit rate 250 250 kbps As defined by [1] Transmit chip rate 2000 2000 kChips/s As defined by [1] Nominal output power -3 0 dBm Delivered to a single ended 50 Ω load through a balun. [1] requires minimum –3 dBm Programmable output power range 24 dB The output power is programmable in 8 steps from approximately –24 to 0 dBm. Harmonics 2 harmonic 3 harmonic rd nd -37 -51 dBm dBm At max output power delivered to a single ended 50 Ω load through a balun. See page 53. Spurious emission 30 - 1000 MHz 1– 12.75 GHz 1.8 – 1.9 GHz 5.15 – 5.3 GHz Error Vector Magnitude (EVM) -36 -30 -47 -47 20 dBm dBm dBm dBm % Maximum output power. Complies with EN 300 328, EN 300 440, CFR47 Part 15 and ARIB STD-T-66 Measured as defined by [1] [1] requires max. 35 % Optimum load impedance 115 + j180 Ω Differential impedance as seen from the RF-port (RF_P and RF_N) towards the antenna. For matching details see the Input / Output Matching section on page 53. Receive Section Receiver Sensitivity -90 -94 dBm PER = 1%, as specified by [1] Measured in 50 Ω single endedly through a balun. [1] requires –85 dBm Chipcon AS SmartRF® CC2420 Preliminary Datasheet (rev 1.2), 2004-06-09 Page 9 of 87 SmartRF ® CC2420 Parameter Saturation (maximum input level) Min. 0 Typ. 10 Max. Unit dBm Condition / Note PER = 1%, as specified by [1] Measured in 50 Ω single endedly through a balun. [1] requires –20 dBm Adjacent channel rejection + 5 MHz channel spacing 46 dB Wanted signal @ -82 dBm, adjacent modulated channel at +5 MHz, PER = 1 %, as specified by [1]. [1] requires 0 dB Adjacent channel rejection - 5 MHz channel spacing 39 dB Wanted signal @ -82 dBm, adjacent modulated channel at -5 MHz, PER = 1 %, as specified by [1]. [1] requires 0 dB Alternate channel rejection + 10 MHz channel spacing 58 dB Wanted signal @ -82 dBm, adjacent modulated channel at +10 MHz, PER = 1 %, as specified by [1] [1] requires 30 dB Alternate channel rejection - 10 MHz channel spacing 55 dB Wanted signal @ -82 dBm, adjacent modulated channel at -10 MHz, PER = 1 %, as specified by [1] [1] requires 30 dB Channel rejection ≥ + 15 MHz ≤ - 15 MHz 39 dB Wanted signal @ -82 dBm. Undesired signal is a 802.15.4 modulated channel, stepped through all channels from 2405 to 2480 MHz. Signal level for PER = 1%. Blocking / Desensitisation +/- 5 MHz from channel centre +/- 10 MHz from channel centre +/- 20 MHz from channel centre +/- 50 MHz from channel centre -24 -24 -24 -23 -50 -45 -40 -30 dBm dBm dBm dBm Wanted signal 3 dB above the sensitivity level, CW jammer, PER = 1%. Maximum values according to EN 300 440 class 2. Spurious emission 30 – 1000 MHz 1 – 12.75 GHz −57 −47 dBm dBm Complies with EN 300 328, EN 300 440 class 2, CFR47, Part 15 and ARIB STD-T-66 Difference between centre frequency of the received RF signal and local oscillator frequency [1] requires 200 kHz Symbol rate error tolerance 120 ppm Difference between incoming symbol rate and the internally generated symbol rate [1] requires 80 ppm RSSI / Carrier Sense Frequency error tolerance -300 300 kHz Carrier sense level − 77 dBm Programmable in RSSI.CCA_THR Chipcon AS SmartRF® CC2420 Preliminary Datasheet (rev 1.2), 2004-06-09 Page 10 of 87 SmartRF ® CC2420 Parameter RSSI dynamic range Min. Typ. 100 Max. Unit dB Condition / Note The range is approximately from –100 dBm to 0 dBm See page 47 for details RSSI accuracy ±6 dB RSSI linearity ±3 dB RSSI average time IF Section 128 µs 8 symbol periods, as specified by [1] Intermediate frequency (IF) 2 MHz Frequency Synthesizer Section Crystal oscillator frequency 16 MHz See page 52 for details. Crystal frequency accuracy requirement - 40 40 ppm Including aging and temperature dependency, as specified by [1] Crystal operation Parallel C381 and C391 are loading capacitors, see page 52 Crystal load capacitance 12 16 20 pF 16 pF recommended Crystal ESR 60 Ω Crystal oscillator start-up time 0.86 ms 16 pF load Phase noise −109 −117 −117 −117 dBc/Hz dBc/Hz dBc/Hz dBc/Hz Unmodulated carrier At ±1 MHz offset from carrier At ±2 MHz offset from carrier At ±3 MHz offset from carrier At ±5 MHz offset from carrier PLL loop bandwidth PLL lock time 50 192 kHz µs The startup time from the crystal oscillator is running and RX / TX turnaround time Digital Inputs/Outputs Signal levels are referred to the voltage level at pin DVDD3.3 0 0.3* DVDD V Logic "0" input voltage Logic "1" input voltage 0.7* DVDD DVDD V Chipcon AS SmartRF® CC2420 Preliminary Datasheet (rev 1.2), 2004-06-09 Page 11 of 87 SmartRF ® CC2420 Parameter Logic "0" output voltage Min. 0 Typ. Max. 0.4 Unit V Condition / Note Output current −8 mA, 3.3 V supply voltage Output current 8 mA, 3.3 V supply voltage Input signal equals GND Logic "1" output voltage 2.5 VDD V Logic "0" input current NA −1 µA Logic "1" input current NA 1 µA Input signal equals VDD FIFO setup time 20 ns TX un-buffered mode, minimum time FIFO must be ready before the positive edge of FIFOP TX un-buffered mode, minimum time FIFO must be held after the positive edge of FIFOP FIFO hold time 10 ns Serial interface pins (SCLK, SI, SO and CSn) timing specification See Table 4 on page 26 Voltage Regulator Note that the internal voltage regulator can only supply CC2420 and no external circuitry. 2.1 3.0 3.6 V On the VREG_IN pin Input Voltage Output Voltage 1.7 1.8 1.9 V On the VREG_OUT pin Quiescent current 13 20 29 µA No current drawn from the VREG_OUT pin. Min and max numbers include 2.1 through 3.6 V input voltage Startup time 0.3 0.6 ms Battery Monitor Current consumption 6 30 90 µA When enabled Startup time 100 µs Voltage regulator already enabled Settling time 2 µs New toggle voltage programmed Step size 50 mV Hysteresis 10 mV Absolute accuracy -80 80 mV May be software calibrated for known reference voltage Chipcon AS SmartRF® CC2420 Preliminary Datasheet (rev 1.2), 2004-06-09 Page 12 of 87 SmartRF ® CC2420 Parameter Relative accuracy Min. -50 Typ. Max. 50 Unit mV Condition / Note Power Supply Current consumption in different modes (see Figure 24, page 43) Voltage regulator off (OFF) Power Down mode (PD) Idle mode (IDLE) Current Consumption, receive mode Current Consumption, transmit mode: P = -25 dBm P = -15 dBm P = -10 dBm P = −5 dBm P = 0 dBm 8.5 9.9 11 14 17.4 mA mA mA mA mA The output power is delivered differentially to a 50 Ω singled ended load through a balun, see also page 53. 1 20 426 19.7 µA µA µA mA Current drawn from VREG_IN, through voltage regulator Voltage regulator off Voltage regulator on Including crystal oscillator and voltage regulator Chipcon AS SmartRF® CC2420 Preliminary Datasheet (rev 1.2), 2004-06-09 Page 13 of 87 SmartRF ® CC2420 Pin Assignment AVDD_XOSC16 37 36 35 34 33 XOSC16_Q1 39 AVDD_CHP R_BIAS VREG_IN 48 47 46 45 44 43 42 41 40 VCO_GUARD AVDD_VCO AVDD_PRE AVDD_RF1 GND RF_P TXRX_SW ITCH RF_N GND AVDD_SW NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 NC 24 14 AVDD_RF2 18 20 21 22 23 15 AVDD_IF2 16 17 19 38 XOSC16_Q2 VREG_OUT VREG_EN AVDD_IF1 ATEST1 ATEST2 NC NC DVDD_RAM SO SI SCLK CSn FIFO FIFOP CCA SFD DVDD1.8 DVDD3.3 CC2420 QLP48 7x7 32 31 30 29 28 27 26 25 DVDD_ADC DGND_GUARD DGND DSUB_PADS DSUB_CORE AVDD_ADC DGUARD RESETn Figure 1. CC2420 Pinout – Top View NC AGND Exposed die attach pad Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 Pin Name AGND VCO_GUARD AVDD_VCO AVDD_PRE AVDD_RF1 GND RF_P TXRX_SWITCH Pin type Ground (analog) Power (analog) Power (analog) Power (analog) Power (analog) Ground (analog) RF I/O Power (analog) RF I/O Ground (analog) Power (analog) - Pin Description Exposed die attach pad. Must be connected to solid ground plane Connection of guard ring for VCO (to AVDD) shielding 1.8 V Power supply for VCO 1.8 V Power supply for Prescaler 1.8 V Power supply for RF front-end Grounded pin for RF shielding Positive RF input/output signal to LNA/from PA in receive/transmit mode Common supply connection for integrated RF front-end. Must be connected to RF_P and RF_N externally through a DC path Negative RF input/output signal to LNA/from PA in receive/transmit mode Grounded pin for RF shielding 1.8 V Power supply for LNA / PA switch Not Connect Not Connect Not Connect RF_N GND AVDD_SW NC NC NC Chipcon AS SmartRF® CC2420 Preliminary Datasheet (rev 1.2), 2004-06-09 Page 14 of 87 SmartRF ® CC2420 Pin 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 NOTES: The exposed die attach pad must be connected to a solid ground plane as this is the main ground connection for the chip. Note that digital inputs SCLK, SI and CSn are high-impedance inputs (no internal pull-up) and should have external pull-ups if not driven. SO is high-impedance when CSn is high. An external pull-up should be used at SO to prevent floating input at microcontroller. Pin Name AVDD_RF2 AVDD_IF2 NC AVDD_ADC DVDD_ADC DGND_GUARD DGUARD RESETn DGND DSUB_PADS DSUB_CORE DVDD3.3 DVDD1.8 SFD CCA FIFOP FIFO CSn SCLK SI SO DVDD_RAM NC AVDD_XOSC16 XOSC16_Q2 XOSC16_Q1 NC VREG_EN VREG_OUT VREG_IN AVDD_IF1 R_BIAS ATEST2 ATEST1 AVDD_CHP Pin type Power (analog) Power (analog) Power (analog) Power (digital) Ground (digital) Power (digital) Digital Input Ground (digital) Ground (digital) Ground (digital) Power (digital) Power (digital) Digital output Digital output Digital output Digital I/O Digital input Digital input Digital input Digital output (tristate) Power (digital) Power (analog) Analog I/O Analog I/O Digital input Power output Power (analog) Power (analog) Analog output Analog I/O Analog I/O Power (analog) Pin Description 1.8 V Power supply for receive and transmit mixers 1.8 V Power supply for transmit / receive IF chain Not Connect 1.8 V Power supply for analog parts of ADCs and DACs 1.8 V Power supply for digital parts of receive ADCs Ground connection for digital noise isolation 1.8 V Power supply connection for digital noise isolation Asynchronous, active low digital reset Ground connection for digital core and pads Substrate connection for digital pads Substrate connection for digital modules 3.3 V Power supply for digital I/Os 1.8 V Power supply for digital core SFD (Start of Frame Delimiter) / digital mux output CCA (Clear Channel Assessment) / digital mux output High when number of bytes in FIFO exceeds threshold / serial RF clock output in test mode High when data in FIFO / serial RF data input / output in test mode SPI Chip select, active low SPI Clock input, up to 10 MHz SPI Slave Input. Sampled on the positive edge of SCLK SPI Slave Output. Updated on the negative edge of SCLK. Tristate when CSn high. 1.8 V Power supply for digital RAM Not Connect 1.8 V crystal oscillator power supply 16 MHz Crystal oscillator pin 2 16 MHz Crystal oscillator pin 1 or external clock input Not Connect Voltage regulator enable, active high, held at VREG_IN voltage level when active Voltage regulator 1.8 V power supply output Voltage regulator 2.1 to 3.6 V power supply input 1.8 V Power supply for transmit / receive IF chain External precision resistor, 43 kΩ, ± 1 % Analog test I/O for prototype and production testing Analog test I/O for prototype and production testing 1.8 V Power supply for phase detector and charge pump Chipcon AS SmartRF® CC2420 Preliminary Datasheet (rev 1.2), 2004-06-09 Page 15 of 87 SmartRF ® CC2420 Circuit Description AUTOMATIC GAIN CONTROL ADC LNA DIGITAL DEMODULATOR - Digital RSSI - Gain Control - Image Suppression - Channel Filtering - Demodulation - Frame synchronization Serial voltage regulator ADC TX/RX CONTROL CC2420 Pow er Control 0 90 FREQ SYNTH TX POWER CONTROL DIGITAL INTERFACE WITH FIFO BUFFERS, CRC AND ENCRYPTION DAC PA DIGITAL MODULATOR - Data spreading - Modulation Σ DAC Digital and Analog test interface XOSC On-chip BIAS R 16 MHz Figure 2. CC2420 simplified block diagram A simplified block diagram of CC2420 is shown in Figure 2. The CC2420 transmitter is based on direct up-conversion. The data is buffered in a 128 byte transmit FIFO (separate from the receive FIFO). The preamble and start of frame delimiter are generated by hardware. Each symbol (4 bits) is spread using the IEEE 802.15.4 spreading sequence to 32 chips and output to the digital-to-analog converters (DACs). An analog lowpass filter passes the signal to the quadrature (I and Q) upconversion mixers. The RF signal is amplified in the power amplifier (PA) and fed to the antenna. The internal T/R switch circuitry makes the antenna interface and matching easy. The RF connection is differential. A balun may be used for single-ended antennas. The biasing of the PA and LNA is done by connecting TXRX_SWITCH to RF_P and RF_N through an external DC path. The frequency synthesizer includes a completely on-chip LC VCO and a 90 Page 16 of 87 CC2420 features a low-IF receiver. The received RF signal is amplified by the lownoise amplifier (LNA) and down-converted in quadrature (I and Q) to the intermediate frequency (IF). At IF (2 MHz), the complex I/Q signal is filtered and amplified, and then digitized by the ADCs. Automatic gain control, final channel filtering, despreading, symbol correlation and byte synchronisation are performed digitally. When the SFD pin goes high, this indicates that a start of frame delimiter has been detected. CC2420 buffers the received data in a 128 byte receive FIFO. The user may read the FIFO through an SPI interface. CRC is verified in hardware. RSSI and correlation values are appended to the frame. CCA is available on a pin in receive mode. Serial (unbuffered) data modes are also available for test purposes. Chipcon AS SmartRF® CC2420 Preliminary Datasheet (rev 1.2), 2004-06-09 Serial microcontroller interface SmartRF ® CONTROL LOGIC SmartRF ® CC2420 degrees phase splitter for generating the I and Q LO signals to the down-conversion mixers in receive mode and up-conversion mixers in transmit mode. The VCO operates in the frequency range 4800 – 4966 MHz, and the frequency is divided by two when split in I and Q. A crystal must be connected to XOSC16_Q1 and XOSC16_Q2 and provides the reference frequency for the synthesizer. A digital lock signal is available from the PLL. The digital baseband includes support for frame handling, address recognition, data buffering and MAC security. The 4-wire SPI serial interface is used for configuration and data buffering. An on-chip voltage regulator delivers the regulated 1.8 V supply voltage. The voltage regulator may be enabled / disabled through a separate pin. A battery monitor may optionally be used to monitor the unregulated power supply voltage. The battery monitor is configurable through the SPI interface. Chipcon AS SmartRF® CC2420 Preliminary Datasheet (rev 1.2), 2004-06-09 Page 17 of 87 SmartRF ® CC2420 Application Circuit Few external components are required for the operation of CC2420. A typical application circuit is shown in Figure 3. The external components are described in Table 1 and typical values are given in Table 2. hence bias is provided without degradation in antenna performance. A 27 nH series inductor may be connected to the TXRX_SWITCH pin to improve the transmitted EVM, but is not necessary to comply with the requirements in [1]. Input / output matching The RF input/output is high impedance and differential. The optimum differential load for the RF port is 115+j180 Ω. When using an unbalanced antenna such as a monopole, a balun should be used in order to optimise performance. The balun can be implemented using low-cost discrete inductors and capacitors. The balun consists of C61, C62, C71, C81, L61, L62 and L81, and will match the RF input/output to 50 Ω, see Figure 3. L61 and L62 also provide DC biasing of the LNA/PA input/output. An internal T/R switch circuit is used to switch between the LNA and the PA. See Input/output matching section on page 53 for more details. If a balanced antenna such as a folded dipole is used, the balun can be omitted. If the antenna also provides a DC path from TXRX_SWITCH pin to the RF pins, inductors are not needed for DC bias. Figure 4 shows a suggested application circuit using a differential antenna. The antenna type is a standard folded dipole. The dipole has a virtual ground point; Bias resistor The bias resistor R451 is used to set an accurate bias current. Crystal An external crystal with two loading capacitors (C381 and C391) is used for the crystal oscillator. See page 52 for details. Voltage regulator The on chip voltage regulator supplies all 1.8 V power supply inputs. C42 is required for stability of the regulator. A series resistor may be used to comply with the ESR requirement. Power supply decoupling and filtering Proper power supply decoupling must be used for optimum performance. The placement and size of the decoupling capacitors and the power supply filtering are very important to achieve the best performance in an application. Chipcon provides a compact reference design that should be followed very closely. Chipcon AS SmartRF® CC2420 Preliminary Datasheet (rev 1.2), 2004-06-09 Page 18 of 87 SmartRF ® CC2420 Ref C42 C61 C62 C71 C81 C381 C391 L61 L62 L81 R451 XTAL Description Voltage regulator load capacitance Discrete balun and match, see page 53 DC block to antenna and match Front-end bias decoupling and match, see page 53 Discrete balun and match, see page 53 16MHz crystal load capacitor, see page 52 16MHz crystal load capacitor, see page 52 DC bias and match, see page 53 DC bias and match, see page 53 Discrete balun and match, see page 53 Precision resistor for current reference generator 16MHz crystal, see page 52 Table 1. Overview of external components 3.3 V Power supply C391 R451 C42 XTAL C381 1 VCO_GUARD 2 AVDD_VCO AVDD_XOSC16 37 AVDD_CHP 48 ATEST1 47 ATEST2 46 R_BIAS 45 AVDD_IF1 44 VREG_IN 43 VREG_OUT 42 VREG_EN 41 NC 40 XOSC16_Q1 39 XOSC16_Q2 38 NC 36 DVDD_RAM 35 SO 34 SI 33 Antenna (50 Ohm) C61 L62 3 4 5 AVDD_PRE AVDD_RF1 GND RF_P TXRX_SWITCH RF_N GND CC2420 Transceiver QLP48 RF 7x7 SCLK 32 CSn 31 FIFO 30 FIFOP 29 CCA 28 SFD 27 DVDD1.8 26 C62 C71 L61 6 7 8 L81 C81 9 10 AVDD_SW 11 NC 12 NC DVDD3.3 25 Figure 3. Typical application circuit with discrete balun for single-ended operation Chipcon AS SmartRF® CC2420 Preliminary Datasheet (rev 1.2), 2004-06-09 Page 19 of 87 Digital Inteface DGND_GUARD 19 DSUB_PADS 23 DSUB_CORE 24 AVDD_RF2 14 AVDD_IF2 15 AVDD_ADC 17 DVDD_ADC 18 RESETn 21 DGUARD 20 DGND 22 NC 13 NC 16 SmartRF ® CC2420 3.3 V Power supply C391 R451 C42 XTAL C381 1 VCO_GUARD 2 AVDD_VCO 3 4 5 AVDD_PRE AVDD_RF1 GND RF_P TXRX_SWITCH RF_N GND AVDD_XOSC16 37 AVDD_CHP 48 ATEST1 47 ATEST2 46 R_BIAS 45 AVDD_IF1 44 VREG_IN 43 VREG_OUT 42 VREG_EN 41 NC 40 XOSC16_Q1 39 XOSC16_Q2 38 NC 36 DVDD_RAM 35 SO 34 SI 33 CC2420 Transceiver QLP48 RF 7x7 SCLK 32 CSn 31 FIFO 30 FIFOP 29 CCA 28 SFD 27 DVDD1.8 26 8 9 10 AVDD_SW 11 NC 12 NC DVDD3.3 25 Figure 4. Suggested application circuit with differential antenna (folded dipole) Chipcon AS SmartRF® CC2420 Preliminary Datasheet (rev 1.2), 2004-06-09 Page 20 of 87 Digital Inteface Folded dipole antenna L61 6 7 DGND_GUARD 19 DSUB_PADS 23 DSUB_CORE 24 AVDD_RF2 14 AVDD_IF2 15 AVDD_ADC 17 DVDD_ADC 18 RESETn 21 DGUARD 20 DGND 22 NC 13 NC 16 SmartRF ® CC2420 Item C42 C61 C62 C71 C81 C381 C391 L61 L62 L81 R451 XTAL Single ended output, discrete balun 10 µF, 0.5Ω < ESR < 5Ω 0.5 pF, +/- 0.25pF, NP0, 0402 5.6 pF, +/- 0.25pF, NP0, 0402 5.6 pF, 10%, X5R, 0402 0.5 pF, +/- 0.25pF, NP0, 0402 22 pF, 5%, NP0, 0402 22 pF, 5%, NP0, 0402 7.5 nH, 5%, Monolithic/multilayer, 0402 5.6 nH, 5%, Monolithic/multilayer, 0402 7.5 nH, 5%, Monolithic/multilayer, 0402 43 kΩ, 1%, 0402 16 MHz crystal, 16 pF load (CL), ESR < 60 Ω Differential antenna 10 µF, 0.5Ω < ESR < 5Ω Not used Not used 5.6 pF, 10%, X5R, 0402 Not used 27 pF, 5%, NP0, 0402 27 pF, 5%, NP0, 0402 27 nH, 5%, Monolithic/multilayer, 0402 Not used Not used 43 kΩ, 1%, 0402 16 MHz crystal, 16 pF load (CL), ESR < 60 Ω Table 2. Bill of materials for the application circuits Chipcon AS SmartRF® CC2420 Preliminary Datasheet (rev 1.2), 2004-06-09 Page 21 of 87 SmartRF ® CC2420 IEEE 802.15.4 Modulation Format This section is meant as an introduction to the 2.4 GHz direct sequence spread spectrum (DSSS) RF modulation format defined in IEEE 802.15.4. For a complete description, please refer to [1]. The modulation and spreading functions are illustrated at block level in Figure 5 [1]. Each byte is divided into two symbols, 4 bits each. The least significant symbol is transmitted first. For multi-byte fields, the least significant byte is transmitted first, except for security related fields where the most significant byte it transmitted first. Each symbol is mapped to one out of 16 pseudo-random sequences, 32 chips each. The symbol to chip mapping is shown in Table 3. The chip sequence is then transmitted at 2 MChips/s, with the least significant chip (C0) transmitted first for each symbol. Transmitted bit-stream (LSB first) Bit-toSymbol Symbolto-Chip O-QPSK Modulator Modulated Signal Figure 5. Modulation and spreading functions [1] Symbol 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Chip sequence (C0, C1, C2, … , C31) 11011001110000110101001000101110 11101101100111000011010100100010 00101110110110011100001101010010 00100010111011011001110000110101 01010010001011101101100111000011 00110101001000101110110110011100 11000011010100100010111011011001 10011100001101010010001011101101 10001100100101100000011101111011 10111000110010010110000001110111 01111011100011001001011000000111 01110111101110001100100101100000 00000111011110111000110010010110 01100000011101111011100011001001 10010110000001110111101110001100 11001001011000000111011110111000 Table 3. IEEE 802.15.4 symbol-to-chip mapping [1] The modulation format is Offset – Quadrature Phase Shift Keying (O-QPSK) with half-sine chip shaping. This is equivalent to MSK modulation. Each chip is shaped as a half-sine, transmitted alternately in the I and Q channels with one half chip period offset. This is illustrated for the zero-symbol in Figure 6. Chipcon AS SmartRF® CC2420 Preliminary Datasheet (rev 1.2), 2004-06-09 Page 22 of 87 SmartRF ® CC2420 TC I-phase Q-phase 1 0 1 0 1 0 0 1 0 0 0 1 0 1 1 1 1 1 0 1 1 0 0 1 1 1 0 0 0 0 1 0 2TC Figure 6. I / Q Phases when transmitting a zero-symbol chip sequence, TC = 0.5 µs Configuration Overview CC2420 can be configured to achieve the best performance for different applications. Through the programmable configuration registers the following key parameters can be programmed: • • • Receive / transmit mode RF channel selection RF output power • • • • • Power-down / power-up mode Crystal oscillator power-up / power down Clear Channel Assessment mode Packet handling hardware support Encryption / Authentication modes Chipcon AS SmartRF® CC2420 Preliminary Datasheet (rev 1.2), 2004-06-09 Page 23 of 87 SmartRF ® CC2420 Evaluation Software Chipcon provides users of CC2420 with a software program, SmartRF® Studio (Windows interface) which may be used for radio performance and functionality evaluation. Figure 7 shows the user interface of the CC2420 configuration software. Figure 7. SmartRF Studio user interface Chipcon AS SmartRF® CC2420 Preliminary Datasheet (rev 1.2), 2004-06-09 Page 24 of 87 SmartRF ® CC2420 4-wire Serial Configuration and Data Interface CC2420 is configured via a simple 4-wire SPI-compatible interface (pins SI, SO, SCLK and CSn) where CC2420 is the slave. This interface is also used to read and write buffered data (see page 37). All address and data transfer on the SPI interface is done most significant bit first. The configuration registers can also be read by the microcontroller via the same configuration interface. The R/W bit must be set high to initiate the data read-back. CC2420 then returns the data from the addressed register on the 16 clock cycles following the register address. The SO pin is used as the data output and must be configured as an input by the microcontroller. The timing for the programming is also shown in Figure 8 with reference to Table 4. The clocking of the data on SI into the CC2420 is done on the positive edge of SCLK. When the last bit, D0, of the 16 data-bits has been written, the data word is loaded in the internal configuration register. Multiple registers may be written without releasing CSn, as described in the Multiple SPI access section on page 29. The register data will be retained during power down mode, but not when the power-supply is turned off (e.g. by disabling the voltage regulator using the VREG_EN pin). The registers can be programmed in any order. Register access There are 33 16-bit configuration and status registers, 15 command strobe registers, and two 8-bit registers to access the separate transmit and receive FIFOs. Each of the 50 registers is addressed by a 6-bit address. The RAM/Register bit (bit 7) must be cleared for register access. The Read/Write bit (bit 6) selects a read or a write operation and makes up the 8-bit address field together with the 6-bit address. In each register read or write cycle, 24 bits are sent on the SI-line. The CSn pin (Chip Select, active low) must be kept low during this transfer. The bit to be sent first is the RAM/Register bit (set to 0 for register access), followed by the R/W bit (0 for write, 1 for read). The following 6 bits are the address-bits (A5:0). A5 is the most significant bit of the address and is sent first. The 16 data-bits are then transferred (D15:0), also MSB first. See Figure 8 for an illustration. Chipcon AS SmartRF® CC2420 Preliminary Datasheet (rev 1.2), 2004-06-09 Page 25 of 87 SmartRF ® CC2420 tsp tch tcl tsd thd tns SCLK CSn Write to register / RXFIFO: SI SO 0 S7 0 S6 A5 S5 A4 S4 A3 S3 A2 S2 A1 S1 A0 S0 X DW 15 DW 14 DW 13 DW 12 DW11 DW 10 DW9 DW 8 X X DW 7 DW 6 DW 5 DW 4 DW3 DW2 DW1 DW0 X Write to TXFIFO: SI SO 0 S7 0 S6 A5 S5 A4 S4 A3 S3 A2 S2 A1 S1 A0 S0 X DW 7 S7 DW 6 S6 DW5 S5 DW4 S4 DW3 S3 DW2 S2 DW1 S1 DW 0 S0 X DW 7 S7 DW 6 S6 DW 5 S5 DW 4 S4 DW3 S3 DW2 S2 DW1 S1 DW0 S0 X S7 Read from register / RXFIFO: SI SO 0 S7 1 S6 A5 S5 A4 S4 A3 S3 A2 S2 A1 S1 A0 S0 DR15 DR14 DR13 DR12 DR11 DR10 DR9 DR8 X DR7 DR6 DR5 DR4 DR3 DR2 DR1 DR0 DR15 Read and w rite one byte to RAM: (multiple read / writes also possible) SI SO 1 S7 A6 S6 A5 S5 A4 S4 A3 S3 A2 S2 A1 S1 A0 S0 X B1 B0 0 X X X X X X X DW 7 DR7 DW 6 DR6 DW 5 DR5 DW 4 DR4 DW3 DR3 DW2 DR2 DW1 DR1 DW0 DR0 X DR7 Read one byte from RAM: (multiple reads also possible) SI SO 1 S7 A6 S6 A5 S5 A4 S4 A3 S3 A2 S2 A1 S1 A0 S0 X B1 B0 1 X X X X X X DR7 DR6 DR5 DR4 X DR3 DR2 DR1 DR0 DR7 Figure 8. SPI timing diagram Parameter Symbol Min Max Units Conditions SCLK, clock frequency SCLK low pulse duration SCLK high pulse duration CSn setup time CSn hold time SI setup time FSCLK 10 MHz tcl 25 ns The minimum time SCLK must be low. tch 25 ns The minimum time SCLK must be high. tsp 25 ns The minimum time CSn must be low before the first positive edge of SCLK. The minimum time CSn must be held low after the last negative edge of SCLK. The minimum time data on SI must be ready before the positive edge of SCLK. The minimum time data must be held at SI, after the positive edge of SCLK. The maximum rise time for SCLK and CSn The maximum fall time for SCLK and CSn tns tsd 25 25 ns ns SI hold time Rise time Fall time thd trise tfall 25 100 100 ns ns ns Note: The set-up- and hold-times refer to 50% of VDD. Table 4. SPI timing specification Status byte During transfer of the register access byte, command strobes, the first RAM address byte and data transfer to the TXFIFO, the CC2420 status byte is returned on the SO pin. The status byte contains 6 status bits which are described in Table 5. Issuing a SNOP (no operation) command strobe may be used to read the status byte. It may also be read during access to Chipcon AS SmartRF® CC2420 Preliminary Datasheet (rev 1.2), 2004-06-09 Page 26 of 87 SmartRF ® CC2420 chip functions such as register or FIFO access. Bit # 7 6 Name Description Reserved, ignore value Indicates whether the 16 MHz oscillator is running or not 0 : The 16 MHz crystal oscillator is not running 1 : The 16 MHz crystal oscillator is running 5 XOSC16M_STABLE TX_UNDERFLOW Indicates whether an FIFO underflow has occurred during transmission. Must be cleared manually with a SFLUSHTX command strobe. 0 : No underflow has occurred 1 : An underflow has occurred 4 ENC_BUSY Indicates whether the encryption module is busy 0 : Encryption module is idle 1 : Encryption module is busy 3 TX_ACTIVE Indicates whether RF transmission is active 0 : RF Transmission is idle 1 : RF Transmission is active 2 LOCK Indicates whether the frequency synthesizer PLL is in lock or not 0 : The PLL is out of lock 1 : The PLL is in lock 1 RSSI_VALID Indicates whether the RSSI value is valid or not. 0 : The RSSI value is not valid 1 : The RSSI value is valid, always true when reception has been enabled at least 8 symbol periods (128 us) 0 - Reserved, ignore value Table 5. Status byte returned during address transfer and TXFIFO writing R/W bit (set to 0) and the 6 address bits (in the range 0x00 through 0x0E) are written. A command strobe may be followed by any other SPI access without pulling CSn high, and is executed on the last falling edge on SCLK. Command strobes Command strobes may be viewed as single byte instructions to CC2420. By addressing a command strobe register internal sequences will be started. These commands must be used to enable the crystal oscillator, enable receive mode, start decryption etc. All 15 command strobes are listed in Table 11 on page 61. When the crystal oscillator is disabled (Power Down state in Figure 24 on page 43), only the SXOSCON command strobe may be used. All other command strobes will be ignored and will have no effect. The crystal oscillator must stabilise (see the XOSC16M_STABLE status bit in Table 5) before other command strobes are accepted. The command strobe register is accessed in the same way as for a register write operation, but no data is transferred. That is, only the RAM/Register bit (set to 0), RAM access The internal 368 byte RAM may be accessed through the SPI interface. Single or multiple bytes may be read or written sending the address part (2 bytes) only once. The address is then automatically incremented by the CC2420 hardware for each new byte. Data is read and written one byte at a time, unlike register access where 2 bytes are always required after each address byte. The crystal oscillator must be running when accessing the RAM. The RAM/Register bit must be set high to enable RAM access. The 9 bit RAM Page 27 of 87 Chipcon AS SmartRF® CC2420 Preliminary Datasheet (rev 1.2), 2004-06-09 SmartRF ® CC2420 address consists of two parts, B1:0 (MSB) selecting one of the three memory banks and A6:0 (LSB) selecting the address within the selected bank. The RAM is divided into three memory banks: TXFIFO (bank 0), RXFIFO (bank 1) and security (bank 2). The FIFO banks are 128 bytes each, while the security bank is 112 bytes. A6:0 is transmitted directly after the RAM/Register bit as shown in Figure 8. For RAM access, a second byte is also required before the data transfer. This byte contains B1:0 in bits 7 and 6, followed by the R/W bit (0 for read+write, 1 for read). Bits 4 through 0 are don’t care as shown in Figure 8. For RAM write, data to be written must be input on the SI pin directly after the second address byte. RAM data read is CSn: Command strobe: Multiple command strobes: Read or write a whole register (16 bit): Read 8 MSB of a register: Multiple register read or write Read or write n bytes from/to RF FIFO: Read or write n bytes from/to RAM: ADDR ADDR ADDR ADDR ADDR ADDRFIFO ADDR DATA8MSB DATA8MSB DATA8MSB DATAbyte0 DATA8LSB DATAbyte1 ADDR DATAbyte2 DATA8MSB DATAbyte3 ... ... ADDR DATA8MSB DATA8LSB ADDR DATA8LSB ... ... ADDR ADDR output on the SO pin simultaneously, but may be ignored by the user if only writing is of interest. For RAM read, the selected byte(s) are output on the SO pin directly after the second address byte. See Figure 9 for an illustration on how multiple RAM bytes may be read or written in one operation. The RAM memory space is shown in Table 6. As with register data, data stored in RAM will be retained during power down mode, but not when the power-supply is turned off (e.g. by disabling the voltage regulator using the VREG_EN pin). DATAbyte n-3 DATAbyte n-2 DATAbyte n-1 DATAADDR+n ADDRLRAM ADDRHRAM DATAADDR DATAADDR+1 DATAADDR+2 ... Note: FIFO and RAM access must be terminated with setting the CSn pin high. Command strobes and register access may be followed by any other access, since they are completed on the last negative edge on SCLK. They may however also be terminated with setting CSn high, if desirable, e.g. for reading only 8 bits from a configuration register. Figure 9. Configuration registers write and read operations via SPI Chipcon AS SmartRF® CC2420 Preliminary Datasheet (rev 1.2), 2004-06-09 Page 28 of 87 SmartRF ® CC2420 Address 0x16F – 0x16C 0x16B – 0x16A 0x169 – 0x168 0x167 – 0x160 0x15F – 0x150 0x14F – 0x140 0x13F – 0x130 0x12F – 0x120 0x11F – 0x110 0x10F – 0x100 0x0FF – 0x080 0x07F – 0x000 Byte Ordering MSB LSB MSB LSB MSB LSB MSB LSB MSB (Flags) LSB MSB LSB MSB LSB MSB (Flags) LSB MSB LSB MSB LSB MSB LSB Name SHORTADR PANID IEEEADR CBCSTATE TXNONCE / TXCTR KEY1 SABUF RXNONCE / RXCTR KEY0 RXFIFO TXFIFO Description Not used 16-bit Short address, used for address recognition. 16-bit PAN identifier, used for address recognition. 64-bit IEEE address of current node, used for address recognition. Temporary storage for CBC-MAC calculations Transmitter nonce for in-line authentication and transmitter counter for in-line encryption. Encryption key 1 Stand-alone encryption buffer, for plaintext input and ciphertext output Receiver nonce for in-line authentication or receiver counter for in-line decryption. Encryption key 0 128 bytes receive FIFO 128 bytes transmit FIFO Table 6. CC2420 RAM Memory Space FIFO access can only be terminated by setting the CSn pin high once it has been started. The FIFO and FIFOP pins also provide additional information on the data in the receive FIFO, as will be described in the Microcontroller Interface and Pin Description section on page 30. Note that the FIFO and FIFOP pins only apply to the RXFIFO. The TXFIFO has its underflow flag in the status byte. The TXFIFO may be flushed by issuing a SFLUSHTX command strobe. Similarly, a SFLUSHRX command strobe will flush the receive FIFO. FIFO access The TXFIFO and RXFIFO may be accessed through the TXFIFO (0x3E) and RXFIFO (0x3F) registers. The TXFIFO is write only, but may be read back using RAM access as described in the previous section. Data is read and written one byte at a time, as with RAM access. The RXFIFO is both writeable and readable. Writing to the RXFIFO should however only be done for debugging or for using the RXFIFO for security operations (decryption / authentication). The crystal oscillator must be running when accessing the FIFOs. When writing to the TXFIFO, the status byte (see Table 5) is output for each new data byte on SO, as shown in Figure 8. This could be used to detect TXFIFO underflow (see section RF Data Buffering section on page 37) while writing data to the TXFIFO. Multiple FIFO bytes may be accessed in one operation, as with the RAM access. Multiple SPI access Register access, command strobes, FIFO access and RAM access may be issued continuously without setting CSn high. E.g. the user may issue a command strobe, a register write and writing 3 bytes to the TXFIFO in one operation, as illustrated in Figure 10. The only exception Chipcon AS SmartRF® CC2420 Preliminary Datasheet (rev 1.2), 2004-06-09 Page 29 of 87 SmartRF ® CC2420 is that FIFO and RAM access must be terminated by setting CSn high. CSn SI SO ADDR Status Command Strobe ADDR Status DATA8MSB Register Read DATA8LSB ADDRTXFIFO DATAADDR DATAADDR+1 DATAADDR+2 Status Status Status Status TXFIFO Write Figure 10. Multiple SPI Access Example Microcontroller Interface and Pin Description When used in a typical system, CC2420 will interface to a microcontroller. This microcontroller must be able to: • Program CC2420 into different modes, read and write buffered data, and read back status information via the 4-wire SPI-bus configuration interface (SI, SO, SCLK and CSn). • Interface to the receive and transmit FIFOs using the FIFO and FIFOP status pins. • Interface to the CCA pin for clear channel assessment. • Interface to the SFD pin for timing information (particularly for beaconing networks). configuration interface (SI, SO, SCLK and CSn). SO should be connected to an input at the microcontroller. SI, SCLK and CSn must be microcontroller outputs. Preferably the microcontroller should have a hardware SPI interface. The microcontroller pins connected to SI, SO and SCLK can be shared with other SPI-interface devices. SO is a high impedance output as long as CSn is not activated (active low). CSn should have an external pull-up resistor or be set to a high level when the voltage regulator is turned off in order to prevent the input from floating. SI and SCLK should be set to a defined level to prevent the inputs from floating. Configuration interface A CC2420 to microcontroller interface example is shown in Figure 11. The microcontroller uses 4 I/O pins for the SPI Chipcon AS SmartRF® CC2420 Preliminary Datasheet (rev 1.2), 2004-06-09 Page 30 of 87 SmartRF ® CC2420 CC2420 FIFO FIFOP CCA SFD GIO0 Interrupt GIO1 Timer Capture µC CSn SI SO SCLK GIO2 MOSI MISO SCLK Figure 11. Microcontroller interface example Receive mode In receive mode, the SFD pin goes high after the start of frame delimiter (SFD) field has been completely received. If address recognition is disabled or is successful, the SFD pin goes low again only after the last byte of the MPDU has been received. If the received frame fails address recognition, the SFD pin goes low immediately. This is illustrated in Figure 12. The FIFO pin is high when there is one or more data bytes in the RXFIFO. The first byte to be stored in the RXFIFO is the length field of the received frame, i.e. the FIFO pin is set high when the length field is written to the RXFIFO. The FIFO pin then remains high until the RXFIFO is empty. If a previously received frame is completely or partially inside the RXFIFO, the FIFO pin will remain high until the RXFIFO is empty. The FIFOP pin is high when the number of unread bytes in the RXFIFO exceeds the threshold programmed into IOCFG0.FIFOP_THR. When address recognition is enabled the FIFOP pin will not go high until the incoming frame passes address recognition, even if the number of bytes in the RXFIFO exceeds the programmed threshold. The FIFOP pin will also go high when the last byte of a new packet is received, even if the threshold is not exceeded. If so the FIFOP pin will go back to low once one byte has been read out of the RXFIFO. When address recognition is enabled, data should not be read out of the RXFIFO before the address is completely received, since the frame may be automatically flushed by CC2420 if it fails address recognition. This may be handled by using the FIFOP pin, since this pin does not go high until the frame passes address recognition. Figure 13 shows an example of pin activity when reading a packet from the RXFIFO. In this example, the packet size is 8 bytes, IOCFG0.FIFOP_THR = 3 and MODEMCTRL0.AUTOCRC is set. The length will be 8 bytes, RSSI will contain the average RSSI level during receiving of the packet and FCS/corr contain information of FCS check result and the correlation levels. RXFIFO overflow The RXFIFO can only contain a maximum of 128 bytes at a given time. This may be divided between multiple frames, as long as the total number of bytes is 128 or less. If an overflow occurs in the RXFIFO, this is signalled to the microcontroller by setting the FIFO pin low while the FIFOP pin is high. Data already in the RXFIFO will not be affected by the overflow, i.e. frames already received may be read out. A SFLUSHRX command strobe is required after a RXFIFO overflow to enable reception of new data. Note that the Page 31 of 87 Chipcon AS SmartRF® CC2420 Preliminary Datasheet (rev 1.2), 2004-06-09 SmartRF ® CC2420 SFLUSHRX command strobe should be issued twice to ensure that the SFD pin goes back to its idle state. For security enabled frames, the MAC layer must read the source address of the received frame before it can decide which key to use to decrypt or authenticate. This data must therefore not be overwritten even if it has been read out of the RXFIFO by the microcontroller. If the SECCTRL0.RXFIFO_PROTECTION control bit is set, CC2420 also protects the frame header of security enabled frames until decryption has been performed. If no MAC security is used or if it is implemented outside the CC2420, this bit may be cleared to achieve optimal use of the RXFIFO. S FD c te de d te th ng Le te by ive ce re d iti cn go re sd es te dr le Ad omp c on Ud PD eive t M ec as te r Ly b Data received over RF Address recognition OK SFD Pin FIFO Pin FIFOP Pin, if threshold higher than frame length FIFOP Pin, if threshold lower than frame length Preamble SFD Length MAC Protocol Data Unit (MPDU) with correct address Data received over RF Address recognition fails SFD Pin FIFO Pin FIFOP Pin Preamble SFD Length MAC Protocol Data Unit (MPDU) with wrong address Figure 12. Pin activity examples during receive gh f hi r o ns be HR ai m um _T re n P P as IFO FO ng F FI s lo s > a yte b n he w te w by l o st es la go t of FO ou FI ad s re tart s SCLK SFD CSn SI SO FIFOP FIFO ADDRTXFIFO Status Length PSDU0 PSDU1 PSDU2 PSDU3 PSDU4 PSDU5 RSSI FCS/Corr Figure 13. Example of pin activity when reading RXFIFO. Chipcon AS SmartRF® CC2420 Preliminary Datasheet (rev 1.2), 2004-06-09 Page 32 of 87 SmartRF ® CC2420 Transmit mode During transmit, the FIFO and FIFOP pins are still only related to the RXFIFO. The SFD pin is however active during transmission of a data frame, as shown in Figure 14. The SFD pin goes high when the SFD field has been completely transmitted. It goes low again when the complete MPDU (as defined by the length field) has been transmitted or if an underflow is detected. m co N XO e ST trob s d an m D ed itt m ns tra See the RF Data Buffering section on page 37 for more information on TXFIFO underflow. As can be seen from comparing Figure 12 and Figure 14, the SFD pin behaves very similarly during reception and transmission of a data frame. If the SFD pins of the transmitter and the receiver are compared during the transmission of a data frame, a small delay of approximately 2 µs can be seen because of bandwidth limitations in both the transmitter and the receiver. d U itte PD m M ans flow st tr er La yte nd b Xu T or SF Data transmitted over RF SFD Pin Preamble SFD Length MAC Protocol Data Unit (MPDU) 12 symbol periods Automatically generated preamble and SFD Data fetched from TXFIFO CRC generated by CC2420 Figure 14. Pin activity example during transmit received data frames. The SFD pin will go high when a start of frame delimiter has been completely detected / transmitted. The SFD pin should preferably be connected to a timer capture pin on the microcontroller. For debug purposes, the SFD and CCA pins can be used to monitor several status signals as selected by the IOCFG1 register. See Table 12 and Table 13 for available signals. The polarity of FIFO, FIFOP, SFD and CCA can be controlled by the IOCFG0 register (address 0x1C). General control and status pins In receive mode, the FIFOP pin can be used to interrupt the microcontroller when a threshold has been exceeded or a complete frame has been received. This pin should then be connected to a microcontroller interrupt pin. In receive mode, the FIFO pin can be used to detect if there is data at all in the receive FIFO. The SFD pin can be used to extract the timing information of transmitted and Demodulator, Symbol Synchroniser and Data Decision The block diagram for the CC2420 demodulator is shown in Figure 15. Channel filtering and frequency offset compensation is performed digitally. The signal level in the channel is estimated to generate the RSSI level (see the RSSI / Energy Detection section on page 47 for more information). Data filtering is also included for enhanced performance. With the ±40 ppm frequency accuracy requirement from [1], a compliant receiver must be able to compensate for up to 80 ppm or 200 kHz. The CC2420 demodulator tolerates up to 300 kHz offset without significant degradation of the receiver performance. Soft decision is used at the chip level, i.e. the demodulator does not make a decision for each chip, only for each received symbol. De-spreading is performed using over sampled symbol correlators. Symbol synchronisation is achieved by a Page 33 of 87 Chipcon AS SmartRF® CC2420 Preliminary Datasheet (rev 1.2), 2004-06-09 SmartRF ® CC2420 continuous start of frame delimiter (SFD) search. When a SFD is detected, data is written to the RXFIFO and may be read out by the microcontroller at a lower bit rate than the 250 kbps generated by the receiver. The CC2420 demodulator also handles symbol rate errors in excess of 120 ppm without performance degradation. Resynchronisation is performed continuously to adjust for error in the incoming symbol rate. The MDMCTRL1.CORR_THR control bits should be written to 20 to set the threshold for detecting IEEE 802.15.4 start of frame delimiters. I / Q Analog IF signal ADC Digital IF Channel Filtering Frequency Offset Compensation Digital Data Filtering Symbol Correlators and Synchronisation Data Symbol Output RSSI Generator RSSI Average Correlation Value (may be used for LQI) Figure 15. Demodulator Simplified Block Diagram Frame Format CC2420 has hardware support for parts of the IEEE 802.15.4 frame format. This section gives a brief summary to the IEEE 802.15.4 frame format, and describes how CC2420 is set up to comply with this. Figure 16 [1] shows a schematic view of the IEEE 802.15.4 frame format. Similar figures describing specific frame formats (data frames, beacon frames, acknowledgment frames and MAC command frames) are included in [1]. Bytes: MAC Layer 1 0 to 20 2 Frame Data Address Control Field Sequence Information (FCF) Number MAC Header (MHR) n Frame payload MAC Payload 2 Frame Check Sequence (FCS) MAC Footer (MFR) Bytes: PHY Layer Preamble Sequence 1 1 Start of frame Frame Delimiter Length (SFD) Synchronisation Header PHY Header (SHR) (PHR) 4 11 + (0 to 20) + n PHY Protocol Data Unit (PPDU) 5 + (0 to 20) + n MAC Protocol Data Unit (MPDU) PHY Service Data Unit (PSDU) Figure 16. Schematic view of the IEEE 802.15.4 Frame Format [1] Synchronisation header The synchronisation header (SHR) consists of the preamble sequence followed by the start of frame delimiter (SFD). In [1], the preamble sequence is defined to be 4 bytes of 0x00. The SFD is one byte, set to 0xA7. Page 34 of 87 Chipcon AS SmartRF® CC2420 Preliminary Datasheet (rev 1.2), 2004-06-09 SmartRF ® CC2420 In CC2420, the preamble length and SFD is configurable. The default values are compliant with [1]. Changing these values will make the system non-compliant to IEEE 802.15.4. A synchronisation header is always transmitted first in all transmit modes. The preamble sequence length can be set by MDMCTRL0.PREAMBLE_LENGTH, while the SFD is programmed in the SYNCWORD register. SYNCWORD is 2 bytes long, which gives the user some extra flexibility as described below. Figure 17 shows how the CC2420 synchronisation header relates to the IEEE 802.15.4 specification. The programmable preamble length only applies to transmission, it does not affect receive mode. The preamble length should not be set shorter than the default value. Note that 2 of the 8 zero-symbols in the preamble sequence required by [1] are included in the SYNCWORD register so that the CC2420 preamble sequence is only 6 symbols long for compliance with [1]. Two additional zero symbols in SYNCWORD make CC2420 compliant with [1]. In reception, CC2420 synchronises to received zero-symbols and searches for the SFD sequence defined by the SYNCWORD register. The least significant symbols in SYNCWORD set to 0xF will be ignored, while symbols different from 0xF will be required for synchronisation. The default setting of 0xA70F thereby requires one additional zero-symbol for synchronisation. This will reduce the number of false frames detected due to noise. In receive mode CC2420 uses the preamble sequence for symbol synchronisation and frequency offset adjustments. The SFD is used for byte synchronisation, and is not part of the data stored in the receive buffer (RXFIFO). Synchronisation Header Preamble IEEE 802.15.4 0 0 0 0 0 0 0 SW0 0 SW1 7 SW2 SFD A SW3 CC2420 2·(PREAMBLE_LENGTH + 1) zero symbols SW0 = SYNCWORD[3:0] SW1 = SYNCWORD[7:4] if different from 'F', else '0' if different from 'F', else '0' SW2 = SYNCWORD[11:8] if different from 'F', else '0' SW3 = SYNCWORD[15:12] if different from 'F', else '0' Figure 17. Transmitted Synchronisation Header significant bit in the length field is reserved [1], and should be set to zero. Length field The frame length field shown in Figure 16 defines the number of bytes in the MPDU. Note that the length field does not include the length field itself. It does however include the FCS (Frame Check Sequence), even if this is inserted automatically by CC2420 hardware. It also includes the MIC if authentication is used. The length field is 7 bits and has a maximum value of 127. The most CC2420 uses the length field both for transmission and reception, so this field must always be included. In transmit mode, the length field is used for underflow detection, as described in the FIFO access section on page 29. MAC protocol data unit The FCF, data sequence number and address information follows the length field Page 35 of 87 Chipcon AS SmartRF® CC2420 Preliminary Datasheet (rev 1.2), 2004-06-09 SmartRF ® CC2420 as shown in Figure 16. Together with the MAC data payload and Frame Check Sequence, they form the MAC Protocol Data Unit (MPDU). The format of the FCF is shown in Figure 18. Please refer to [1] for details. There is no hardware support for the data sequence number, this field must be inserted and verified by software. CC2420 includes hardware address recognition, as described in the Address Recognition section on page 39. Bits: 0-2 Frame Type 3 Security Enabled 4 Frame Pending 5 Acknowledge request 6 Intra PAN 7-9 Reserved 10-11 Destination addressing mode 12-13 Reserved 14-15 Source addressing mode Figure 18. Format of the Frame Control Field (FCF) [1] Frame check sequence A 2-byte frame check sequence (FCS) follows the last MAC payload byte as shown in Figure 16. The FCS is calculated over the MPDU, i.e. the length field is not part of the FCS. This field is automatically generated and verified by hardware when the MODEMCTRL0.AUTOCRC control bit is set. It is recommended to always have this enabled, except possibly for debug purposes. If cleared, CRC generation and verification must be performed by software. The FCS polynomial is [1]: x16 + x12 + x5 + 1 The CC2420 hardware implementation is shown in Figure 19. Please refer to [1] for further details. In transmit mode the FCS is appended at the correct position defined by the length field. The FCS is not written to the TXFIFO, but stored in a separate 16-bit register. In receive mode the FCS is verified by hardware. The user is normally only interested in the correctness of the FCS, not the FCS sequence itself. The FCS sequence itself is therefore not written to the RXFIFO during receive. Instead, when MODEMCTRL0.AUTOCRC is set the two FCS bytes are replaced by the RSSI value, average correlation value (used for LQI) and CRC OK/not OK. This is illustrated in Figure 20. The first FCS byte is replaced by the 8-bit RSSI value. See the RSSI section on page 47 for details. The 7 least significant bits in the last FCS byte are replaced by the average correlation value of the 8 first symbols of the received PHY header (length field) and PHY Service Data Unit (PSDU). This correlation value may be used as a basis for calculating the LQI. See the Link Quality Indication section on page 48 for details. The most significant bit in the last byte of each frame is set high if the CRC of the received frame is correct and low otherwise. Chipcon AS SmartRF® CC2420 Preliminary Datasheet (rev 1.2), 2004-06-09 Page 36 of 87 SmartRF ® CC2420 Data input (LSB first) r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 Figure 19. CC2420 Frame Check Sequence (FCS) hardware implementation [1] Length byte Data in RXFIFO n MPDU1 MPDU2 MPDU MPDUn-2 RSSI (signed) CRC / Corr Bit number 7 CRC OK 6 5 4 3 2 1 0 Correlation value (unsigned) Figure 20. Data in RXFIFO when MDMCTRL0.AUTOCRC is set RF Data Buffering CC2420 can be configured for different transmit and receive modes, as set in the MDMCTRL1.TX_MODE and MDMCTRL1.RX_MODE control bits. Buffered mode (mode 0) will be used for normal operation of CC2420, while other modes are available for test purposes. section on page 42 for an illustration of how the transmit command strobes affect the state of CC2420. The STXONCCA strobe is ignored if the channel is busy. See the Buffered transmit mode In buffered transmit mode (TX_MODE 0), the 128 byte TXFIFO, located in CC2420 RAM, is used to buffer data before transmission. A preamble sequence (defined in the Frame Format section below) is automatically inserted before the length field during transmission. The length field must always be the first byte written to the transmit buffer for all frames. Writing one or multiple bytes to the TXFIFO is described in the FIFO access section on page 29. Reading data from the TXFIFO is possible with RAM access, but this does not remove the byte from the FIFO. Transmission is enabled by issuing a STXON or STXONCCA command strobe. See the Radio control state machine Chipcon AS SmartRF® CC2420 Preliminary Datasheet (rev 1.2), 2004-06-09 Page 37 of 87 SmartRF ® CC2420 Clear Channel Assessment section on page 49 for details on CCA. The preamble sequence is started 12 symbol periods after the command strobe. After the programmable start of frame delimiter has been transmitted, data is fetched from the TXFIFO. A TXFIFO underflow is issued if too few bytes are written to the TXFIFO. Transmission is then automatically stopped. The underflow is indicated in the TX_UNDERFLOW status bit, which is returned during each address byte and each byte written to the TXFIFO. The underflow bit is only cleared by issuing a SFLUSHTX command strobe. The TXFIFO can only contain one data frame at a given time. After complete transmission of a data frame, the TXFIFO is automatically refilled with the last transmitted frame. Issuing a new STXON or STXONCCA command strobe will then cause CC2420 to retransmit the last frame. Writing to the TXFIFO after a frame has been transmitted will cause the TXFIFO to be automatically flushed before the new byte is written. The only exception is if a TXFIFO underflow has occurred, when a SFLUSHTX command strobe is required. Multiple data frames may be in the RXFIFO simultaneously, as long as the total number of bytes does not exceed 128. See the RXFIFO overflow section on page 31 for details on how a RXFIFO overflow is detected and signaled. Un-buffered, serial mode Un-buffered mode should be used for evaluation / debugging purposes only. Buffered mode is recommended for all applications. In un-buffered mode, the FIFO and FIFOP pins are reconfigured as data and data clock pins. The TXFIFO and RXFIFO buffers are not used in this mode. A synchronous data clock is provided by CC2420 at the FIFOP pin, and the FIFO pin is used as data input/output. The FIFOP clock frequency is 250 kHz when active. This is illustrated in Figure 21. In serial transmit mode a (MDMCTRL1.TX_MODE=1), synchronisation sequence is inserted at the start of each frame by hardware, as in buffered mode. Data is sampled by CC2420 on the positive edge of FIFOP and should be updated by the microcontroller on the negative edge of FIFOP. See Figure 21 for an illustration of the timing in serial transmit mode. The SFD and CCA pins retain their normal operation also in serial mode. CC2420 will remain in serial transmit mode until transmission is turned off manually. In serial receive mode byte (MDMCTRL1.RX_MODE=1) synchronisation is still performed by CC2420. This means that the FIFOP clock pin will remain idle low until a start of frame delimiter has been detected. Buffered receive mode In buffered receive mode (RX_MODE 0), the 128 byte RXFIFO, located in CC2420 RAM, is used to buffer data received by the demodulator. Accessing data in the RXFIFO is described in the FIFO access section on page 29. The FIFO and FIFOP pins are used to assist the microcontroller in supervising the RXFIFO. Please note that the FIFO and FIFOP pins are only related to the RXFIFO, even if CC2420 is in transmit mode. Chipcon AS SmartRF® CC2420 Preliminary Datasheet (rev 1.2), 2004-06-09 Page 38 of 87 SmartRF ® CC2420 Incoming / outgoing RF data Transmit mode: FIFOP FIFO (from uC) b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b8 b9 b10 b11 Preamble SFD 4 us s0 s1 s2 Receive mode: FIFOP FIFO (from CC2420) b0 b1 b2 b3 b4 Figure 21. Un-buffered test mode, pin activity Address Recognition CC2420 includes hardware support for address recognition, as specified in [1]. Hardware address recognition may be enabled / disabled using the MDMCTRL0.ADR_DECODE control bit. Address recognition is based on the following requirements, listed from section 7.5.6.2 in [1]: • • The frame type subfield shall not contain an illegal frame type If the frame type indicates that the frame is a beacon frame, the source PAN identifier shall match macPANId unless macPANId is equal to 0xFFFF, in which case the beacon frame shall be accepted regardless of the source PAN identifier. If a destination PAN identifier is included in the frame, it shall match macPANId or shall be the broadcast PAN identifier (0xFFFF). If a short destination address is included in the frame, it shall match either macShortAddress or the broadcast address (0xFFFF). Otherwise if an extended destination address is included in the frame, it shall match aExtendedAddress. • If only source addressing fields are included in a data or MAC command frame, the frame shall only be accepted if the device is a PAN coordinator and the source PAN identifier matches macPANId. If any of the above requirements are not satisfied and address recognition is enabled, CC2420 will disregard the incoming frame and flush the data from the RXFIFO. Only data from the rejected frame is flushed, data from previously accepted frames may still be in the RXFIFO. The IOCFG0.BCN_ACCEPT control bit must be set when the PAN identifier programmed into CC2420 RAM is equal to 0xFFFF and cleared otherwise. This particularly applies to active and passive scans as defined by [1] which requires all received beacons to be processed by the MAC sublayer. Incoming frames with reserved frame types (FCF frame type subfield is 4, 5, 6 or 7) is however accepted if the RESERVED_FRAME_MODE control bit in MDMCTRL0 is set. In this case, no further address recognition is performed on these frames. This option is included for future expansions of the IEEE 802.15.4 standard. • • Chipcon AS SmartRF® CC2420 Preliminary Datasheet (rev 1.2), 2004-06-09 Page 39 of 87 SmartRF ® CC2420 If a frame is rejected, CC2420 will only start searching for a new frame after the rejected frame has been completely received (as defined by the length field) to avoid detecting false SFDs within the frame. The MDMCTRL0.PAN_COORDINATOR control bit must be correctly set, since parts of the address recognition procedure requires knowledge about whether the current device is a PAN coordinator or not. Acknowledge Frames CC2420 includes hardware support for transmitting acknowledge frames, as specified in [1]. Figure 22 shows the format of the acknowledge frame. If MDMCTRL0.AUTOACK is enabled, an acknowledge frame is transmitted for all incoming frames accepted by the address recognition with the acknowledge request flag set and a valid CRC. AUTOACK therefore does not make sense unless also ADR_DECODE and AUTOCRC are enabled. The sequence number is copied from the incoming frame. AUTOACK may be used for non-beacon systems as long as the frame pending field (see Figure 18) is cleared. The acknowledge frame is then transmitted 12 symbol periods after the last symbol of the incoming frame. This is as specified by [1] for non-beacon networks. Bytes: 1 1 Start of Frame Preamble Frame Delimiter Sequence Length (SFD) Synchronisation Header PHY Header (SHR) (PHR) 4 1 2 Frame Data Control Field Sequence (FCF) Number MAC Header (MHR) 2 Frame Check Sequence (FCS) MAC Footer (MFR) Figure 22. Acknowledge frame format [1] Two command strobes, SACK and SACKPEND are defined to transmit acknowledge frames with the frame pending field cleared or set, respectively. The acknowledge frame is only transmitted if the CRC is valid. For systems using beacons, there is an additional timing requirement that the acknowledge frame transmission should be started on the first backoff-slot boundary (20 symbol periods) at least 12 symbol periods after the last symbol of the incoming frame. This timing must be controlled by the microcontroller by issuing the SACK and SACKPEND command strobe 12 symbol periods before the following backoff-slot boundary, as illustrated in Figure 23. If a SACK or SACKPEND command strobe is issued while receiving an incoming frame, the acknowledge frame is transmitted 12 symbol periods after the last symbol of the incoming frame. This should be used to transmit acknowledge frames in non-beacon networks. This timing is also illustrated in Figure 23. Using SACKPEND will set the pending data flag for automatically transmitted acknowledge frames using AUTOACK. The pending flag will then be set also for future acknowledge frames, until a SACK command strobe is issued. Acknowledge frames may be manually transmitted using normal data transmission if desired. Chipcon AS SmartRF® CC2420 Preliminary Datasheet (rev 1.2), 2004-06-09 Page 40 of 87 SmartRF ® CC2420 r D l da b o PEN un m K bo sy AC ot U S sl D f / of PP ck st ACK La Ba S y Beacon network PPDU 12 symbol periods tack Acknowledge 12 symbol periods