CS18LV20483AFC-55

High Speed Super Low Power SRAM 256K-Word By 8 Bit CS18LV20483 Revision History Rev. No. 1.0 History Initial issue Issue Date Jan.26,2005 Remark 1 Rev. 1.0 Chiplus reserves the right to change product or specification without notice. High Speed Super Low Power SRAM 256K-Word By 8 Bit CS18LV20483 GENERAL DESCRIPTION The CS18LV20483 is a high performance, high speed, and super low power CMOS Static Random Access Memory organized as 262,144 words by 8 bits and operates from a wide range of 2.7 to 3.6V supply voltage. Advanced CMOS technology and circuit techniques provide both high speed and low power features with a typical CMOS standby current of 0.50uA and maximum access time of 55/70ns in 3.0V operation. Easy memory expansion is provided by an active LOW chip enable inputs (/CE1,CE2) and active LOW output enable (/OE) and three-state output drivers. The CS18LV20483 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The CS18LV20483 is available in JEDEC standard 32-pin sTSOP (8x13.4 mm), TSOP (8x20mm), TSOP (II) (400mil) and SOP (450 mil) packages. . FEATURES Low operation voltage : 2.7 ~ 3.6V Ultra low power consumption : 2mA＠1MHz (Max.) operating current 0.50 uA (Typ.) CMOS standby current High speed access time : 55/70ns (Max.) at Vcc = 3.0V. Automatic power down when chip is deselected. Three state outputs and TTL compatible Data retention supply voltage as low as 1.5V. Easy expansion with /CE and /OE options. Product Family Product Family Operating Temp Vcc. Range Speed (ns) Standby (Typ.) Package Type 32 SOP 0~70oC 0.50 uA (Vcc = 3.0V) 32 STSOP 32 TSOP 32 TSOP (II) Dice 32 SOP o 2.7~3.6 55/70 CS18LV20483 -40~85 C 2.7~3.6 55/70 0.8 uA (Vcc= 3.0V) 32 STSOP 32 TSOP 32 TSOP (II) Dice 2 Rev. 1.0 Chiplus reserves the right to change product or specification without notice. High Speed Super Low Power SRAM 256K-Word By 8 Bit CS18LV20483 PIN CONFIGURATIONS FUNCTIONAL BLOCK DIAGRAM 3 Rev. 1.0 Chiplus reserves the right to change product or specification without notice. High Speed Super Low Power SRAM 256K-Word By 8 Bit CS18LV20483 PIN DESCRIPTIONS Type Name A0 – A17 Input Address inputs for selecting one of the 262,144 x 8 bit words in the RAM /CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active when data read from or write to the device. If either chip enable is /CE1, CE2 Input not active, the device is deselected and in a standby power down mode. The DQ pins will be in high impedance state when the device is deselected. The Write enable input is active LOW. It controls read and write /WE Input operations. With the chip selected, when /WE is HIGH and /OE is LOW, output data will be present on the DQ pins, when /WE is LOW, the data present on the DQ pins will be written into the selected memory location. The output enable input is active LOW. If the output enable is active /OE Input while the chip is selected and the write enable is inactive, data will be present on the DQ pins and they will be enabled. The DQ pins will be in the high impedance state when /OE is inactive. DQ0~DQ7 Vcc Gnd NC I/O Power Power These 8 bi-directional ports are used to read data from or write data into the RAM. Power Supply Ground No connection Function TRUTH TABLE MODE Standby X Output Disabled Read Write L L L /CE1 H CE2 X L H H H /WE X X H H L /OE X High Z L H L X High Z DOUT DIN ICC ICC ICC ICCSB, ICCSB1 DQ0~7 Vcc Current 4 Rev. 1.0 Chiplus reserves the right to change product or specification without notice. High Speed Super Low Power SRAM 256K-Word By 8 Bit CS18LV20483 Rating -0.5 to Vcc+0.5 -40 to +125 -60 to +150 1.0 25 ABSOLUTE MAXIMUM RATINGS (1) Symbol VTERM TBIAS TSTG PT IOUT Parameter Terminal Voltage with Respect to GND Temperature Under Bias Storage Temperature Power Dissipation DC Output Current Unit V O O C C W mA 1.Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. OPERATING RANGE Range Commercial Industrial Ambient Temperature 0~70 C -40~85 C o o Vcc 2.7V ~ 3.6V 2.7V ~ 3.6V 1. Overshoot : Vcc +2.0V in case of pulse width ≦20ns. 2. Undershoot : - 2.0V in case of pulse width ≦20ns. 3. Overshoot and undershoot are sampled, not 100% tested. CAPACITANCE (1) (TA = 25oC, f =1.0 MHz) Symbol CIN CDQ Parameter Input Capacitance Input/Output Capacitance Conditions VIN=0V VI/O=0V MAX. 6 8 Unit pF pF 1. This parameter is guaranteed and not tested. 5 Rev. 1.0 Chiplus reserves the right to change product or specification without notice. High Speed Super Low Power SRAM 256K-Word By 8 Bit CS18LV20483 ( TA = 0 to + 70 C , Vcc = 3.0V ) o DC ELECTRICAL CHARACTERISTICS Parameter Name VIL VIH IIL IOL VOL VOH ICC ICCSB ICCSB1 Parameter Guaranteed Input Low Voltage (2) Test Conduction MIN -0.5 TYP(1) MAX 0.8 Unit V Guaranteed Input High Voltage (2) 2.0 Vcc+0.2 V Input Leakage Current VCC=MAX, VIN=0 to VCC Output Leakage Current Output Low Voltage VCC=MAX, /CE=VIN, or /OE=VIN , VIO=0V to VCC VCC=MAX, IOL = 2mA VCC=MIN, IOH = -1mA /CE=VIL, IDQ=0mA, /CE=VIH, IDQ=0mA, /CE≧VCC-0.2V, VIN≧ VCC-0.2V or VIN≦0.2V o -1 -1 1 1 uA uA 0.4 V Output High Voltage Operating Power Supply Current Standby Supply - TTL Standby Current -CMOS 2.4 25 V mA F=FMAX(3) 1 0.5 4 mA uA 1. Typical characteristics are at TA = 25 C. 2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included. 3. Fmax = 1/tRC. DATA RETENTION CHARACTERISTICS ( TA = 0 to + 70oC) Parameter Name VDR ICCDR TCDR tR 1. Read Cycle Time. 6 Rev. 1.0 Parameter Test Conduction VIN≧VCC-0.2V or VIN≦0.2V MIN 1.5 TYP MAX Unit V VCC for Data Retention /CE≧VCC-0.2V, Data Retention Current /CE≧VCC-0.2V, VCC=1.5V VIN≧VCC-0.2V or VIN≦0.2V Chip Deselect to Data Retention Time Operation Recovery Time See Retention Waveform 0.3 2 uA 0 ns tRC (1) ns Chiplus reserves the right to change product or specification without notice. High Speed Super Low Power SRAM 256K-Word By 8 Bit CS18LV20483 LOW Vcc DATA RETENTION WAVEFORM 1 ( /CE1 Controlled ) LOW Vcc DATA RETENTION WAVEFORM 2 ( CE2 Controlled ) AC TEST CONDITIONS Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Level Output Load Vcc/0V 5ns KEY TO SWITCHING WAVEFORMS WAVEFORMS INPUTS OUTPUTS MUST BE STEADY MUST BE STEADY 0.5Vcc See FIGURE 1A and 1B MAY CHANGE FROM L TO H DON’T CARE ANY CHANGE PERMITTED DOES NOT APPLY WILL BE CHANGE FROM L TO H CHANGE STATE UNKNOWN CENTER LINE IS HIGH IMPEDANCE OFF STATE MAY CHANGE FROM H TO L WILL BE CHANGE FROM H TO L 7 Rev. 1.0 Chiplus reserves the right to change product or specification without notice. High Speed Super Low Power SRAM 256K-Word By 8 Bit CS18LV20483 AC TEST LOADS AND WAVEFORMS TERMINAL EQUIVALENT 667Ω OUTPUT ALL INPUT PULSES VCC GND 10% 90% 90% 10% 1.73V FIGURE 1A FIGURE 1B FIGURE 2 5ns 5ns AC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70oC , Vcc = 3.3V ) < READ CYCLE > JEDEC Parameter Parameter Name Name tAVAX tAVQV tELQV tGLQV tELQX tGLQX tEHQZ tGHQZ tAXOX tRC tAA tCO tOE tLZ tOLZ tCHZ tOHZ tOH Description -55 -70 MAX ns 70 70 35 10 5 20 20 0 0 10 25 25 ns ns ns ns ns ns ns ns Unit MIN MAX MIN Read Cycle Time Address Access Time Chip Select Access Time Output Enable to Output Valid Chip Select to Output Low Z Output Enable to Output in Low Z Chip Deselect to Output in High Z Output Disable to Output in High Z Out Disable to Address Change 10 5 0 0 10 55 55 55 25 70 8 Rev. 1.0 Chiplus reserves the right to change product or specification without notice. High Speed Super Low Power SRAM 256K-Word By 8 Bit CS18LV20483 SWITCHING WAVEFORMS (READ CYCLE) NOTES: 1. tHZ and tOHZ are defined as the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection. 9 Rev. 1.0 Chiplus reserves the right to change product or specification without notice. High Speed Super Low Power SRAM 256K-Word By 8 Bit CS18LV20483 AC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70oC , Vcc = 3.3V ) < WRITE CYCLE > JEDEC Parameter Parameter Name Name tAVAX tE1LWH tAVWL tAVWH tWLWH tWHAX tWLQZ tDVWH tWHDX tWHOX tWC tCW tAS tAW tWP tWR tWHZ tDW tDH tOW Description -55 -70 MAX ns ns ns ns ns ns 20 30 0 5 ns ns ns ns Unit MIN MAX MIN Write Cycle Time Chip Select to End of Write Address Setup Time Address Valid to End of Write Write Pulse Width Write Recovery Time Write to Output in High Z Data to Write Time Overlap Data Hold from Write Time End of Write to Output Active 25 0 5 55 45 0 45 40 0 20 70 60 0 60 50 0 10 Rev. 1.0 Chiplus reserves the right to change product or specification without notice. High Speed Super Low Power SRAM 256K-Word By 8 Bit CS18LV20483 SWITCHING WAVEFORMS (WRITE CYCLE) 11 Rev. 1.0 Chiplus reserves the right to change product or specification without notice. High Speed Super Low Power SRAM 256K-Word By 8 Bit NOTES: CS18LV20483 1. A write occurs during the overlap(tWP) of low /CE1, a high CE2 and low /WE. A write begins when /CE1 goes low, CE2 going high and /WE goes low. A write ends at the earliest transition when /CE1 goes high , CE2 goes high an /WE goes high. The tWP is measured from the beginning of the write to the end of write. 2. tCW is measured from the /CE1 going low or CE2 going low to end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end or write to the address change. TWR applied in case a write ends as /CE1 or /WE going high or CE2 going low. ORDER INFORMATION 12 Rev. 1.0 Chiplus reserves the right to change product or specification without notice.