CS5825

Century Semiconductor Inc. GENERAL DESCRIPTION CS5825 receives four LVDS data channels and one LVDS clock channel. Each data channel is deserialized into 7-bit parallel data bus for output. The clock channel is used for frame sync and fed into an internal PLL that generates the 7X serial clock used in the deserializer. A digital phase alignment circuit can generate the sampling clock of the deserializer front-end. The frame sync clock aligned to the output 7-bit data is also output for timing reference. CS5825 supports open-safe design of LVDS when the input is not connected to LVDS drivers and the receiver outputs are forced low. Putting CS5825 into inhibit mode by a shutdown control (SHTDNN) signal can lower power consumption. FEATURES CS5825 28:4 LVDS Receiver • Four 7-bit serial data LVDS channels and one clock LVDS channel. • Compatible with ANSI TIA/EIA-644 LVDS standard. • Wide serial clocking speed ranges from 31MHz to 68MHz. • Support open-safe LVDS design. • Fully integrated on-chip PLL and digital phase alignment provide accurate deserializer operation. • Support power-down mode. • 5V/3.3V tolerant data input. • Single 3.3V supply operation. • CMOS low power consumption. • Functional compatible with DS90CF384 and SN75LVDS86. • Available in 56-pin TSSOP package. BLOCK DIAGRAM CS5825 AIP AIM DIN CLK PARALLEL-IN SERIAL-OUT 7-Bit SHIFT REGISTER D0,D1,D2,D3, D4,D6,D7 BIP BIM DIN CLK CIP CIM DIN CLK DIP DIM DIN CLK PARALLEL-IN SERIAL-OUT 7-Bit SHIFT REGISTER D8,D9,D12,D13, D14,D15,D18 PARALLEL-IN SERIAL-OUT 7-Bit SHIFT REGISTER D19,D20,D21,D22, D24,D25,D26 PARALLEL-IN SERIAL-OUT 7-Bit SHIFT REGISTER D27,D5,D10,D11, D16,D17,D23 7xCLK CKIP CKIM PHASE LOCK LOOP AND PHASE ALIGNER CLKOUT SHTDNN CONTROL LOGIC CS5825 Century Semiconductor, Inc. Taiwan: No. 2, Industry East Rd. 3rd, Science-Based Industrial Park, Hsin-Chu, Taiwan Tel: 886-3-5784866 Fax: 886-3-5784349 Sales@century-semi.com Sales@century-semi.com.tw www.century-semi.com Rev.0.0 May 2001 page 1 of 13 USA: 1485 Saratoga Ave. #200 San Jose, CA, 95129 Tel: 408-973-8388 Fax: 408-973-9388 Century Semiconductor Inc. PIN CONNECTION DIAGRAM CS5825 D22 D23 D24 VSS D25 D26 D27 LVDS_VSS AIM AIP BIM BIP LVDS_VDD LVDS_VSS CIM CIP CKIM CKIP DIM DIP LVDS_VSS PLL_VSS PLL_VDD PLL_VSS SHTDNN CLKOUT D0 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 VDD D21 D20 D19 VSS D18 D17 D16 VDD D15 D14 D13 VSS D12 D11 D10 VDD D9 D8 D7 VSS D6 D5 D4 D3 VDD D2 D1 CS5825 Figure-1 56-pin TSSOP page 2 of 13 Century Semiconductor Inc. PIN DESCRIPTION Name AIP, AIM BIP, BIM CIP, CIM DIP, DIM CKIP, CKIM D0,D1,D2,D3,D4, D6, D7 D8,D9,D12,D13, D14,D15,D18 D19,D20,D21,D22 ,D24,D25,D26 D27,D5,D10,D11, D16,D17,D23 CLKOUT SHTDNN Pin I Description CS5825 LVDS data channel A input. These are differential LVDS inputs for A channel corresponds to D0, D1, D2, D3, D4, D6, D7. AIP is the positive data input and AIM is the negative input. LVDS data channel B output. These are differential LVDS inputs for B channel corresponds to D8, D9, D12, D13, D14, D15, D18. LVDS data channel C output. These are differential LVDS outputs for C channel corresponds to D19, D20, D21, D22, D24, D25, D26. LVDS data channel C output. These are differential LVDS outputs for D channel corresponds to D27, D5, D10, D11, D16, D17, D23. LVDS clock channel input. These are differential LVDS input for the frame sync clock. The clock is sent to an on-chip PLL to generate 7X serial clock; An phase aligner is used to align the deserializer clock. Parallel data output for LVDS channel A. D[0] is LSB and D[7] is MSB. MSB is shifted in first. Parallel data output for LVDS channel B. D[8] is LSB and D[18] is MSB. Parallel data output for LVDS channel C. D[19] is LSB and D[26] is MSB. Parallel data output for LVDS channel C. D[19] is LSB and D[23] is MSB. Parallel data clock output. This clock signal recovered clock for data output reference. The falling edge should be used as the strobe for the next stage. Shutdown control (low active). When SHTDNN is low, the internal PLL is put into inhibit mode and all data outputs are forced low. This also resets all internal registers. For normal operation, SHTDNN should be set to high. Positive power supply for TTL outputs. A 3.3V supply should be used. Negative power supply. Connect to 0V. Positive power supply for LVDS inputs. Negative power supply for LVDS inputs. Positive power supply for PLL. Negative power supply for PLL. I I I I O O O O O I VDD VSS LVDS_VDD LVDS_VSS PLL_VDD PLL_VSS P P P P P P page 3 of 13 Century Semiconductor Inc. FUNCTIONAL DESCRIPTION Serial-In Parallel-Out 7-Bit Shift Register CS5825 It receives the serial data from the transmitter. It uses the 7xclk to strobe the serial data and sends 7-bit parallel data with input clock’s frequency. Phase Lock Loop and Phase Aligner The PLL generates the seven times input clock which is used for deserialized. The phase aligner is used for synchronous the input clock and output. Control logic There are two modes in this circuit. One is normal mode, and another is power down mode. Two modes are controlled by the control signal “SHTDNN”. If SHTDNN is high, the circuit is in the normal mode, else if low, the circuit is in the power down mode. In the power down mode, every block is off to make sure the least power consumption. page 4 of 13 Century Semiconductor Inc. Recommended Operating Conditions Symbol VCC VIH(SHTDN) VIL(SHTDN) Supply voltage High-level input voltage Low-level input voltage Receiver input range TA Operating free-air temperature Parameter Min 3 2 0 0 Typ 3.3 Max 3.6 0.8 2.4 70 CS5825 Unit V V V V °C Timing Requirements Symbol tc tsu1 th1 Parameter Cycle time, input clock* Setup time, input Hold time, input Min 14.7 600 600 Typ tc Max 32.4 Unit ns ps ps Note: Parameter tc is defined as the mean duration of a minimum of 32000 clock cycles. Electrical Characteristics over recommended operating conditions (unless otherwise noted) Symbol VIT+ VITVOH VOL Parameter Differential input high threshold voltage Differential input low threshold voltage High-level output voltage Low-level output voltage IOH = -4mA IOL = 4mA Disabled (power down mode), All inputs open Enabled, AnP = 1V, AnM = 1.4V, tc = 15.38ns ICC Quiescent current (average) Enabled, CL = 8 pF, Grayscale pattern, tc = 15.38ns Enabled, CL = 8 pF, Grayscale pattern, tc = 15.38ns IIH IIL II IOZ High-level input current (SHTDN) Low-level input current (SHTDN) Input current (LVDS input terminals A and CLKIN) High-impedance output current VIH = VCC VIL = 0 0 ≤ V1 ≤ 2.4V VO = 0 or VCC Condition Min -100 2.4 Typ 280 58 Max 100 0.4 72 Unit mV mV V V µA mA - 69 - mA - 94 - ±20 ±20 ±10 ±10 mA µA µA µA µA page 5 of 13 Century Semiconductor Inc. Symbol tsu2 th2 tRSKM Parameter Setup time, D0 - D20 valid to CLKOUT↓ Hold time, CLKOUT↓ to D0 - D20 valid Receive input skew margin Delay time, CLKIN↑ to CLKOUT ↓ Cycle time, change in output clock period# Enable time, SHTDN↑ to Dn valid Disable time, SHTDN↓ to off state Transition time, output (10% to 90% tr or tf) Pulse duration, output clock Figure-6 Figure-7 CL = 8pF - CS5825 Min 5 Typ Max Unit ns ns ps Switching Characteristics over recommended operating conditions (unless otherwise noted) Condition CL = 8pF (Figure-3) tc = 15.38 ns (±0.2%), Input clock jitter < 50 ps (Figure-4) tc = 15.38 ns (±0.2%), CL = 8 p F 5 490 td ∆ tc(o) ten tdis tt tw - 3.7 ± 100 1 400 3 0.43tc - ns ps ms ns ns ns Switching Characteristics Symbol LHT HLT Pos0 Pos1 Pos2 Pos3 Pos4 Pos5 Pos6 SKM COP COH COL SRC HRC CCD PLLs PDD Parameter low to high transition time high to low transitions time input strobe position for bit 0 (f = 65MHz) input strobe position for bit 1 (f = 65MHz) input strobe position for bit 2 (f = 65MHz) input strobe position for bit 3 (f = 65MHz) input strobe position for bit 4 (f = 65MHz) input strobe position for bit 5 (f = 65MHz) input strobe position for bit 6 (f = 65MHz) Rxin skew margin (f = 65MHz) RxCLK OUT Period RxCLK OUT high time (f = 65MHz) RxCKK OUT low time (f = 65MHz) RxOUT setup to RxCLKOUT (f = 65MHz) RxOUT hold to RxCLKOUT (f = 65MHz) RxCLK In to RxCLK OUT delay Phase Lock Loop set Power down delay Min 0.7 2.9 5.1 7.3 9.5 11.7 13.9 400 14.7 7.5 3.5 2.5 2.5 5 Typ 2.2 2.2 1.1 3.3 5.5 7.7 9.9 12.1 14.3 Max 5 5 1.4 3.6 5.8 8.0 10.2 12.4 14.6 32.2 9 10 1 Unit ns ns ns ns ns ns ns ns ns ps ns ns ns ns ns ns ms µs page 6 of 13 Century Semiconductor Inc. Electrical Characteristics Symbol IRCCG IRCCW IRCCS Parameter Receiver Supply Current Receiver Supply Current Receiver Power Down Supply Current Condition CL= 8pF, f = 65MHz (Worst Case pattern) CL = 8pF,f = 65MHz (Grayscale pattern) Power Down = Low Min Typ 200 CS5825 Max 300 Unit mA mA µA page 7 of 13 Century Semiconductor Inc. TIMING DIAGRAMS CS5825 CMOS/TTL OUTPUT CS 8pF Figure-2 CMOS/TTL Output Load 80% 80% 20% LHT HLT 20% Figure-3 CMOS/TTL Output Transition Times COP 2.0v 2.0v CLKOUT 0.8v COH COL SRC HRC 2.0v Hold D[20:0] 2.0v Setup Figure-4 Setup/Hold and High/Low Times page 8 of 13 Century Semiconductor Inc. TEST PATTERN CS5825 CLKIN D0, 6, 12 D1, 7, 13 D2, 8, 14 D3, 9, 15 D18, 19, 20 D4, 5, 10, 11, 16, 17 Figure-5 16-Grayscale Testing Pattern Waveforms tsu2 CLKIN/CLKOUT Even Dn Odd Dn Figure-6 The Worst-case Testing Pattern Waveforms tsu2 70% VOH D0 - D20 30% VOH th2 70% VOH CLKOUT 30% VOH Figure-7 Setup and Hold Time Waveforms page 9 of 13 Century Semiconductor Inc. PARAMETER MEASUREMENT INFORMATION CS5825 tc 4/7 tc ± t(RSKM) (see Note A) tsu1 3/7 tc ± t(RSKM) (see Note A) th1 An and An CLKIN 7 x CLK (Internal) td tW CLKOUT tr < 1ns 80% CLKIN or An 20% td tW VOH 1.4V VOL CLKOUT ≈ 300mV 0V ≈ -300mV NOTE A: CLKIN is advanced or delayed with respect to data until errors are observed at the receiver outputs. The advance or delay is then reduced until there are no data errors observed. The magnitude of the advance or delay is t(RSKM). Figure-8 Receiver Input Skew Margin, Setup/Hold Time, and Delay Time Definitions page 10 of 13 Century Semiconductor Inc. CS5825 CKIP/CKIM CLKOUT Vdiff=0v CCD Figure-9 Clock-in to Clock-out Delay 2V Power Down 3V Vcc PLLs CKIP/CKIM RxCLK OUT 2V Figure-10 Phase Lock Loop Stable Time Power Down (Low Active) 1.5V RxCLK In PDD RxOUT Low Figure-11 Power Down Delay page 11 of 13 Century Semiconductor Inc. CS5825 CKIP/CKIM AI BI CI Pos0 Min. Pos0 Max. Pos1 Min Pos1 Max. Pos2 Min. Pos2 Max. Pos3 Min. Pos3 Max. Pos4 Min. Pos4 Max. Pos5 Min. Pos5 Max. Pos6 Min. Pos6 Max. Figure-12 Strobe positions of LVDS inputs Ideal Strobe Position *IP or *IM ~1.4V C *IM or *IP RSKM min. Tpposn max. min. Rsposn max. RSKM min. max. ~1.0V Tpposn+1 Figure-13 Skew Margin of LVDS data inputs page 12 of 13 Century Semiconductor Inc. PACKAGE OUTLINE (56-pin TSSOP) CS5825 D c E1 E L θ A2 A1 e b A Symbol A A1 A2 b c D E E1 e L θ Dimensions in Millimeters MIN 1.05 0.05 0.17 0.09 13.90 7.80 6.00 0.50 0° NOM 0.90 0.20 0.15 14.00 8.10 6.10 0.50 MAX 1.20 0.15 0.27 0.20 14.10 8.40 6.20 0.75 7° Dimensions in Inches MIN 0.041 0.002 0.007 0.004 0.547 0.307 0.236 0.020 0° NOM 0.035 0.008 0.006 0.551 0.319 0.240 0.0197 MAX 0.047 0.006 0.010 0.008 0.555 0.330 0.244 0.030 7° page 13 of 13