EM42AM1684RTA-75L

256Mb DDR SDRAM Ordering Information EM 42 AM 16 8 4 R T A – 75 L EOREX MEMORY EDO/FPM D-RAMBUS DDRSDRAM DDRSGRAM SGRAM SDRAM : : : : : : 40 41 42 43 46 48 Power S : Standard L : Low power Package F : Pb-free G: Green Density 32M : 32 Mega Bits 16M : 16 Mega Bits 8M : 8 Mega Bits 4M : 4 Mega Bits 2M : 2 Mega Bits 1M : 1 Mega Bit Organization 4: 8: 9: x4 x8 x9 16 : x16 18 : x18 32 : x32 Refresh 1 : 1K 8 : 8K 2 : 2K 6 :16K 4 : 4K Bank 2 : 2Bank 6 : 16Bank 4 : 4Bank 3 : 32Bank 8 : 8Bank Min Cycle Time ( Max Freq.) -5 : 5ns ( 200MHz ) -6 : 6ns ( 167MHz ) -7 : 7ns ( 143MHz ) -75 : 7.5ns ( 133MHz ) -8 : 8ns ( 125MHz ) -10 : 10ns ( 100MHz ) Revision A : 1st B : 2nd C : 3rd D : 4th G : for VGA version only Interface V : 3.3V R : 2.5V Preliminary DCC-DD041157-3 Package C : CSP B : uBGA T : TSOP Q : TQFP P : PQFP ( QFP ) L : LQFP 1/37 256Mb DDR SDRAM 256Mb( 4Banks ) Double Data Rate SDRAM EM42AM1684RTA ( 16Mx16 ) Description The EM42AM1684RTA is a high speed synchronous graphic RAM fabricated with ultra high performance CMOS process containing 268,435,456 bits which organized as 4 Banks, each banks has 8,192 rows x 512 columns x 16 bits. The 256Mb DDR SDRAM uses a double data rate architecture to accomplish high-speed operation. The data path internally prefetches multiple bits and it transfers the data for both rising and falling edges of the system clock. It means the doubled data bandwidth can be achieved at the I /O pins. Features • Internal Double-data-rate architecture with 2 accesses per clock cycle • 4 banks operation • Bi-directional, intermittent data strobe (DQS) • All inputs except data and DM are sampled at the positive edge of the system clock. • Data Mask (DM) for write data • Auto & self refresh supported • 8K Refresh cycle / 64ms • Burst length of 2,4,8 • Sequential & Interleaved Burst type available • 2,2.5, 3 Clock read latency • Auto Precharge option for each burst accesses • DQS edge-aligned with data for Read cycles • DQS center-aligned with data for Write cycles • DLL aligns DQ & DQS transitions with CLK transition • 2.5V+/- 0.2V VDD • 2.5V SSTL-2 compatible I/O Ordering Information Part Number EM42AM1684RTA-5 EM42AM1684RTA-6 EM42AM1684RTA-75 Max. Frequency I/O Interface 200 MHz 166 MHz 133 MHz SSTL-2 SSTL-2 SSTL-2 Package 66 pins, TSOPII 66 pins, TSOPII 66 pins, TSOPII * EOREX reserves the right to change products or specification without notice. Preliminary DCC-DD041157-3 2/37 256Mb DDR SDRAM Pin Assignment ( Top View ) VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 NC VDDQ LDQS NC VDD /QFC/NC LDM /WE /CAS /RAS /CS NC BA0 BA1 AP/A10 A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 NC VSSQ UDQS NC VREF VSS UDM /CK CK CKE NC A12 A11 A9 A8 A7 A6 A5 A4 VSS 66pin TSOP-II (400mil x 875 mil) (0.65mm Pin pitch) Preliminary DCC-DD041157-3 3/37 256Mb DDR SDRAM Pin Descriptions ( Simplified ) Pin CLK, /CLK Name System Clock Pin Function Clock input active on the Positive rising edge except for DQ and DM are active on both edge of the DQS. Clock and /Clock are differential clock inputs. /CS enables the command decoder when “L” and disabled the command decoder when “H”. The new commands are overlooked when the command decoder is disabled but previous operation will still continue. Activates the CLK when “H” and deactivates when “L”. when deactivate the clock, CKE low signifies the power down or self refresh mode. Row address (A0 to A12) and Column address (CA0 to CA8) are multiplexed on the same pins. CA10 defines auto precharge at Column address . Selects which bank is to be active. Latches Row Addresses on the positive rising edge of the CLK with /RAS “L”. Enables row access & pre-charge. Latches Column Addresses on the positive rising edge of the CLK with /CAS low. Enables column access. Latches Column Addresses on the positive rising edge of the CLK with /CAS low. Enables column access. Data Inputs and Outputs are synchronized with both edge of DQS. DM controls data inputs. LDM corresponds to the data on DQ0-DQ7. UDM corresponds to the data on DQ8-DQ15 FET Control : EMRS Option output during every Read and Write access. It can be used to control isolation switches on modules. Data inputs and outputs are multiplexed on the same pin. VDD and VSS are power supply pins for internal circuits. VDDQ and VSSQ are power supply pins for the output buffers. This pin is recommended to be left No Connection on the device. SSTL-2 Reference voltage for input buffer. /CS Chip select CKE Clock Enable A0 ~ A12 Address BA0, BA1 Bank Address /RAS Row address strobe /CAS Column address strobe /WE Write Enable LDQS,UDQS LDM,UDM /QFC DQ0 ~ 15 VDD/VSS VDDQ/VSSQ NC/ RFU VREF Data input/output Data input/output Mask Data output Data input/output Power supply/Ground Power supply/Ground No connection / Reserved for Future Use Input Preliminary DCC-DD041157-3 4/37 256Mb DDR SDRAM Block Diagram A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 BA0 BA1 Auto/Self Refresh Counter DM Write DQM Control Row Add. Buffer Address Register Row Decoder Memory Array Data In S/A & I/O gating Col. Decoder Col. Add. Buffer Data Out DQi Mode Register Set (Extended M-R-S) Col. Add. Counter Burst Counter Timing Register CLK /CLK CKE /CS /RAS /CAS /WE DM DQS Preliminary DCC-DD041157-3 5/37 256Mb DDR SDRAM Simplified State Diagram Self Refresh LF SE LF SE it Ex Mode Register Set MRS IDLE CK REF CBR (Auto) Refresh Power Down CK CK EH EL CK EL EH Write Row Active Re ACT Re ad Power Down Wr i te wit h BS T ad Read h wit WRITE Read Write READ A Re ad A ite Wr WRITEA PR E E PR d READA B st ur en POWER ON PRE/PALL Precharge Manual Input Automatic Sequence Preliminary DCC-DD041157-3 6/37 256Mb DDR SDRAM Absolute Maximum Ratings Symbol VIN, VOUT VDD, VDDQ TOP TSTG PD IOS Item Input, Output Voltage Power Supply Voltage Operating Temperature Storage Temperature Power Dissipation Short Circuit Current Rating -0.3 ~ 3.6 -0.3 ~ 3.6 0 ~ 70 -55 ~ 150 1 50 Units V V C C W mA Note : Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Recommended DC Operation Conditions ( Ta = 0 ~ 70 C ) Symbol VDD VDDQ VREF VTT VIH VIL Parameter Power Supply Voltage Power Supply Voltage (for I/O Buffer) I/O Logic high voltage I/O Termination voltage Input Logic high voltage Input Logic low voltage Min. 2.3 2.3 1.15 VREF-0.04 VREF+0.18 -0.3 Typical 2.5 2.5 1.25 - Max. 2.7 2.7 1.35 VREF+0.04 VDDQ+0.3 VREF-0.18 Units V V V V V V Capacitance ( Vcc =2.5V, f = 1MHz, Ta = 25 C ) Symbol CCLK CI CO Parameter Clock capacitance ( CLK, /CLK ) Input capacitance for CKE, Address, /CS, /RAS, /CAS, /WE DM , Data & DQS Input/Output capacitance Min. 2.5 2.5 4.0 Max. 4.0 4.5 6.5 Units pF pF pF Preliminary DCC-DD041157-3 7/37 256Mb DDR SDRAM Recommended DC Operating Conditions ( Ta = 0 ~ 70 C ) Parameter Symbol Test condition Burst length = 2, tRC ≥ tRC (min), IOL = 0 mA, One bank active Speed -5 110 -6 95 -75 85 Units Notes Operating current Precharge standby current in power down mode Precharge standby current in non-power down mode Active standby current in power down mode Active standby current in non-power down mode Operating current ( Burst mode ) Refresh current Self Refresh current IDD1 mA 1 IDD2P CKE ≤ VIL (max.), tCk = min 4.5 mA IDD2N CKE ≥ VIH (min.), tCK = min, /CS ≥ VIH (min.) Input signals are changed one time during 2clks 40 mA IDD3P CKE ≤ VIL(max.), tCK = min CKE ≥ VIH(min), tCK = min, / CS ≥ VIH(min) Input signals are changed one time during 2clks tCK ≥ tCK(min.), IOL = 0 mA All banks active tRC ≥ tRFC(min.), All banks active CKE ≤ 0.2V READ WRITE 15 mA IDD3N 45 100 110 160 2 2 mA IDD4 IDD5 IDD6 mA mA mA 1 2 Note : 1. IDD1 and IDD4 depends on output loading and cycle rates. Specified values are obtained with the output open. 2. Min. of tRFC ( Auto Refresh Row Cycle Times ) is shown at AC Characteristics. Preliminary DCC-DD041157-3 8/37 256Mb DDR SDRAM Recommended DC Operating Conditions ( Continued ) Parameter Symbol Min. Max. Unit Note Input leakage current ILI -5 5 uA 1 Output leakage current High level output voltage Low level output voltage ILO VOH VOL -5 VTT + 0.76 - 5 VTT - 0.76 uA V V 2 IOH=-15.2mA IOH=-15.2mA Note : 1. VIN= 0 to 3.6V All other pins are not tested under VIN= 0V. 2. DOUT is disabled, VIN= 0 to 2.7V. Preliminary DCC-DD041157-3 9/37 256Mb DDR SDRAM Operating AC Characteristics ( VDD = 2.5V +/- 0.2 V, Ta = 0 ~ 70 C ) Parameter DQ output access from CLK, /CLK DQS output access from CLK, /CLK CK low / high level width Clock cycle time DQ and DM hold / setup time DQ and DM input pulse width for each input Data out high / low impedance time from CLK, /CLK DQS-DQ skew for associated DQ signal Write command to first latching DQS transition DQS input valid window Mode Register Set command cycle time Write Preamble setup time Write Postamble Address /control input hold / setup time Read Preamble Read Postamble Active to Precharge command period Active to Active command period Auto Refresh Row Cycle Time Active to Read or write delay Precharge command period Active bank A to B command period Column address to column address delay Symbol tDQCK tDQSCK tCL,tCH CL=2 -5 -6 -75 Min. Max. Min. Max. Min. Max. -0. 5 +0. 5 -0.7 -0. 5 +0. 5 -0.6 +0.7 -0.75 +0.75 +0.6 -0.75 +0.75 Units ns ns tCK ns ns ns ns ns ns tCK tCK tCK ns 0.45 0.55 0.45 0.55 0.45 0.55 7.5 6 0.4 1.75 -0.7 +0.7 12 12 6 6 0.45 1.75 -0.7 12 12 7.5 7.5 0.5 1.75 +0.7 -0.75 +0.75 0.5 12 12 tCK CL=2.5 tDH,tDS tDIPW tHZ, tLZ tDQSQ tDQSS tDSL, tDSH tMRD tWPRES tWPST tIH,tIS tRPRE tRPST tRAS tRC tRFC tRCD tRP tRRD tCCD 0.4 0.7 0.45 1.25 0.75 1.25 0.75 1.25 0.35 2 0 0.6 0.7 0.4 0.8 1.1 0.6 70K 55 70 15 15 10 1 0.9 0.4 42 1.1 0.6 70K 60 72 18 18 12 1 0.9 0.4 45 0.6 0.4 1.0 1.1 0.6 70K 65 75 20 20 15 1 0.35 2 0 0.6 0.35 2 0 0.4 tCK ns tCK tCK ns ns ns ns ns ns tCK 0.9 0.4 40 Preliminary DCC-DD041157-3 10/37 256Mb DDR SDRAM Operating AC Characteristics ( Continued ) ( VDD = 2.5V +/- 0.2 V, Ta = 0 ~ 70 C ) Parameter Last data in to Read command Last data in to Write command Last data in to Precharge Command Exit self Refresh to non-read command Exit self Refresh to read command Average periodic refresh interval /QFC preamble during reads /QFC postamble during reads /QFC output access time from CK/ /CK /QFC output hold time Symbol tCDLR tCDLW tDPL tXSNR tXSRD tREFI tQPRE tQPST tQCK tQOH 0.4 0.9 0.4 0 0.6 0.4 -75 -8 -10 Units tCK tCK tCK ns ns 15.6 0.9 0.4 0 0.6 0.4 0.6 1.1 0.6 us tCK tCK ns tCK Min. Max. Min. Max. Min. Max. 2.5tCK-tDQSS 2.5tCK-tDQSS 2.5tCK-tDQSS 0 2 75 200 15.6 1.1 0.6 0 2 75 200 15.6 0.9 0.4 0 1.1 0.6 0 2 75 200 Preliminary DCC-DD041157-3 11/37 256Mb DDR SDRAM Truth Table 1. Command Truth Table Command Ignore Command No operation Burst stop Read Read with auto pre-charge Write Write with auto pre-charge Bank activate Pre-charge select bank Pre-charge all banks Mode register set Symbol DESL NOP BSTH READ READA WRIT WRITA ACT PRE PALL MRS CKE n-1 H H H H H H H H H H H n X X X X X X X X X X X /CS /RAS /CAS /WE H L L L L L L L L L L X H H H H H H L L L L X H H L L L L H H H L X H L H H L L H L L L BA0, A10 BA1 X X X V V V V V V X L X X X L H L H V L H L A12 ~A0 X X X V V V V V X X V Note : H = High level, L = Low level, X = High or Low level (Don't care), V = Valid data input 2. CKE Truth Table Command Idle Idle Self refresh Idle Power down Command CBR refresh command Self refresh entry Self refresh exit Power down entry Power down exit Symbol REF SELF CKE n-1 H H L L H L n H L H H L H /CS /RAS /CAS /WE Addr. L L L H X X L L H X X X L L H X X X H H H X X X X X X X X X Remark H = High level, L = Low level, X = High or Low level ( Don't care ) Preliminary DCC-DD041157-3 12/37 256Mb DDR SDRAM 3. Operative Command Table Current state /CS /R /C /W H L L L Idle L L L L H L L L Row active L L L L L H L L L Read L L L L L X H H H L L L L X H H H H L L L L X H H H H L L L L X H H L H H L L X H H L L H H L L X H H L L H H L L X H L X H L H L X H L H L H L H L X H L H L H L H L BA/RA BA/A10 X Op-Code, Mode-Add ACT PRE/PREA REFA MRS ILLEGAL Terminate burst, Precharge ILLEGAL ILLEGAL 1 Addr. X X X BA/CA/A10 BA/RA BA/A10 X Op-Code, Mode-Add X X X BA/CA/A10 BA/CA/A10 BA/RA BA/A10 X Op-Code, Mode-Add X X X BA/CA/A10 Command DESEL NOP TERM READ/WRIT/BW ACT PRE/PREA REFA MRS DESEL NOP TERM READ/READA WRITE/WRITEA ACT PRE/PREA REFA MRS DESEL NOP TERM READ/READA NOP NOP NOP ILLEGAL Action Notes 1 3 4 5 Bank active , Latch RA NOP Auto refresh Mode register NOP NOP NOP Begin Read, Latch CA, Determine auto-precharge Begin Write, Latch CA, Determine auto-precharge ILLEGAL Precharge / Precharge all ILLEGAL ILLEGAL NOP ( Continue burst to end ) NOP ( Continue burst to end ) Terminal burst Terminal burst. Latch CA,Begin new read, Determine Auto-precharge 1 Remark: H =High Level, L=Low level, X=High or Low level ( Don’t care ), AP= Auto Precharge Preliminary DCC-DD041157-3 13/37 256Mb DDR SDRAM Current state /CS /R /C /W H L L L X H H H H L L L L X H H H L L L L X H H H L L L L X H H L L H H L L X H H L H H L L X H H L H H L L X H L H L H L H L X H L X H L H L X H L X H L H L Addr. X X X BA/CA/A10 BA/CA/A10 BA/RA BA/A10 X Op-Code, Mode-Add X X BA/CA/A10 BA/RA BA/A10 X X Op-Code, Mode-Add X X X BA/CA/A10 BA/RA BA/A10 X Op-Code, Mode-Add Command DESEL NOP TERM READ/READA WRITE/WRITEA ACT PRE/PREA REFA MRS DESEL NOP TERM READ/WRITE ACT PRE/PREA REFA MRS DESEL NOP TERM READ/WRITE ACT PRE/PREA REFA MRS Action NOP ( Continue burst to end ) NOP ( Continue burst to end ) ILLEGAL Terminate burst with DM=“H”, Latch CA , Begin read,Determine auto-precharge Terminate burst , Latch CA ,Begin new write, Determine auto-precharge ILLEGAL Terminate burst with DM=“H”, Precharge ILLEGAL ILLEGAL NOP ( Continue burst to end ) NOP ( Continue burst to end ) ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP (Continue burst to end ) NOP (Continue burst to end ) ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Notes 5 2 5 2 1 Write L L L L L H L L 5 Read with Autoprecharge L L L L L H L L 1 1 1 Write with Autoprecharge L L L L L 1 1 1 Remark: H =High Level, L=Low level, X=High or Low level ( Don’t care ), AP= Auto Precharge Preliminary DCC-DD041157-3 14/37 256Mb DDR SDRAM Current state /CS /R /C /W H L L L Write recovering L L L L L H L L L Refreshing L L L L H L L L Precharging L L L L H L L Row activating L L L L L X H H H H L L L L X H H H L L L L X H H H L L L L X H H H L L L L X H H L L H H L L X H H L H H L L X H H L H H L L X H H L H H L L X H L H L H L H L X H L X H L H L X H L X H L H L X H L X H L H L Addr. X X X BA/CA/A10 BA/CA/A10 BA/RA BA/A10 X Op-Code, Mode-Add X X X BA/CA/A10 BA/RA BA/A10 X Op-Code, Mode-Add X X X BA/CA/A10 BA/RA BA/A10 X Op-Code, Mode-Add X X X BA/CA/A10 BA/RA BA/A10 X Op-Code, Mode-Add Command DESEL NOP TERM READ WRITE/WRITEA ACT PRE/PREA REFA MRS DESEL NOP TERM READ/WRITE ACT PRE/PREA REFA MRS DESEL NOP TERM READ/WRITE ACT PRE/PREA REFA MRS DESEL NOP TERM READ/WRITE ACT PRE/PREA REFA MRS NOP NOP NOP ILLEGAL Action Notes 1 1 1 New write, Determine AP ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP ( ldle after tRP) NOP ( ldle after tRP) NOP ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP ( Idle after tRP ) NOP ( Idle after tRP ) NOP ILLEGAL ILLEGAL NOP( Idle after tRP ) ILLEGAL ILLEGAL NOP (Row active after tRCD) NOP (Row active after tRCD) NOP ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL 1 1 3 1 1 1 Remark: H =High Level, L=Low level, X=High or Low level ( Don’t care ), AP= Auto Precharge Note 1. ILLEGAL to bank in specified state: → Function may be legal in the Bank indicated by Bans Address (BA), depending on the state of the bank. 2. Must satisfy bus contention, bus turn around, and/or write recovery requirements. 3. NOP to bank precharging or in idle sate. May precharge bank indicated by BA. 4. ILLEGAL of any bank is not idle. Preliminary DCC-DD041157-3 15/37 256Mb DDR SDRAM 4. Command Truth Table for CKE Current state CKE n-1 H L L Self refreshing L L L L H L L Both bank precharge power down L L L L H H H H All Banks Idle H H H H H L Any state other than listed above n X H H H H H L X H H H H H L H L L L L L L L L X /CS /R X H L L L L X X H L L L L X X H L L L L L L L X X X H H H L X X X H H H L X X X H H H L L L L X /C /W X X H H L X X X X H H L X X X X H H L H L L L X X X H L X X X X X H L X X X X X H L X H H L L X Addr. X X X X X X X X X X X X X X X X X X X RA X OP Code Op-Code X INVALID Exist Self-Refresh Exist Self-Refresh ILLEGAL ILLEGAL ILLEGAL Action Notes 1 1 NOP ( Maintain Self-refresh ) INVALID Exist Power down Exist Power down ILLEGAL ILLEGAL ILLEGAL NOP ( Maintain Power down ) Refer to function true table Enter power down Enter power down ILLEGAL ILLEGAL Row active / Bank active Enter self-refresh Mode register access Special mode register access Refer to current state 3 3 3 2 2 H H X X X X X Refer to command truth table Remark : H = High level, L = Low level, X = High or Low level (Don't care) Notes 1. After CKE’s low to high transition to exist self refresh mode. And a time of tRC (min) has to be elapse after CKE’s low to high transition to issue a new command. 2. CKE low to high transition is asynchronous as if restarts internal clock. 3. Power down and self refresh can be entered only from the idle state of all blanks. Preliminary DCC-DD041157-3 16/37 256Mb DDR SDRAM Mode Register Definition Mode Register Set The mode register stores the data for controlling the various operating modes of DDR SDRAM which contains addressing mode, burst length, /CAS latency, test mode, DLL reset and various vendor’s specific opinions. The defaults values of the register is not defined, so the mode register must be written after EMRS setting for proper DDR SDRAM operation. The mode register is written by asserting low on /CS, /RAS, /CAS, /WE and BA0 ( The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the mode register. ) The state of the address pins A0-A12 in the same cycle as /CS, /RAS, /CAS, /WE and BA0 going low is written in the mode register. Two clock cycles are requested to complete the write operation in the mode register. The mode register contents can be changed using the same command and clock cycle requirements during operating as long as all banks are in the idle state. The mode register is divided into various fields depending on functionality. The burst length uses A0-A2, addressing mode uses A3, /CAS latency ( read latency from column address ) uses A4-A6. A7 is used for test mode. A8 is used for DDR reset. A7 must be set to low for normal MRS operation. MRS Cycle 0 1 2 3 4 5 6 7 8 CLK, /CLK Command NOP Precharge All Banks tRP NOP MRS NOP 2 CLK Any Command NOP NOP NOP Preliminary DCC-DD041157-3 17/37 256Mb DDR SDRAM Address Input for Mode Register Set BA1 BA0 A12/11 A10 A9 A8 A7 TM A6 A5 A4 A3 BT A2 A1 A0 RFU CAS Latency Burst Length A8 0 1 DLL Reset No Yes BA0 0 1 An – A0 MRS Cycle EMRS Sequential Reserved 2 4 8 Reserved Reserved Reserved Reserved Burst Type Sequential Interleave Burst Length Interleave A2 Reserved 0 2 0 4 0 8 0 Reserved 1 Reserved 1 Reserved 1 Reserved 1 A3 0 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 CAS Latency Reserved Reserved 2 Reserved Reserved Reserved 2.5 Reserved A7 0 1 A6 0 0 0 0 1 1 1 1 A5 0 0 1 1 0 0 1 1 A4 0 1 0 1 0 1 0 1 Operation Mode Normal Test Preliminary DCC-DD041157-3 18/37 256Mb DDR SDRAM Burst Type ( A3 ) Burst Length 2 4 A2 A1 A0 XX0 XX1 X00 X01 X10 X11 000 001 010 011 100 101 110 111 Sequential Addressing 01 10 0123 1230 2301 3012 01234567 12345670 23456701 34567012 45670123 56701234 67012345 70123456 Interleave Addressing 01 10 0123 1032 2301 3210 01234567 10325476 23016745 32107654 45670123 54761032 67452301 76543210 8 * Page length is a function of I/O organization and column addressing DLL Enable / Disable The DLL must be enabled for normal operation. DLL enable is required during power-up initialization and upon returning to normal operation after having disable the DLL for the purpose of debug or evaluation ( upon existing Self Refresh Mode, the DLL is enable automatically. ) Any time the DLL is enabled, 200 clock cycles must occur before a READ command can be issued. Output Drive Strength The normal drive strength got all outputs is specified to be SSTL-2, Class II. Some vendors might also support a weak drive strength option, intended for lighter load and/or point to point environments. Preliminary DCC-DD041157-3 19/37 256Mb DDR SDRAM Extended Mode Register Set ( EMRS ) The Extended mode register stores the data enabling or disabling DLL. The value of the extended mode register is not defined, so the extended mode register must be written after power up for enabling or disabling DLL. The extended mode register is written by asserting low on /CS, /RAS, /CAS, /WE and high on BA0 ( The DDR SDRAM should be in all bank precharge with CKE already prior to writing into the extended mode register. ) The state of address pins A0-A10 and BA1 in the same cycle as /CS, /RAS, /CAS, and /WE going low is written in the extended mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. A0 is used for DLL enable or disable. High on BA0 is used for EMRS. All the other address pins except A0 and BA0 must be set to low for proper EMRS operation. BA1 BA0 RFU 1 A12/11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 RFU : Must be set as 0 /QFC D.I.C DLL A0 0 1 BA0 0 1 An – A0 MRS Cycle EMRS DLL Enable Enable Disable Output Driver Impedance Control Normal 0 Weak 1 QFC Control Disable Enable 0 1 Preliminary DCC-DD041157-3 20/37 256Mb DDR SDRAM /QFC Function /QFC Definition When drive low in reads coincident with the start of DQS, this DRAM output signal says that one cycle later there will be the first valid DQS output and returned on Hi-Z after this finishing a burst operation. It is also driven low shortly after a write command is received and returned to Hi-Z shortly after the last data strobe transition is received. Whenever the device is in standby, the signal is Hi-Z. DQS is intended to enable an external data switch. QFC can be enabled or disabled through EMRS control. /QFC Timing or Read Operation QFC on reads is enabled coincident with the start of DQS preamble, and disabled coincident with the end of DQS postamble 0 1 2 3 4 5 6 7 8 CLK, /CLK Command Read DQS DQS Hi-Z Dout0 Dout1 /QFC tQPRE tQPST CL=2. BL=2 Preliminary DCC-DD041157-3 21/37 256Mb DDR SDRAM /QFC Timing on Write Operation with tDQSSmax /QFC on writes is enabled as soon as possible after the clock edge of write command and disabled as soon as possible after the last DQS-in low going edge. 0 1 2 3 4 5 6 7 8 CLK, /CLK Command DQS@tDQSmax Write DQS@tDQSSmax Hi-Z Dout0 Dout1 /QFC tQCK tQOH BL=2 Preliminary DCC-DD041157-3 22/37 256Mb DDR SDRAM /QFC Timing on Write Operation with tDQSSmin /QFC on writes is enabled as soon as possible after the clock edge of write command and disabled as soon as possible after the last DQS-in low going edge. 0 1 2 3 4 5 6 7 8 CLK, /CLK Command DQS@tDQSmin Write DQS@tDQSSmin Hi-Z Dout0 Dout1 /QFC tQCK tQOH BL=2 Preliminary DCC-DD041157-3 23/37 256Mb DDR SDRAM Package Dimension 1.20 MAX 0.047 11.76 +/- 0.20 1.00+/- 0.10 0.039+/- 0.004 0.21+/- 0.05 0.008+/- 0.002 0.05 MIN 0.002 0.463 +/- 0.008 PIN #1 22.22+/- 0.10 0.875+/- 0.004 22.62 MAX 0.891 0.10 MAX 0.004 0.125 +0.075 / -0.035 0.005+0.003 / -0.001 0.71 0.028 0.65 0.0256 0.30 +0.08 / -0.08 0.012+0.003 / -0.003 10.16 0.400 0 – 0.50 0.020 0.45 – 0.75 0.018 – 0.030 * EOREX reserves the right to change products or specification without notice. Preliminary DCC-DD041157-3 0.25 TYP 0.010 8’ 24/37