EUP7212

Preliminary EUP7212 Dual 150/300mA LDO with POR DESCRIPTION The EUP7212 is a dual low dropout linear regulator. The first regulator is capable of sourcing 150mA, while the second regulator can source up to 300mA and includes a power-on reset function. The EUP7212 is stable with small ceramic output capacitors. The performance of EUP7212 is optimized for battery power systems to deliver low noise, low dropout voltage, low quiescent current and excellent line and load transient response. The EUP7212 is available in fixed output voltages in the 8-pin 3mm×3mm DFN leadless package. FEATURES Input Voltage Range: 2.5V to 5.5V Stable with Ceramic Output Capacitor 2 LDO Outputs: Output 1-150mA Output Current Output 2-300mA Output Current Power-on Reset Function with Adjustable Delay Time Low Dropout Voltage of 100mV@150mA Low Quiescent Current of 150µA High PSRR 70dB at 1kHz: Thermal Shutdown Protection Current Limit Protection 3mm×3mm DFN-8 Package RoHS Compliant and 100% Lead (Pb)-Free APPLICATIONS Cellular Phones Wireless Modems PDAs Typical Application DS7212 Ver 0.3 Nov. 2005 1 Preliminary Block Diagram EUP7212 Pin Configurations Part Number Pin Configurations EUP7212 DFN-8 Pin Description PIN VIN EN BYPASS SET GND POR VOUT2 VOUT1 Pin 1 2 3 4 5 6 7 8 DESCRIPTION Input voltage of the LDO Enable input: Enables to regulator 1 outputs. Active high input. High=on, low=off. Do not leave floating. Optional bypass capacitor for noise reduction Delay Set Input: Connect external capacitor to GND to set the internal delay for the POR output. When left open, there is no delay. This pin cannot be grounded Ground Power-On Reset Output: Open-Drain Output. Active low indicates an output undervoltage condition on regulator 2 Output of regulator 2: 300mA output current Output of regulator 1: 150mA output current DS7212 Ver 0.3 Nov. 2005 2 Preliminary Ordering Information Order Number EUP7212-1.8/2.8JIR1 EUP7212-1.8/2.8JIR0 EUP7212-3.3/1.8JIR1 EUP7212-3.3/1.8JIR0 Package Type DFN-8 DFN-8 DFN-8 DFN-8 Marking DExx P7212 DExx P7212 HDxx P7212 HDxx P7212 EUP7212 Operating Temperature range -40 °C to 125°C -40 °C to 125°C -40 °C to 125°C -40 °C to 125°C EUP7212□□□/□□□ □ □ □ □ Lead Free Code 1: Lead Free 0: Lead Packing R: Tape & Reel Operating temperature range I: Industry Standard Package Type J: DFN Output Voltage Option DS7212 Ver 0.3 Nov. 2005 3 Preliminary Absolute Maximum Ratings EUP7212 VIN,VEN ---------------------------------------------------------------------------------- 0V to 7V Power Dissipation (PD) ------------------------------------------------------ Internally Limited Junction Temperature ------------------------------------------------------ -40°C to +125°C Storage Temperature ------------------------------------------------------ -65°C to +150°C Lead Temp -----------------------------------------------------------------------------260°C Operating Ratings VIN ------------------------------------------------------------------------------------ 2.5 to 5.5V VEN -------------------------------------------------------------------------------------- 0V to VIN Junction Temperature ------------------------------------------------------ -40°C to +125°C Thermal Resistance θJA(DFN-8) --------------------------------------------------- 60°C/W Electrical Characteristics VIN= VOUT +1.0V, IOUT=1mA, COUT=1µF. Typical values and limits appearing in standard typeface are for TJ= 25°C Symbol Parameter Conditions Min Typ Max Units △VOUT -1.5 1.5 % Output Voltage Accuracy Variation from nominal Vout Reg Line Line Regulation Input range Vin=Vout+1V to 5.5V -0.2 0.02 0.2 %/V Iout=100µA to 150mA(Vout 1 & Vout 2) 0.7 2 Reg Load Load Regulation % Iout=100µA to 300mA(Vout) 1 2.5 Iout=150mA(Vout 1) 120 180 VDrop Dropout Voltage mV Iout= 300mA(Vout 2) 240 350 Iout 1=Iout2=0 150 170 IQ Ground Pin Current µA Iout 1=150mA & Iout=300mA 250 300 Ground Pin Current in IQ_SD VEN≦0.4V 3 5 µA Shutdown PSRR Ripple Rejection Freq.=1Khz; Cout=1.0µF; CBYP=10nF 70 dB Output 1 Short to Ground 150 340 Iout(Max) Current Limit mA Output 2 Short to Ground 300 580 Cout=1.0µF; CBYP=10nF; Noise Output Voltage Noise 40 µVrms BW=10~100KHz Enable Input Logic Low (Regulator Shutdown) 0.6 VEN Enable Input voltage V Logic High(Regulator Enable) 1.8 VIL1.8V (Regulator Enable) -0.5 0.01 0.5 POR Output Low Threshold, % of nominal Vout 2 Low Threshold 90 % (Flag ON) VTH High Threshold, % of nominal Vout 2 High Threshold 96 % (Flag OFF) POR output logic low VOL IL=250µA 0.17 0.2 V voltage; IPOR Flag leakage Current Flag 0FF -1 0.01 1 µA SET Input ISET SET Pin Current Source Set pin Voltage to 0 0.75 1.25 1.75 µA SET Pin Threshold POR = High VSET 1.25 V Voltage DS7212 Ver 0.3 Nov. 2005 4 Preliminary Typical Operating Characteristics EUP7212 Unless otherwise specified, CIN=CCOUT=1µF Ceramic, CBYPASS=100nF, VIN=VOUT+1V, IOUT= 100µA TA=25°C, Enable pin is tied to VIN. DS7212 Ver 0.3 Nov. 2005 5 Preliminary EUP7212 DS7212 Ver 0.3 Nov. 2005 6 Preliminary EUP7212 DS7212 Ver 0.3 Nov. 2005 7 Preliminary EUP7212 DS7212 Ver 0.3 Nov. 2005 8 Preliminary Application Note Function Description The EUP7212 is a high performance, low quiescent current power management IC consisting of two µCap low dropout regulators, a power-on reset (POR) circuit and an open-drain driver. The first regulator is capable of sourcing 150mA at output voltages from 1.25V to 5V. The second regulator is capable of sourcing 300mA of current at output voltages from 1.25V to 5V. The second regulator has a POR circuit that monitors its output voltage and indicates when the output voltage is within 5% of nominal. The POR offers a delay time that is externally programmable with a single capacitor to ground. An open-drain driver completes the power management chipset, offering the capability of driving LEDs for keypad backlighting in applications such as cellphones. Enable The enable input allows for logic control of both output voltages with one enable input. The EUP7212 is turned off by pulling the VEN pin low, and turned on by pulling it high. If this feature is not used, the VEN pin should be tied to VIN to keep the regulator output on at all time. To assure proper operation, the signal source used to drive the VEN input must be able to swing above and below the specified turn-on/off voltage thresholds listed in the Electrical Characteristics section under VIL and VIH. Power-On Reset (POR) The power-on reset output is an open-drain N-Channel device, requiring a pull-up resistor to either the input voltage output voltage for proper voltage for proper voltage levels. The POR output has a delay time that is programmable with a capacitor from the SET pin to ground. The delay time can be programmed to be as long as 1 second. The SET pin is a current source output that charges a capacitor that sets the delay time for the power-on reset output. The current source is a 1µA current source that charges a capacitor up from 0V. When the capacitor reaches 1.25V, the output of the POR is allowed to go high. External Capacitors Like any low-dropout regulator, the EUP7212 requires external capacitors for regulator stability. The EUP7212 is specifically designed for portable applications requiring minimum board space and smallest components. These capacitors must be correctly selected for good performance. Input Capacitor An input capacitance of ≈ 1µF or greater is required between the EUP7212 input pin and ground (the amount of the capacitance may be increased without limit). EUP7212 This capacitor must be located a distance of not more than 1cm from the input pin and returned to a clean analog ground. Any good quality ceramic, tantalum, or film capacitor may be used at the input. Output Capacitor The EUP7212 is designed specifically to work with very small ceramic output capacitors. A ceramic capacitor (temperature characteristics X7R, X5R, Z5U, or Y5V) in 1 to 22µF range with 5mΩ to 500mΩ ESR range is suitable in the EUP7212 application circuit. The output capacitor must meet the requirement for minimum amount of capacitance and also have an ESR (Equivalent Series Resistance) value which is within a stable range (5mΩ to 500mΩ) No-Load Stability The EUP7212 will remain stable and in regulation with no external load. This is specially important in CMOS RAM keep-alive applications. Capacitor Characteristics The EUP7212 is designed to work with ceramic capacitors on the output to take advantage of the benefits they offer: for capacitance values in the range of 1µF to 4.7µF range, ceramic capacitors are the smallest, least expensive and have the lowest ESR values (which makes them best for eliminating high frequency noise). The ESR of a typical 1µF ceramic capacitor is in the range of 20mΩ to 40mΩ, which easily meets the ESR requirement for stability by the EUP7212. The ceramic capacitor’s capacitance can vary with temperature. The capacitor type X7R, which operates over a temperature range of -55°C to +125°C, will only vary the capacitance to within ±15%. Most large value ceramic capacitors ( ≈ 2.2µF) are manufactured with Z5U or Y5V temperature characteristics. Their capacitance can drop by more than 50% as the temperature goes from 25°C to 85°C. Therefore, X7R is recommended over Z5U and Y5V in applications where the ambient temperature will change significantly above or below 25°C. Noise Bypass Capacitor Connecting a 0.01µF capacitor between the CBYPASS pin and ground significantly reduces noise on the regulator output. This cap is connected directly to a high impedance node in the bandgap reference circuit. Any significant loading on this node will cause a change on the regulated output voltage. For this reason, DC leakage current through this pin must be kept as low as possible for best output voltage accuracy. The types of capacitors best suited for the noise bypass capacitor are ceramic and film. Unlike many other LDO’s, addition of a noise reduction capacitor does not effect the load transient response of the device. DS7212 Ver 0.3 Nov. 2005 9 Preliminary Packaging Information DFN-8 EUP7212 NOTE 1. All dimensions are in millimeters, θ is in degrees 2. M: The maximum allowable corner on the molded plastic body corner 3. Dimension D does not include mold protrusions or gate burrs. Mold protrusions and gate burrs shall not exceed 0.15mm per side 4. Dimension E does not include interterminal mold protrusions or terminal protrusions. Interminal mold protrusions and/or terminal protrusions shall not exceed 0.20mm per side 5. Dimension b applies to plated terminals. Dimension A1 is primarily Y terminal plating, but may or may not include a small protrusion of terminal below the bottom surface of the package 6. Burr shall not exceed 0.060mm 7. JEDEC MO-229 SYMBOLS A A1 A3 B D D1 E E1 e L aaa bbb ccc M θ MIN. 0.81 0 -----0.25 2.85 -----2.85 ----------0.25 ---------------------12 DIMENSIONS IN MILLIMETERS NOM. MAX. 0.9 1.00 0.015 0.03 0.20 REF -----0.30 0.37 3.00 BSC 3.15 2.3 BSC -----3.00 BSC 3.15 1.5 BSC -----0.65 BSC ----0.35 0.45 0.25 -----0.10 -----0.10 ----------0.05 -----0 DS7212 Ver 0.3 Nov. 2005 10