GLT44108-35TQ

G -LINK GLT44108 512K X 8 CMOS DYNAMIC RAM WITH FAST PAGE MODE Preliminary Aug 1999 (Rev.2.1) Features : ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ 524,288 words by 8 bits organization. Fast access time and cycle time. Low power dissipation. Operating Current-150mA max. TTL Standby Current-2mA max. Read-Modify-Write, RAS -Only Refresh, Description : The GLT44108 is a 524,288 x 8 bit highperformance CMOS dynamic random access memory. The GLT44108 offers Fast Page mode with asymmetric address and accepts 512-cycle refresh in 8ms interval. All inputs are TTL compatible. Fast Page Mode operation allows random access up to 512 x 8 bits within a page, with cycle times as short as 22ns. The GLT44108 is best suited for graphics, digital signal processing and high performance peripherals. CAS -Before- RAS Refresh, Hidden Refresh and Test Mode Capability. 1024 refresh cycles/16ms. Available in 28pin 400 mil SOJ Single +5.0V±10% Power Supply. All inputs and Outputs are TTLcompatible. Fast Page Mode supports sustained data rates up to 50MHZ. PIN CONFIGURATION : GLT44108 28 Lead SOJ Vcc DQ0 DQ1 DQ2 DQ3 NC WE RAS A9 A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VSS DQ7 DQ6 DQ5 DQ4 CAS OE NC A8 A7 A6 A5 A4 VSS G-Link Technology 2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A. G-Link Technology Corporation,Taiwan 6F, No.24-2, Industry E. RD. IV, Science Based Industrial Park, Hsin Chu, Taiwan. -1- G -LINK GLT44108 512K X 8 CMOS DYNAMIC RAM WITH FAST PAGE MODE Preliminary Aug 1999 (Rev.2.1) HIGH PERFORMANCE Max. RAS Access Time, (tRAC) Max. Column Address Access Time, (tAA) Min. Fast Page Mode Cycle Time, (tPC) Min. Read/Write Cycle Time, (tRC) Max. CAS Access Time (tCAC) -40 40 ns 20 ns 22 ns 75 ns 12 ns -50 50 ns 25 ns 31 ns 90 ns 13 ns -60 60 ns 30 ns 40 ns 110 ns 15 ns Pin Descriptions: Name A0 – A9 RAS CAS WE OE DQ0 - DQ7 VCC VSS Block Diagram: OE WE CAS Function Address Inputs Row Address Strobe Column Address Strobe Write Enable Output Enable Data Inputs / Outputs +5V Power Supply Ground RAS RAS CLOCK GENERATOR CAS CLOCK GENERATOR W E CLOCK GENERATOR OE CLOCK GENERATOR V CC V SS Data I/O B U S COLUMN DECODERS REFRESH COUNTER Y 0 - Y8 9 1024 A0 A1 A8 A9 512×8 I/O0 SENSE AMPLIFIERS I/O BUFFER I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 . . ADDRESS BUFFERS AND PREDECODERS X 0 - x9 ROW DECODERS MEMORY ARRAY G-Link Technology 2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A. G-Link Technology Corporation,Taiwan 6F, No.24-2, Industry E. RD. IV, Science Based Industrial Park, Hsin Chu, Taiwan. -2- G -LINK GLT44108 512K X 8 CMOS DYNAMIC RAM WITH FAST PAGE MODE Preliminary Aug 1999 (Rev.2.1) Absolute Maximum Ratings* Operating Temperature, TA (ambient) Capacitance* TA=25°C, VCC=5V±10%, VSS=0V Symbol CIN1 CIN2 COUT Parameter Address Input RAS , CAS , WE , OE Data Input/Output Max. Unit 5 7 7 pF pF pF ......................................-10°C to +80°C Storage Temperature(plastic)....-55°C to +150°C Voltage Relative to VSS...............-1.0V to + 7.0V Short Circuit Output Current......................50mA Power Dissipation......................................1.0W *Note:Operation above Absolute Maximum Ratings can adversely affect device reliability. *Note: Capacitance is sampled and not 100% tested Electrical Specifications l l All voltages are referenced to GND. After power up, wait more than 200µs and then, execute eight CAS before RAS or RAS only refresh cycles as dummy cycles to initialize internal circuit. G-Link Technology 2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A. G-Link Technology Corporation,Taiwan 6F, No.24-2, Industry E. RD. IV, Science Based Industrial Park, Hsin Chu, Taiwan. -3- G -LINK GLT44108 512K X 8 CMOS DYNAMIC RAM WITH FAST PAGE MODE Preliminary Aug 1999 (Rev.2.1) DC and Operating Characteristics (1-2) TA = 0°C to 70°C, VCC=5V±10%, VSS=0V, unless otherwise specified. Sym. ILI Parameter Input Leakage Current (any input pin) Output Leakage Current (for High-Z State) Operating Current, Random READ/WRITE Standby Current,(TTL) Refresh Current, RAS -Only Test Conditions 0V ≤ VIN ≤ 5.5V (All other pins not under test=0V) 0V ≤ Vout ≤ 5.5V Output is disabled (Hiz) tRC = tRC (min.) RAS , CAS , at VIH other inputs ≥ VSS RAS cycling, CAS at VIH tRC = tRC (min.) RAS at VIL, CAS ,address cycling:tPC=tPC(min.) Access Time Min. -10 Typ Max. Unit Notes +10 µA ILO ICC1 -10 tRAC = 40ns tRAC = 50ns tRAC = 60ns +10 150 140 120 2 µA mA 1,2 ICC2 ICC3 mA mA 2 tRAC = 40ns tRAC = 50ns tRAC = 60ns tRAC = 40ns tRAC = 50ns tRAC = 60ns tRAC = 40ns tRAC = 50ns tRAC = 60ns 150 140 120 150 140 120 150 140 120 1 ICC4 Operating Current, FAST Page Mode mA 1,2 ICC5 Refresh Current, CAS Before RAS RAS , CAS , address cycling: tRC=tRC(min.) RAS ≥ VCC-0.2V, CAS ≥ VCC-0.2V, All other inputs ≥VSS mA 1 ICC6 Standby Current, (CMOS) mA VIL VIH VOL VOH Notes: Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage -1 2.4 IOL = 4.2mA IOH = -5mA 2.4 +0.8 VCC+1 0.4 V V V V 3 3 1.ICC is dependent on output loading when the device output is selected. Specified ICC(max.) is measured with the output open. 2.ICC is dependent upon the number of address transitions specified. ICC(max.) is measured with a maximum of one transition per address cycle in random Read/Write and Fast Page Mode. 3. Specified VIL(min.) is steady state operation. During transitions, VIL(min.) may undershoot to -1.0V for a period not to exceed 20ns.All AC parameters are measured with VIL(min.)≥Vss and VIH(max.)≤Vcc. G-Link Technology 2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A. G-Link Technology Corporation,Taiwan 6F, No.24-2, Industry E. RD. IV, Science Based Industrial Park, Hsin Chu, Taiwan. -4- G -LINK AC Characteristics (0° C≤ TA≤ 70° C,See note 1,2) GLT44108 512K X 8 CMOS DYNAMIC RAM WITH FAST PAGE MODE Preliminary Aug 1999 (Rev.2.1) Test condition:VCC=5.0V±10%, VIH/VIL=2.4V/0.8V,VOH/VOL=2.0V/0.8V Parameter 40 ns 50 ns Symbol MIN. MAX. MIN. MAX. Read/Write Cycle Time Read Midify Write Cycle Time Access Time from RAS Access Time from CAS Access Time from Column Address CAS to Output in Low-Z Output Buffer Turn-off Delay from CAS Transition Time(Rise and Fall) RAS Precharge Time RAS Pulse Width RAS Hold Time CAS Hold Time CAS Pulse Width RAS to CAS Delay Time RAS to Column Address Delay Time CAS to RAS Precharge Time Row Address Setup Time Row Address Hold Time Column Address Setup Time Column Address Hold Time Column Address Hold Time Referenced to RAS Column Address Lead Time Referenced to RAS Read Command Setup Time Read Command Hold Time Referenced to RAS Read Command Hold Time Referenced to CAS WE Hold Time Referenced to CAS Write Command Hold Time Referenced to RAS tWCH tWCR 6 30 7 40 tRC tRWC tRAC tCAC tAA tCLZ tOFF tT tRP tRAS tRSH tCSH tCAS tRCD tRAD tCRP tASR tRAH tASC tCAH tAR tRAL tRCS tRRH tRCH 75 120 0 0 3 25 40 12 40 12 16 11 5 0 6 0 6 30 20 0 0 0 40 12 20 8 50 10000 10000 30 22 90 140 0 0 3 30 50 13 50 13 18 13 5 0 8 0 8 40 25 0 0 0 50 13 25 10 50 10000 10000 37 25 - 60 ns MIN. MAX. Unit 110 160 0 0 3 40 60 15 60 15 20 15 5 0 10 0 10 45 30 0 0 0 10 45 60 15 30 13 50 10000 10000 45 30 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Notes 3,4 3,4 3,4 3 7 2 4 4 8 9 9 10 5 G-Link Technology 2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A. G-Link Technology Corporation,Taiwan 6F, No.24-2, Industry E. RD. IV, Science Based Industrial Park, Hsin Chu, Taiwan. -5- G -LINK GLT44108 512K X 8 CMOS DYNAMIC RAM WITH FAST PAGE MODE Preliminary Aug 1999 (Rev.2.1) Parameter Symbol WE Pulse Width WE Lead Time Referenced to RAS WE Lead Time Referenced to CAS Data-In Setup Time Data-In Hold Time Data Hold Time Referenced to RAS Refresh Time(256cycles) WE Setup Time RAS to WE Delay Time CAS to WE Delay Time Column Address to WE Delay Time CAS Setup Time( CAS before RAS Refresh) CAS Hold Time( CAS before RAS Refresh) RAS to CAS Precharge Time CAS Precharge Time(CBR Counter Test Cycle) Access Time from CAS Precharge Fast Page mode Read/Write Cycle Time Fast Page mode Read Modify Write Cycle Time CAS Precharge Time(Fast Page mode) RAS Pulse Width(Fast Page mode) RAS Hold Time from CAS Precharge Access Time from OE OE to Delay Time Output Buffer Turn-off Delay Time from OE OE Hold Time WE Hold Time(Hidden Refresh Cycle) tOEH tWHR tWP tRWL tCWL tDS tDH tDHR tREF tWCS tRWD tCWD tAWD tCSR tCHR tRPC tCPT tCPA tPC tPRWC tCP tRASP tRHCP tOEA tOED tOEZ 40 ns MIN. MAX. 6 13 13 0 6 33 0 60 28 38 5 10 5 20 30 65 7 40 25 8 0 0 15 8 25 125000 50 ns MIN. MAX. 7 17 14 0 7 40 0 70 33 43 5 10 5 20 35 80 8 50 30 10 0 0 15 8 30 125000 60 ns MIN. MAX. Unit 10 15 15 0 10 45 0 85 38 53 5 10 5 20 40 90 10 60 35 13 0 0 15 8 35 125000 Notes 10 ns ns ns ns ns ns ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 11 11 6 5 5 5 5 3 10 8 - 13 10 - 15 13 - 7 G-Link Technology 2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A. G-Link Technology Corporation,Taiwan 6F, No.24-2, Industry E. RD. IV, Science Based Industrial Park, Hsin Chu, Taiwan. -6- G -LINK GLT44108 512K X 8 CMOS DYNAMIC RAM WITH FAST PAGE MODE Preliminary Aug 1999 (Rev.2.1) Notes 1. An initial pause of 200µs is required after power-up followed by any 8 RAS only Refresh or CAS before RAS Refresh cycles to initialize the internal circuit. 2. VIH(min.) and VIL(min.) are reference levels for measuring timing of input signals. Transition times are measured between VIH(min.) and VIL(max.) are assumed to be 5ns for all inputs. 3. Measured with an equivalent to 1 TTL loads and 50pF. 4. For read cycles, the access time is defined as follows: Input Conditions Access Time tRAC(MAX.) tRAD ≤ tRAD(MAX.) and tRCD ≤ tRCD(MAX.) tAA(MAX.) tRAD(max.)< tRAD and tRCD ≤ tRCD(MAX.) tRCD(max.)< tRCD tCACMAX.) tRAD(MAX.) and tRCD(MAX.) indicate the points which the access time changes and are not the limits of operation. 5. tWCS,tRWD,tCWD and tAWD are non restrictive operating parameters. They are included in the data sheet as electric characteristics only. If tWCS ≥ tWCS(min.), the cycle is an early write cycle and the data output will remain high impedance for the duration of the cycle.If tCWD ≥ tCWD(min.),tRWD ≥ tRWD (min.) and tAWD ≥ tAWD(min.), then the cycle is a read-modify-write cycle and the data output will contain the data read from the selected address. If neither of the above conditions is satisfied, the condition of the data out is indeterminate. 6. tAR,tWCR, and tDHR are referenced to tRAD(max.). 7. tOFF(max.) and tOEZ(max.) define the time at which the output achieves the open circuit condition and are not referenced to VOH or VOL. 8. tCRP(min) requirement should be applicable for RAS , CAS cycle preceded by any cycles. 9. Either tRCH(min.) or tRRH(min.) must be satisfied for a read cycle. 10. tWP(min.) is applicable for late write cycle or read modify write cycle. In early write cycles,tWCH(min.) should be satisfied. 11.This specification is referenced to CAS falling edge in early write cycles and to WE falling edge in late write or read modify write cycles. G-Link Technology 2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A. G-Link Technology Corporation,Taiwan 6F, No.24-2, Industry E. RD. IV, Science Based Industrial Park, Hsin Chu, Taiwan. -7- G -LINK GLT44108 512K X 8 CMOS DYNAMIC RAM WITH FAST PAGE MODE Preliminary Aug 1999 (Rev.2.1) Read Cycle tRC tRAS VIH- tRP RAS VIL- tCRP VIH- tCSH tRCD tRSH tCAS tRAD tRAL tASC tCAH COLUMN ADDRESS tCRP CAS VIL- tASR Address VIHVIL- tRAH ROW ADDRESS tRCS VIH- tRCH tRRH WE VIL- tAR tAA tOEZ tOEA tCAC tRAC tCLZ DATA-OUT tOFF VIH- OE VIL- DQ VOHVOL- OPEN Don't Care Early Write Cycle NOTE : DOUT = Open tRC tRP VIH- tRAS RAS VIL- tCSH tCRP VIH- tRCD tCAS tRSH tCRP CAS VIL- VIH- tASR tRAH ROW ADDRESS tRAD tASC tCAH COLUMN ADDRESS tRAL Address VIL- tCWL tRWL tAR VIH- tWCS WE VIL- tWCR tWCH tWP VIH- OE VIL- tDHR tDS VIH- tDH DATA - IN DQ VIL- Don't Care G-Link Technology 2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A. G-Link Technology Corporation,Taiwan 6F, No.24-2, Industry E. RD. IV, Science Based Industrial Park, Hsin Chu, Taiwan. -8- G -LINK GLT44108 512K X 8 CMOS DYNAMIC RAM WITH FAST PAGE MODE Preliminary Aug 1999 (Rev.2.1) Late Write Cycle ( OE Controlled Write) VIHVIL- NOTE : DOUT = Open tRC tRP tRAS RAS tCSH tCRP CAS VIHVIL- tRCD tCAS tRSH tCRP VIH- tASR tRAH ROW ADDRESS tRAD tASC tRAL tCAH COLUMN ADDRESS Address VIL- tCWL tRWL tRCS VIH- WE tWP VIL- VIH- OE VIL- tOED tDS tOEH tDH COLUMN ADDRESS Don't Care VIH- DQ VIL- Read - Modify - Write Cycle tRC tRP RAS VIHVIL- tRAS tCRP CAS VIHVIL- tRCD tRSH tCAS tCSH tCRP tASR Address VIHVIL- tRAD tASC tCAH COLUMN ADDRESS tRAH ROW ADDR. tAWD tCWD WE VIHVIL- tRWL tCWL tWP OE VIHVIL- tOEA tCLZ tAA tCAC tOED tOEZ tDS tDH VALID DATA-IN Don't Care DQ VI/OHVI/OL- tRAC VALID DATA-OUT G-Link Technology 2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A. G-Link Technology Corporation,Taiwan 6F, No.24-2, Industry E. RD. IV, Science Based Industrial Park, Hsin Chu, Taiwan. -9- G -LINK GLT44108 512K X 8 CMOS DYNAMIC RAM WITH FAST PAGE MODE Preliminary Aug 1999 (Rev.2.1) Fast Page Read Cycle tRASP VIH- tRP RAS VIL- tPC tCRP VIH- tPC tCAS tCP tRSH tCAS tRCD tCAS tCP CAS VIL- tRAD tCSH tASR tRAH tASC tCAH COLUMN ADDRESS tASC tCAH tASC tCAH Address VIHVIL- ROW ADDR. COLUMN ADDRESS COLUMN ADDRESS tRCS VIH- tRCH tRCS tRCS tRRH tRCH WE VIL- tCAC tOEA tCAC tOEA VIH- OE VIL- tRAC tCLZ VIH- tAA tAA tOFF tCLZ tOEZ tAA tOFF tCLZ tOEZ tOFF tOEZ DQ VILVALID DATA-UOT VALID DATA-UOT VALID DATA-UOT Don't Care Fast Page Write Cycle VIH- NOTE : DOUT = Open tRASP t RP tRHCP tPC tCRP tRCD tCAS tCP tPC tCAS tCP tRSH tCAS tRAD tASR tRAH tASC tCSH tCAH COLUMN ADDRESS RAS VIL- VIH- CAS VIL- tASC tCAH tASC COLUMN ADDRESS tCAH Address VIHVIL- ROW ADDR. COLUMN ADDRESS tWCS VIH- tWCH tWP tCWL tWCS tWP tWCH tWCS tWCH tWP WE VIL- tCWL tCWL tRWL VIH- OE VIL- tDS VIH- tDH VALID DATA-IN tDS VALID DATA-IN tDS tDS VALID DATA-IN tDS DQ VIL- Don't Care G-Link Technology 2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A. G-Link Technology Corporation,Taiwan 6F, No.24-2, Industry E. RD. IV, Science Based Industrial Park, Hsin Chu, Taiwan. - 10 - G -LINK GLT44108 512K X 8 CMOS DYNAMIC RAM WITH FAST PAGE MODE Preliminary Aug 1999 (Rev.2.1) Fast Page Mode Late Write Cycle tRASP VIH- t RP tRHCP RAS VIL- tCSH tCRP CAS VIHVIL- t PC tCAS tCP tCAS tCP tRSH tCAS tCRP tRCD tRAD tASR Address VIHVILROW ADDR. tCAH tASC COLUMN ADDRESS tRAH tASC COLUMN ADDRESS tCAH tASC COLUMN ADDRESS tRAL tCAH tRCS VIH- tCWL tWP tRCS tCWL tWP tRCS tCWL tRWL tWP WE VIL- tOEH VIH- tOEH tOEH OE VIL- tOED VIH- tDS tDH tOED tDS Hi-Z tDH tOED tDS Hi-Z tDH Hi-Z DQ VIL- VALID DATA-IN VALID DATA-IN VALID DATA-IN Don't Care Fast Page Read - Modify - Write Cycle tRASP RAS VIHVIL- tRP tCSH tRSH tCAS tRCD VIH- tCAS tCP tCRP CAS VIL- tASR VIH- tRAD tRAH tASC tCAH tASC COL. ADDR. COL. ADDR. tPRWC tRAL tCAH Address VIL- ROW ADDR. tRCS VIH- tCWL tCWD tAWD tRWD tWP tCWD tAWD tCPWD tRWL tCWL tWP WE VIL- tOEH tDH tOED tOEZ tDS tOEA tCAC tAA tOED tOEZ tDH tDS VIH- OE tOEA tCAC tAA tRAC VIL- VI/OH- DQ VI/OL- tCLZ VALID DATA-OUT VALID DATA-IN tCLZ VALID DATA-OUT VALID DATA-IN Don't Care G-Link Technology 2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A. G-Link Technology Corporation,Taiwan 6F, No.24-2, Industry E. RD. IV, Science Based Industrial Park, Hsin Chu, Taiwan. - 11 - G -LINK GLT44108 512K X 8 CMOS DYNAMIC RAM WITH FAST PAGE MODE Preliminary Aug 1999 (Rev.2.1) CAS Before RAS Refresh Cycle tRC tRAS V IH- tRC tRP tRAS tRP RAS V IL- tCSR CAS V IHV IL- tCHR tRPC tCSR tCHR tRPC tCRP RAS -Only Refresh Cycle tRC tRAS VIH- tRC tRP tRAS tRP RAS VIL- tCRP CAS VIHVIL- tRPC tCRP tASR Address VIH- tRAH ROW tASR tRAH ROW VIL- Hidden Refresh Cycle ( Read ) tRC tRAS RAS VIHVIL- tRC tRP tRAS tRP tCRP VIH- tRCD tRSH tCHR CAS VIL- tRAD tASR Address VIHVIL- tRAL tASC COLUMN ADDRESS tCAH tCAH ROW ADDRESS tRCS VIH- tWHR WE VIL- tAA tOEA VIH- OE VIL- tCAC tRAC DQ VIHVIL- tCLZ tOEZ DATA-OUT tOFF OPEN Don't Care G-Link Technology 2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A. G-Link Technology Corporation,Taiwan 6F, No.24-2, Industry E. RD. IV, Science Based Industrial Park, Hsin Chu, Taiwan. - 12 - G -LINK GLT44108 512K X 8 CMOS DYNAMIC RAM WITH FAST PAGE MODE Preliminary Aug 1999 (Rev.2.1) Hidden Refresh Cycle ( Write ) VIHVIL- NOTE : DOUT =Open tRC tRAS tRP tRAS tRC tRP RAS tCRP VIH- tRCD tRSH tCHR CAS VIL- tRAD tASC Address VIHVIL- tCAH tASC COLUMN ADDRESS tCAH ROW ADDRESS tWCS VIH- tWCH tWP WE VIL- VIH- OE VIL- tDS DQ VIHDATA-IN tDH VIL- Don't Care G-Link Technology 2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A. G-Link Technology Corporation,Taiwan 6F, No.24-2, Industry E. RD. IV, Science Based Industrial Park, Hsin Chu, Taiwan. - 13 - G -LINK GLT44108 512K X 8 CMOS DYNAMIC RAM WITH FAST PAGE MODE Preliminary Aug 1999 (Rev.2.1) CAS - Before RAS Refresh Counter Test Cycle tRAS VIHRAS VIL- tRP tCSR VIHCAS VIL- tCHR tCPT tRSH tCAS tRAL tCAH tASC AddressVIHVILCOLUMN ADDRESS Read Cycle WE VILOE VILVIH- tWRP tWRH tAA tCAC tRCS tOEA tCLZ tOEZ VALID DATA-OUT tRRH tRCH VIH- tCEZ DQ VOL- VOH- Write Cycle VIHWE VIL- tWRP tWRH tWCS tWP tRWL tCWL tWCH OE VIL- VIH- tDS VIHDQ VIL- tDH VALID DATA-IN OPEN tRCS Read-Modify-Write WE VILVIH- tAWD tCWD tCAC tAA tOEA tOED tCLZ tOEZ tCWL tRWL tWP OE VIL- VIH- tDH tDS DQ VI/OL- VI/OH- VALID VALID DATA-OUT DATA-IN Don't Care G-Link Technology 2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A. G-Link Technology Corporation,Taiwan 6F, No.24-2, Industry E. RD. IV, Science Based Industrial Park, Hsin Chu, Taiwan. - 14 - G -LINK GLT44108 512K X 8 CMOS DYNAMIC RAM WITH FAST PAGE MODE Preliminary Aug 1999 (Rev.2.1) Ordering Information Part Number GLT44108-40J4 GLT44108-50J4 GLT44108-60J4 SPEED 40ns 50ns 60ns POWER Normal Normal Normal FEATURE FPM FPM FPM PACKAGE SOJ 400mil 28L SOJ 400mil 28L SOJ 400mil 28L Parts Numbers (Top Mark) Definition : GLT 4 41 4 : DRAM 6 : Standard SRAM 7 : Cache SRAM 8 : Synchronous Burst SRAM 08 - 40 J4 PACKAGE -SRAM CONFIG. SPEED T : PDIP(300mil) 064 : 8K 04 : x04 -SRAM TS : TSOP(Type I) 256 : 256K 08 : x08 12 : 12ns TC : TSOP(Type ll) 512 : 512K 16 : x16 15 : 15ns PL : PLCC 100 : 1M 32 : x32 20 : 20ns FA : 300mil SOP -DRAM 70 : 70ns FB : 330mil SOP 10 : 1M(C/EDO)* -DRAM FC : 445mil SOP 11 : 1M(C/FPM)* 35 : 35ns J3 : 300mil SOJ 12 : 1M(H/EDO)* 40 : 40ns J4 : 400mil SOJ 13 : 1M(H/FPM)* 45 : 45ns VOLTAGE P : PDIP(600mil) 20 : 2M(EDO) 50 : 50ns Blank : 5V Q : PQFP 21 : 2M(FPM) 60 : 60ns L : 3.3V TQ : TQFP 40 : 4M(EDO) M : Mix Voltage 41 : 4M(FPM) 80 : 8M(EDO) 81 : 8M(FPM) *See note Note : CÙCDROM , HÙHDD. Example : 1.GLT710008-15T 1Mbit(128Kx8)15ns 5V SRAM PDIP(300mil)Package type. 2.GLT44016-40J4 4Mbit(256Kx16)40ns 5V DRAM SOJ(400mil)Package type. G-Link Technology 2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A. G-Link Technology Corporation,Taiwan 6F, No.24-2, Industry E. RD. IV, Science Based Industrial Park, Hsin Chu, Taiwan. - 15 - G -LINK GLT44108 512K X 8 CMOS DYNAMIC RAM WITH FAST PAGE MODE Preliminary Aug 1999 (Rev.2.1) Package Information 400mil 28 Lead Small Outline J-form Package (SOJ) G-Link Technology 2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A. G-Link Technology Corporation,Taiwan 6F, No.24-2, Industry E. RD. IV, Science Based Industrial Park, Hsin Chu, Taiwan. - 16 -