HPL5331U5C-TR

HPL5331 3A Bus Termination Regulator Features • • • • Provide Bi-direction Current - Sourcing or Sinking Current up to 3A 1.25V/0.9V Output for DDR I/II Applications Fast Transient Response High Output Accuracy - ±20mV over Load, VOUT Offset and Temperature • • • • • Adjustable Output Voltage by External Resistors Current-Limit Protection On-Chip Thermal Shutdown Shutdown for Standby or Suspend Mode Simple SOP-8, SOP-8-P with thermal pad, TO-252- 5 and TO-263-5 Packages General Description (Cont.) On-chip thermal shutdown provides protection against any combination of overload that would create excessive junction temperature. The output voltage of HPL5331 track the voltage at VREF pin. A resistor divider connected to VIN, GND and VREF pins is used to provide a half voltage of VIN to VREF pin. In addition, an external ceramic capacitor and an opendrain transistor connected to VREF pin provides softstart and shutdown control respectively. Pulling and holding the VREF to GND shuts off the output. The output of HPL5331 will be high impedance after being shut down by VREF or thermal shutdown function. Pin Configuration VIN GND Applications • • • DDR I/II SDRAM Termination SSTL-2/3 Termination Voltage Applications Requiring the Regulator with Bi-direction 3A Current Capability 1 2 3 4 8 7 6 5 VCNTL VCNTL VCNTL VCNTL VOUT VREF VCNTL GND VIN VREF VOUT TAB is VCNTL SOP-8 (Top View) VIN TO-252-5 (Top View) 5 4 3 2 1 VOUT VREF VCNTL GND VIN 1 2 3 4 8 7 6 5 NC NC General Description The HPL5331 linear regulator is designed to provide a regulated voltage with bi-directional output current for DDR-SDRAM termination. The HPL5331 integrates two power transistors to source or sink current up to 3A. It also incorporate current-limit, thermal shutdown and shutdown control functions into a single chip. Current-limit circuit limits the short-circuit current. GND VREF VOUT TAB is VCNTL VCNTL NC SOP-8-P (Top View) NC = No internal connection TO-263-5 (Top View) = Thermal Pad (connected to GND plane for better heat dissipation)  Copyright HIPAC Semiconductor, Inc. Rev. A.8 - Oct., 2003 1 www.hipacsemi.com 1 2 3 4 5 HPL5331 Ordering and Marking Information H PL5331 L ead Free Code H andling Code Temp. Range Package Code Package Code K : SOP-8 KA : SOP-8-P U5 : TO-252-5 G5 : TO-263-5 Temp. Range C : 0 to 70 o C Handling Code TR : Tape & Reel Lead Free Code L : Lead Free Device Blank : Original Device HPL5331KC-TR : HPL5331KAC-TR : H PL5331 XXXXX XXXXX - Date Code HPL5331U5C-TR : HPL5331G5C-TR : H PL5331 XXXXX XXXXX - Date Code Pin Description PIN NAME V IN I/O I DESCRIPTION Main power input pin. Connect this pin to a voltage source and an input capacitor. The HPL5331 sources current to VOUT pin by controlling the upper NPN pass transistor, providing a current path from VIN pin. Power and signal ground. Connect this pin to system ground plane with shortest traces. The HPL5331 sinks current from VOUT pin by controlling the lower NPN pass transistor, providing a current path to GND pin. This pin is also the ground path for internal control circuitry. Power input pin for internal control circuitry. V C NTL Connect this pin to a voltage source, providing a bias for the internal control circuitry. A bypass capacitor is usually connected near this pin. Reference voltage input and active-low shutdown control pin. Apply a voltage to this pin as a reference voltage for the HPL5331. Connect this pin to a resistor divider, between VIN and GND, and a capacitor for soft-start and filtering noise C u rre n t purposes. Applying and holding this pin low by an open-drain transistor to shut Lim it down the output. Output pin of the regulator. Connect this pin to load. Output capacitors connected this pin improves stability and transient response. The output voltage tracks the reference voltage and is capable of sourcing or sinking current up to 3A. G ND O V CNTL I V REF I V OUT O Block Diagram V C NTL V IN V RE F V o lt ag e R e g ulat io n Th erm a l L im it C u rre nt L im it V OUT S h u td ow n G ND  Copyright HIPAC Semiconductor, Inc. Rev. A.8 - Oct., 2003 2 www.hipacsemi.com HPL5331 Absolute Maximum Ratings S ymbol V CNTL V IN PD TJ T STG T SDR V ESD Parameter V CNTL Supply Voltage, VCNTL to GND V IN Supply Voltage, VIN to GND P ower Dissipation J unction Temperature S torage Temperature S oldering Temperature, 10 Seconds M inimum ESD Rating (Human Body Mode) Rating -0.2 ~ 7 -0.2 ~ 3.9 Internally Limited 150 -65 ~ 150 300 ±3 Unit V V W o o o C C C kV Thermal Characteristics Symbol θJA Parameter Thermal Resistance in Free Air SOP-8 SOP-8-P TO-252-5 TO-263-5 Rating 160 80 80 50 Unit °C/W Recommended Operating Conditions Symbol V CNTL V IN V REF IOUT TJ Parameter V CNTL Supply Voltage V IN Supply Voltage V REF Input Voltage V OUT Output Current (Note1, 2) J unction Temperature Range 3.1 ~ 6V 1.6 ~ 3.5 0.8 ~ 1.75 -3 ~ +3 0 ~ 125 Unit V V V A o C Note1 : The symbol “+” means the VOUT sources current to load; the symbol “-“ means the VOUT sinks current to GND. Note2 : The max. IOUT varies with the TJ. Please refer to the typical characteristics.  Copyright HIPAC Semiconductor, Inc. Rev. A.8 - Oct., 2003 3 www.hipacsemi.com HPL5331 Electrical Characteristics Refer to the typical application circuit. These specifications apply over, VCNTL=3.3V, VIN=2.5V/1.8V, VREF=0.5VIN and TJ= 0 to 125°C, unless otherwise specified. Typical values refer to TJ =25°C. S ymbol O utput Voltage V OUT V OUT Output Voltage S ystem Accuracy V OS V OUT Offset Voltage (V OUT –V REF) L oad Regulation P rotection S ourcing Current (V IN =2.5V) S inking Current (V IN =2.5V) S ourcing Current (V IN =1.8V) Sinking Current (V IN =1.8V) T J =25°C T J =125°C T J =25°C T J =125°C T J =25°C T J =125°C T J =25°C T J =125°C +3.3 - 3.3 +2.9 - 2.9 +3.6 +3.1 -3.6 -3.1 +3.2 +2.6 -3.2 -2.6 1 50 40 2 4.5 50 2 .6 1 50 20 0 .2 500 40 nA µA V 6 110 mA I OUT=0A Over temperature, VOUT offset, and load regulation I OUT=+10mA I OUT=-10mA I OUT=+10mA to +3A I OUT = - 10mA to -3A -6 V REF -20 -14 -9 2 -3 7 12 8 20 V mV mV mV Parameter Test Conditions HPL5331 Min Typ Max Unit I LIM C urrent Limit A T SD T hermal Shutdown Rising T J Temperature T hermal Shutdown Hysteresis I OUT =0A I OUT = ± 3A (Normal Operation), V CNTL =5V V REF=GND (Shutdown) V REF=1.25V/0.9V (Normal Operation) o o C C Input Current ICNTL V CNTL Supply Current IVREF V REF Bias Current (The current flows out of VREF) V REF=GND (Shutdown) S hutdown Threshold Voltage S hutdown Control 0.35 0.65  Copyright HIPAC Semiconductor, Inc. Rev. A.8 - Oct., 2003 4 www.hipacsemi.com HPL5331 Typical Application Circuit 1. VOUT=1.25V/0.9V Application VC N TL +3 .3 V VIN +2 .5 V/1 .8 V R1 1k C IN 4 70 uF Shu td o w n Q1 GN D R2 1k VR EF C SS 0 .1u F C C N TL 4 7u F VIN VC N TL VR EF GN D VO U T VOU T +1 .2 5 V/0.9 V -3 ~+3 A C OU T 4 70 uF GN D COUT : 470µF, ESR=25mΩ R1, R2 : 1kΩ, 1% Q1 : HPM2300 AC Note : Since R1 and R2 are very small, the voltage offset caused by the bias current of VREF can be ignore. 2. VOUT=1.4V Application VCNT L +5V VIN +2.8V R1 1k C IN 470 µ F R2 1k GND VRE F CSS 0.1 µ F C CNT L 47 µ F C O UT 470 µ F VIN VC N TL VR EF GN D VOU T VOUT +1.4V/ -3~+3 A GND  Copyright HIPAC Semiconductor, Inc. Rev. A.8 - Oct., 2003 5 www.hipacsemi.com HPL5331 Typical Characteristics Sourcing Current-Limit vs Junction Temperature 5.0 VCNTL=5V,VIN=2.5V Sinking Current-Limit vs Junction Temperature -2.0 VCNTL=5V,VIN=1.8V VCNTL=3.3V,VIN=1.8V Current-Limit, ILIM (A) 4.0 Current-Limit, ILIM (A) 4.5 VCNTL=3.3V,VIN=2.5V -2.5 -3.0 3.5 3.0 -3.5 -4.0 VCNTL=5V,VIN=2.5V VCNTL=3.3V,VIN=2.5V VCNTL=5V,VIN=1.8V VCNTL=3.3V,VIN=1.8V 2.5 -4.5 2.0 -50 -25 0 25 50 75 100 125 -5.0 -50 -25 0 25 50 75 100 125 Junction Temperature (°C) Junction Temperature (°C) VREF Bias Current vs Junction Temperature 0.40 0.6 VREF Shutdown Threshold vs Junction Temperature VREF Shutdown Threshold (V) VREF Bias Current, IVREF (µA) VREF=1.25V/0.9V 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0.00 -50 -25 0 25 50 75 100 125 0.5 VCNTL=5V 0.4 0.3 VCNTL=3.3V 0.2 0.1 -50 -25 0 25 50 75 100 125 Junction Temperature (°C) Junction Temperature (°C)  Copyright HIPAC Semiconductor, Inc. Rev. A.8 - Oct., 2003 6 www.hipacsemi.com HPL5331 Typical Characteristics (Cont.) VOUT Offset Voltage vs Junction Temperature 6 Quiescent VCNTL Current vs Junction Temperature 7.0 VOUT Offset Voltage, VOS (mV) 4 2 0 -2 -4 -6 -8 -10 -12 -14 -16 -50 VREF=1.25V/0.9V Quiescent VCNTL Current (mA) 6.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 IOUT=0A VCNTL=5V IOUT=-10mA VCNTL=3.3V IOUT=+10mA -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125 Junction Temperature (°C) Junction Temperature (°C) VREF Bias Current vs VREF Supply Voltage 22 VREF Bias Current, IVREF (µA) 20 18 16 14 12 10 8 6 4 2 0 0.0 TJ=25°C 0.2 0.4 0.6 0.8 1.0 1.2 1.4 VREF Supply Votage, VREF (V)  Copyright HIPAC Semiconductor, Inc. Rev. A.8 - Oct., 2003 7 www.hipacsemi.com HPL5331 Operating Waveforms 1. Load Transient Response : IOUT = +10mA -> +3A -> +10mA - VIN = 2.5V, VCNTL = 3.3V - VREF is 1.250V supplied by a regulator - COUT = 470µF/10V, ESR = 30mΩ - IOUT slew rate = ±3A/µS IOUT = +10mA -> +3A IOUT = +10mA -> +3A -> +10mA Load Regulation = -2.8mV IOUT = +3A -> +10mA VOUT IOUT VOUT VOUT +3A +10mA IOUT IOUT Ch1 : VOUT, 20mV/Div, DC, Offset = 1.250V Ax1 : IOUT, 1A/Div Time : 1µS/Div Ch1 : VOUT, 20mV/Div, DC, Offset = 1.250V Ax1 : IOUT, 1A/Div Time : 20µS/Div Ch1 : VOUT, 20mV/Div, DC, Offset = 1.250V Ax1 : IOUT, 1A/Div Time : 1µS/Div 2. Load Transient Response : IOUT = -10mA -> -3A -> -10mA - VIN = 2.5V, VCNTL = 3.3V - VREF is 1.250V supplied by a regulator - COUT = 470µF/10V, ESR = 30mΩ - IOUT slew rate = ±3A/µS IOUT = -10mA -> -3A VOUT IOUT = -10mA -> -3A -> -10mA Load Regulation = +6.2mV IOUT = -3A -> -10mA VOUT VOUT -10mA IOUT IOUT IOUT -3A Ch1 : VOUT, 20mV/Div, DC, Offset = 1.250V Ax1 : IOUT, 1A/Div Time : 1µS/Div Ch1 : VOUT, 20mV/Div, DC, Offset = 1.250V Ax1 : IOUT, 1A/Div Time : 20µS/Div 8 Ch1 : VOUT, 20mV/Div, DC, Offset = 1.250V Ax1 : IOUT, 1A/Div Time : 1µS/Div www.hipacsemi.com  Copyright HIPAC Semiconductor, Inc. Rev. A.8 - Oct., 2003 HPL5331 Operating Waveforms (Cont.) 3. Load Transient Response : IOUT = +3A -> -3A -> +3A - VIN = 2.5V, VCNTL = 3.3V - VREF is 1.250V supplied by a regulator - COUT = 470µF/10V, ESR = 30mΩ - IOUT slew rate = ±3A/µS IOUT = +3A -> -3A VOUT IOUT = +3A -> -3A -> +3A IOUT = -3A -> +3A VOUT VOUT IOUT +3A IOUT IOUT -3A Ch1 : VOUT, 50mV/Div, DC, Offset = 1.250V Ax1 : IOUT, 2A/Div Time : 1µS/Div Ch1 : VOUT, 50mV/Div, DC, Offset = 1.250V Ax1 : IOUT, 2A/Div Time : 20µS/Div Ch1 : VOUT, 50mV/Div, DC, Offset = 1.250V Ax1 : IOUT, 2A/Div Time : 1µS/Div 4. Short-Circuit Test - VIN = 2.5V, VCNTL = 3.3V VOUT is Shorted to GND IOUT IOUT VOUT is Shorted to VIN (2.5V) VOUT VOUT VOUT IOUT Ch1 : VOUT, 500mV/Div, DC, Ax1 : IOUT, 2A/Div Time : 5mS/Div Ch1 : VOUT, 500mV/Div, DC, Ax1 : IOUT, 2A/Div Time : 5mS/Div  Copyright HIPAC Semiconductor, Inc. Rev. A.8 - Oct., 2003 9 www.hipacsemi.com HPL5331 Application Information General The HPL5331 is a linear regulator and is capable of sourcing or sinking current up to 3A. The HPL5331 has fast transient response, accurate output voltage (small voltage offset, load regulation), active-low shutdown control and fault protections (current-limit, thermal shutdown). The HPL5331 is available in several packages to meet different of power dissipation in requirement various applications. Output Voltage Regulation The output voltage at VOUT pin tracks the reference voltage applied at VREF pin. Two internal NPN pass transistors controlled by separate high bandwidth error amplifiers regulate the output voltage by sourcing current from VIN pin or sinking current to GND pin. The base currents of the pass transistors are provided by VCNTL pin. An internal kelvin sensing scheme use at the VOUT pin for perfect load regulation at various load current. To prevent the two pass transistors from shoot-through, a small voltage offset is created between the positive inputs of the two error amplifiers. This results in higher output voltage while the regulator sinks light or heavy load current. Since the HPL5331 exhibits very fast load transient response, lesser amount of capacitors can be use. In addition, capacitors with high ESR can also be use. Shutdown and Soft-Start The VREF pin is a dual-function input pin, acting as reference input and shutdown control input. Applying and holding a voltage below 0.35V(typ.) to VREF pin shuts down the output of the regulator. An NPN transistor or N-channel MOSFET is used to pull down the VREF while applying a “high” signal to turn on the transistor. When shutdown function is active, the two pass transistors are turned off and the impedance of the VOUT is about 10MΩ (typ.), sourcing or sinking no current. When release the VREF pin, the current through the resistor divider charges the softstart capacitor to initiate a soft-start cycle. The output voltage tracks the rising VREF. The soft start process limits the input surge current. Thermal Shutdown An thermal shutdown circuit limits the junction temperature of the HPL5331. When the junction temperature exceeds TJ= +150oC, a thermal sensor turns off both pass transistors, allowing the device to cool down. The regulator starts to regulate again after the junction temperature reduces by 40oC, resulting in a pulsed output during continuous thermal overload conditions. The thermal limit designed with a 40oC hysteresis lowers the average TJ during continuous thermal overload conditions, extend life time of HPL5331. Current Limit The HPL5331 monitors sourcing and sinking current, and limits the maximum output current to prevent damages during overload or short-circuit, To increase the input voltage of VIN or VCNTL will get higher current-limit points.  Copyright HIPAC Semiconductor, Inc. Rev. A.8 - Oct., 2003 10 www.hipacsemi.com HPL5331 Application Information Power Inputs Input power sequence are not required for VIN and VCNTL. However, do not apply a voltage to VOUT when there is not voltage VCNTL. This is due to the internal parasitic diodes between VOUT to VIN and VOUT to VCNTL which will be forward bias. The HPL5331 can source few current or sinks current up to 3A for load when the input Voltage at VIN is not present. Reference Voltage A reference voltage is applied at the VREF pin by a resistor divider between VIN and GND pins. Normally the bias current of the VREF pin flows out of the IC and is about 150nA(typ.), creating voltage offset at the resistor divider and affecting the output voltage accuracy. The recommended resistor is 2KV, VMM > 200V 10ms, 1tr > 100mA Carrier Tape t P P1 D Po E F W Bo Ao Ko D1 T2 J C A B T1  Copyright HIPAC Semiconductor, Inc. Rev. A.8 - Oct., 2003 19 www.hipacsemi.com HPL5331 Carrier Tape Application SOP- 8 SOP-8-P Application A 330 ± 1 F 5.5± 1 A 330 ±3 TO-252 F 7.5 ± 0.1 Application A 380±3 TO-263 F 11.5 ± 0.1 B 62 +1.5 D C 12.75+ 0.15 D1 J 2 ± 0.5 Po 4.0 ± 0.1 J 2 ± 0.5 Po 4.0 ± 0.1 J 2 ± 0.5 Po 4.0 ± 0.1 T1 12.4 ± 0.2 P1 2.0 ± 0.1 T1 16.4 + 0.3 -0.2 P1 2.0 ± 0.1 T1 24 ± 4 P1 2.0 ± 0.1 T2 2 ± 0.2 Ao 6.4 ± 0.1 T2 2.5± 0.5 Ao 6.8 ± 0.1 T2 2± 0.3 Ao 10.8 ± 0.1 W 12± 0. 3 Bo 5.2± 0. 1 W 16+ 0.3 - 0.1 Bo 10.4± 0.1 W 24 + 0.3 - 0.1 Bo 16.1± 0.1 P 8± 0.1 Ko 2.1± 0.1 P 8 ± 0.1 Ko 2.5± 0.1 P 16 ± 0.1 Ko 5.2± 0.1 E 1.75±0.1 t 0.3±0.013 E 1.75± 0.1 t 0.3±0.05 E 1.75± 0.1 t 0.35±0.013 1.55 +0.1 1.55+ 0.25 B 100 ± 2 D 1.5 +0.1 B 80 ± 2 D 1.5 +0.1 C 13 ± 0. 5 D1 1.5± 0.25 C 13 ± 0. 5 D1 1.5± 0.25 (mm) Cover Tape Dimensions Application SOP- 8 / SOP-8-P TO- 252 TO- 263 Carrier Width 12 16 24 Cover Tape Width 9.3 13.3 21.3 Devices Per Reel 2500 2500 1000 CONTACT HIPAC Semiconductor, Inc. 2540 North First Street, Suite 308 San Jose, CA 95131-1016 U.S.A. Tel: 1-408-943-0808 Fax: 1-408-943-0878 E-Mail: info@hipacsemi.com  Copyright HIPAC Semiconductor, Inc. Rev. A.8 - Oct., 2003 20 www.hipacsemi.com