LD1010DA

PWRLITE LD1010DA High Performance N-Channel POWERJFETTM with PN Diode Features Superior gate charge x Rdson product (FOM) Trench Power JFET with low threshold voltage Vth. Device fully “ON” with Vgs = 0.7V Optimum for “Low Side” Buck Converters Excellent for high frequency dc/dc converters Optimized for Secondary Rectification in isolated DC-DC Low Rg and low Cds for high speed switching Description The Power JFET transistor from Lovoltech is a device that presents a Low Rdson allowing for improved efficiencies in DCDC switching applications. The device is designed with a low threshold such that drivers can operate at 5V, which reduces the driver power dissipation and increases the overall efficiency. Lower threshold produces faster turn-on/turn-off, which minimizes the required dead time. A PN Diode is added for applications where a freewheeling diode is required. This product has tin plated leads. Applications DC-DC Converters Synchronous Rectifiers PC Motherboard Converters Step-down power supplies Brick Modules VRM Modules DPAK Lead-free Pin Assignments D G D G S S N – C h a nn el Pow er J F E T with P N D io d e Pin Definitions Pin Number 1 2 3 Pin Name Gate Drain Source Pin Function Description Gate. Transistor Gate Drain. Transistor Drain Source. Transistor Source VDS (V) 24V Product Summary Rdson (Ω) 0.0045 ID (A) 501 Absolute Maximum Ratings Parameter Drain-Source Voltage Gate-Source Voltage Gate-Drain Voltage Continuous Drain Current Pulsed Drain Current Single Pulse Drain-to-Source Avalanche Energy at 25°C (VDD= 6VDC, IL=60APK, L=0.3mH, RG=100 Ω) Junction Temperature Storage Temperature Lead Soldering Temperature, 10 seconds Power Dissipation (Derated at 25°C) Symbol VDS VGS VGD ID ID EAS TJ TSTG T PD Ratings 24 -12 -28 501 100 220 -55 to 150°C -65 to 150°C 260°C 80 Units V V V A A mJ °C °C °C W LD1010DA Rev 1.03 – 03-05 Thermal Resistance Symbol RΘJA RΘJC Parameter Thermal Resistance Junction-to-Ambient Thermal Resistance Junction-to-Case DPAK Ratings 80 1.56 Units °C/W °C/W Electrical Specifications (TA = +25°C, unless otherwise noted.) The φ denotes a specification which apply over the full operating temperature range. Symbol Parameter Conditions Min. Static BVDSX Breakdown Voltage ID = 0.5 mA 24 Drain to Source VGS= -4 V BVGDO Breakdown Voltage IG = -50µA Gate to Drain BVGSO Breakdown Voltage IG = -50µA Gate to Source RDS(ON) Drain to Source On IG = 40 mA, ID=10A Resistance2 IG = 10 mA, ID=10A IG = 5 mA, ID=10A VGS(TH) Gate Threshold Voltage VDS=0.1 V, ID=250µA TCVGSTH Temperature Coefficient of VDS=0.1 V, ID=250µA Gate Threshold Voltage Dynamic QGsync Total Gate Charge Sync JFET ∆VDrive =5V,VDS=0.1V QG Total Gate Charge ∆VDrive =5V, ID=10A,VDS=15V QGD Gate to Drain Charge VDS=13.5V to VDS=1.5V QGS Gate to Source Charge VGS =-4.5V to VDS=13.5V QSW Switching Charge VGS =-2V to VDS=1.5V RG Gate Resistance TD(ON) Turn-on Delay Time VDD=15V, ID=10A TR Rise Time VDrive = 5 V TD(OFF) Turn-off Delay Resistive Load TF Fall Time CISS Input Capacitance COSS Output Capacitance VDS=10V, VGS= -5 V, 1MHz. CGS Gate-Source Capacitance CGD Gate-Drain Capacitance CDS Drain-Source Capacitance PN Diode IR Reverse Leakage VR=20V, Vgs = -4V VF Forward Voltage IF = 1 A VF Forward Voltage IF = 10 A VF Forward Voltage IF = 20 A Qrr Reverse Recovery Charge Is = 10 A di/dt = 100A/us, Trr Reverse Recovery Time Is = 10 A di/dt = 100A/us, Notes: 1. Current is limited by bondwire; with an Rthjc = 1.56 oC/W the chip is able to carry 102A. 2. Pulse width