MSP3430

PRELIMINARY DATA SHEET MICRONAS MSP 34x0G Multistandard Sound Processor Family Edition March 5, 2001 6251-476-4PD MICRONAS MSP 34x0G Contents Page 5 6 6 7 8 9 9 9 9 10 10 10 12 12 12 12 12 12 12 13 13 13 13 13 13 13 14 14 14 14 15 15 15 16 16 17 17 17 17 17 17 17 17 21 22 Section 1. 1.1. 1.2. 1.3. 2. 2.1. 2.2. 2.2.1. 2.2.2. 2.2.3. 2.2.4. 2.2.5. 2.3. 2.4. 2.5. 2.5.1. 2.5.2. 2.5.3. 2.5.4. 2.5.5. 2.5.5.1. 2.5.5.2. 2.5.5.3. 2.6. 2.6.1. 2.6.2. 2.7. 2.8. 2.9. 2.10. 3. 3.1. 3.1.1. 3.1.2. 3.1.3. 3.1.4. 3.1.4.1. 3.1.4.2. 3.1.4.3. 3.1.4.4. 3.2. 3.3. 3.3.1. 3.3.2. 3.3.2.1. Title PRELIMINARY DATA SHEET Introduction Features of the MSP 34x0G Family and Differences to MSPD MSP 34x0G Version List MSP 34x0G Versions and their Application Fields Functional Description Architecture of the MSP 34x0G Family Sound IF Processing Analog Sound IF Input Demodulator: Standards and Features Preprocessing of Demodulator Signals Automatic Sound Select Manual Mode Preprocessing for SCART and I²S Input Signals Source Selection and Output Channel Matrix Audio Baseband Processing Automatic Volume Correction (AVC) Loudspeaker and Headphone Outputs Subwoofer Output Quasi-Peak Detector Micronas Dynamic Bass (MDB) Dynamic Amplification Adding Harmonics MDB Parameters SCART Signal Routing SCART DSP In and SCART Out Select Stand-by Mode I2S Bus Interface ADR Bus Interface Digital Control I/O Pins and Status Change Indication Clock PLL Oscillator and Crystal Specifications Control Interface I2C Bus Interface Internal Hardware Error Handling Description of CONTROL Register Protocol Description Proposals for General MSP 34x0G I2C Telegrams Symbols Write Telegrams Read Telegrams Examples Start-Up Sequence: Power-Up and I2C-Controlling MSP 34x0G Programming Interface User Registers Overview Description of User Registers STANDARD SELECT Register 2 Micronas PRELIMINARY DATA SHEET MSP 34x0G Contents, continued Page 22 22 24 26 27 40 41 41 41 41 41 42 42 42 44 44 46 49 52 56 58 58 59 59 59 60 61 62 62 63 64 65 66 68 69 69 70 73 77 77 78 79 79 80 80 Section 3.3.2.2. 3.3.2.3. 3.3.2.4. 3.3.2.5. 3.3.2.6. 3.3.2.7. 3.4. 3.5. 3.5.1. 3.5.2. 3.5.3. 3.5.4. 3.5.5. 3.5.6. 4. 4.1. 4.2. 4.3. 4.4. 4.5. 4.6. 4.6.1. 4.6.2. 4.6.2.1. 4.6.2.2. 4.6.2.3. 4.6.2.4. 4.6.3. 4.6.3.1. 4.6.3.2. 4.6.3.3. 4.6.3.4. 4.6.3.5. 4.6.3.6. 4.6.3.7. 4.6.3.8. 4.6.3.9. 4.6.3.10. 5. 5.1. 5.2. 5.3. 5.4. 5.5. 5.6. Title Refresh of STANDARD SELECT Register STANDARD RESULT Register Write Registers on I2C Subaddress 10hex Read Registers on I2C Subaddress 11hex Write Registers on I2C Subaddress 12hex Read Registers on I2C Subaddress 13hex Programming Tips Examples of Minimum Initialization Codes B/G-FM (A2 or NICAM) BTSC-Stereo BTSC-SAP with SAP at Loudspeaker Channel FM-Stereo Radio Automatic Standard Detection Software Flow for Interrupt driven STATUS Check Specifications Outline Dimensions Pin Connections and Short Descriptions Pin Descriptions Pin Configurations Pin Circuits Electrical Characteristics Absolute Maximum Ratings Recommended Operating Conditions General Recommended Operating Conditions Analog Input and Output Recommendations Recommendations for Analog Sound IF Input Signal Crystal Recommendations Characteristics General Characteristics Digital Inputs, Digital Outputs Reset Input and Power-Up I2C-Bus Characteristics I2S-Bus Characteristics Analog Baseband Inputs and Outputs, AGNDC Sound IF Inputs Power Supply Rejection Analog Performance Sound Standard Dependent Characteristics Appendix A: Overview of TV-Sound Standards NICAM 728 A2-Systems BTSC-Sound System Japanese FM Stereo System (EIA-J) FM Satellite Sound FM-Stereo Radio Micronas 3 MSP 34x0G Contents, continued Page 81 81 82 83 83 83 83 85 85 86 87 89 89 91 91 91 91 92 92 92 92 93 93 93 93 93 94 94 94 94 94 94 95 95 95 97 97 97 98 99 100 Section 6. 6.1. 6.2. 6.3. 6.3.1. 6.3.1.1. 6.3.1.2. 6.3.2. 6.3.3. 6.3.4. 6.3.5. 6.3.6. 6.3.7. 6.4. 6.4.1. 6.4.2. 6.4.3. 6.4.4. 6.4.5. 6.4.6. 6.4.7. 6.5. 6.5.1. 6.5.2. 6.5.3. 6.5.4. 6.5.5. 6.5.6. 6.5.7. 6.6. 6.6.1. 6.6.2. 6.7. 6.7.1. 6.7.2. 6.8. 6.9. 6.10. 7. 8. 9. Title PRELIMINARY DATA SHEET Appendix B: Manual/Compatibility Mode Demodulator Write and Read Registers for Manual/Compatibility Mode DSP Write and Read Registers for Manual/Compatibility Mode Manual/Compatibility Mode: Description of Demodulator Write Registers Automatic Switching between NICAM and Analog Sound Function in Automatic Sound Select Mode Function in Manual Mode A2 Threshold Carrier-Mute Threshold Register AD_CV Register MODE_REG FIR-Parameter, Registers FIR1 and FIR2 DCO-Registers Manual/Compatibility Mode: Description of Demodulator Read Registers NICAM Mode Control/Additional Data Bits Register Additional Data Bits Register CIB Bits Register NICAM Error Rate Register PLL_CAPS Readback Register AGC_GAIN Readback Register Automatic Search Function for FM-Carrier Detection in Satellite Mode Manual/Compatibility Mode: Description of DSP Write Registers Additional Channel Matrix Modes Volume Modes of SCART1/2 Outputs FM Fixed Deemphasis FM Adaptive Deemphasis NICAM Deemphasis Identification Mode for A2 Stereo Systems FM DC Notch Manual/Compatibility Mode: Description of DSP Read Registers Stereo Detection Register for A2 Stereo Systems DC Level Register Demodulator Source Channels in Manual Mode Terrestric Sound Standards SAT Sound Standards Exclusions of Audio Baseband Features Phase Relationship of Analog Outputs Compatibility Restrictions to MSP 34x0D Appendix D: MSP 34x0G Version History Appendix E: Application Circuit Data Sheet History License Notice: “Dolby Pro Logic” is a trademark of Dolby Laboratories. Supply of this implementation of Dolby Technology does not convey a license nor imply a right under any patent, or any other industrial or intellectual property right of Dolby Laboratories, to use this implementation in any finished end-user or ready-to-use final product. Companies planning to use this implementation in products must obtain a license from Dolby Laboratories Licensing Corporation before designing such products. 4 Micronas PRELIMINARY DATA SHEET MSP 34x0G Current ICs have to perform adjustment procedures in order to achieve good stereo separation for BTSC and EIA-J. The MSP 34x0G has optimum stereo performance without any adjustments. All MSP 34xxG versions are pin compatible to the MSP 34xxD. Only minor modifications are necessary to adapt a MSP 34xxD controlling software to the MSP 34xxG. The MSP 34x0G further simplifies controlling software. Standard selection requires a single I2C transmission only. The MSP 34x0G has built-in automatic functions: The IC is able to detect the actual sound standard automatically (Automatic Standard Detection). Furthermore, pilot levels and identification signals can be evaluated internally with subsequent switching between mono/ stereo/bilingual; no I2C interaction is necessary (Automatic Sound Selection). The MSP 34x0G can handle very high FM deviations even in conjunction with NICAM processing. This is especially important for the introduction of NICAM in China. The ICs are produced in submicron CMOS technology. The MSP 34x0G is available in the following packages: PLCC68 (not intended for new design), PSDIP64, PSDIP52, PQFP80, and PLQFP64. Multistandard Sound Processor Family Release Note: Revision bars indicate significant changes to the previous edition. The hardware and software description in this document is valid for the MSP 34x0G version B8 and following versions. 1. Introduction The MSP 34x0G family of single-chip Multistandard Sound Processors covers the sound processing of all analog TV-Standards worldwide, as well as the NICAM digital sound standards. The full TV sound processing, starting with analog sound IF signal-in, down to processed analog AF-out, is performed on a single chip. Figure 1–1 shows a simplified functional block diagram of the MSP 34x0G. This new generation of TV sound processing ICs now includes versions for processing the multichannel television sound (MTS) signal conforming to the standard recommended by the Broadcast Television Systems Committee (BTSC). The DBX noise reduction, or alternatively, Micronas Noise Reduction (MNR) is performed alignment free. Other processed standards are the Japanese FM-FM multiplex standard (EIA-J) and the FM Stereo Radio standard. Sound IF1 ADC Sound IF2 Demodulator Preprocessing Loudspeaker Sound Processing DAC Loudspeaker Subwoofer Source Select I2S1 I2S2 SCART1 Headphone Sound Processing DAC Headphone Prescale I2S DAC SCART2 SCART3 SCART4 MONO SCART DSP Input Select SCART1 ADC Prescale DAC SCART Output Select SCART2 Fig. 1–1: Simplified functional block diagram of the MSP 34x0G Micronas 5 MSP 34x0G 1.1. Features of the MSP 34x0G Family and Differences to MSPD Feature (New features not available for MSPD are shaded gray.) 3400 X X X X X X X X X X X X X X X X X 3410 X X X X X X X X X X X X X X X X X X X X X X X PRELIMINARY DATA SHEET 3420 X X X X X X X X X X X X X X X X 3440 X X X X X X X X X X X X X X X X 3450 X X X X X X X X X X X X X X X X X X X X X 3460 X X Standard Selection with single I2C transmission Automatic Standard Detection of terrestrial TV standards/Automatic Carrier Mute function Automatic Sound Selection (mono/stereo/bilingual), new registers MODUS, STATUS Two selectable sound IF (SIF) inputs Automatic Carrier Mute function Interrupt output programmable (indicating status change) Loudspeaker / Headphone channel with volume, balance, bass, treble, loudness Loudspeaker channel with MDB (Micronas Dynamic Bass) AVC: Automatic Volume Correction Subwoofer output with programmable low-pass and complementary high-pass filter 5-band graphic equalizer for loudspeaker channel Spatial effect for loudspeaker channel Four Stereo SCART (line) inputs, one Mono input; two Stereo SCART outputs Complete SCART in/out switching matrix Two I2S inputs; one I2S output All analog Mono sound carriers including AM-SECAM L All analog FM-Stereo A2 and satellite standards Simultaneous demodulation of (very) high-deviation FM-Mono and NICAM Adaptive deemphasis for satellite (Wegener-Panda, acc. to ASTRA specification) ASTRA Digital Radio (ADR) together with DRP 3510A All NICAM standards Demodulation of the BTSC multiplex signal and the SAP channel Alignment free digital DBX noise reduction for BTSC Stereo and SAP Alignment free digital Micronas Noise Reduction (MNR) for BTSC Stereo and SAP BTSC stereo separation (MSP 3420/40G also EIA-J) significantly better than spec. SAP and stereo detection for BTSC system Korean FM-Stereo A2 standard Alignment-free Japanese standard EIA-J Demodulation of the FM-Radio multiplex signal X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 1.2. MSP 34x0G Version List Version MSP 3400G MSP 3410G MSP 3420G MSP 3440G MSP 3450G MSP 3460G Status available available available available available not confirmed Description FM Stereo (A2) Version NICAM and FM Stereo (A2) Version NTSC Version (A2 Korea, BTSC with Micronas Noise Reduction (MNR), Japanese EIA-J system) NTSC Version (A2 Korea, BTSC with DBX noise reduction, Japanese EIA-J system) Global Version (all sound standards) Global Mono Version (all sound standards) 6 Micronas PRELIMINARY DATA SHEET MSP 34x0G 1.3. MSP 34x0G Versions and their Application Fields Table 1–1 provides an overview of TV sound standards that can be processed by the MSP 34x0G family. In addition, the MSP 34x0G is able to handle the FMRadio standard. With the MSP 34x0G, a complete multimedia receiver covering all TV sound standards together with terrestrial/cable and satellite radio sound can be built; even ASTRA Digital Radio can be processed (with a DRP 3510A coprocessor). Table 1–1: TV Stereo Sound Standards covered by the MSP 34x0G IC Family (details see Appendix A) MSP Version 3400 TVSystem B/G 5.5/5.85 L I 6.5/5.85 6.0/6.552 6.5/6.2578125 3400 3410 6.5/6.7421875 D/K 6.5/5.7421875 3450 6.5/5.85 6.5 7.02/7.2 7.38/7.56 etc. 4.5/4.724212 3420, 3440 M/N 4.5 4.5 FM-Radio 3460 10.7 FM-Stereo (A2, D/K3) FM-Mono/NICAM (D/K, NICAM) FM-Mono FM-Stereo ASTRA Digital Radio (ADR) with DRP 3510A FM-Stereo (A2) FM-FM (EIA-J) BTSC-Stereo + SAP FM-Stereo Radio SECAM-East PAL Poland China, Hungary FM-Mono/NICAM AM-Mono/NICAM FM-Mono/NICAM FM-Stereo (A2, D/K1) FM-Stereo (A2, D/K2) PAL SECAM-L PAL SECAM-East PAL Scandinavia, Spain France UK, Hong Kong Slovak. Rep. currently no broadcast Position of Sound Carrier /MHz 5.5/5.7421875 Sound Modulation FM-Stereo (A2) Color System PAL Broadcast e.g. in: Germany 3400 Satellite PAL Europe Sat. ASTRA NTSC NTSC NTSC, PAL Korea Japan USA, Argentina USA, Europe all Standards as above but Mono demodulation only. 33 34 39 MHz 4.5 9 MHz SAW Filter Tuner Sound IF Mixer Loudspeaker 1 Mono Vision Demodulator SCART1 2 Subwoofer MSP 34x0G 2 Headphone 2 2 2 Composite Video SCART Inputs SCART2 SCART3 SCART4 2 SCART1 SCART2 SCART Outputs I2S1 ADR I2S2 Dolby Pro Logic Processor DPL 351xA ADR Decoder DRP 3510A Fig. 1–2: Typical MSP 34x0G application Micronas 7 Source Select SCART DSP Input Select (13hex) SC1_IN_L SC1_IN_R SC2_IN_L SC2_IN_R SC3_IN_L SC3_IN_R SC4_IN_L SC4_IN_R MONO_IN (41hex) (40hex) SCART Output Select 8 ANA_IN1+ AGC A D ANA_IN2+ DEMODULATOR (incl. Carrier Mute) Standard Selection Deemphasis: 50/75 µs, J17 DBX/MNR Panda1 FM/AM Prescale (0Ehex) 2. Functional Description MSP 34x0G Automatic Sound Select FM/AM 0 Stereo or A/B 1 3 Loudspeaker Channel Matrix (08hex) AVC (29hex) Bass/ Treble or Equalize (02hex) (03hex) Σ Loudness (04hex) Complementary Spatial Balance Highpass Effects 0.5 (2Dhex) (05hex) (01hex) D Volume DACM_L DACM_R MDB (00hex) ADR-Bus Interface Decoded Standards: − NICAM − A2 − AM − BTSC − EIA-J − SAT − FM-Radio NICAM Deemphasis J17 Prescale (10hex) Stereo or A Lowpass Beeper (14hex) (2Dhex) Level Adjust (2Chex) A DACM_SUB Stereo or B 4 Standard and Sound Detection I2C Read Register I S1 I2S_DA_IN1 I2S Interface Prescale (16hex) 2 5 Headphone Channel Matrix (09hex) Volume Bass/ Treble (31/32 hex) Σ D A Loudness Balance DACA_L (33hex) (30hex) (06hex) DACA_R I S2 I2S_DA_IN2 I2S Interface Prescale (12hex) 2 6 I2S Channel Matrix (0Bhex) I2S Interface I2S_DA_OUT Quasi-Peak Channel Matrix (0Chex) Quasi-Peak Detector I2C Read Register (19hex) (1Ahex) A D SCART 2 Prescale (0Dhex) SCART1 Channel Matrix (0Ahex) Volume D SCART1_L/R A (07hex) SCART2 Channel Matrix Volume D SCART2_L/R A SC1_OUT_L SC1_OUT_R PRELIMINARY DATA SHEET SC2_OUT_L SC2_OUT_R Micronas (13hex) Fig. 2–1: Signal flow block diagram of the MSP 34x0G (input and output names correspond to pin names) PRELIMINARY DATA SHEET MSP 34x0G BTSC-Mono + SAP: Detection and FM demodulation of the aural carrier resulting in the MTS/MPX signal. Detection and evaluation of the pilot carrier, detection and FM demodulation of the SAP subcarrier. Processing of DBX noise reduction or Micronas Noise Reduction (MNR). Japan Stereo: Detection and FM demodulation of the aural carrier resulting in the MPX signal. Demodulation and evaluation of the identification signal and FM demodulation of the (L−R)-carrier. FM-Satellite Sound: Demodulation of one or two FM carriers. Processing of high-deviation mono or narrow bandwidth mono, stereo, or bilingual satellite sound according to the ASTRA specification. FM-Stereo-Radio: Detection and FM demodulation of the aural carrier resulting in the MPX signal. Detection and evaluation of the pilot carrier and AM demodulation of the (L−R)-carrier. The demodulator blocks of all MSP 34x0G versions have identical user interfaces. Even completely different systems like the BTSC and NICAM systems are controlled the same way. Standards are selected by means of MSP Standard Codes. Automatic processes handle standard detection and identification without controller interaction. The key features of the MSP 34x0G demodulator blocks are: Standard Selection: The controlling of the demodulator is minimized: All parameters, such as tuning frequencies or filter bandwidth, are adjusted automatically by transmitting one single value to the STANDARD SELECT register. For all standards, specific MSP standard codes are defined. Automatic Standard Detection: If the TV sound standard is unknown, the MSP 34x0G can automatically detect the actual standard, switch to that standard, and respond the actual MSP standard code. Automatic Carrier Mute: To prevent noise effects or FM identification problems in the absence of an FM carrier, the MSP 34x0G offers a configurable carrier mute feature, which is activated automatically if the TV sound standard is selected by means of the STANDARD SELECT register. If no FM carrier is detected at one of the two MSP demodulator channels, the corresponding demodulator output is muted. This is indicated in the STATUS register. 2.1. Architecture of the MSP 34x0G Family Fig. 2–1 on page 8 shows a simplified block diagram of the IC. The block diagram contains all features of the MSP 3450G. Other members of the MSP 34x0G family do not have the complete set of features: The demodulator handles only a subset of the standards presented in the demodulator block; NICAM processing is only possible in the MSP 3410G and MSP 3450G. 2.2. Sound IF Processing 2.2.1. Analog Sound IF Input The input pins ANA_IN1+, ANA_IN2+, and ANA_IN− offer the possibility to connect two different sound IF (SIF) sources to the MSP 34x0G. The analog-to-digital conversion of the preselected sound IF signal is done by an A/D-converter. An analog automatic gain circuit (AGC) allows a wide range of input levels. The highpass filters formed by the coupling capacitors at pins ANA_IN1+ and ANA_IN2+ see Section 8. “Appendix E: Application Circuit” on page 99 are sufficient in most cases to suppress video components. Some combinations of SAW filters and sound IF mixer ICs, however, show large picture components on their outputs. In this case, further filtering is recommended. 2.2.2. Demodulator: Standards and Features The MSP 34x0G is able to demodulate all TV-sound standards worldwide including the digital NICAM system. Depending on the MSP 34x0G version, the following demodulation modes can be performed: A2 Systems: Detection and demodulation of two separate FM carriers (FM1 and FM2), demodulation and evaluation of the identification signal of carrier FM2. NICAM Systems: Demodulation and decoding of the NICAM carrier, detection and demodulation of the analog (FM or AM) carrier. For D/K-NICAM, the FM carrier may have a maximum deviation of 384 kHz. Very high deviation FM-Mono: Detection and robust demodulation of one FM carrier with a maximum deviation of 540 kHz. BTSC-Stereo: Detection and FM demodulation of the aural carrier resulting in the MTS/MPX signal. Detection and evaluation of the pilot carrier, AM demodulation of the (L−R)-carrier and detection of the SAP subcarrier. Processing of DBX noise reduction or Micronas Noise Reduction (MNR). Micronas 9 MSP 34x0G 2.2.3. Preprocessing of Demodulator Signals The NICAM signals must be processed by a deemphasis filter and adjusted in level. The analog demodulated signals must be processed by a deemphasis filter, adjusted in level, and dematrixed. The correct deemphasis filters are already selected by setting the standard in the STANDARD SELECT register. The level adjustment has to be done by means of the FM/ AM and NICAM prescale registers. The necessary dematrix function depends on the selected sound standard and the actual broadcasted sound mode (mono, stereo, or bilingual). It can be manually set by the FM Matrix Mode register or automatically by the Automatic Sound Selection. PRELIMINARY DATA SHEET – “Stereo or A” channel: Analog or digital mono sound, stereo if available. In case of bilingual broadcast, it contains language A (on left and right). – “Stereo or B” channel: Analog or digital mono sound, stereo if available. In case of bilingual broadcast, it contains language B (on left and right). Fig. 2–2 and Table 2–2 show the source channel assignment of the demodulated signals in case of Automatic Sound Select mode for all sound standards. Note: The analog primary input channel contains the signal of the mono FM/AM carrier or the L+R signal of the MPX carrier. The secondary input channel contains the signal of the 2nd FM carrier, the L-R signal of the MPX carrier, or the SAP signal. 2.2.4. Automatic Sound Select In the Automatic Sound Select mode, the dematrix function is automatically selected based on the identification information in the STATUS register. No I2C interaction is necessary when the broadcasted sound mode changes (e.g. from mono to stereo). The demodulator supports the identification check by switching between mono-compatible standards (standards that have the same FM-Mono carrier) automatically and non-audible. If B/G-FM or B/G-NICAM is selected, the MSP will switch between these standards. The same action is performed for the standards: D/K1-FM, D/K2-FM, D/K3-FM and D/K-NICAM. Switching is only done in the absence of any stereo or bilingual identification. If identification is found, the MSP keeps the detected standard. In case of high bit-error rates, the MSP 34x0G automatically falls back from digital NICAM sound to analog FM or AM mono. Table 2–1 summarizes all actions that take place when Automatic Sound Select is switched on. primary channel primary channel secondary channel FM/AM Prescale FM/AM 0 LS Ch. Matrix Source Select NICAM A NICAM Automatic Sound Select Stereo or A/B 1 Stereo or A 3 Output-Ch. matrices must be set once to stereo. NICAM B Prescale Stereo or B 4 Fig. 2–2: Source channel assignment of demodulated signals in Automatic Sound Select Mode 2.2.5. Manual Mode Fig. 2–3 shows the source channel assignment of demodulated signals in case of manual mode. If manual mode is required, more information can be found in Section 6.7. “Demodulator Source Channels in Manual Mode” on page 95. FM/AM FM-Matrix FM/AM 0 LS Ch. Matrix Source Select To provide more flexibility, the Automatic Sound Select block prepares four different source channels of demodulated sound (Fig. 2–2). By choosing one of the four demodulator channels, the preferred sound mode can be selected for each of the output channels (loudspeaker, headphone, etc.). This is done by means of the Source Select registers. The following source channels of demodulated sound are defined: – “FM/AM” channel: Analog mono sound, stereo if available. In case of NICAM, analog mono only (FM or AM mono). – “Stereo or A/B” channel: Analog or digital mono sound, stereo if available. In case of bilingual broadcast, it contains both languages A (left) and B (right). secondary channel Prescale NICAM A NICAM NICAM (Stereo or A/B) 1 Output-Ch. matrices must be set according to the standard. NICAM B Prescale Fig. 2–3: Source channel assignment of demodulated signals in Manual Mode 2.3. Preprocessing for SCART and I²S Input Signals The SCART and I2S inputs need only be adjusted in level by means of the SCART and I2S prescale registers. 10 Micronas PRELIMINARY DATA SHEET MSP 34x0G Table 2–1: Performed actions of the Automatic Sound Selection Selected TV Sound Standard B/G-FM, D/K-FM, M-Korea, and M-Japan B/G-NICAM, L-NICAM, I-NICAM, D/K-NICAM Performed Actions Evaluation of the identification signal and automatic switching to mono, stereo, or bilingual. Preparing four demodulator source channels according to Table 2–2. Evaluation of NICAM-C-bits and automatic switching to mono, stereo, or bilingual. Preparing four demodulator source channels according to Table 2–2. In case of bad or no NICAM reception, the MSP switches automatically to FM/AM mono and switches back to NICAM if possible. A hysteresis prevents periodical switching. B/G-FM, B/G-NICAM or D/K1-FM, D/K2-FM, D/K3-FM, and D/K-NICAM Automatic searching for stereo/bilingual-identification in case of mono transmission. Automatic and nonaudible changes between Dual-FM and FM-NICAM standards while listening to the basic FM-mono sound carrier. Example: If starting with B/G-FM-Stereo, there will be a periodical alternation to B/G-NICAM in the absence of FM-Stereo/Bilingual or NICAM-identification. Once an identification is detected, the MSP keeps the corresponding standard. Evaluation of the pilot signal and automatic switching to mono or stereo. Preparing four demodulator source channels according to Table 2–2. Detection of the SAP carrier. In the absence of SAP, the MSP switches to BTSC-stereo if available. If SAP is detected, the MSP switches automatically to SAP (see Table 2–2). BTSC-STEREO, FM Radio M-BTSC-SAP Table 2–2: Sound modes for the demodulator source channels with Automatic Sound Select Source Channels in Automatic Sound Select Mode Broadcasted Sound Standard M-Korea B/G-FM D/K-FM M-Japan Selected MSP Standard Code3) 02 03, 081) 04, 05, 07, 0B1) 30 Broadcasted Sound Mode MONO STEREO BILINGUAL: Languages A and B B/G-NICAM L-NICAM I-NICAM D/K-NICAM D/K-NICAM (with high deviation FM) FM/AM (source select: 0) Stereo or A/B (source select: 1) Stereo or A (source select: 3) Stereo or B (source select: 4) Mono Stereo Right = B analog Mono analog Mono analog Mono analog Mono Mono Stereo Mono Stereo Left = Mono Right = SAP Left = Mono Right = SAP Mono Stereo Mono Stereo Left = A Right = B analog Mono NICAM Mono NICAM Stereo Left = NICAM A Right = NICAM B Mono Stereo Mono Stereo Left = Mono Right = SAP Left = Mono Right = SAP Mono Stereo Mono Stereo A analog Mono NICAM Mono NICAM Stereo NICAM A Mono Stereo Mono Stereo Mono Mono Mono Stereo Mono Stereo B analog Mono NICAM Mono NICAM Stereo NICAM B Mono Stereo Mono Stereo SAP SAP Mono Stereo 08, 032) 09 0A 0B, 042), 052) 0C, 0D NICAM not available or error rate too high MONO STEREO BILINGUAL: Languages A and B 20, 21 MONO STEREO 20 BTSC 21 MONO + SAP STEREO + SAP MONO + SAP STEREO + SAP FM Radio 40 MONO STEREO 1) 2) 3) The Automatic Sound Select process will automatically switch to the mono compatible analog standard. The Automatic Sound Select process will automatically switch to the mono compatible digital standard. The MSP Standard Codes are defined in (see Table 3–7 on page 21). Micronas 11 MSP 34x0G 2.4. Source Selection and Output Channel Matrix The Source Selector makes it possible to distribute all source signals (one of the demodulator source channels, SCART, or I2S input) to the desired output channels (loudspeaker, headphone, etc.). All input and output signals can be processed simultaneously. Each source channel is identified by a unique source address. For each output channel, the sound mode can be set to sound A, sound B, stereo, or mono by means of the output channel matrix. If Automatic Sound Select is on, the output channel matrix can stay fixed to stereo (transparent) for demodulated signals. PRELIMINARY DATA SHEET 2.5.2. Loudspeaker and Headphone Outputs The following baseband features are implemented in the loudspeaker and headphone output channels: bass/treble, loudness, balance, and volume. A square wave beeper can be added to the loudspeaker and headphone channel. The loudspeaker channel additionally performs: equalizer (not simultaneously with bass/treble), spatial effects, and a subwoofer crossover filter. 2.5.3. Subwoofer Output The subwoofer signal is created by combining the left and right channels directly behind the loudness block using the formula (L+R)/2. Due to the division by 2, the D/A converter will not be overloaded, even with full scale input signals. The subwoofer signal is filtered by a third-order low-pass with programmable corner frequency followed by a level adjustment. At the loudspeaker channels, a complementary high-pass filter can be switched on. Subwoofer and loudspeaker output use the same volume (Loudspeaker Volume Register). 2.5. Audio Baseband Processing 2.5.1. Automatic Volume Correction (AVC) Different sound sources (e.g. terrestrial channels, SAT channels, or SCART) fairly often do not have the same volume level. Advertisements during movies usually have a higher volume level than the movie itself. This results in annoying volume changes. The Automatic Volume Correction (AVC) solves this problem by equalizing the volume level. To prevent clipping, the AVC’s gain decreases quickly in dynamic boost conditions. To suppress oscillation effects, the gain increases rather slowly for low level inputs. The decay time is programmable by means of the AVC register (see page 31). For input signals ranging from −24 dBr to 0 dBr, the AVC maintains a fixed output level of −18 dBr. Fig. 2–4 shows the AVC output level versus its input level. For prescale and volume registers set to 0 dB, a level of 0 dBr corresponds to full scale input/output. This is – SCART input/output 0 dBr = 2.0 Vrms – Loudspeaker and Aux output 0 dBr = 1.4 Vrms output level [dBr] −18 −24 2.5.4. Quasi-Peak Detector The quasi-peak readout register can be used to read out the quasi-peak level of any input source. The feature is based on following filter time constants: attack time: 1.3 ms decay time: 37 ms −30 −24 −18 −12 −6 0 input level [dBr] Fig. 2–4: Simplified AVC characteristics 12 Micronas PRELIMINARY DATA SHEET MSP 34x0G 2.5.5. Micronas Dynamic Bass (MDB) The Micronas Dynamic Bass system (MDB) extends the frequency range of loudspeakers or headphones. After the adaption of MDB to the loudspeakers and the cabinet, further customizing of MDB allows individual fine tuning of the sound. The MDB is placed in the subwoofer path. For applications without a subwoofer, the enhanced bass signal can be added back onto the Left/Right channels (see Fig. 2–1 on page 8). Micronas Dynamic Bass combines two effects: dynamic amplification and adding harmonics. Frequency MDB_HP Amplitude (db) Fig. 2–6: Adding harmonics 2.5.5.3. MDB Parameters 2.5.5.1. Dynamic Amplification Low frequency signals can be boosted while the output signal amplitude is measured. If the amplitude comes close to a definable limit, the gain is reduced automatically in dynamic Volume mode. Therefore, the system adapts to the signal amplitude which is really present at the output of the MSP device. Clipping effects are avoided. Amplitude (db) Several parameters allow tuning the characteristics of MDB according to the TV loudspeaker, the cabinet, and personal preferences (see Table 3–11). For more detailed information on how to set up MDB, please refer to the corresponding application note on the Micronas homepage. 2.6. SCART Signal Routing 2.6.1. SCART DSP In and SCART Out Select The SCART DSP Input Select and SCART Output Select blocks include full matrix switching facilities. To design a TV set with four pairs of SCART-inputs and two pairs of SCART-outputs, no external switching hardware is required. The switches are controlled by the ACB user register (see page 39). Frequency MDB_HP MDB_LP SUBW_FREQ Signal Level MDB_LIMIT 2.6.2. Stand-by Mode If the MSP 34x0G is switched off by first pulling STANDBYQ low and then (after >1 µs delay) switching off DVSUP and AVSUP, but keeping AHVSUP (‘Stand-by’-mode), the SCART switches maintain their position and function. This allows the copying from SCART-input to SCART-output in the TV set’s stand-by mode. In case of power on or starting from stand-by (switching on the DVSUP and AVSUP, RESETQ going high 2 ms later), all internal registers except the ACB register (see page 39) are reset to the default configuration (see Table 3–5 on page 18). The reset position of the ACB register becomes active after the first I2C transmission into the Baseband Processing part. By transmitting the ACB register first, the reset state can be redefined. Fig. 2–5: Dynamic amplification 2.5.5.2. Adding Harmonics MDB exploits the psychoacoustic phenomenon of the ‘missing fundamental’. Adding harmonics of the frequency components below the cutoff frequency gives the impression of actually hearing the low frequency fundamental. In other words: The listener has the impression that a loudspeaker system seems to reproduce frequencies althoug physically not possible. Micronas 13 MSP 34x0G 2.7. I2S Bus Interface The MSP 34x0G has a synchronous master/slave input/output interface running on 32 kHz. The interface accepts two formats: 1. I2S_WS changes at the word boundary 2. I2S_WS changes one I2S-clock period before the word boundaries. All I2S options are set by means of the MODUS and the I2S_CONFIGURATION registers. The I2S bus interface consists of five pins: – I2S_DA_IN1, I2S_DA_IN2: I2S serial data input: 16, 18....32 bits per sample – I2S_DA_OUT: I2S serial data output: 16, 18...32 bits per sample – I2S_CL: I2S serial clock – I2S_WS: I2S word strobe signal defines the left and right sample If the MSP 34x0G serves as the master on the I2S interface, the clock and word strobe lines are driven by the IC. In this mode, only 16 or 32 bits per sample can be selected. In slave mode, these lines are input to the IC and the MSP clock is synchronized to 576 times the I2S_WS rate (32 kHz). NICAM operation is not possible in slave mode. An I2S timing diagram is shown in Fig. 4–28 on page 67. 2.8. ADR Bus Interface PRELIMINARY DATA SHEET For the ASTRA Digital Radio System (ADR), the MSP 3400G, MSP 3410G, and MSP 3450G performs preprocessing such as carrier selection and filtering. Via the 3-line ADR-bus, the resulting signals are transferred to the DRP 3510A coprocessor, where the source decoding is performed. To be prepared for an upgrade to ADR with an additional DRP board, the following lines of MSP 34x0G should be provided on a feature connector: – AUD_CL_OUT – I2S_DA_IN1 or I2S_DA_IN2 – I2S_DA_OUT – I2S_WS – I2S_CL – ADR_CL, ADR_WS, ADR_DA For more details, please refer to the DRP 3510A data sheet. 2.9. Digital Control I/O Pins and Status Change Indication The static level of the digital input/output pins D_CTR_I/O_0/1 is switchable between HIGH and LOW via the I2C-bus by means of the ACB register (see page 39). This enables the controlling of external hardware switches or other devices via I2C-bus. The digital input/output pins can be set to high impedance by means of the MODUS register (see page 24). In this mode, the pins can be used as input. The current state can be read out of the STATUS register (see page 26). Optionally, the pin D_CTR_I/O_1 can be used as an interrupt request signal to the controller, indicating any changes in the read register STATUS. This makes polling unnecessary, I2C bus interactions are reduced to a minimum (see STATUS register on page 26 and MODUS register on page 24). 2.10. Clock PLL Oscillator and Crystal Specifications The MSP 34x0G derives all internal system clocks from the 18.432 MHz oscillator. In NICAM or in I2SSlave mode, the clock is phase-locked to the corresponding source. Therefore, it is not possible to use NICAM and I2S-Slave mode at the same time. For proper performance, the MSP clock oscillator requires a 18.432 MHz crystal. Note that for the phase-locked modes (NICAM, I2S-Slave), crystals with tighter tolerance are required. 14 Micronas PRELIMINARY DATA SHEET MSP 34x0G response time is about 0.3 ms. If the MSP cannot accept another byte of data (e.g. while servicing an internal interrupt), it holds the clock line I2C_CL low to force the transmitter into a wait state. The I2C Bus Master must read back the clock line to detect when the MSP is ready to receive the next I2C transmission. The positions within a transmission where this may happen are indicated by ’Wait’ in Section 3.1.3. The maximum wait period of the MSP during normal operation mode is less than 1 ms. 3. Control Interface 3.1. I2C Bus Interface The MSP 34x0G is controlled via the I2C bus slave interface. The IC is selected by transmitting one of the MSP 34x0G device addresses. In order to allow up to three MSP ICs to be connected to a single bus, an address select pin (ADR_SEL) has been implemented. With ADR_SEL pulled to high, low, or left open, the MSP 34x0G responds to different device addresses. A device address pair is defined as a write address and a read address (see Table 3–1). Writing is done by sending the write device address, followed by the subaddress byte, two address bytes, and two data bytes. Reading is done by sending the write device address, followed by the subaddress byte and two address bytes. Without sending a stop condition, reading of the addressed data is completed by sending the device read address and reading two bytes of data. Refer to Section 3.1.3. for the I2C bus protocol and to Section 3.4. “Programming Tips” on page 41 for proposals of MSP 34x0G I2C telegrams. See Table 3–2 for a list of available subaddresses. Besides the possibility of hardware reset, the MSP can also be reset by means of the RESET bit in the CONTROL register by the controller via I2C bus. Due to the architecture of the MSP 34x0G, the IC cannot react immediately to an I2C request. The typical Table 3–1: I2C Bus Device Addresses ADR_SEL Mode MSP device address Low (connected to DVSS) Write 80hex Read 81hex 3.1.1. Internal Hardware Error Handling In case of any hardware problems (e.g. interruption of the power supply of the MSP), the MSP’s wait period is extended to 1.8 ms. After this time period elapses, the MSP releases data and clock lines. Indication and solving the error status: To indicate the error status, the remaining acknowledge bits of the actual I2C-protocol will be left high. Additionally, bit[14] of CONTROL is set to one. The MSP can then be reset via the I2C bus by transmitting the RESET condition to CONTROL. Indication of reset: Any reset, even caused by an unstable reset line etc., is indicated in bit[15] of CONTROL. A general timing diagram of the I2C bus is shown in Fig. 4–27 on page 65. High (connected to DVSUP) Write 84hex Read 85hex Write 88hex Left Open Read 89hex Table 3–2: I2C Bus Subaddresses Name CONTROL WR_DEM RD_DEM WR_DSP RD_DSP Binary Value 0000 0000 0001 0000 0001 0001 0001 0010 0001 0011 Hex Value 00 10 11 12 13 Mode Read/Write Write Write Write Write Function Write: Software reset of MSP (see Table 3–3) Read: Hardware error status of MSP write address demodulator read address demodulator write address DSP read address DSP Micronas 15 MSP 34x0G 3.1.2. Description of CONTROL Register PRELIMINARY DATA SHEET Table 3–3: CONTROL as a Write Register Name CONTROL Subaddress 00hex Bit[15] (MSB) 1 : RESET 0 : normal Bits[14:0] 0 Table 3–4: CONTROL as a Read Register Name CONTROL Subaddress 00hex %LW>@ 06% RESET status after last reading of CONTROL: 0 : no reset occured 1 : reset occured Bit>@ Internal hardware status: 0 : no error occured 1 : internal error occured BitV>@ not of interest Reading of CONTROL will reset the bits[15,14] of CONTROL. After Power-on, bit[15] of CONTROL will be set; it must be read once to be reset. 3.1.3. Protocol Description Write to DSP or Demodulator S Wait write device address ACK sub-addr ACK addr-byte ACK addr-byte ACK data-byte ACK data-byte ACK P high low high low Read from DSP or Demodulator S Wait write device address ACK sub-addr ACK addr-byte ACK addr-byte ACK S high low read device address Wait ACK data-byte- ACK data-byte NAK P high low Write to Control Register S Wait write device address ACK sub-addr ACK data-byte ACK data-byte ACK P high low Read from Control Register S Wait write device address ACK 00hex ACK S read device address Wait ACK data-byte- ACK data-byte NAK P high low Note: S = P= ACK = NAK = I2C-Bus Start Condition from master I2C-Bus Stop Condition from master Acknowledge-Bit: LOW on I2C_DA from slave (= MSP, light gray) or master (= controller, dark gray) Not Acknowledge-Bit: HIGH on I2C_DA from master (dark gray) to indicate ‘End of Read’ or from MSP indicating internal error state Wait = I2C-Clock line is held low, while the MSP is processing the I2C command. This waiting time is max. 1 ms 16 Micronas PRELIMINARY DATA SHEET MSP 34x0G I2C_DA S I2C_CL 1 0 P Fig. 3–1: I2C bus protocol (MSB first; data must be stable while clock is high) 3.1.4. Proposals for General MSP 34x0G I2C Telegrams 3.1.4.1. Symbols daw dar < > aa dd write device address (80hex, 84hex or 88hex) read device address (81hex, 85hex or 89hex) Start Condition Stop Condition Address Byte Data Byte 3.2. Start-Up Sequence: Power-Up and I2C-Controlling After POWER-ON or RESET (see Fig. 4–26), the IC is in an inactive state. All registers are in the Reset position (see Table 3–5 and Table 3–6), the analog outputs are muted. The controller has to initialize all registers for which a non-default setting is necessary. 3.3. MSP 34x0G Programming Interface 3.3.1. User Registers Overview 3.1.4.2. Write Telegrams write to CONTROL register write data into demodulator write data into DSP 3.1.4.3. Read Telegrams read data from CONTROL register