MTU8B56EP

MYSON TECHNOLOGY FEATURES • Total of 33 single word instructions . • The fast execution time may be 200ns for all single cycle instructions under 20MHz operating. • Operating voltage range: 2.3V ~ 6.5V • 8-bit data bus. • 14-bit instruction word. • Four-level stacks. • On chip EPROM size : 512x14 bits for MTU8B54E/55E, 1Kx14 bits for MTU8B56E, 2Kx14 bits for MTU8B57E. • Internal RAM size : 25 bytes for MTU8B54E/56E, 24 bytes for MTU8B55E, • 72 bytes for MTU8B57E. • Direct and indirect addressing modes for data accessing • 8-bit real time clock/counter with 8-bit programmable prescaler. • Internal power-on Reset. • Device Reset Timer. • Code protection. • Sleep mode for power saving. • On chip Watchdog Timer(WDT) based on internal RC oscillator. • Three I/O ports PA, PB nad PC with independent direction control. MTU8B54E/55E/56E/57E EPROM-Based 8-Bit CMOS Microcontroller • 4 types of oscillator can be selected by code options: - RC : Low-cost RC oscillator - XTAL : Standard crystal oscillator - HFXTAL : High frequency crystal oscillator - LFXTAL : Low frequency crystal oscillator GENERAL DESCRIPTION MTU8B5X series is an EPROM based 8-bit microcontroller which employs a full CMOS technology enhanced with low-cost, high speed and high noise immunity. Watchdog Timer, RAM, EPROM, tri-state I/O port, power down mode, and real time programmable clock/counter are integrated into this chip. MTU8B5X contains 33 instructions, all are single cycle except for program branches which take two cycles. On chip memory is available with 512x14 bits of EPROM for MTU8B54E/55E, 1Kx14 bits of EPROM for MTU8B56E, 2Kx14 bits of EPROM for MTU8B57E and 24 to 72 bytes of static RAM. BLOCK DIAGRAM Vdd Vss Configuration Word Osc Mode 2 Select Four-level Stack 11 Program Counter 11 Enable /Disable OSCI OSCO MCLR Sleep WatchDog Timer Oscillator Circuit EPROM 512 X 14 TO 2048 X 14 14 Instruction Register T0CKI WDT/Timer0 Prescaler 6 WDT Time Out 14 Timer0 Data Instruction Decoder 4 T0MODE Register 6 8 RAM 24, 25 or 27 Bytes PortA PA3:PA0 Accumulator FSR PortB 8 PB7:PB0 PortC Status ALU 8 Only in MTU8B55E/57E 8 PC7:PC0 This datasheet contains new product information. Myson Technology reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of this procuts. No rights under any patent accompany the sales of the product. Revision 1.2 -1 24 October 2000 MYSON TECHNOLOGY 1.0 PIN CONNECTION MTU8B54E/55E/56E/57E T0CKI Vdd PA2 PA3 T0CKI MCLR/Vpp Vss PB0 PB1 PB2 PB3 1 2 3 4 5 MTU8B54E 6 MTU8B56E 7 8 9 18 17 16 15 14 13 12 11 10 PA1 PA0 OSCI OSCO Vdd PB7 PB6 PB5 PB4 N/C Vss N/C PA0 PA1 PA2 PA3 PB0 PB1 PB2 PB3 PB4 1 2 3 4 5 6 7 MTU8B55E 8 MTU8B57E 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 MCLR/Vpp OSCI OSCO PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PB7 PB6 PB5 2.0 PIN DESCRIPTIONS Name OSCI I/O I Descriptions RC type: Input pin of RC oscillator XTAL type: Input terminal of crystal oscillator RC type: OSCO outputs with 1/4 frequency of OSCI to denotes the cycle rate for instruction. XTAL type: Output terminal of crystal oscillator OSCO T0CKI/SCL O I Input pin of real time counter/clock. Must be tied to Vss or Vdd if not in use. Input pin for device reset or high voltage programming input for EPROM. If this pin is low, the device is reset. MCLR/Vpp I In programmimg mode, this pin is connected to 12V. In normal operating mode, this pin must not exceed Vdd to avoid entering unintended programming mode. PA0~PA3 as bi-directional I/O port PB0~PB7 as bi-directional I/O port PC0~PC7 as bi-directional I/O port Power supply Ground PA0~PA3 PB0~PB7 PC0~PC7 Vdd Vss I/O I/O I/O - Revision 1.2 -2- 24 October 2000 MYSON TECHNOLOGY 3.0 FUNCTIONAL DESCRIPTIONS 3.1 REGISTER MAP MTU8B54E/55E/56E/57E The register map of MTU8B5X is depicted as below:. The Register Map of MTU8B54E/56E Address 00h 01h 02h 03h 04h 05h 06h 07h-1Fh Description Indirect Addressing Register Timer0 PC STATUS FSR PORTA PORTB General Purpose Register The Register Map of MTU8B55E Address 00h 01h 02h 03h 04h 05h 06h 07h 08h-1Fh The Register Map of MTU8B57E Address FSR 00h 01h 02h 03h 04h 05h 06h 07h 08h~0Fh Bank 0 00 Indirect Addressing Register Timer0 PC STATUS FSR PORTA PORTB PORTC General Purpose Register 10h~1Fh General Purpose Register 30h~3Fh General Purpose Register 50h~5Fh General Purpose Register 70h~7Fh General Purpose Register Map back to address in Bank 0 Bank 1 01 Description Bank 2 10 Bank 3 11 Description Indirect Addressing Register Timer0 PC STATUS FSR PORTA PORTB PORTC General Purpose Register Revision 1.2 -3- 24 October 2000 MYSON TECHNOLOGY MTU8B54E/55E/56E/57E 3.1.1 INAR(Indirect Address Register) : R0 R0 is not a physically implemented register. It is used as an indirect addressing pointer. Any instruction accessing this register can access data pointed by FSR(R4). 3.1.2 Timer0(8-bit real-time clock/timer) : R1 This register increases by an external signal edge applied to T0CKI pin, or by internal instruction cycle. It can be read or written as any other register. 3.1.3 PC(Program Counter) : R2 This register increases itself every instruction cycle, except the following condition shown in Figure 1: LCALL, LGOTO : from instruction word RETIA : from STACK LCALL A10~A0 RETIA FIGURE 1. Program Counter 3.1.4 STATUS(Status Register): The content of R3 is listed in Table 1. TABLE 1. STATUS Register Bit Symbol Carry/borrow bit 0 C ADDWF = 1, a carry occurred = 0, a carry did not occur Half carry/half borrow bit ADDWF = 1, a carry from the 4th low order bit of the result occurred 1 DC = 0, a carry from the 4th low order bit of the result did not occur SUBWF = 1, a borrow from the 4th low order bit of the result did not occur = 0, a borrow from the 4th low order bit of the result occurred Zero bit: 2 Z = 1, the result of a logic operation is zero = 0, the result of a logic operation is not zero Power down flag bit: 3 PD = 1, after power-up or by the CLRWDT instruction = 0, by the SLEEP instruction Time overflow flag bit: 4 5, 6, 7 TO = 1, after power-up or by the CLRWDT or SLEEP instruction = 0, a WDT time-overflow occurred Unused Stack1 Stack2 Stack3 Stack4 Description SUBWF = 1, a borrow did not occur = 0, a borrow occurred Revision 1.2 -4- 24 October 2000 MYSON TECHNOLOGY MTU8B54E/55E/56E/57E 3.1.5 FSR(File select register pointer): R4 Bit 0~4 are used to select up to 32 registers (address: 00h~1Fh) and Bit 5~6 are Bank Select (Bank0~3) in the indirect addressing mode shown in Figure 2. 3.1.6 PORT A: R5 PA3:PA0, bi-directional I/O Register 3.1.7 PORT B: R6 PB7:PB0, bi-directional I/O Register 3.1.8 PORT C: R7 PB7:PB0, bi-directional I/O Register, and for MTU8B55E/57E only 3.1.9 T0MODE REGISTER: T0MODE is a write-only register and the content is listed in Table 2. 3.1.10 IOST (Control Port I/O Mode Register) The IOST register is “write-only” = 0, I/O pin in output mode; = 1, I/O pin in input mode. Bank Select Indirect Addressing Mode Location Select B7 B6 B5 B4 B3 B2 B1 B0 Read 1 70h 50h Bank 3 Bank 2 30h Bank 1 Bank 0 10h 16 Bytes SRAM 7Fh 5Fh 3Fh 1Fh 00h 01h 02h 03h 04h 05h 06h 07h 08h 0Fh INAR Timer0 PC STATUS FSR PORT A PORT B PORT C 8 Bytes SRAM Bank 0 FIGURE 2. Data Memory Configuraion Revision 1.2 -5- 24 October 2000 MYSON TECHNOLOGY TABLE 2. T0MODE Register Bit Symbol Bit Value 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 MTU8B54E/55E/56E/57E Description Timer Rate 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256 WDT Rate 1:1 1:2 1:4 1:8 1:16 1:32 1:64 1:128 2-0 PS2:PS0 Prescaler assign bit: 3 PSC = 0, Timer0 = 1, WDT Timer0 source signal edge select bit: 4 TE = 0, increment when low-to-high transition on T0CKI pin = 1, increment when high-to-low transition on T0CKI pin Timer0 source signal select bit: 5 TS = 0, internal instruction clock cycle = 1, transition on T0CKI pin 6, 7 Unused Revision 1.2 -6- 24 October 2000 MYSON TECHNOLOGY 3.2 INSTRUCTION SET Mnemonic Operands BCR R, bit BSR R, bit BTRSC R, bit MTU8B54E/55E/56E/57E Description Clear bit in R Set bit in R Test bit in R and skip if clear Cycles 1 1 1 or 2(skip) 1 or 2(skip) 1 1 1 1 1 1 1 1 2 2 2 1 1 1 1 1 1 1 1 1 1 1 or 2(skip) Instruction Code 11 11bb brrr rrrr 11 10bb brrr rrrr 11 01bb brrr rrrr Status Affected None None None BTRSS R, bit CLRWDT T0MODE SLEEP IOST R ANDIA I XORIA I MOVIA I IORIA I RETIA I LCALL I LGOTO I NOP MOVAR R COMR R, d MOVR R RRR R, d RLR R, d SWAPR R, d CLRA CLRR R INCR R, d INCRSZ R, d Test bit in R and skip if set Clear Watchdog Timer Load T0MODE Register Go into standby mode Load IOST Register AND immediate with Acc Exclusive OR immediate with Acc Move immediate to Acc Inclusive OR immediate with Acc Return, place immediate in A Call subroutine Unconditional branch No operation Move Acc to R Complement R Move R Rotate right R Rotate left R Swap halves R Clear Acc Clear R Increment R Increment R, Skip if 0 11 00bb brrr rrrr 01 0000 0000 0001 01 0000 0000 0010 01 0000 0000 0011 01 0000 0000 0rrr 00 1001 iiii iiii 00 1000 iiii iiii 00 0001 iiii iiii 00 0011 iiii iiii 00 1100 iiii iiii 10 0iii iiii iiii 10 1iii iiii iiii 01 0000 0000 0000 01 0000 1rrr rrrr 01 0010 drrr rrrr 01 0011 drrr rrrr 01 1110 drrr rrrr 01 1100 drrr rrrr 01 1101 drrr rrrr 01 0001 0000 0000 01 0001 1rrr rrrr 01 1000 drrr rrrr 01 1001 drrr rrrr None TO, PD None TO, PD None Z Z None Z None None None None None Z Z C C None Z Z Z None Revision 1.2 -7- 24 October 2000 MYSON TECHNOLOGY Mnemonic Operands DECR R, d MTU8B54E/55E/56E/57E Description Decrement R Cycles 1 1 or 2(skip) 1 1 1 1 Instruction Code Status A ffected 01 0110 drrr rrrr Z 01 0111 drrr rrrr None 01 1010 drrr rrrr C, DC, Z 01 1011 drrr rrrr Z 01 0100 drrr rrrr Z 01 0101 drrr rrrr C, DC, Z DECRSZ R, d Decrement R, Skip if 0 SUBAR R, d XORAR R, d ANDAR R, d ADDAR R, d Subtract Acc from R Exclusive OR Acc with R AND Acc with R Add Acc and R IORAR R, d Inclusive OR Acc with R 1 01 1111 drrr rrrr Z Note: b : Bit position WDT : Watchdog Timer R : Register address i : Immediate data Acc : Accumulator T0MODE : T0MODE register PD : Power down flag TO : Time overflow bit IOST : I/O port status register Z : Zero flag C : Carry flag DC : Digital carry flag I : (i7i6i5i4i3i2i1i0) R : (r6r5r4r3r2r1r0) d ∈ [ 0, 1 ] :Destination If d is “0”, the result is stored in the Acc register. If d is “1”, the result is stored back in register R. 3.3 I/O PORTS EQUIVALENT CIRCUIT Acc Data D Q VDD IOST Latch IOST R CK QB I/O Pin Data Bus D QB Data Latch WR Port CK Q VSS RD Port Note : 1. The IOST registers are “write-only” and set upon RESET. 2. If the IOST latch is “0”, the corresponding I/O pin is in output mode; if the IOST latch is “1”, the corresponding I/O pin is in input mode. Revision 1.2 -824 October 2000 MYSON TECHNOLOGY 3.4 RESET MTU8B54E/55E/56E/57E This device may be reset by one of the following ways: (1) Power-on Reset : At power-up, this device will be kept in a RESET condition for a period of 18ms after the voltage on MCLR/Vpp pin has reached a logic high level. (2) MCLR reset (normal operation). (3) WDT reset (normal operation). (4) MCLR wake-up (from sleep mode). (5) WDT wake-up (from sleep mode) : Executing the SLEEP instruction can force this device entering into sleep mode (power saving mode). While in sleep mode, the WDT is cleared but keeps running. This device can be awakened by WDT time-out or reset input on MCLR pin. The contents of registers after reset are listed below: Address 00h 01h 02h 03h 04h 05h 06h 07h 07h-1Fh N/A N/A N/A INAR Timer0 PC STATUS FSR PORTA PORTB PORTC General Purpose Register Acc IOST T0MODE Register Power-On Reset xxxx xxxx xxxx xxxx 1111 1111 0001 1xxx 1xxx xxxx ---- xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 1111 1111 --11 1111 /MCLR or WDT Reset uuuu uuuu uuuu uuuu 1111 1111 000# #uuu 1uuu uuuu ---- uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 1111 1111 --11 1111 Note: x = unknown, u = unchanged, - = unimplemented, read as “0”, # = refer to the following table Condition /MCLR Reset (not during SLEEP) /MCLR Reset during SLEEP WDT Reset (not during SLEEP) WDT Reset during SLEEP Status:bit 4 u 1 0 0 Status:bit 3 u 0 1 0 Revision 1.2 -9- 24 October 2000 MYSON TECHNOLOGY T0CKI TE FOSC/4 1 0 M U X 1 TS PSC MUX 0 MTU8B54E/55E/56E/57E 3.5 REAL TIME CLOCK (TIMER0) AND WATCHDOG TIMER WDT enable WDT 0 PSC MUX 1 Sync 2 cycles 8-bit prescaler 8 bits Timer0 8 bits PS2:PS0 8-to-1 MUX Data Bus PSC 1 MUX 0 WDT Time-Out 3.5.1 Timer0 Timer0 is an 8-bit timer/counter. The clock source of Timer0 can come from the internal clock or by an external clock source presented at the T0CKI pin. To select the internal clock source, bit 5 of the T0MODE register should be reset. In this mode, Timer0 will increase by 1 in every instruction cycle (without prescaler). To select the external clock source, bit 5 of the T0MODE register should be set. In this mode, Timer0 will increase by 1 on every falling or rising edge of T0CKI pin is controlled by bit 4 of T0MODE register. 3.5.2 Watchdog Timer(WDT) The Watchdog Timer is a free running on-chip RC oscillator. This RC oscillator is separated from the RC oscillator of the OSCI pin. That means the WDT will keep running even when the oscillator driver is turned off, such as in sleep mode. During normal operation or in sleep mode, a WDT time-out will cause the device reset and the TO bit (bit 4 of STATUS register) will be cleared. Without prescaler, the WDT time-out period is 18ms. This period can be increased by using the prescaler. The division ratio of prescaler is up to 1:128. Thus, the longest time-out period is approximately 2.3s. 3.5.3 Prescaler The 8-bit prescaler may be assigned to either the Timer0 or the WDT through the PSC bit (bit 3 of the T0MODE register). Setting this bit assigns the prescaler to the WDT. Resetting this bit assigns the prescaler to the Timer0. The PS2:PS0 bits determine the prescale ratio. When assigned to Timer0, the prescaler will be cleared by instructions which write to Timer0 Register. A CLRWDT instruction will clear the WDT and prescaler when assigned to WDT. The prescaler can not be assigned to both the Timer0 and WDT simultaneously. Revision 1.2 - 10 - 24 October 2000 MYSON TECHNOLOGY 3.6 OSCILLATOR CONFIGURATION MTU8B54E/55E/56E/57E This device supports four oscillator modes. Users can program two configuration bits to select the appropriate mode. These oscillator modes offered as: • RC: Low-cost crystal • XTAL: Standard crystal oscillator • HFXTAL: High frequency crystal oscillator • LFXTAL: Low frequency crystal oscillator 3.6.1 XTAL, HFXTAL or LFXTAL modes MTU8B54E/55E/56E/57E Internal Circuit MTU8B54E/55E/56E/57E SLEEP OSCI RF XTAL C1 OSCO RS OSCI OSCO C2 Open Clock from external system (a) Crystal Operation (or Ceramic Resonator) 3.6.2 RC Oscillator Mode R OSCI C 0÷4 (b) External Clock Input Operation MTU8B54E/55E/56E/57E internal clock OSCO 3.7 CONFIGURATION WORD Bit 3 Bit2 Bit1 Bit0 Code Protect WDT Enable Oscillator Type Oscillator Type 1 x x x 0 x x x x 1 x x x 0 x x x x 1 1 x x 1 0 x x 0 1 x x 0 0 Function EPROM unprotected EPROM protected Watchdog Timer enable Watchdog Timer disable RC HFXTAL XTAL LFXTAL Remark Default Default Default Revision 1.2 - 11 - 24 October 2000 MYSON TECHNOLOGY 4.0 ABSOLUTE MAXIMUM RATINGS Ambient Operating Temperature Store Temperature DC Supply Voltage(Vdd) Voltage with respect to Ground(Vss) Voltage on MCLR(Vpp) with respect to Ground(Vss) MTU8B54E/55E/56E/57E -55oC to +125oC -65oC to +150oC 0V to +7.5V 0.6V to (Vdd + 0.6)V 0V to +12V 5.0 OPERATING CONDITIONS DC Supply Voltage Operaing Temprature +2.3V to +6.5V -40oC to +85oC 6.0 ELECTRICAL CHARACTERISTICS (Under Operating Conditions) 6.1 ELECTRICAL CHARACTERISTICS of MTU8B54E/56E Parameter Input High Voltage Input Low Volatge Output Voltage Sleep Current Sym VIH VIL VOh VOL IPD IPD 3.0