MX26F128J3

MX26F128J3 Macronix NBit TM M emory Family 128M [x8/x16] SINGLE 3V PAGE MODE eLiteFlashTM MEMORY FEATURES • 3.0V to 3.6V operation voltage • Block Structure - 128 x 128Kbyte Erase Blocks • Fast random / page mode access time - 120/25 ns Read Access Time - 150/25 ns Read Access Time • Page Depth: 4-word • 128-bit Protection Register - 64-bit Unique Device Identifier - 64-bit User Programmable OTP Cells • 32-Byte Write Buffer - 6 us/byte Effective Programming Time • Enhanced Data Protection Features Absolute Protection with VPEN = GND - Flexible Block Locking - Block Erase/Program Lockout during Power Transitions Software Feature • Support Common Flash Interface (CFI) - eLiteFlashTM memory device parameters stored on the device and provide the host system to access. Hardware Feature • A0 pin - Select low byte address when device is in byte mode. Not used in word mode. • STS pin - Indicates the status of the internal state machine. • VPEN pin - For Erase /Program/ Block Lock enable. • VCCQ Pin - The output buffer power supply, control the device 's output voltage. Packaging Performance • Low power dissipation - typical 15mA active current for page mode read - 80uA/(max.) standby current • High Performance - Block erase time: 2s typ. - Byte programming time: 210us typ. - Block programming time: 0.8s typ. (using Write to Buffer Command) • Program/Erase Endurance cycles: 100 cycles - 56-Lead TSOP - 64-ball CSP Technology - 0.25u Macronix NBitTM Flash Technology P/N:PM0960 REV. 1.1, OCT. 18, 2004 1 MX26F128J3 GENERAL DESCRIPTION The MXIC's MX26F128J3 series eLiteFlashTM memory use the most advance 2 bits/cell Nbit technology, double the storage capacity of memory cell. The device provide the high density eLiteFlashTM memory solution with reliable performance and most cost-effective. The device organized as by 8 bits or by 16 bits of output bus. The device is packaged in 56-Lead TSOP and 64ball CSP. It is designed to be reprogrammed and erased in system or in standard EPROM programmers. The device offers fast access time and allowing operation of high-speed microprocessors without wait states. To eliminate bus contention, the device has separate chip enable (CE0, CE1, CE2) and output enable (OE) controls. The device augment EPROM functionality with incircuit electrical erasure and programming. The device uses a command register to manage this functionality. The MXIC's Nbit technology reliably stores memory contents even after the specific erase and program cycles. The MXIC cell is designed to optimize the erase and program mechanisms by utilizing the dielectric's character to trap or release charges from ONO layer. The device uses a 3.0V to 3.6V VCC supply to perform the High Reliability Erase and auto Program/Erase algorithms. The highest degree of latch-up protection is achieved with MXIC's proprietary non-epi process. Latch-up protection is proved for stresses up to 100 milliamps on address and data pin from -1V to VCC + 1V. PIN CONFIGURATION 56 TSOP (14mm x 20mm) A22 CE1 A21 A20 A19 A18 A17 A16 VCC A15 A14 A13 A12 CE0 VPEN RESET A11 A10 A9 A8 GND A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 NC WE OE STS Q15 Q7 Q14 Q6 GND Q13 Q5 Q12 Q4 VCCQ GND Q11 Q3 Q10 Q2 VCC Q9 Q1 Q8 Q0 A0 BYTE A23 CE2 P/N:PM0960 REV. 1.1,OCT. 18, 2004 2 MX26F128J3 64 Ball CSP (10x13x1.2mm, 1.0mm-ball pitch) 1 2 3 4 5 6 7 8 A A1 A6 A8 VPEN A13 VCC A18 A22 B A2 GND A9 CE0 A14 DU A19 CE1 C A3 A7 A10 A12 A15 DU A20 A21 D A4 A5 A11 RESET DU DU A16 A17 E Q8 Q1 Q9 Q3 Q4 DU Q15 STS 13 mm F BYTE Q0 Q10 Q11 Q12 DU DU OE G A23 A0 Q2 VCCQ Q5 Q6 Q14 WE H CE2 DU VCC GND Q13 GND Q7 NC 10mm Notes: 1. Don't Use (DU) pins refer to pins that should not be connected. PIN DESCRIPTION SYMBOL A0 A1~A23 Q0~Q15 WE OE RESET PIN NAME Byte Select Address Address Input Data Inputs/Outputs Write Enable Input Output Enable Input Reset/Power Down mode SYMBOL STS BYTE VPEN VCCQ VCC GND NC DU PIN NAME STATUS Pin Byte Mode Enable ERASE/PROGRAM/BLOCK Lock Enable Output Buffer Power Supply Device Power Supply Device Ground Pin Not Connected Internally Don't Use CE0, CE1, CE2 Chip Enable Input P/N:PM0960 REV. 1.1,OCT. 18, 2004 3 MX26F128J3 BLOCK DIAGRAM CE0 CE1 CE2 OE WE RESET CONTROL INPUT LOGIC PROGRAM/ERASE HIGH VOLTAGE WRITE STATE MACHINE (WSM) STATE REGISTER X-DECODER ADDRESS LATCH A0-A23 AND BUFFER ARRAY ARRAY SOURCE HV Y-PASS GATE COMMAND DATA DECODER Y-DECODER SENSE AMPLIFIER PGM DATA HV COMMAND DATA LATCH PROGRAM DATA LATCH Q0-Q15 I/O BUFFER P/N:PM0960 REV. 1.1,OCT. 18, 2004 4 MX26F128J3 Figure 1. Block Architecture eLiteFlashTM memory reads erases and writes in-system via the local CPU. All bus cycles to or from the eLiteFlashTM memory conform to standard microprocessor bus cycles. A[23-0]: 128Mbit A[23-1]: 128Mbit 7FFFFF 128-Kbyte Block 127 7F0000 64-Kword Block 127 FFFFFF FE0000 . . . 7FFFFF 7E0000 128-Kbyte Block 63 3FFFFF 3F0000 . . . 64-Kword Block 63 3FFFFF 3E0000 128-Kbyte Block 31 1FFFFF 1F0000 64-Kword Block 31 . . . 03FFFF 020000 01FFFF 000000 128-Kbyte Block 128-Kbyte Block 1 0 01FFFF 010000 00FFFF 000000 . . . 64-Kword Block 64-Kword Block 1 0 Byte Mode (x8) Word Mode (x16) Table 1. Chip Enable Truth Table CE2 VIL VIL VIL VIL VIH VIH VIH VIH CE1 VIL VIL VIH VIH VIL VIL VIH VIH CE0 VIL VIH VIL VIH VIL VIH VIL VIH DEVICE Enabled Disabled Disabled Disabled Enabled Enabled Enabled Disabled NOTE: For Single-chip applications, CE2 and CE1 can be strapped to GND. P/N:PM0960 REV. 1.1,OCT. 18, 2004 5 128 Mbit . . . . . . MX26F128J3 Table 2. Bus Operations Command Sequence Read Array Output Standby RESET Read ID Read Disable Mode/ Query Power Down Mode Read Read Status Status (WSM off) (WSM on) Write Notes RESET 4,5,6 VIH VIH VIH VIL VIH Enabled VIL VIH See Figure 2 X VIH VIH VIH Enabled VIL VIH X X 6,10,11 VIH Enabled VIH VIL X VPENH CE0,CE1,CE2(1) Enabled Enabled Disabled X OE (2) WE (2) Address VPEN Q (3) VIL VIH X X VIH VIH X X X X X X High Z X X X X Enabled Enabled VIL VIH VIL VIH See X Table 6 X X Note 9 Data out Data out High Z High Z Note 8 STS (default mode) High Z (7) X X High Z High Z (7) (7) High Z (7) Q7=Data out Data in Q15-8=High Z Q6-0=High Z X NOTES: 1. See Table 1 on page 7 for valid CE configurations. 2. OE and WE should never be enabled simultaneously. 3. DQ refers to Q0-Q7 if BYTE is low and Q0-Q15 if BYTE is high. 4. Refer to DC Characteristics. When VPEN < VPENLK , memory contents can be read, but not altered. 5. X can be VIL or VIH for control and address pins, and VPENLK or VPENH for VPEN . See DC Characteristics for VPENLK and VPENH voltages. 6. In default mode, STS is VOL when the WSM is executing internal block erase, program, or lock-bit configuration algorithms. It is VOH when the WSM is not busy, or in reset/power-down mode. 7. High Z will be VOH with an external pull-up resistor. 8. See Section , "Read Identifier Codes" for read identifier code data. 9. See Section , "Read Query Mode Command" for read query data. 10.Command writes involving block erase, program, or lock-bit configuration are reliably executed when VPEN= VPENH and VCC is within specification. 11.Refer to Table 3 on page 10 for valid DIN during a write operation. P/N:PM0960 REV. 1.1,OCT. 18, 2004 6 MX26F128J3 FUNCTION The device includes on-chip program/erase control circuitry. The Write State Machine (WSM) controls block erase and byte/word/page program operations. Operational modes are selected by the commands written to the Command User Interface (CUI). The Status Register indicates the status of the WSM and when the WSM successfully completes the desired program or block erase operation. STANDBY When CE0, CE1 and CE2 disable the device (see table1) and place it in standby mode. The power consumption of this device is reduced. Data input/output are in a highimpedance(High-Z) state. If the memory is deselected during block erase, program or lock-bit configuration, the internal control circuits remain active and the device consume normal active power until the operation completes. POWER-DOWN READ The device has three read modes, which accesses to the memory array, the Device Identifier or the Status Register independent of the VPEN voltage. The appropriate read command are required to be written to the CUI. Upon initial device powerup or after exit from powerdown, the device automatically resets to read array mode. In the read array mode, low level input to CE0, CE1, CE2 and OE, high level input to WE and RESET and address signals to the address inputs (A23-A0) output the data of the addressed location to the data input/ output (Q15~Q0). When reading information in read array mode, the device defaults to asynchronous page mode. In this state, data is internally read and stored in a high-speed page buffer. A2:0 addresses data in the page buffer. The page size is 4 words or 8 bytes. Asynchronous word/byte mode is supported with no additional commands required. When RESET pin is at VIL the device is in the powerdown mode and its power consumption is substantially low around 25uA. During read modes, the memory is deselected and the data input/output are in a highimpedance(High-Z) state. To return from power down mode requires RESET pin at VIH. After return from powerdown, the CUI is reset to Read Array , and the Status Register is set to value 80H. During block erase program or lock-bit configuration modes, RESET pin at VIL will abort either operation. Memory array data of the block being altered become invalid. In default mode, STS transitions low and remains low for a maximum time of tPLPH+tPHRH until the reset operation is complete. Memory contents being altered are no longer valid; the data may be partially corrupted after a program or partially altered after an erase or lockbit configuration. Time tPHWL is required after RESET goes to logic-high (VIH) before another command can be written. WRITE Writes to the CUI enables reading of memory array data, device identifiers and reading and clearing of the Status Register and when VPEN=VPENH block erasure program and lock-bit configuration. The CUI is written when the device is enable, WE is active and OE is at high level. Address and data are latched on the earlier rising edge of WE and CE. Standard micro-processor write timings are used. READ QUERY The read query operation outputs block status information, CFI (Common Flash Interface) ID string, system interface information, device geometry information and MXIC extended query information. OUTPUT DISABLE When OE is at VIH, output from the devices is disabled. Data input/output are in a high-impedance(High-Z) state. P/N:PM0960 REV. 1.1,OCT. 18, 2004 7 MX26F128J3 COMMAND DEFINITIONS Device operations are selected by writing specific address and data sequences into the CUI. Table 3 defines the valid register command sequences. When VPEN