NT7702
240 Output LCD Segment/Common Driver
Features
(Segment mode) ! Shift Clock frequency: 20 MHz (Max.) (VDD = 5 V ± 10%) ! Adopts a data bus system ! 4-bit/8-bit parallel input modes are selectable with a mode (MD) pin ! Automatic transfer function with an enable signal ! Automatic counting function when in the chip select mode, causes the internal clock to be stopped by automatically counting 240 bits of input data (Common mode) ! Shift clock frequency : 4.0 MHz (Max.) ! Built-in 240-bits bidirectional shift register (divisible into 120-bits x 2) ! Available in a single mode (240-bits shift register) or in a dual mode(120-bits shift register x 2) 1. Y1 → Y240 Single mode 2. Y240 → Y1 Single mode 3. Y1 → Y120, Y121 → Y240 Dual mode 4. Y240 → Y121, Y120 → Y1 Dual mode The above 4 shift directions are pin-selectable (Both for segment mode and common mode) ! ! ! ! ! ! ! ! Supply voltage for LCD driver: 15.0 to 30.0 V Number of LCD driver outputs: 240 Low output impedance Low power consumption Supply voltage for the logic system: +2.5 to +5.5 V COMS process Package: 272pin TCP (Tape Carrier Package) Not designed or rated as radiation hardened
General Description
The NT7702 is a 240-bit output segment/common driver LSI suitable for driving large scale dot matrix LCD panels using as PDA/personal computers/work stations. Through the use of SST (Super Slim TCP) technology, it is ideal for substantially decreasing the size of the frame section of the LCD module. The NT7702 is good as both a segment driver and as a common driver, and a low power consuming, highprecision LCD panel display can be assembled using the NT7702. In the segment mode, the data input is selected as 4bit parallel input mode or as 8bit parallel input mode by a mode (MD) pin. In the common mode, the data input/output pins are bi-directional and the four data shift directions are pin-selectable.
Pin Configuration
D U M M Y Y 2 4 0 Y 2 3 9 Y 2 3 8 Y 2 3 7 Y 2 3 6 Y 1 2 3 Y 1 2 2 Y 1 2 1 Y 1 2 0 Y 1 1 9 Y 1 1 8 Y 5 Y 4 Y 3 Y 2 Y 1 D U M M Y
272 271 270 269 268
155 154 153 152 151 150
37 36 35 34 33
NT7702
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 DV VVVVVVS EDDDDDDDDXD L E F L MNVNVVVVVD U00145SD/ I 01234567C I P I R/ DCSC54100U MLL23LSDCO KS O R S R32RRM M LL 2 P 1 RR M Y O Y F F
1
V1.0
NT7702
Pad Configuration
282 59
x
283 Dummy Pad
x
58 45
x
x
NT7702
Dummy Pad
ALK_R
x
296
ALK_L
x
x
x
1
44
Block Diagram
V0R V12R V43R V5R Y1 Y2 Y239 Y240
FR Level Shifter
DISPOFF
V5L
240 Bits 4 Level Driver
/240
V43L V12L
240 Bits Level Shifter
EIO1 Active Control EIO2
/16 /16 /16 /16 /16 /240
V0L
240 Bits Line Latch/Shift Register
LP XCK
8Bits2 Data Latch Control Logic
Data Latch Control
L/R MD S/C
/8
SP Conversion & Data Control (4 to 8 or 8 to 8)
D0
D1
D2
D3
D4
D5
D6
D7
VDD
VSS VSS
2
x
xx
xx
NT7702
Pin Description
Pin No. 1, 2 3 4 5 6 7 8 9 10 - 16 17 18 19 20 21 22 23 24 25, 27 26 28 29 30 31, 32 33 - 272 Designation V0L V12L V43L V5L VSS VDD S/C EIO2 D0 - D6 D7 XCK DISPOFF LP EIO1 FR L/R MD NC VSS V5R V43R V12R V0R Y1 - Y240 I/O P P P P P P I I/O I I I I I I/O I I I P P P P P O Power supply for LCD driver Power supply for LCD driver Power supply for LCD driver Power supply for LCD driver Ground (0V), these two pads must be connected to each other Power supply for the logic system (+2.5 to +5.5V) Segment mode/common mode selection Input/output for chip select or data of the shift register Display data input for segment mode Display data input for Segment mode/ Dual mode data input Display data shift clock input for segment mode Control input for deselect output level Latch pulse input/shift clock input for the shift register Input/output for chip select or data of the shift register AC-converting signal input for LCD driver waveform Display data shift direction selection Mode selection input No connected Ground (0V), these two pads must be connected to each other Power supply for LCD driver Power supply for LCD driver Power supply for LCD driver Power supply for LCD driver LCD driver output Description
3
NT7702
Pad Description
Pad No. 1, 2 3, 4 5, 6 7, 8 9, 10 11, 12 - 23, 24 25, 26 27, 28 29, 30 31, 32 33, 34 35, 36 37, 38 39, 40 41, 42 43, 44 45, 46 47, 48 49, 50 51 - 290 291, 292 293, 294 295, 296 Designation V5L VSS VDD S/C EIO2 D0 - D6 D7 XCK DISPOFF LP EIO1 FR L/R MD VSS V5R V43R V12R V0R Y1 - Y240 V0L V12L V43L I/O P P P I I/O I I I I I I/O I I I P P P P P O P P P Power supply for LCD driver Ground (0V), these two pads must be connected to each other Power supply for the logic system (+2.5 to +5.5V) Segment mode/common mode selection Input/output for chip select or data of the shift register Display data input for segment mode Display data input for Segment mode/ Dual mode data input Display data shift clock input for segment mode Control input for deselect output level Latch pulse input/shift clock input for the shift register Input/output for chip select or data of the shift register AC-converting signal input for LCD driver waveform Display data shift direction selection Mode selection input Ground (0V), these two pads must be connected to each other Power supply for LCD driver Power supply for LCD driver Power supply for LCD driver Power supply for LCD driver LCD driver output Power supply for LCD driver Power supply for LCD driver Power supply for LCD driver Description
4
NT7702
Input / Output Circuits
VDD
I
Input Signal
Applicable Pins L/R, S/C, D0 - D6, DISPOFF , LP, FR, MD
VSS
Input Circuit (1)
VDD
I Control Signal
Input Signal
Applicable Pins D7, XCK
VSS
VSS
Input Circuit (2)
5
NT7702
VDD
Input Signal Control Signal
VSS
VDD
VSS
Output Signal
I/O
Control Signal
VSS
Applicable Pins EIO1, EIO2
Input / Output Circuit
V0
V12
Control Signal 1 O Control Signal 3
Control Signal 2
Control Signal 4
Applicable Pins Y1 to Y240
V43 VSS V5
LCD Driver Output circuit
6
NT7702
Pad Description
Segment mode Symbol VDD VSS VOR, VOL V12R, V12L V43R, V43L V5R, V5L Function Logic system power supply pin connects to +2.5 to +5.5V Ground pin connects to 0V Power supply pin for LCD driver voltage bias " Normally, the bias voltage used is set by a resistor divider " Ensure that the voltages are set such that VSS ≤ V5 < V43 < V12 < V0 " To further reduce the differences between the output waveforms of the LCD driver output pins Y1 and Y240, externally connect ViR and ViL (I = 0, 12, 43, 5) Input pin for display data " In 4-bit parallel input mode, input data into the 4 pins D0 - D3. Connect D4 - D7 to VSS or VDD " In 8-bit parallel input mode, input data into the 8 pins D0 - D Clock input pin for taking display data " Data is read on the falling edge of the clock pulse Latch pulse input pin for display data " Data is latched on the falling edge of the clock pulse Direction selection pin for reading display data " When set to VSS level "L", data is read sequentially from Y240 to Y1 " When set to VDD level "H", data is read sequentially from Y1 to Y240 Control input pin for output deselect level " The input signal is level-shifted from logic voltage level to LCD driver voltage level, and controls LCD driver circuit. " When set to VSS level “L”, the LCD driver output pins (Y1-Y240) are set to level V5 DISPOFF " While DISPOFF set to “L”, the contents of the line latch are reset, but read the display data in the data latch are read regardless of the condition of DISPOFF . When the DISPOFF function is canceled, the driver outputs deselect level (V12 or V43), then outputs the contents of the date latch onto the next falling edge of the LP. That time, if DISPOFF removal time can not keep regulation what is shown AC characteristics, can not output the reading data correctly AC signal input for LCD driving waveform " The input signal is level-shifted from the logic voltage level to the driver voltage level and controls the LCD driver circuit. " Normally inputs a frame inversion signal The LCD driver output pin’s output voltage level can be set to the line latch output signal and the FR signal Mode selection pin " When set to VSS level “L”, 8-bit parallel input mode is set " When set to VDD level “H", 4-bit parallel input mode is set
D0 - D7
XCK LP
L/R
FR
MD
7
NT7702
Segment mode continued Symbol S/C Function Segment mode/common mode selection pin " When set to VDD level "H", segment mode is set " When set to VSS level "L", common mode is set Input/output pin for chip selection " When L/R input is at VSS level “L”, EIO1 is set for output, and EIO2 is set for input " When L/R input is at VDD level “H”, EIO1 is set for input, and EIO2 is set for output " During output, it is set to “H” while LP* XCK is “H” and after 240-bits of data have been read, it is set to “L” for one cycle (from falling edge to falling edge of XCK), after which it returns to “H” " During input, after the LP signal is input, the chip is selected while EI is set to “L”. After 240-bits of data have been read, the chip is deselected LCD driver output pins These correspond directly to each bit of the data latch, one level (V0, V12, V43, or V5) is selected and output
EIO1, EIO2
Y1 - Y240
Common mode Symbol VDD VSS V0R, V0L V12R, V12L V43R, V43L V5R, V5L Function Logic system power supply pin connects to +2.5 to +5.5V Ground pin connects to 0V Power supply pin for LCD driver voltage bias. " Normally, the bias voltage used is set by a resistor divider " Ensure the voltages are set such that VSS ≤ V5 Y1 Y240 ---------------------->Y1 Y240 ---------------------->Y1 last data
EIO2
EIO1 L/R D0~D7
EIO2
EIO1 L/R D0~D7
EIO2
EIO1 L/R D0~D7
XCK
XCK
XCK
MD
MD
MD
FR
FR
XCK LP MD FR D0~D7 VSS /8
4.2. Case of L/R = “H”
VDD D0~D7 FR MD LP XCK /8
XCK
XCK
FR
LP
LP
LP
D0~D7
D0~D7
D0~D7
L/R VSS EIO1 EIO2
L/R EIO1 EIO2
L/R EIO1 EIO2
Y1 ---------------------->Y240 (data taking flow) first data
Y1 ---------------------->Y240
Y1 ---------------------->Y240
last data
14
XCK
MD
MD
MD
FR
FR
FR
LP
LP
LP
NT7702
5. Timing waveform of 4-Device cascade Connection of Segment Drivers
FR
LP
XCK
First data D0~D7 n12 device A EI (device A) n12 device B n12 device C n12 device D
Last data n12
H L
EO (device A)
EO (device B)
EO (device C) n: 4-bit parallel mode 60 8-bit parallel mode 30
15
NT7702
6. Connection Examples for Common Drivers
First Last
Y240
Y1
Y240
Y1
Y240
Y1
D
EIO2 DISPOFF
EIO1
EIO2 DISPOFF
EIO1
EIO2 DISPOFF
EIO1
L/R
MD
L/R
MD
L/R
MD
CS
CS
CS
FR
FR
D7
D7
LP VSS (VDD) VSS VSS DISPOFF CS FR
LP
Single Mode (Shifting towards the left)
FR DISPOFF VSS VSS VSS (VDD) LP
MD
MD
D7
LP
LP
MD
D7
D7
D7
LP
LP
DISPOFF
DISPOFF
DISPOFF
L/R
L/R
D
EIO1
EIO2
EIO1
EIO2
EIO1
L/R
FR
FR
FR
EIO2
Y1
Y240
Y1
Y240
Y1
Y240
First
Last
Single Mode (Sifting towards the right)
16
LP
FR
NT7702
First1 Last1 First2 Last2
Y240
Y1
Y240
Y121 Y120
Y1
Y240
Y1
D1
EIO2 DISPOFF
EIO1
EIO2 DISPOFF
EIO1
EIO2 DISPOFF D7
EIO1
L/R
L/R
L/R
MD
MD
MD
FR
D7
D7
FR
LP D2 VSS (VDD) VDD VSS DISPOFF FR
Dual mode (Shifting towards the left)
FR DISPOFF VSS VDD VSS (VDD) D2 LP
MD
MD
D7
LP
LP
LP
DISPOFF
DISPOFF
DISPOFF
MD
D7
D7
LP
LP
L/R
L/R
D1
EIO1
EIO2
EIO1
EIO2
EIO1
L/R
FR
FR
FR
EIO2
Y1
Y240
Y1
Y120 Y121
Y240
Y1
Y240
First1
Last1 First2
Last2
Dual mode (Shifting towards the right)
17
LP
FR
NT7702
7. Precaution Be careful when connecting or disconnecting the power This LSI has a high-voltage LCD driver, so it may be permanently damaged by a high current, which may occar, if a voltage is supplied to the LCD driver power supply while the logic system power supply is floating. The details are as follows: ! ! When connecting the power supply, connect the LCD driver power after connecting the logic system power. Furthermore, when disconnecting the power, disconnect the logic system power after disconnecting the LCD driver power. We recommend that you connect a serial resistor (50-100 Ω) or fuse to the LCD driver power V0 of the system as a current limiting device. Also, set a suitable value of the resistor in consideration of LCD display grade.
In addition, when connecting the logic power supply, the logic condition of this LSI inside is insecure. Therefore connect the LCD driver power supply after resetting the logic condition of this LSI inside to DISPOFF function. After that, the DISPOFF cancel the function after the LCD driver power supply has become stable. Furthermore, when disconnecting the power, set the LCD driver output pins to level V5 on the DISPOFF function. After that, disconnect the logic system power after disconnecting the LCD driver power. When connecting the power supply, follow the recommended sequence shown.
VDD
VDD VSS VDD
DISPOFF
VSS V0
V0 VSS
18
NT7702
Absolute Maximum Rating*
DC Supply Voltage VDD . . . . . . . . . . . . -0.3V to +7.0V DC Supply Voltage V0 . . . . . . . . . . . . . -0.3V to +30V Input Voltage . . . . . . . . . . . . . . . . . -0.3V to VDD +0.3V Operating Ambient Temperature . . . . -30°C to +85°C Storage Temperature . . . . . . . . . . . . .-45°C to +125°C
*Comments
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device under these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability.
Electrical Characteristics
DC Characteristics Segment Mode (VSS = V5 = 0V, VDD = 2.5 - 5.5V, V0 = 15 to 30 V, and TA = -30 to +85°C, unless otherwise noted) Parameter Operating Voltage 1 Operating Voltage 2 Input high voltage Input low voltage Output high voltage Output low voltage Input leakage current 1 Symbol VDD V0 VIH VIL VOH VOL IIH Min. 2.5 15 0.8 VDD VDD - 0.4 Typ. Max. 5.5 30 0.2 VDD +0.4 +1 Unit V V V V V V µA µA kΩ µA mA mA mA D0 - 7, XCK, LP, L/R, FR, MD, S/C, EIO1, EIO2, DISPOFF pins EIO1, EIO2 pins, IOH = -0.4mA EIO1, EIO2 pins, IOL = +0.4mA D0 - 7, XCK, LP, L/R, FR, MD, S/C, EIO1, EIO2, DISPOFF pins, VI = VDD D0 - 7, XCK, LP, L/R, FR, MD, S/C, EIO1, EIO2, DISPOFF pins, VI = VSS V0 = +30.0V V0 = +20.0V VSS pin, Note 1 VDD pin, Note 2 VDD pin, Note 3 V0 pin, Note 4 Y1 - Y240 pins, ∆V O N = 0.5V Condition
Input leakage current 2
IIL
-
1.5 2.0 -
-1 2.0 2.5 10 2 12 1.5
Output resistance Stand-by current Consumed current (1) (Deselection) Consumed current (2) (Selection) Consumed current
RON ISB IDD1 IDD2 I0 -
Note: 1. VDD = +5.0V, V0 = +30V, VI = VSS 2. VDD = +5.0V, V0 = +30V, fXCK = 20MHz, No-load, EI = VDD The input data is turned over by the data taking clock (4-bit Parallel input mode) 3. VDD = +5.0V, V0 = +30V, fXCK = 20MHz, No-load. EI = VSS The input data is turned over by the data taking clock (4-bit parallel input mode) 4. VDD = +5.0V, V0 = +30V, fXCK = 20MHz, fLP = 41.6kHz. fFR = 80 Hz, No-load The input data is turned over by the data taking clock (4-bit parallel-input mode)
19
NT7702
Common Mode (VSS = V5 = 0V, VDD = 2.5 - 5.5V, V0 = 15 to 30 V, and TA = -30 to +85°C, unless otherwise noted) Parameter Operating Voltage Operating Voltage Input high voltage Input low voltage Output high voltage Output low voltage Input leakage current 1 Symbol VDD V0 VIH VIL VOH VOL IIH Min. 2.5 15 0.8 VDD VDD - 0.4 Typ. Max. 5.5 30 0.2 VDD +0.4 +10.0 Unit V V V V V V µA µA µA kΩ µA µA µA D0 - 7, XCK, LP, L/R, FR, MD, S/C, EIO1, EIO2, DISPOFF pins EIO1, EIO2 pins, IOH = -0.4mA EIO1, EIO2 pins, IOL = +0.4mA D0 - 6, LP, L/R, FR, MD, S/C and DISPOFF pins, VI = VDD D0 - 7, XCK, LP, L/R, FR, MD, S/C, EIO1, EIO2, DISPOFF pins, VI = VSS XCK, EIO1, EIO2, D7 pins V0 = +30.0V V0 = +20.0V VSS pin, Note 1 VDD pin, Note 2 V0 pin, Note 2 Y1 - Y240 pins, ∆V O N = 0.5V Condition
Input leakage current 2 Input pull down current Output resistance Stand-by current Consumed current (1) Consumed current (2)
IIL IPD RON
-
1.5 2.0 -
-10.0 100 2.0 2.5 75 120 240
ISB IDD I0
-
Note: 1. VDD = +5.0V, V0 = +30.0V, VI = VSS 2. VDD = +5.0V, V0 = +30.0V, fLP = 41.6KHz, fFR = 80Hz, case of 1/480 duty operation, No-load
20
NT7702
AC Characteristics Segment Mode 1 (VSS = V5 = 0V, VDD = 4.5 - 5.5V, V0 = 15 to 30V, and TA = -30 to +85°C, unless otherwise noted) Parameter Shift clock period Shift clock "H" pulse width Shift clock "L" pulse width Data setup time Data hole time Latch pulse "H" pulse width Shift clock rise to Latch pulse rise time Shift clock fall to Latch pulse fall time Latch pulse rise to Shift clock rise time Latch pulse fall to Shift clock rise time Input signal rise time Input signal fall time Enable setup time DISPOFF Removal time DISPOFF enable pulse width Output delay time (1) Output delay time (2) Output delay time (3) Symbol tWCK tWCKH tWCKL tDS tDH tWLPH tLD tSL tLS tLH tr tf tS tSD tWDL tD tpd1, tpd2 tpd3 10 100 1.2 Min. 50 15 15 10 12 15 0 30 25 25 Typ. 30 1.2 1.2 50 50 Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns µs ns µs µs CL = 15pF CL = 15pF CL = 15pF Note 2 Note 2 Condition tr, tf 10ns, Note 1
Note 1. Take the cascade connection into consideration. 2. (tCK-tWCKII-twckl)/2 is the maximum in the case of high speed operation.
21
NT7702
Segment Mode 2 (VSS = V5 = 0V, VDD = 3.0 - 4.5V, V0 = 15 to 30V, and TA = -30 to +85°C, unless otherwise noted) Parameter Shift clock period Shift clock "H" pulse width Shift clock "L" pulse width Data setup time Data hole time Latch pulse "H" pulse width Shift clock rise to Latch pulse rise time Shift clock fall to Latch pulse fall time Latch pulse rise to Shift clock rise time Latch pulse fall to Shift clock fall time Input signal rise time Input signal fall time Enable setup time DISPOFF Removal time DISPOFF enable pulse width Output delay time (1) Output delay time (2) Output delay time (3) Symbol tWCK tWCKH tWCKL tDS tDH tWLPH tLD tSL tLS tLH tr tf tS tSD tWDL tD tpd1, tpd2 tpd3 15 100 1.2 Min. 66 23 23 15 23 30 0 50 30 30 Typ. 41 1.2 1.2 50 50 Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns µs ns µs µs CL = 15pF CL = 15pF CL = 15pF Note 2 Note 2 Condition tr, tf 10ns, Note 1
Note 1. Take the cascade connection into consideration. 2. (tCK-tWCKII-tWCKL)/2 is the maximum in the case of high speed operation.
22
NT7702
Segment Mode 3 (VSS = V5 = 0V, VDD = 2.5 - 3.0V, V0 = 15 to 30V, and TA = -30 to +85°C, unless otherwise noted) Parameter Shift clock period Shift clock "H" pulse width Shift clock "L" pulse width Data setup time Data hole time Latch pulse "H" pulse width Shift clock rise to Latch pulse rise time Shift clock fall to Latch pulse fall time Latch pulse rise to Shift clock rise time Latch pulse fall to Shift clock fall time Input signal rise time Input signal fall time Enable setup time DISPOFF Removal time DISPOFF enable pulse width Output delay time (1) Output delay time (2) Output delay time (3) Symbol tWCK tWCKH tWCKL tDS tDH tWLPH tLD tSL tLS tLH tr tf tS tSD tWDL tD tpd1, tpd2 tpd3 15 100 1.2 Min. 82 28 28 20 23 30 0 65 30 30 Typ. 57 1.2 1.2 50 50 Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns µs ns µs µs CL = 15pF CL = 15pF CL = 15pF Note 2 Note 2 Condition tr, tf 10ns, Note 1
Note 1. Take the cascade connection into consideration. 2. (tCK-tWCKII-tWCKL)/2 is the maximum in the case of high speed operation.
23
NT7702
Timing waveform of the Segment Mode
tWLPH
LP
tLD tLS
tSL
tLH tWCKH
tWCKL
XCK
tr
tr tWCK
tDS
tDH
D0 - D7
LAST DATA
TOP DATA
tWDL
tSD
DISPOFF
LP
1 2 n
XCK
tS
EI
tD
EO
n: 4-bit parallel mode 60 8-bit parallel mode 30
FR
tpd1
LP
tpd2
DISPOFF
tpd3
Y1 - Y240
24
NT7702
Common Mode (VSS = V5 = 0V, VDD = 2.5 - 5.5V, V0 = 15 to 30V and TA = -30 to +85°C, unless otherwise noted) Parameter Shift clock period Shift clock "H" pulse width Data setup time Data hole time Input signal rise time Input signal fall time DISPOFF Removal time DISPOFF enable pulse width Output delay time (1) Output delay time (2) Output delay time (3) Symbol tWLP tWLPH 30 tSU tH tr tf tSD tWDL tDL tpd1, tpd2 tpd3 100 1.2 30 50 50 50 200 1.2 1.2 ns ns ns ns ns ns µs ns µs µs CL = 15pF CL = 15pF CL = 15pF VDD = +2.5 - +4.5V Min. 250 15 Typ. Max. Unit ns ns Condition tr, tf 20ns VDD = +5.0V 10%
25
NT7702
Timing Characteristics of Common Mode
tWLP
LP
tr
tWLPH tSU
tf tH
EIO2 (DI7)
tDL
EIO1
tWDL
tSD
DISPOFF
FR
tpd1
LP
tpd2
DISPOFF
tpd3
Y1 - Y240
26
NT7702
Application Circuit (for reference only)
SEG640 SEG639
EIO1
Y1~Y240
FR LP DISPOFF XCK
MD S/C L/R D0~D7 EIO2
EIO1
Y1~Y240
FR LP DISPOFF
MD S/C L/R D0~D7 EIO2
1920*480 DOT MATRIX LCD PANEL
XCK
EIO1
Y1~Y240
FR LP DISPOFF XCK
MD S/C L/R D0~D7 EIO2 EIO1
Y1~Y240
SEG3 SEG2 SEG1 C O M 4 7 9 C O M 4 8 0
MD FR LP DISPOFF XCK S/C L/R D0~D7 EIO2
C O M 1
C O M 2
C O M 3
Y1~Y240
Y1~Y240
XCK
XCK
Y1~Y240
DISPOFF
DISPOFF
NT7702*3
D0~D7
D0~D7
D0~D7
EIO1
EIO2
EIO1
EIO2
EIO1
DISPOFF
EIO2
S/C
S/C
S/C
L/R
L/R
L/R
MD
MD
MD
XCK
LP
LP
FR
FR
FR
LP
50~100 Ω
YD
(case of 1/n bias)
DISPOFF
XCK
FR
LP
R
R
(n-4)R
R
R
LCD controller
VEE
V0
V1
V2
V3
V4
V5
VDD
VSS
27
XD0~XD7
NT7702*4
/8
/5 /5
/8
NT7702
Bonding Diagram
11720um 282 59
x
283
x
58 1030um 45
x
x
NT7702
296
ALK_L
Y
Dummy Pad
(0,0)
X
Dummy Pad
ALK_R
x
x
x
x
1
44
Pad Location
Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Designation V5L V5L VSS VSS VDD VDD SC SC EIO2 EIO2 D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7 XCK XCK DISPOFF DISPOFF X -5440 -5280 -5120 -4960 -4800 -4640 -2400 -2240 -2080 -1920 -1760 -1600 -1440 -1280 -1120 -960 -800 -640 -480 -320 -160 0 160 320 480 640 800 960 1120 1280 Y -440 -440 -440 -440 -440 -440 -440 -440 -440 -440 -440 -440 -440 -440 -440 -440 -440 -440 -440 -440 -440 -440 -440 -440 -440 -440 -440 -440 -440 -440 Pad No. 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Designation LP LP EIO1 EIO1 FR FR L/R L/R MD MD VSS VSS V5R V5R V43R V43R V12R V12R V0R V0R Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 X 1440 1600 1760 1920 2080 2240 2400 2560 2720 2880 4960 5120 5280 5440 5779 5779 5779 5779 5779 5779 5779 5779 5779 5779 5779 5779 5779 5779 5575 5525 Y -440 -440 -440 -440 -440 -440 -440 -440 -440 -440 -440 -440 -440 -440 -300 -250 -200 -150 -100 -50 0 50 100 150 200 250 300 350 440 440
28
x
xx
xx
NT7702
Pad Location (continued)
Pad No. 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Designation Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Y21 Y22 Y23 Y24 Y25 Y26 Y27 Y28 Y29 Y30 Y31 Y32 Y33 Y34 Y35 Y36 Y37 Y38 Y39 Y40 Y41 Y42 Y43 Y44 Y45 Y46 Y47 Y48 Y49 Y50 X 5475 5425 5375 5325 5275 5225 5175 5125 5075 5025 4975 4925 4875 4825 4775 4725 4675 4625 4575 4525 4475 4425 4375 4325 4275 4225 4175 4125 4075 4025 3975 3925 3875 3825 3775 3725 3675 3625 3575 3525 Y 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 Pad No. 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 139 139 140 Designation Y51 Y52 Y53 Y54 Y55 Y56 Y57 Y58 Y59 Y60 Y61 Y62 Y63 Y64 Y65 Y66 Y67 Y68 Y69 Y70 Y71 Y72 Y73 Y74 Y75 Y76 Y77 Y78 Y79 Y80 Y81 Y82 Y83 Y84 Y85 Y86 Y87 Y88 Y89 Y90 X 3475 3425 3375 3325 3275 3225 3175 3125 3075 3025 2975 2925 2875 2825 2775 2725 2675 2625 2575 2525 2475 2425 2375 2325 2275 2225 2175 2125 2075 2025 1975 1925 1875 1825 1775 1725 1675 1625 1575 1525 Y 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440
29
NT7702
Pad Location (continued)
Pad No. 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 Designation Y91 Y92 Y93 Y94 Y95 Y96 Y97 Y98 Y99 Y100 Y101 Y102 Y103 Y104 Y105 Y106 Y107 Y108 Y109 Y110 Y111 Y112 Y113 Y114 Y115 Y116 Y117 Y118 Y119 Y120 Y121 Y122 Y123 Y124 Y125 Y126 Y127 Y128 Y129 Y130 X 1475 1425 1375 1325 1275 1225 1175 1125 1075 1025 975 925 875 825 775 725 675 625 575 525 475 425 375 325 275 225 175 125 75 25 -25 -75 -125 -175 -225 -275 -325 -375 -425 -475 Y 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 Pad No. 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 Designation Y131 Y132 Y133 Y134 Y135 Y136 Y137 Y138 Y139 Y140 Y141 Y142 Y143 Y144 Y145 Y146 Y147 Y148 Y149 Y150 Y151 Y152 Y153 Y154 Y155 Y156 Y157 Y158 Y159 Y160 Y161 Y162 Y163 Y164 Y165 Y166 Y167 Y168 Y169 Y170 X -525 -575 -625 -675 -725 -775 -825 -875 -925 -975 -1025 -1075 -1125 -1175 -1225 -1275 -1325 -1375 -1425 -1475 -1525 -1575 -1625 -1675 -1725 -1775 -1825 -1875 -1925 -1975 -2025 -2075 -2125 -2175 -2225 -2275 -2325 -2375 -2425 -2475 Y 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440
30
NT7702
Pad Location (continued)
Pad No. 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 Designation Y171 Y172 Y173 Y174 Y175 Y176 Y177 Y178 Y179 Y180 Y181 Y182 Y183 Y184 Y185 Y186 Y187 Y188 Y189 Y190 Y191 Y192 Y193 Y194 Y195 Y196 Y197 Y198 Y199 Y200 Y201 Y202 Y203 Y204 Y205 Y206 Y207 Y208 Y209 X -2525 -2575 -2625 -2675 -2725 -2775 -2825 -2875 -2925 -2975 -3025 -3075 -3125 -3175 -3225 -3275 -3325 -3375 -3425 -3475 -3525 -3575 -3625 -3675 -3725 -3775 -3825 -3875 -3925 -3975 -4025 -4075 -4125 -4175 -4225 -4275 -4325 -4375 -4425 Y 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 Pad No. 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 Designation Y210 Y211 Y212 Y213 Y214 Y215 Y216 Y217 Y218 Y219 Y220 Y221 Y222 Y223 Y224 Y225 Y226 Y227 Y228 Y229 Y230 Y231 Y232 Y233 Y234 Y235 Y236 Y237 Y238 Y239 Y240 V0L V0L V12L V12L V43L V43L ALK_R ALK_L X -4475 -4525 -4575 -4625 -4675 -4725 -4775 -4825 -4875 -4925 -4975 -5025 -5075 -5125 -5175 -5225 -5275 -5325 -5375 -5425 -5475 -5525 -5575 -5779 -5779 -5779 -5779 -5779 -5779 -5779 -5779 -5779 -5779 -5779 -5779 -5779 -5779 5668 -5668 Y 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 440 350 300 250 200 150 100 50 0 -50 -100 -150 -200 -250 -300 -323 -323
31
NT7702
Dummy Pad Location (Total: 35 pad)
NO 1 2 3 4 5 6 7 8 9 X -5600 -4480 -4320 -4160 -4000 -3840 -3680 -3520 -3360 Y -440 -440 -440 -440 -440 -440 -440 -440 -440 NO 10 11 12 13 14 15 16 17 18 X -3200 -3040 -2880 -2720 -2560 3040 3200 3360 3520 Y -440 -440 -440 -440 -440 -440 -440 -440 -440 NO 19 20 21 22 23 24 25 26 27 X 3680 3840 4000 4160 4320 4480 4640 4800 5600 Y -440 -440 -440 -440 -440 -440 -440 -440 -440 NO 28 29 30 31 32 33 34 35 X 5779 5779 5779 5635 -5635 -5779 -5779 -5779 Y -410 -350 410 440 440 410 -350 -410
32
NT7702
Package Information
A1 A2
D3 224 m2 n D1
D3
A1 A2
C1 m1 D3 m1 m2
C2 n m1 m1
C1 D3
D1 m2 14 n m2 J r
NT7702
H m1 n C2 71 m1 n H
D1 m2 r J 14 n m2
D3 m1 C1 n
D3 m1 n C1
B
D2
B
Chip Outline Dimensions
Symbol A1 A2 B C1 C2 D1 D2 Dimensions in um 225 81 260 105 75 50 160 Symbol D3 m1 m2 n r H J Dimensions in um 60 57 37 59 35 117 111
unit: um
33
NT7702
TCP Pin Layout
DUMMY Y1 Y2 Y3 Y4 Y5 33 34 35 36 37
DUMMY 32 31 30 29 28 27 26 25 24 23 22 21 V0R V0R V12R V43R V5R NC VSS NC MD L/R FR EIO1 LP DISPOFF XCK D7 D6 D5 D4 D3 D2 D1 D0 EIO2 S/C VDD VSS V5L V43L V12L V0L V0L DUMMY
NT7702
20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
Y118 Y119 Y120 Y121 Y122 Y123
150 151 152 153 154 155
Y236 Y237 Y238 Y239 Y240 DUMMY
268 269 270 271 272
(Copper Side View)
34
NT7702
External view of TCP pins
35
NT7702
Cautions concerning storage: 1. When storing the product, it is recommended that it be left in its shipping package. After the seal of the packing bag has been broken, store the products in a nitrogen atmosphere. 2. Storage conditions : Storage state Storage conditions Temperature: 5 to 30; humidity: 80%RH or less. unopened (less than 90 days) After seal of broken (less than 30 days) Room temperature, dry nitrogen atmosphere 3. Don't store in a location exposed to corrosive gas or excessive dust. 4. Don't store in a location exposed to direct sunlight of subject to sharp changes in temperature. 5. Don't store the product such that it is subjected to an excessive load weight, such as by stacking. 6. Deterioration of the plating may occur after long-term storage, so special care is required. It is recommended that the products be inspected before use.
36
NT7702
Tray Information
f
Y
e
c
W1
W2
T2
T1
X
X
d
Y
g h
W1 W2 a g h T2 T1 b e
f
SECTION X-X
Symbol a b c d e f
Dimensions in mm 1.46 2.04 12.14 13.35 1.60 1.40
Symbol g h W1 W2 T1 T2
SECTION Y-Y
5*33
Dimensions in mm 0.84 4.20 76.0 68.0 71.0 68.3
37
NT7702
Ordering Information
Part No. NT7702H-BDT NT7702H-TABF4 Package Au bump on chip tray TCP Form
38
工商网监
湘ICP备2023018690号
