OV9625

Omni General Description ision TM Advanced Information Preliminary Datasheet OV9625 Color CMOS SXGA (1.3 MPixel) CAMERACHIPTM OV9121 B&W CMOS SXGA (1.3 MPixel) CAMERACHIPTM Applications • • • • • • Digital still cameras PC camera/dual mode Video conference applications Machine vision Security cameras Biometrics The OV9625 (color) and OV9121 (black and white) are high-performance 1.3 mega-pixel CAMERACHIPSTM for digital still image and video camera products. Both devices incorporate a 1280 x 1024 (SXGA) image array and an on-chip 10-bit A/D converter capable of operating at up to 15 frames per second (fps) at full resolution and an improved micro lens design to decrease shading. Proprietary sensor technology utilizes advanced algorithms to cancel Fixed Pattern Noise (FPN), eliminate smearing, and drastically reduce blooming. The control registers allow for flexible control of timing, polarity, and CameraChip operation, which, in turn, allows the engineer a great deal of freedom in product design. Key Specifications SXGA VGA Core Power Supply Analog I/O Power Active Requirements Standby Output Formats (10-bit) Lens Size Max. Image SXGA Transfer Rate VGA Sensitivity S/N Ratio Dynamic Range Scan Mode Gamma Correction SXGA Electronics Exposure VGA Pixel Size Dark Current Fixed Pattern Noise Image Area Package Dimensions Array Size 1280 x 1024 640 x 480 2.5VDC + 10% 3.3VDC + 10% 3.3VDC + 10% < 50 mA < 10 µA Raw RGB Data 1/2" 15 fps 30 fps 1.0 V/Lux-sec 54 dB 60 dB (due to ADC limitations) Progressive N/A Up to 1050:1 Up to 500:1 5.2 µm x 5.2 µm 28 mV/s < 0.03% of VPEAK-TO-PEAK 6.66 mm x 5.32 mm .560 in. x .560 in. Features • • • • • • • • • • • • Optical Black Level Calibration (BLC) Improved micro lens design to decrease shading Video or snapshot operations Programmable/Auto Exposure and Gain Control Programmable/Auto White Balance Control Horizontal and vertical sub-sampling (4:2 and 4:2) Programmable image windowing Variable frame rate control On-chip R/G/B channel and luminance average counter Internal/External frame synchronization SCCB slave interface Power-on reset and power-down mode Figure 1 OV9625/OV9121 Pin Diagram ADGND ADVDD 20 XCLK2 XCLK1 VrAD2 19 18 ASUB 17 AGND 16 AVDD 15 VcCHG 14 FSIN 13 VGA 12 EXPSTB 11 SCCB_E 10 RESET 9 8 7 43 NC 44 NC 45 SIO_D 46 SIO_C 47 VcCHG 48 SGND 1 SVDD 2 VrHIGH 3 NBIT 4 DEVDD 5 DEGND 6 VrLOW NC FREX PWDN DGND 23 DVDD 22 D4 D3 D2 D1 25 D0 24 Ordering Information PCLK 31 32 33 34 35 36 30 29 28 27 26 21 Product OV09625-C00A (Color, SXGA, VGA) OV09121-C00A (B&W with microlens, SXGA, VGA) Package CLCC-48 CLCC-48 D5 D6 D7 D8 D9 DOVDD DOGND HREF CHSYNC VSYNC NC OV9625/OV9121 37 38 39 40 41 42 Version 1.3, September 15, 2003 Proprietary to OmniVision Technologies 1 OV9625/OV9121 CMOS SXGA (1.3 MPixel) CAMERACHIP™ Omni ision Functional Description Figure 2 shows the functional block diagram of the OV9625/OV9121 image sensor. The OV9625/OV9121 includes: • Image Sensor Array (1280 x 1024 resolution) • Gain Control • Channel Balance • 10-Bit Analog-to-Digital Converter • Black Level Compensation • SCCB Interface • Digital Video Port • Timing Generator Figure 2 Functional Block Diagram D[9:0] PCLK Column Sense Amps AMP Channel Balance 10-Bit A/D Black Level Compensation Digital Video Port HREF HSYNC VSYNC Image Array (1312 x 1036) Gain Control Balance Control Control Register Bank Row Select PLL Timing Generator and Control Logic SCCB Slave Interface XCLK RESET PWDN FSI VGA FREX EXPSTB SIO_C SIO_D SCCB_E 2 Proprietary to OmniVision Technologies Version 1.3, September 15, 2003 Omni ision Functional Description Image Sensor Array The OV9625/OV9121 sensor is a 1/2-inch format CMOS imaging device. The sensor contains 1,359,232 pixels. Figure 3 shows the active regions of sensor array. 10-Bit Analog-to-Digital Converter The balanced signal then will be digitized by the on-chip 10-bit ADC. It can operate at up to 12 MHz, and is fully synchronous to the pixel clock. The actual conversion rate is determined by the frame rate. Figure 3 Sensor Array Region Column R o0BG w1G R 0 2 3 4 5 6 B G R G R G R B G B G B G G R G R G R B G B G B G G R G R G R B G B G B G G R G R G R B G B G B G G R G R G R B G B G B G G R G R G R 1024 Active Lines 1032 1033 1034 1035 B G B G G R G R B G B G G R G R B G B G G R G R B G B G G R G R B G B G G R G R B G B G G R G R Dummy Dummy B G G R 1306 1307 1308 1309 1310 1311 Black Level Compensation Dummy Dummy Dummy Dummy Optical Black Dummy Dummy Dummy Dummy 1 2 3 4 B G B G B G B G G R G R 5 G R G R B G B G G R G R B G B G G R G R B G B G G R G R 7G 8 B After the pixel data has been digitized, black level calibration can be performed before the data is output. The black level calibration block subtracts the average signal level of optical black pixels to compensate for the dark current in the pixel output. Black level calibration can be disabled by the user. 9G 10 11 B G Windowing OV9625/OV9121 allows the user to define window size or region of interest (ROI), as required by the application. Window size setting (in pixels) ranges from 2 x 4 to 1280 x 1024 (SXGA) or 2 x 2 to 640 x 480 (VGA), and can be anywhere inside the 1312 x 1036 boundary. Note that modifying window size or window position does not alter the frame or pixel rate. The windowing control merely alters the assertion of the HREF signal to be consistent with the programmed horizontal and vertical ROI. The default window size is 1280 x 1024. See Figure 4 and registers HREFST, HREFEND, VSTRT, VEND, and COMM for details. The maximum output window size is 1292 columns by 1024 rows. Note that after writing to register COMH (0x12) to change the sensor mode, registers related to the sensor’s cropping window will be reset back to its default value. The color filters are Bayer pattern. The primary color BG/GR array is arranged in line-alternating fashion. Of the 1,359,232 pixels, 1,310,720 are active. The other pixels are used for black level calibration and interpolation. The sensor array design is based on a field integration read-out system with line-by-line transfer and an electronic shutter with a synchronous pixel read-out scheme. Gain Control When the column sample/hold circuit has sampled one row of pixels, the pixel data will shift out one-by-one into an analog amplifier. The amplifier gain can either be programmed by the user or controlled by the internal automatic gain control circuit (AGC). The gain adjustment range is 0-24 dB. Figure 4 Windowing Column Start HREF R Column o w Column End Channel Balance Row Start The amplified signals are then balanced with a channel balance block. In this block, Red/Blue channel gain is increased or decreased to match Green channel luminance level and gamma correction is performed. The adjustment range is 54 dB. This function can be done manually by the user or with the internal automatic white balance controller (AWB). HREF Display Window Row End Sensor Array Boundary Version 1.3, September 15, 2003 Proprietary to OmniVision Technologies 3 OV9625/OV9121 CMOS SXGA (1.3 MPixel) CAMERACHIP™ Omni ision Sub-sampling Mode Default resolution for the OV9625/OV9121 is 1280 x 1024 pixels, with all active pixels being output (see Figure 5). The OV9625/OV9121 can be programmed to output in 640 x 480 (VGA) sized images for applications where higher resolution image capture is not required. Slave Operation Mode The OV9625/OV9121 can be programmed to operate in slave mode (default is master mode). When used as a slave device, the OV9625/OV9121 changes the HSYNC and VSYNC outputs to input pins for use as horizontal and vertical synchronization input triggers supplied by the master device. The master device must provide the following signals: 1. 2. 3. System clock MCLK to XCLK1 pin Horizontal sync MHSYNC to CHSYNC pin Vertical frame sync MVSYNC to VSYNC pin Figure 5 Pixel Array Column # i n n+1 n+2 n+3 Row # n+4 n+5 n+6 n+7 B G B G B G B G i+1 i+2 i+3 i+4 i+5 i+6 i+7 i+8 i+9 G R G R G R G R B G B G B G B G G R G R G R G R B G B G B G B G G R G R G R G R B G B G B G B G G R G R G R G R B G B G B G B G G R G R G R G R See Figure 7 for slave mode connections and Figure 8 for detailed timing considerations. In this mode, the clock for all devices should be the same. Otherwise, the devices will suffer from flickering at line frequency. Figure 7 Slave Mode Connection D[9:0] For VGA resolution, the following sub-sampling method is available: CHSYNC VSYNC MHSYNC MVSYNC MCLK Progressive Sub-sampling The entire array is sub-sampled for maximal image quality. Both horizontal and vertical pixels are sub-sampled to an aspect ration of 4:2 as illustrated in Figure 6. XCLK1 OV9625 (OV9121) Master Device Figure 8 Slave Mode Timing Figure 6 Sub-Sampling Mode T frame Column i+1 i+3 i+4 i+7 i+8 i+2 i+5 i+6 i+9 i VSYNC T VS HSYNC MCLK Tclk T line T HS Row n n+1 n+2 n+3 n+4 n+5 n+6 n+7 B G BG GR BG GR GR NOTE: 1) THS > 6 Tclk, Tvs > Tline 2) Tline = 1520 x Tclk (SXGA); Tline = 800 x Tclk (VGA) 3) Tframe = 1050 x Tline (SXGA); Tframe = 500 x Tline (VGA) B G BG GR BG GR GR Channel Average Calculator Skipped Pixels OV9625/OV9121 provides average output level data for the R/G/B channels along with frame-averaged luminance level. Access to the data is via the serial control port. Average values are calculated from 128 pixels per line (64 in VGA). 4 Proprietary to OmniVision Technologies Version 1.3, September 15, 2003 Omni ision Functional Description Reset The RESET pin (pin 10) is active high. There is an internal pull-down (weak) resistor in the sensor so the default status of the RESET pin is low. Figure 9 RESET Timing Diagram RESET 1ms 4096 External Clock Two methods of power-down or standby operation are available with the OV9625/OV9121. • Hardware power-down may be selected by pulling the PWDN pin (pin 7) high (+3.3VDC). When this occurs, the OV9625/OV9121 internal device clock is halted and all internal counters are reset. The current draw is less than 10 µA in this standby mode. • Software power-down can be effected by setting the COMC[4] register bit high. Standby current will be less then 1 mA when in software power-down. All register content is maintained in standby mode. There are two ways for a sensor reset: 1. Hardware reset - Pulling the RESET pin high and keeping it high for at least 1 ms. As shown in Figure 9, after a reset has been initiated, the sensor will be most stable after the period shown as 4096 External Clock. Software reset - Writing 0x80 to register 0x12 (see “COMH” on page 20) for a software reset. If a software reset is used, a reset operation done twice is recommended to make sure the sensor is stable and ready to access registers. When performing a software reset twice, the second reset should be initiated after the 4096 External Clock period as shown in Figure 9. SCCB Interface OV9625/OV9121 provides an on-chip SCCB serial control port that allows access to all internal registers, for complete control and monitoring of OV9625/OV9121 operation. Refer to OmniVision Technologies Serial Camera Control Bus (SCCB) Specification for detailed usage of the SCCB interface. 2. Video Output RGB Raw Data Output The OV9625 CAMERACHIP offers 10-bit RGB raw data output. Power-Down Mode The PWDN pin (pin 7) is active high. There is an internal pull-down (weak) resistor in the sensor so the default status of the PWDN pin is low. Figure 10 PWDN Timing Diagram PWDN Sensor Power Down B&W Output The OV9121 offers 10-bit luminance signal data output. Version 1.3, September 15, 2003 Proprietary to OmniVision Technologies 5 OV9625/OV9121 Digital Video Port MSB/LSB Swap CMOS SXGA (1.3 MPixel) CAMERACHIP™ Omni ision Line/Pixel Timing The OV9625/OV9121 digital video port can be programmed to work in either master or slave mode. In both master and slave modes, pixel data output is synchronous with PCLK (or MCLK if port is a slave), HREF and VSYNC. The default PCLK edge for valid data is the negative edge but may be programmed with register COMK[4] (see “COMK” on page 22) for the positive edge. Basic line/pixel output timing is illustrated in Figure 14 and Figure 15. To minimize image capture circuitry and conserve memory space, PCLK output can be programmed with register COMK[5] (see “COMK” on page 22) to be qualified by the active video period as defined by the HREF signal. See Figure 12 for details. OV9625/OV9121 has a 10-bit digital video port. The MSB and LSB can be swapped with the control registers. Figure 11 shows some examples of connections with external devices. Figure 11 Connection Examples MSB D9 D8 D7 D6 D5 D4 D3 D2 D1 LSB D0 OV9625 (OV9121) D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 External Device LSB D9 D8 D7 D6 D5 D4 D3 D2 D1 MSB D0 OV9625 (OV9121) D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 External Device Figure 12 PCLK Output Only at Valid Pixels PCLK PCLK active edge negative HREF PCLK PCLK active edge positive VSYNC Default 10-bit Connection Swap 10-bit Connection Pixel Output Pattern Table 1 shows the output data order from the OV9625/OV9121. The data output sequence following the first HREF and after VSYNC is: B0,0 G0,1 B0,2 G0,3… B0,1278 G0,1279. After the second HREF, the output is G1,0 R1,1 G1,2 R1,3… G1,1278 R1,1279…, etc. If the OV9625/OV9121 is programmed to output VGA resolution data, horizontal and vertical sub-sampling will occur. The default output sequence for the first line of output will be: B0,0 G0,1 B0,4 G0,5… B0,1276 G0,1277. The second line of output will be: G1,0 R1,1 G1,4 R1,5… G1,1276 R1,1277. MSB D9 D8 D7 D6 D5 D4 D3 D2 D1 LSB D0 OV9625 (OV9121) D7 D6 D5 D4 D3 D2 D1 D0 LSB D9 D8 D7 D6 D5 D4 D3 D2 D1 MSB D0 D0 D1 D2 D3 D4 D5 D6 D7 Table 1 R/C 0 B0,0 G1,0 B2,0 G3,0 1 Data Pattern 2 B0,2 G1,2 B2,2 G3,2 3 G0,3 R1,3 G2,3 R3,3 ... ... ... ... ... . . 1278 B0,1278 G1,1278 B2,1278 G3,1278 1279 G0,1279 R1,1279 G2,1279 R3,1279 External Device OV9625 (OV9121) External Device 0 1 2 3 . . 1022 1023 G0,1 R1,1 G2 R3,1 Default 8-bit Connection Swap 8-bit Connection B1022,0 G1022,1 B1022,2 G1022,3 G1023,0 R1023,1 G1023,2 R1023,3 B1022,1278 G1022,1279 G1023,1278 R1023,1279 6 Proprietary to OmniVision Technologies Version 1.3, September 15, 2003 Omni ision Functional Description Timing Generator In general, the timing generator controls the following functions: • Frame Exposure Mode Timing • Frame Rate Timing • Frame Rate Adjust Frame Rate Timing Default frame timing is illustrated in Figure 16 and Figure 17. Refer to Table 2 for the actual pixel rate at different frame rates. Table 2 Frame and Pixel Rates 15 24 10 16 7.5 12 6 9.6 5 8 Frame Rage (fps) Frame Exposure Mode Timing OV9625/OV9121 supports frame exposure mode. Typically the frame exposure mode must work with the aid of an external shutter. The frame exposure pin, FREX (pin 8) is the frame exposure mode enable pin and EXPSTB (pin 12) serves as the exposure start trigger for the sensor. There are two ways to set Frame Exposure mode: • Control both FREX and EXPSTB pins - Frame Exposure mode can be set by pulling both FREX and EXPSTB pins high at the same time (see Figure 19). • Control FREX only and keep EXPSTB low - In this case, the pre-charge time is tline and sensor exposure time is the period after pre-charge until the shutter closes (see Figure 18). When the external master device asserts the FREX pin high, the sensor array is quickly pre-charged and stays in reset mode until the EXPSTB pin is pulled low by the external master (sensor exposure time can be defined as the period between EXPSTB low to shutter close). After the FREX pin is pulled low, the video data stream is then clocked to the output port in a line-by-line manner. After completing one frame of data output, OV9625/OV9121 will output continuous live video data unless in single frame transfer mode. Figure 18 and Figure 19 show the detailed timing for this mode. For frame exposure, register AEC (0x10) must be set to 0xFF and register GAIN (0x00) should be no larger than 0x10 (maximum 2x gain). PCLK (MHz) NOTE: Based on 24 MHz external clock and internal PLL on, frame rate is adjusted by the main clock divide method. Frame Rate Adjust OV9625/OV9121 offers three methods of frame rate adjustment. 1. Clock prescaler (see “CLKRC” on page 20) By changing the system clock divide ratio, the frame rate and pixel rate will change together. This method can be used for dividing the frame/pixel rate by: 1/2, 1/3, 1/4 … 1/64 of the input clock rate. Line adjustment (see “COML” on page 24 and see “FRARL” on page 25) By adding dummy pixel timing in each line, the frame rate can be changed while leaving the pixel rate as is. Vertical sync adjustment By adding dummy line periods to the vertical sync period (see “ADDVSL” on page 25 and see “ADDVSH” on page 25), the frame rate can be altered while the pixel rate remains the same. 2. 3. After changing registers COML (0x2A) and FRARL (0x2B) to adjust the dummy pixels, it is necessary to write to register COMH (0x12) or CLKRC (0x11) to reset the counter. Generally, OmniVision suggests users write to register COMH (0x12) (to change the sensor mode) as the last one. However, if you want to adjust the cropping window, it is necessary to write to those registers after changing register COMH (0x12). To use COMH to reset the counter, it is necessary to generate a pulse on resolution control register bit COMH[6]. Version 1.3, September 15, 2003 Proprietary to OmniVision Technologies 7 OV9625/OV9121 Pin Description Table 3 Pin Number 01 02 03 04 05 06 07 08 09 10 11 CMOS SXGA (1.3 MPixel) CAMERACHIP™ Omni ision Pin Description Name SVDD VrHIGH NBIT DEVDD DEGND VrLOW PWDN FREX NC RESET SCCB_E Pin Type Power Analog Analog Power Power Analog Input (0)a Input (0) — Input (0) Input (0) Function/Description 3.3 V power supply for the pixel array Sensor high reference - bypass to ground using a 0.1 µF capacitor Sensor bit line reference - bypass to ground using a 0.1 µF capacitor 3.3 V power supply for the sensor array decoder Ground for the sensor array decoder Sensor low reference - bypass to ground using a 0.1 µF capacitor Power down mode enable, active high Snapshot trigger, used to activate a snapshot sequence No connection Chip reset, active high SCCB interface enable, active low Snapshot exposure start trigger 0: Sensor starts exposure - only effective in snapshot mode 1: Sensor stays in reset mode Sensor Resolution Selection 0: SXGA resolution (1280 x 1024) 1: VGA resolution (640 x 480) Frame synchronization input Sensor reference - bypass to ground using a 1 µF capacitor 3.3 V power supply for analog circuits Ground for analog circuits Ground for analog circuit substrate A/D converter reference - bypass to ground using a 0.1 µF capacitor 3.3 V power supply for A/D converter Ground for A/D converter 2.5 V power supply for digital circuits Ground for digital circuits Digital video output bit[0] Digital video output bit[1] Digital video output bit[2] Digital video output bit[3] Digital video output bit[4] 12 EXPSTB Input (0) 13 VGA Input (0) 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 FSIN VcCHG AVDD AGND ASUB VrAD2 ADVDD ADGND DVDD DGND D0 D1 D2 D3 D4 Input (0) Analog Power Power Power Analog Power Power Power Power Output Output Output Output Output 8 Proprietary to OmniVision Technologies Version 1.3, September 15, 2003 Omni ision Pin Description Table 3 Pin Number 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 a. Pin Description (Continued) Name XCLK1 XCLK2 PCLK D5 D6 D7 D8 D9 DOVDD DOGND HREF CHSYNC VSYNC NC NC NC SIO_D SIO_C VcCHG SGND Pin Type Input Output Output Output Output Output Output Output Power Power Output Output Output — — — I/O Input Analog Power Crystal clock input Crystal clock output Pixel clock output Digital video output bit[5] Digital video output bit[6] Digital video output bit[7] Digital video output bit[8] Digital video output bit[9] 3.3 V power supply for digital video port Ground for digital video port Horizontal reference output Horizontal synchronization output when chip is in master mode. Vertical synchronization output when chip is in master mode. No connection No connection No connection SCCB serial interface data I/O SCCB serial interface clock input Sensor reference - bypass to ground using a 1 µF capacitor Ground for pixel array. Function/Description Input (0) represents an internal pull-down low resistor. Version 1.3, September 15, 2003 Proprietary to OmniVision Technologies 9 OV9625/OV9121 CMOS SXGA (1.3 MPixel) CAMERACHIP™ Omni ision Electrical Characteristics Table 4 Absolute Maximum Ratings -40ºC to +125ºC VDD-A Supply Voltages (with respect to Ground) VDD-C VDD-IO All Input/Output Voltages (with respect to Ground) Lead Temperature, Surface-mount process ESD Rating, Human Body model NOTE: 3.3V 2.5V 3.3V -0.3V to VDD-IO+1V +230ºC 2000V Ambient Storage Temperature Exceeding the Absolute Maximum ratings shown above invalidates all AC and DC electrical specifications and may result in permanent device damage. Table 5 Symbol Supply VDD-A VDD-IO VDD-C IDD1 IDD2 IDD3 DC Characteristics (0°C < TA < 70°C) Parameter Min Typ Max Unit Supply voltage (DEVDD, ADVDD, AVDD, SVDD) Supply voltage (DOVDD) Supply voltage (DVDD) Active (Operating) Current Standby Current Standby Current 3.0 3.0 2.25 3.3 3.3 2.5 40 1 10 3.6 3.6 2.75 60 V V V mA mA µA Digital Inputs VIL VIH CIN Input voltage LOW Input voltage HIGH Input capacitor 2 10 0.8 V V pF Digital Outputs (standard loading 25 pF, 1.2 K: to 3 V) VOH VOL Output voltage HIGH Output voltage LOW 2.4 0.6 V V SCCB Inputs VIL VIH SIO_C and SIO_D SIO_C and SIO_D -0.5 2.5 0 3.3 1 VDD + 0.5 V V 10 Proprietary to OmniVision Technologies Version 1.3, September 15, 2003 Omni ision Electrical Characteristics Table 6 Symbol AC Characteristics (TA = 25°C, VDD = 3V) Parameter Min Typ Max Unit ADC Parameters B DLE ILE Analog bandwidth DC differential linearity error DC integral linearity error Settling time for hardware reset Settling time for software reset Settling time for VGA/XSGA mode change Settling time for register setting 12 0.5 1