P01N02LMB

NIKO-SEM N-Channel Logic Level Enhancement Mode Field Effect Transistor P01N02LMB SOT-23 (M3) D PRODUCT SUMMARY V(BR)DSS 25V RDS(ON) 180mΩ ID 1.2A 1. GATE 2. DRAIN 3. SOURCE G S ABSOLUTE MAXIMUM RATINGS (TC = 25 °C Unless Otherwise Noted) PARAMETERS/TEST CONDITIONS Gate-Source Voltage Continuous Drain Current Pulsed Drain Current Power Dissipation 1 SYMBOL VGS LIMITS ±15 1.2 1.0 12 0.6 0.5 -55 to 150 275 UNITS V TC = 25 °C TC = 100 °C ID IDM A TC = 25 °C TC = 100 °C PD Tj, Tstg TL W Operating Junction & Storage Temperature Range Lead Temperature ( /16” from case for 10 sec.) THERMAL RESISTANCE RATINGS THERMAL RESISTANCE Junction-to-Case Junction-to-Ambient 1 1 °C SYMBOL RθJC RθJA TYPICAL MAXIMUM 65 230 UNITS °C / W Pulse width limited by maximum junction temperature. ELECTRICAL CHARACTERISTICS (TC = 25 °C, Unless Otherwise Noted) PARAMETER SYMBOL TEST CONDITIONS STATIC Drain-Source Breakdown Voltage Gate Threshold Voltage Gate-Body Leakage Zero Gate Voltage Drain Current On-State Drain Current 1 LIMITS UNIT MIN TYP MAX V(BR)DSS VGS(th) IGSS IDSS ID(ON) 1 VGS = 0V, ID = 250 µA VDS = VGS, ID = 250 µA VDS = 0V, VGS = ±15V VDS = 20V, VGS = 0V VDS = 20V, VGS = 0V, TJ = 125 °C VDS = 10V, VGS = 10V VGS = 7V, ID = 1.2A VGS = 10V, ID = 1.2A VDS = 20V, ID = 1.2A 25 0.7 1.0 2.5 ±250 25 250 1.2 220 180 16 250 220 V nA µA A mΩ S Drain-Source On-State Resistance Forward Transconductance 1 RDS(ON) gfs 1 AUG-18-2001 NIKO-SEM N-Channel Logic Level Enhancement Mode Field Effect Transistor P01N02LMB SOT-23 (M3) DYNAMIC Input Capacitance Output Capacitance Reverse Transfer Capacitance Total Gate Charge 2 2 Ciss Coss Crss Qg Qgs Qgd 2 120 VGS = 0V, VDS = 15V, f = 1MHz 100 85 11 VDS = 0.5V(BR)DSS, VGS = 10V, ID = 1A 3.0 5.8 7 VDS = 15V, RL = 1Ω ID ≅ 1A, VGS = 10V, RGS = 50Ω 20 13 19 nS nC pF Gate-Source Charge Gate-Drain Charge 2 2 Turn-On Delay Time Rise Time td(on) tr Turn-Off Delay Time Fall Time 2 2 td(off) tf SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS (TC = 25 °C) Continuous Current Pulsed Current 3 1 IS ISM VSD trr Qrr IF = IS, VGS = 0V IF = IS, dlF/dt = 100A / µS 1.2 12 1.3 70 0.22 A V nS µC Forward Voltage Reverse Recovery Time Reverse Recovery Charge 1 2 Pulse test : Pulse Width ≤ 300 µsec, Duty Cycle ≤ 2％. Independent of operating temperature. 3 Pulse width limited by maximum junction temperature. REMARK: THE PRODUCT MARKED WITH “102B” 2 AUG-18-2001 NIKO-SEM N-Channel Logic Level Enhancement Mode Field Effect Transistor P01N02LMB SOT-23 (M3) SOT-23 (M3) MECHANICAL DATA mm Dimension Min. A B C D E F G 2.60 1.40 2.70 1.00 0.00 0.35 0.40 Typ. 0.95 2.80 1.60 2.90 1.10 3.00 1.80 3.10 1.30 0.10 0.50 Max. H I J K L M N Dimension Min. 0.10 0.37 Typ. 0.15 Max. 0.25 mm 3 AUG-18-2001