P06P03LDG

NIKO-SEM P-Channel Logic Level Enhancement Mode Field Effect Transistor P06P03LDG TO-252 Lead-Free D PRODUCT SUMMARY V(BR)DSS -30 RDS(ON) 45mΩ ID -12A G S 1. GATE 2. DRAIN 3. SOURCE ABSOLUTE MAXIMUM RATINGS (TC = 25 °C Unless Otherwise Noted) PARAMETERS/TEST CONDITIONS Drain-Source Voltage Gate-Source Voltage Continuous Drain Current Pulsed Drain Current Power Dissipation 1 SYMBOL VDS VGS LIMITS -30 ±20 -12 -10 -30 48 20 -55 to 150 UNITS V V TC = 25 °C TC = 70 °C ID IDM A TC = 25 °C TC = 70 °C PD Tj, Tstg W Operating Junction & Storage Temperature Range THERMAL RESISTANCE RATINGS THERMAL RESISTANCE Junction-to-Case Junction-to-Ambient 1 2 °C UNITS °C / W °C / W SYMBOL RθJc RθJA TYPICAL MAXIMUM 3 75 Pulse width limited by maximum junction temperature. Duty cycle ≤ 1% ELECTRICAL CHARACTERISTICS (TC = 25 °C, Unless Otherwise Noted) PARAMETER SYMBOL TEST CONDITIONS STATIC Drain-Source Breakdown Voltage Gate Threshold Voltage Gate-Body Leakage Zero Gate Voltage Drain Current On-State Drain Current1 Drain-Source On-State Resistance1 Forward Transconductance1 V(BR)DSS VGS(th) IGSS IDSS ID(ON) RDS(ON) gfs VGS = 0V, ID = -250µA VDS = VGS, ID = -250µA VDS = 0V, VGS = ±20V VDS = -24V, VGS = 0V VDS = -20V, VGS = 0V, TJ = 125 °C VDS = -5V, VGS = -10V VGS = -4.5V, ID =- 10A VGS = -10V, ID = -12A VDS = -10V, ID = -12A -30 60 37 16 75 45 -30 -1 -1.5 -3.0 ±250 nA 1 10 µA A mΩ S V LIMITS UNIT MIN TYP MAX AUG-17-2004 1 NIKO-SEM P-Channel Logic Level Enhancement Mode Field Effect Transistor P06P03LDG TO-252 Lead-Free DYNAMIC Input Capacitance Output Capacitance Reverse Transfer Capacitance Total Gate Charge 2 Ciss Coss Crss Qg Qgs Qgd 2 530 VGS = 0V, VDS = -15V, f = 1MHz 135 70 10 VDS = 0.5V(BR)DSS, VGS = -10V, ID = -12A 2.2 2 5.7 VDS = -15V, RL = 1Ω ID ≅ -1A, VGS = -10V, RGS = 6Ω 10 18 5 nS 14 nC pF Gate-Source Charge2 Gate-Drain Charge 2 2 2 Turn-On Delay Time Rise Time td(on) tr td(off) tf Turn-Off Delay Time Fall Time2 SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS (TC = 25 °C) Continuous Current Pulsed Current3 Forward Voltage1 Reverse Recovery Time Reverse Recovery Charge 1 2 IS ISM VSD trr Qrr IF = -1A, VGS = 0V IF = -5A, dlF/dt = 100A / µS 15.5 7.9 -12 -30 -1.2 A V nS nC Pulse test : Pulse Width ≤ 300 µsec, Duty Cycle ≤ 2％. Independent of operating temperature. 3 Pulse width limited by maximum junction temperature. REMARK: THE PRODUCT MARKED WITH “P06P03LDG”, DATE CODE or LOT # Orders for parts with Lead-Free plating can be placed using the PXXXXXXXG parts name AUG-17-2004 2 NIKO-SEM P-Channel Logic Level Enhancement Mode Field Effect Transistor P06P03LDG TO-252 Lead-Free Typical Characteristics AUG-17-2004 3 NIKO-SEM P-Channel Logic Level Enhancement Mode Field Effect Transistor P06P03LDG TO-252 Lead-Free AUG-17-2004 4 NIKO-SEM P-Channel Logic Level Enhancement Mode Field Effect Transistor P06P03LDG TO-252 Lead-Free TO-252 (DPAK) MECHANICAL DATA mm Dimension Min. A B C D E F G 9.35 2.2 0.45 0.89 0.45 0.03 5.2 Typ. Max. 10.4 2.4 0.6 1.5 0.69 0.23 6.2 H I J K L M N Dimension Min. 0.89 6.35 5.2 0.6 0.5 3.96 4.57 Typ. Max. 2.03 6.80 5.5 1 0.9 5.18 mm A B F C H G L 3 1 K M 2 J I D E AUG-17-2004 5