RDC19220

RDC-19220/2/4 SERIES Make sure the next Card you purchase has... ® 16-BIT MONOLITHIC TRACKING RESOLVER (LVDT)-TO-DIGITAL CONVERTERS FEATURES • +5 Volt Only Option • Only Five External Passive Components • Programmable: - Resolution: 10-, 12-, 14-, or 16-Bit - Bandwidth: to 1200 Hz - Tracking: to 2300 RPS • Differential Resolver and LVDT Input Modes • Velocity Output Eliminates Tachometer • Built-In-Test (BIT) Output • No 180° Hang-Up DESCRIPTION The RDC-19220 Series of converters are low-cost, versatile, 16-bit monolithic, state-of-the-art Resolver(/LVDT)-to-Digital Converters. These single-chip converters are available in small 40-pin DDIP, 44pin J-Lead, and 44-pin MQFP packages and offer programmable features such as resolution, bandwidth and velocity output scaling. Resolution programming allows selection of 10-, 12-, 14-, or 16-bit, with accuracies to 2.3 min. This feature combines the high tracking rate of a 10-bit converter with the precision and low-speed velocity resolution of a 16-bit converter in one package. The velocity output (VEL) from the RDC-19220 Series, which can be used to replace a tachometer, is a 4 V signal (3.5 V with the +5 V only option) referenced to ground with a linearity of 0.75% of output voltage. The full scale value of VEL is set by the user with a single resistor. RDC-19220 Series converters are available with operating temperature ranges of 0° to +70°C, -40° to +85°C and -55° to +125°C. Military processing is available. • Small Size: Available in DDIP PLCC or , MQFP Packages • -55° to +125°C Operating Temperature Available • Programmable for LVDT input APPLICATIONS With its low cost, small size, high accuracy and versatile performance, the RDC-19220 Series converter is ideal for use in modern high-performance industrial and military control systems. Typical applications include motor control, radar antenna positioning, machine tool control, robotics, and process control. MIL-PRF-38534 processing is available for military applications. FOR MORE INFORMATION CONTACT: Data Device Corporation 105 Wilbur Place Bohemia, New York 11716 631-567-5600 Fax: 631-567-7358 www.ddc-web.com Technical Support: 1-800-DDC-5757 ext. 7771 © 1999 Data Device Corporation Data Device Corporation www.ddc-web.com +REF -REF BIT -VSUM C BW R1 GAIN DEMODULATOR C BW 10 RB VEL CONTROL TRANSFORMER HYSTERESIS AB -VCO RS 16 BIT UP/DOWN COUNTER E DATA LATCH VCO & TIMING INTEGRATOR RV RC EM BIT 1 EL THRU BIT 16 A B CB SIN -S - +S + COS -C - +C + 2 +5C +CAP -CAP -5C -5 V INVERTER A GND +5 V GND -5 V INH RDC-19220 SERIES R-12/05-0 FIGURE 1. RDC-19220 SERIES BLOCK DIAGRAM TABLE 1. RDC-19220 SERIES SPECIFICATIONS These specifications apply over the rated power supply, temperature and reference frequency ranges, and 10% signal amplitude variation and harmonic distortion. PARAMETER RESOLUTION ACCURACY REPEATABILITY DIFFERENTIAL LINEARITY REFERENCE Type Voltage: differential single ended overload Frequency Input Impedance SIGNAL INPUT Type Voltage: operating overload Input impedance DIGITAL INPUT/OUTPUT Logic Type Inputs UNIT Bits Min LSB LSB VALUE 10, 12, 14, or 16 4 or 2 + 1 LSB (note 3) 1 max 1 max in the 16th bit (+REF, -REF) Differential 10 max ±5 max ±25 continuous, 100 transient DC to 40,000 (note 4 & note 9) 10M min // 20 pf TABLE 1. RDC-19220 SERIES SPECS (CONT’D) These specifications apply over the rated power supply, temperature and reference frequency ranges, and 10% signal amplitude variation and harmonic distortion. PARAMETER DYNAMIC CHARACTERISTICS Resolution Tracking Rate (max)(note 4) Bandwidth(Closed Loop) (max) (note 4) Ka (Note 7) A1 A2 A B Acceleration (1 LSB lag) Settling Time(179° step) VELOCITY CHARACTERISTICS Polarity Voltage Range(Full Scale) Scale Factor Error Scale Factor TC Reversal Error Linearity Zero Offset Zero Offset TC Load Noise POWER SUPPLIES Nominal Voltage Voltage Range Max Volt. w/o Damage Current TEMPERATURE RANGE Operating (Case) -30X -20X -10X -A0X Storage plastic package ceramic package MOISTURE SENSITIVITY LEVEL MQFP RDC-19224 THERMAL RESISTANCE Junction-to-Case (θjc) 40-pin DDIP (ceramic) 44-pin J-Lead (ceramic) PHYSICAL CHARACTERISTICS Size: 40-pin DDIP 44-pin J-Lead 44-pin MQFP Weight: 40-pin DDIP 44-pin J-Lead 44-pin MQFP UNIT VALUE (at maximum bandwidth) bits rps Hz 1/sec2 1/sec 1/sec 1/sec 1/sec deg/s2 msec 10 1152 1200 5.7M 19.5 295k 2400 1200 2M 2 12 288 1200 5.7M 19.5 295k 2400 1200 500k 8 14 72 600 1.4M 4.9 295k 1200 600 30k 20 16 18 300 360k 1.2 295k 600 300 2k 50 VP-P VP V Hz Ohm (+S, -S, SIN, +C, -C, COS) Resolver, differential, groundbased Vrms 2 ±15% V ±25 continuous Ohm 10M min//10 pf. (Note 6) TTL/CMOS compatible Logic 0 = 0.8 V max. Logic 1 = 2.0 V min. Loading =10 µA max pull-up current source to +5 V //5 pF max. CMOS transient protected Logic 0 inhibits; Data stable within 0.3 µs Logic 0 enables;Data stable with -in 150 ns (logic 0=Transparent) Logic 1 = High Impedance Data High Z within 100 nS Mode B resolver 0 " 0 " 1 " 1 LVDT -5 V " 0 " 1 " -5 V A Resolution 0 10 bits 1 12 bits 0 14 bits 1 16 bits 0 8 bits -5 V 10 bits -5 V 12 bits -5 V 14 bits V % PPM/C % % mv µV/C kΩ (Vp/V)% V % V mA Positive for increasing angle ±4 (at nominal ps) 10 typ 20 max 100 typ 200 max 0.75 typ 1.3 max 0.25 typ 0.50 max 5 typ 10 max 15 typ 30max 8 min 1 typ . 125 min 2 max (note 5) +5 -5 ± 5 ±5 +7 -7 14 typ, 22 max (each) Inhibit (INH) Enable Bits 1 to 8 (EM) Enable Bits 9 to 16 (EL) Resolution and Mode Control (A & B) (see notes 1 and 2. pre-set to logic 1 note 6) °C °C °C °C °C °C 0 to +70 -40 to +85 -55 to +125 -40 to +125 -65 to +150 -65 to +150 Outputs Parallel Data (1-16) JEDEC 2 Converter Busy (CB) Zero Index (Zl) Built-in-Test (BIT) Drive Capability 10, 12, 14, or 16 parallel lines; natural binary angle positive logic (see TABLE 2) 0.25 to 0.75 µs positive pulse leading edge initiates counter update. Logic 1 at all 0s (ENL to -5 V); LSBs are enabled Logic 0 for BIT condition. ±100 LSBs of error typ. with a filter of 500 µS, or total Loss-ofSignal (LOS) 50 pF + Logic 0; 1 TTL load, 1.6 mA at 0.4 V max Logic 1; 10 TTL loads, = 0.4 mA at 2.8 V min Logic 0; 100 mV max driving CMOS Logic 1; +5 V supply minus 100mV min driving CMOS, High Z; 10 uA//5 pF max °C/W °C/W 4.6 2.4 in(mm) 2.0 x 0.6 x 0.2 (50.8 x 15.24 x 5.08) in(mm) 0.690 square (17.526) in(mm) 0.394 square (10.0) Plastic n/a n/a 0.017 (0.5) Ceramic 0.24 (6.80) 0.065 (1.84) n/a oz(g) oz(g) oz(g) Data Device Corporation www.ddc-web.com 3 RDC-19220 SERIES R-12/05-0 Notes for TABLE 1:(from previous page) 1. Unused data bits are set to logic “0.” 2. In LVDT mode, bit 16 is LSB for 14-bit resolution or bit 12 is LSB for 10-bit resolution. 3. Accuracy spec below for LVDT mode, null to + full scale travel (45 degrees).(2 wire-LVDT configuration). 4 Min part = 0.15% + 1 LSB of full scale “resolution set”. 2 Min part = 0.07% + 1 LSB of full scale “resolution set” Accuracy spec below for LVDT mode, null to + full scale travel (90 degrees).(3 wire-LVDT configuration). 4 Min part = 0.07% + 1 LSB of full scale “resolution set”. 2 Min part = 0.035% + 1 LSB of full scale “resolution set” Note that this is the converter spec only and does not consider the front end external resistor tolerances. 4. See text, General Setup Considerations and HigherTracking Rates. 5. See text: General Setup Considerations for RDC19222. 6. Any unused input pins may be left floating (unconnected). All input pins are internally pulled-up to +5 Volts. 7. Ka = Acceleration constant, for a full definition see the RD/RDC application manual acceleration lag section. 8. When using internally generated -5V, the internal -5V charge pump when measured at the converter pin, can read as low as -20% (or 4V). 9. No 180° hangup with A/C reference. φ. Its output is an analog error angle, or difference angle, between the two inputs. The CT performs the ratiometric trigonometric computation of SINθCOSφ - COSθSINφ = SIN(θ-φ) using amplifiers, switches, logic and capacitors in precision ratios. Note: The transfer function of the CT is normally trigonometric, but in LDVT mode the transfer function is triangular (linear) and could thereby convert any linear transducer output. TABLE 2. DIGITAL ANGLE OUTPUTS BIT 1(MSB) 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 DEG/BIT 180 90 45 22.5 11.25 5.625 2.813 1.405 0.7031 0.3516 0.1758 0.0879 0.0439 0.0220 0.0110 0.0055 MIN/BIT 10800 5400 2700 1350 675 337.5 168.75 84.38 42.19 21.09 10.55 5.27 2.64 1.32 0.66 0.33 THEORY OF OPERATION The RDC-19220 Series of converters are single CMOS custom monolithic chips. They are implemented using the latest IC technology which merges precision analog circuitry with digital logic to form a complete, high-performance tracking Resolver-toDigital converter. For user flexibility and convenience, the converter bandwidth, dynamics and velocity scaling are externally set with passive components. FIGURE 1 is the functional block diagram of the RDC-19220 Series. The converter operates with ±5 Vdc power supplies. Analog signals are referenced to analog ground, which is at ground potential. The converter is made up of two main sections; a converter and a digital interface. The converter front-end consists of sine and cosine differential input amplifiers. These inputs are protected to ±25 V with 2 kΩ resistors and diode clamps to the ±5 Vdc supplies. These amplifiers feed the high accuracy Control Transformer (CT). Its other input is the 16-bit digital angle RB CBW Note: EM enables the MSBs and EL enables the LSBs. The converter accuracy is limited by the precision of the computing elements in the CT. For enhanced accuracy, the CT in these converters uses capacitors in precision ratios, instead of the more conventional precision resistor ratios. Capacitors, used as computing elements with op-amps, need to be sampled to eliminate voltage drifting. Therefore, the circuits are sampled at a high rate (67 kHz) to eliminate this drifting and at the same time to cancel out the op-amp offsets. The error processing is performed using the industry standard technique for type II tracking R/D converters. The dc error is integrated yielding a velocity voltage which in turn drives a voltage controlled oscillator (VCO). This VCO is an incremental integrator (constant voltage input to position rate output) which togethVEL C BW /10 RS -VSUM RV VEL -VCO 50 pf C VCO CT RESOLVER INPUT (θ) + GAIN DEMOD R1 VCO 1 CS F S 11 mV/LSB ±1.25 V THRESHOLD - 16 BIT UP/DOWN COUNTER H=1 DIGITAL OUTPUT (φ) FIGURE 2. TRANSFER FUNCTION BLOCK DIAGRAM #1 Data Device Corporation www.ddc-web.com 4 RDC-19220 SERIES R-12/05-0 er with the velocity integrator forms a type II servo feedback loop. A lead in the frequency response is introduced to stabilize the loop and another lag at higher frequency is introduced to reduce the gain and ripple at the carrier frequency and above. The settings of the various error processor gains and break frequencies are done with external resistors and capacitors so that the converter loop dynamics can be easily controlled by the user. GENERAL SETUP CONSIDERATIONS Note: For detailed application and technical information see the RD/RDC converter applications manual which is available for download from the DDC web site @ www.ddc-web.com. DDC has external component selection software which considers all the criteria below, and in a simple fashion, asks the key parameters (carrier frequency, resolution, bandwidth, and tracking rate) to derive the external component value. The following recommendations should be considered when installing the RDC-19220 Series R/D converters: 1) In setting the bandwidth (BW) and Tracking Rate (TR) (selecting five external components), the system requirements need to be considered. For greatest noise immunity, select the minimum BW and TR the system will allow. 2) +5 and -5 volt operation: Power supplies are ±5 V dc. For lowest noise performance it is recommended that a 0.1 µF or larger cap be connected from each supply to ground near the converter package. When using a +5V and -5V supply to power the converter, RDC-19222 pins 22, 23, 25, 26 must be no connection, and on RDC-19224 pins 20, 40, 16, 11, must be no connection. Also, the 10uF cap is not connected to +cap and -cap pins. 3) This converter has 2 internal ground planes, which reduce noise to the analog input due to digital ground currents. The resolver inputs and velocity output are referenced to AGND. The digital outputs and inputs are referenced to GND. The AGND and GND pins must be tied together as close to the converter package as possible. Not shorting these pins together as close to the converter package as possible will cause unstable converter results. TRANSFER FUNCTION AND BODE PLOT The dynamic performance of the converter can be determined from its Transfer Function Block Diagrams and its Bode Plots (open and closed loop). These are shown in FIGURES 2, 3, and 4. The open loop transfer function is as follows: A2 S +1 B Open Loop Transfer Function = S2 S +1 10B ( ( ) ) where A is the gain coefficient and A2= A1A2 and B is the frequency of lead compensation. The components of gain coefficient are error gradient, integrator gain and VCO gain. These can be broken down as follows: - Error Gradient = 0.011 volts per LSB (CT + Error Amp + Demod with 2 Vrms input) - Integrator Gain = Cs Fs volts per second per volt 1.1 CBW - VCO Gain = 1 LSBs per second per volt 1.25 RV CVCO where: Cs = 10 pF Fs = 67 kHz when Rs = 30 kΩ Fs = 100 kHz when Rs = 20 kΩ Fs = 134 kHz when Rs = 15 kΩ CVCO = 50 pF RV, RB, and CBW are selected by the user to set velocity scaling and bandwidth. -1 2d GAIN = 4 b/o ct (CRITICALLY DAMPED) ERROR PROCESSOR RESOLVER INPUT (θ) + CT e A1 S + 1 B S S +1 10B VELOCITY OUT VCO A2 S DIGITAL POSITION OUT (φ) 2A OPEN LOOP B A -6 db ω (rad/sec) 10B /oc t (B = A/2) GAIN = 0.4 f BW = BW (Hz) = 2A π H=1 CLOSED LOOP 2A 2 2A ω (rad/sec) FIGURE 3. TRANSFER FUNCTION BLOCK DIAGRAM #2 Data Device Corporation www.ddc-web.com 5 FIGURE 4. BODE PLOTS RDC-19220 SERIES R-12/05-0 4) The BIT output which is active low is activated by an error of approximately 100 LSBs. During normal operation for step inputs or on power up, a large error can exist. -CAP 5) This device has several high impedance amplifier inputs (+C, -C, +S, -S, -VCO and -VSUM). These nodes are sensitive to noise and coupling components should be connected as close as possible. 6) Setup of bandwidth and velocity scaling for the optimized critically damped case should proceed as follows: - Select the desired f BW (closed loop) based on overall system dynamics. - Select f carrier ≥ 3.5f BW - Select the applications tracking rate (in accordance with TABLE 3), and use appropriate values for R SET and R CLK - Compute Rv = Full Scale Velocity Voltage Tracking Rate (rps) x 2 resolution x 50 pF x 1.25 V 3.2 x Fs (Hz) x 108 Rv x (f BW)2 RDC-19222/4 +CAP 10uF (-5c) -5V (+5c) +5V .01uF .01uF + + 47uF 47uF FIGURE 5. -5V BUILT-IN INVERTER 7) Selecting a fBW that is too low relative to the maximum application tracking rate can create a spin-around condition in which the converter never settles. The relationship to insure against spin-around is as follows (TABLE 3): 8) For RDC-19222 & RDC-19224; package’s only. This version is capable of +5V only operation. It accomplishes this with a charge pump technique that inverts the +5V supply for use as -5V, hence the +5V supply current doubles. The built-in -5 V inverter can be used by connecting pin 2 to 26, pin 17 to 22, a 10 µF/10 Vdc capacitor from pin 23 (negative terminal) to pin 25 (positive terminal), and a 47 µF/10 Vdc capacitor from -5 V to GND. The current drain from the +5 V supply doubles. No external -5 V supply is needed (SEE FIGURE 5). When using the -5 V inverter, the max. tracking rate should be scaled for a velocity output of 3.5 V max. Use the following equation to determine tracking rate used in the formula on page 5: TR (required) x (4.0) = Tracking rate used in calculation (3.5) Note: When using the highest BW and Tracking Rates, using the -5 V inverter is not recommended. - Compute CBW (pF) = - Where Fs = 67 kHz for R CLK = 30 KΩ 100 kHz for R CLK = 20 KΩ 125 kHz for R CLK = 15 KΩ - Compute RB = - Compute CBW 10 As an example: Calculate component values for a 16-bit converter with 100Hz bandwidth, a tracking rate of 10RPS and a full scale velocity of 4 volts. 4V = 97655 Ω 10 rps x 216 x 50 pF x 1.25 V 3.2 x 67 kHz x 108 = 21955 pF 97655 x 100 Hz2 0.9 CBW x f BW - Rv = - Compute CBW (pF) = - Compute RB = 0.9 = 410 kΩ 21955 x 10 -12 x 100 Hz Note: DDC has software available to perform the previous calculations. Contact DDC to request software or visit our website at www.ddc-web.com to download software. TABLE 3. TRACKING/BW RELATIONSHIP RPS (MAX)/BW 1 0.45 0.25 0.125 RESOLUTION 10 12 14 16 HIGHER TRACKING RATES AND CARRIER FREQUENCIES Tracking rate (nominally 4 V) is limited by two factors: velocity voltage saturation and maximum internal clock rate (nominally 1,333,333 Hz). An understanding of their interaction is essential to extending performance. The General Setup Considerations section makes note of the selection of Rv for the desired velocity scaling. Rv is the input resis- Data Device Corporation www.ddc-web.com 6 RDC-19220 SERIES R-12/05-0 bring it to 0 V. The output counts per second per volt input is therefore: 1 (Rv x 50 pF x 1.25) As an example: Calculate Rv for the maximum counting rate, at a VEL voltage of 4 V. For a 12-bit converter there are 212 or 4096 counts per rotation. 1,333,333/4096 = 325 rotations per second or 333,333 counts per second per volt. Rv = 1 = 48 kΩ (333,333 x 50 pF x 1.25) TRANSFORMER ISOLATION System requirements often include electrical isolation. There are transformers available for reference and synchro/resolver signal isolation. TABLE 6 includes a listing of the most common transformers. The synchro/resolver transformers reduce the voltage to 2 Vrms for a direct connection to the converter. See FIGURES 5A, 5B, 5C and 5D for transformer layouts and schematics, and FIGURE 6 for typical connections. DC INPUTS As noted in TABLE 1, the RD-19220/2/4 will accept DC inputs. • Operation from 0° to 180° or 180° to 359° only. This is due to the possibility of a unstable false null. IE: 180° hang-up. This 180° hang-up is unstable and once the converter moves it will go to the correct answer. In real world applications where an instantaneous 180° change are not possible the converter will always be correct within 360°. The problem arises at power-up in real systems. If the converter angle powers up at exactly 180° from the applied input the converter will not move. This is very unlikely although it is theoretically possible. This condition is most often encountered during wrap around verification tests, simulations or troubleshooting. • Set the REF input to DC by tying RH to +5V and RL to GND or -5V. • Set the COS and SIN inputs such that max signal will be equal to 1.8VDC. IE: For 90°, the SIN input will equal 1.8VDC. This will keep the BW hysteresis consistant with AC operation. • Input offsets will affect accuracy. Verify the COS and SIN inputs do not have DC offsets. If offsets are present , a differential op amp configuration can be used to minimize differential offset problems. • With DC inputs the converter BIT will remain at logic 0. • The Bandwidth value of the converter should be chosen based on the rate of change of the system’s input amplitude variation, and should be large enough so to minimize it’s effect on the system dynamics. Note that if the bandwidth is too high the system will be more susceptible to noise. • The accuracy of the converter using a DC input will be degraded from the rated accuracy. Consider the best case where the input is single ended and no additional DC offsets are present on the input converter - the accuracy will degrade by about 2 arc minutes. IE:, If a part is rated at 2 arc minutes, a DC input will degrade the accuracy to approximately 4 arc minutes. The maximum rate capability of the RDC-19220 is set by Rs. When Rs = 30 kΩ it is nominally 1,333,333 counts/sec, which equates to 325 rps (rotations per second). This is the absolute maximum rate; it is recommended to only run at