RTL8309SB

RTL8309SB SINGLE-CHIP 9-PORT 10/100MBPS SWITCH CONTROLLER DATASHEET Rev. 1.4 09 July 2004 Track ID: JATR-1076-21 RTL8309SB Datasheet COPYRIGHT ©2004 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any means without the written permission of Realtek Semiconductor Corp. DISCLAIMER Realtek provides this document “as is”, without warranty of any kind, neither expressed nor implied, including, but not limited to, the particular purpose. Realtek may make improvements and/or changes in this document or in the product described in this document at any time. This document could include technical inaccuracies or typographical errors. TRADEMARKS Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document are trademarks/registered trademarks of their respective owners. USING THIS DOCUMENT This document provides detailed user guidelines to achieve the best performance when implementing a 2-layer board PC design with the RTL8309SB Single-Chip 9-port 10/100Mbps Switch Controller. Though every effort has been made to assure that this document is current and accurate, more information may have become available subsequent to the production of this guide. In that event, please contact your Realtek representative for additional information that may help in the development process. Single-Chip 9-Port 10/100Mbps Switch Controller ii Track ID: JATR-1076-21 Rev. 1.4 RTL8309SB Datasheet REVISION HISTORY Revision 1.0 1.1 Release Date 2003/04/12 2003/05/15 Summary First release. Revised pin descriptions. Revised description for Bi-color LED. New Bi-color LED Reference Schematic figure. Add 3.3V items to electrical characteristics. Add thermal operating range temperatures. Revised pin description of Dis_VLAN. Revised pin description of Max_Pause_Count. Revised default VLAN membership configuration for Disable VLAN function in PHY register 16.11. Update default value of Differential Service Code Point [B] in EEPROM and PHY registers. Update default value of VLAN ID [A] membership in EERPOM. Update default value of ISP MAC Address in EEPROM. Update default value of Port 8 VLAN Index in EEPROM. Revised the definition for WAN port specification in EEPROM and PHY registers. Revised the definition for CPU port specification in EEPROM and PHY registers. Removed the Bypass CRC function in EEPROM. Removed the Good Link Quality Threshold function in EEPROM and PHY registers. Add explanation of Indirect Access Data in PHY 7 Register 17~20. Removed PHY0~PHY7 REG2 and REG3 info. Update pin number ordering on Pin Description Table. Change the term “Auto MDIX” to “Crossover Detection and auto correction”. Removed QoS feature for IPv6. 1.2 2003/12/01 1.3 2004/06/10 1.4 2004/07/09 Single-Chip 9-Port 10/100Mbps Switch Controller iii Track ID: JATR-1076-21 Rev. 1.4 RTL8309SB Datasheet Table of Contents 1. 2. 3. 4. 5. GENERAL DESCRIPTION................................................................................................................................................1 FEATURES...........................................................................................................................................................................3 BLOCK DIAGRAM.............................................................................................................................................................4 PIN ASSIGNMENTS ...........................................................................................................................................................5 PIN DESCRIPTIONS ..........................................................................................................................................................7 5.1. 5.2. 5.3. 5.4. 5.5. 5.6. 5.7. 6. MEDIA CONNECTION PINS ..........................................................................................................................................7 MII PORT MAC INTERFACE PINS ...............................................................................................................................7 MISCELLANEOUS PINS ................................................................................................................................................9 PORT LED PINS ..........................................................................................................................................................9 SERIAL EEPROM AND SMI PINS .............................................................................................................................11 STRAPPING PINS........................................................................................................................................................12 POWER PINS ..............................................................................................................................................................16 EEPROM REGISTER DESCRIPTION ..........................................................................................................................17 6.1. 6.1.1. 6.1.2. 6.1.3. 6.1.4. 6.1.5. 6.1.6. 6.1.7. 6.1.8. 6.2. 6.2.1. 6.2.2. 6.2.3. 6.2.4. 6.2.5. 6.2.6. 6.2.7. 6.2.8. GLOBAL CONTROL REGISTERS..................................................................................................................................17 Global Control Register0 ...................................................................................................................................17 Global Control Register1 ...................................................................................................................................17 Global Control Register2 ...................................................................................................................................18 Global Control Register3 ...................................................................................................................................18 Global Control Register4 ...................................................................................................................................19 Global Control Register5 ...................................................................................................................................19 Global Control Register6 ...................................................................................................................................19 Global Control Register7 ...................................................................................................................................19 PORT 0~7 CONTROL PINS ..........................................................................................................................................20 Port 0 Control 0..................................................................................................................................................20 Port 0 Control 1..................................................................................................................................................20 Port 0 Control 2..................................................................................................................................................21 Port 0 Control 3..................................................................................................................................................21 Port 0 Control 4..................................................................................................................................................21 IP Address...........................................................................................................................................................22 Port 1 Control 0..................................................................................................................................................23 Port 1 Control 1..................................................................................................................................................23 iv Track ID: JATR-1076-21 Rev. 1.4 Single-Chip 9-Port 10/100Mbps Switch Controller RTL8309SB Datasheet 6.2.9. 6.2.10. 6.2.11. 6.2.12. 6.2.13. 6.2.14. 6.2.15. 6.2.16. 6.2.17. 6.2.18. 6.2.19. 6.2.20. 6.2.21. 6.2.22. 6.2.23. 6.2.24. 6.2.25. 6.2.26. 6.2.27. 6.2.28. 6.2.29. 6.3. 6.3.1. 6.3.2. 6.3.3. 6.3.4. 6.4. 6.4.1. 6.4.2. 6.4.3. 6.4.4. 6.4.5. 6.4.6. 6.4.7. 6.4.8. Port 1 Control 2..................................................................................................................................................24 Port 1 Control 3..................................................................................................................................................24 Port 1 Control 4..................................................................................................................................................24 IP Mask ..............................................................................................................................................................25 Port 2 Control 0..................................................................................................................................................25 Port 2 Control 1..................................................................................................................................................26 Port 2 Control 2..................................................................................................................................................26 Port 2 Control 3..................................................................................................................................................26 Port 2 Control 4..................................................................................................................................................27 Switch MAC Address ..........................................................................................................................................27 Port 3 Control 0..................................................................................................................................................28 Port 3 Control 1..................................................................................................................................................28 Port 3 Control 2..................................................................................................................................................29 Port 3 Control 3..................................................................................................................................................29 Port 3 Control 4..................................................................................................................................................29 ISP MAC Address ...............................................................................................................................................30 Port 4 Control 0..................................................................................................................................................30 Port 4 Control 1..................................................................................................................................................30 Port 4 Control 2..................................................................................................................................................31 Port 4 Control 3..................................................................................................................................................31 Port 4 Control 4..................................................................................................................................................31 MII PORT CONTROL PINS..........................................................................................................................................32 MII Port Control 0..............................................................................................................................................32 MII Port Control 1..............................................................................................................................................32 MII Port Control 2..............................................................................................................................................33 CPU Port and WAN Port....................................................................................................................................33 PORT 5~7 CONTROL PINS ..........................................................................................................................................34 Port 5 Control 0..................................................................................................................................................34 Port 5 Control 1..................................................................................................................................................34 Port 5 Control 2..................................................................................................................................................35 Port 5 Control 3..................................................................................................................................................35 Port 5 Control 4..................................................................................................................................................35 Port 6 Control 0..................................................................................................................................................36 Port 6 Control 1..................................................................................................................................................36 Port 6 Control 2..................................................................................................................................................36 Single-Chip 9-Port 10/100Mbps Switch Controller v Track ID: JATR-1076-21 Rev. 1.4 RTL8309SB Datasheet 6.4.9. 6.4.10. 6.4.11. 6.4.12. 6.4.13. 6.4.14. 6.4.15. 7. Port 6 Control 3..................................................................................................................................................37 Port 6 Control 4..................................................................................................................................................37 Port 7 Control 0..................................................................................................................................................38 Port 7 Control 1..................................................................................................................................................38 Port 7 Control 2..................................................................................................................................................38 Port 7 Control 3..................................................................................................................................................39 Port 7 Control 4..................................................................................................................................................39 PHY REGISTERS DESCRIPTION .................................................................................................................................40 7.1. 7.1.1. 7.1.2. 7.1.3. 7.1.4. 7.1.5. 7.1.6. 7.1.7. 7.1.8. 7.1.9. 7.1.10. 7.1.11. 7.1.12. 7.1.13. 7.2. 7.2.1. 7.2.2. 7.2.3. 7.2.4. 7.2.5. 7.2.6. 7.2.7. 7.2.8. 7.2.9. 7.2.10. 7.2.11. PHY 0 REGISTERS ....................................................................................................................................................40 PHY 0 Register 0: Control..................................................................................................................................40 PHY 0 Register 1: Status ....................................................................................................................................41 PHY 0 Register 4: Auto-Negotiation Advertisement...........................................................................................42 PHY 0 Register 5: Auto-Negotiation Link Partner Ability..................................................................................42 PHY 0 Register 6: Auto-Negotiation Expansion.................................................................................................43 PHY 0 Register 16: Global Control 0.................................................................................................................43 PHY 0 Register 17: Global Control 1.................................................................................................................45 PHY 0 Register 18: Global Control 2.................................................................................................................46 PHY 0 Register 19: Global Control 3.................................................................................................................46 PHY 0 Register 22: Port 0 Control 0..................................................................................................................46 PHY 0 Register 23: Port 0 Control 1..................................................................................................................48 PHY 0 Register 24: Port 0 Control 2 & VLAN Entry [A]...................................................................................48 PHY 0 Register 25: VLAN Entry [A] ..................................................................................................................48 PHY 1 REGISTERS ....................................................................................................................................................49 PHY 1 Register 0: Control..................................................................................................................................49 PHY 1 Register 1: Status ....................................................................................................................................49 PHY 1 Register 4: Auto-Negotiation Advertisement...........................................................................................49 PHY 1 Register 5: Auto-Negotiation Link Partner Ability..................................................................................49 PHY 1 Register 6: Auto-Negotiation Expansion.................................................................................................49 PHY 1 Register 16~17: IP Priority Address [A].................................................................................................49 PHY 1 Register 18~19: IP Priority Address [B].................................................................................................49 PHY 1 Register 22: Port 1 Control 0..................................................................................................................50 PHY 1 Register 23: Port 1 Control 1..................................................................................................................50 PHY 1 Register 24: Port 1 Control 2 & VLAN Entry [B]...................................................................................50 PHY 1 Register 25: VLAN Entry [B] ..................................................................................................................50 Single-Chip 9-Port 10/100Mbps Switch Controller vi Track ID: JATR-1076-21 Rev. 1.4 RTL8309SB Datasheet 7.3. 7.3.1. 7.3.2. 7.3.3. 7.3.4. 7.3.5. 7.3.6. 7.3.7. 7.3.8. 7.3.9. 7.3.10. 7.3.11. 7.4. 7.4.1. 7.4.2. 7.4.3. 7.4.4. 7.4.5. 7.4.6. 7.4.7. 7.4.8. 7.4.9. 7.4.10. 7.5. 7.5.1. 7.5.2. 7.5.3. 7.5.4. 7.5.5. 7.5.6. 7.5.7. 7.5.8. 7.5.9. 7.5.10. PHY 2 REGISTERS ....................................................................................................................................................50 PHY 2 Register 0: Control..................................................................................................................................50 PHY 2 Register 1: Status ....................................................................................................................................50 PHY 2 Register 4: Auto-Negotiation Advertisement...........................................................................................50 PHY 2 Register 5: Auto-Negotiation Link Partner Ability..................................................................................51 PHY 2 Register 6: Auto-Negotiation Expansion.................................................................................................51 PHY 2 Register 16~17: IP Priority Mask [A] ....................................................................................................51 PHY 2 Register 18~19: IP Priority Mask [B] ....................................................................................................51 PHY 2 Register 22: Port 2 Control 0..................................................................................................................51 PHY 2 Register 23: Port 2 Control 1..................................................................................................................51 PHY 2 Register 24: Port 2 Control 2 & VLAN Entry [C]...................................................................................52 PHY 2 Register 25: VLAN Entry [C]..................................................................................................................52 PHY 3 REGISTERS ....................................................................................................................................................52 PHY 3 Register 0: Control..................................................................................................................................52 PHY 3 Register 1: Status ....................................................................................................................................52 PHY 3 Register 4: Auto-Negotiation Advertisement...........................................................................................52 PHY 3 Register 5: Auto-Negotiation Link Partner Ability..................................................................................52 PHY 3 Register 6: Auto-Negotiation Expansion.................................................................................................52 PHY 3 Register 16~18: Switch MAC Address ....................................................................................................52 PHY 3 Register 22: Port 3 Control 0..................................................................................................................53 PHY 3 Register 23: Port 3 Control 1..................................................................................................................53 PHY 3 Register 24: Port 3 Control 2 & VLAN Entry [D] ..................................................................................53 PHY 3 Register 25: VLAN Entry [D]..................................................................................................................53 PHY 4 REGISTERS ....................................................................................................................................................54 PHY 4 Register 0: Control..................................................................................................................................54 PHY 4 Register 1: Status ....................................................................................................................................54 PHY 4 Register 4: Auto-Negotiation Advertisement...........................................................................................54 PHY 4 Register 5: Auto-Negotiation Link Partner Ability..................................................................................54 PHY 4 Register 6: Auto-Negotiation Expansion.................................................................................................54 PHY 4 Register 16~18: ISP MAC Address .........................................................................................................54 PHY 4 Register 22: Port 4 Control 0..................................................................................................................54 PHY 4 Register 23: Port 4 Control 1..................................................................................................................54 PHY 4 Register 24: Port 4 Control 2 & VLAN Entry [E]...................................................................................55 PHY 4 Register 25: VLAN Entry [E] ..................................................................................................................55 Single-Chip 9-Port 10/100Mbps Switch Controller vii Track ID: JATR-1076-21 Rev. 1.4 RTL8309SB Datasheet 7.6. 7.6.1. 7.6.2. 7.6.3. 7.6.4. 7.6.5. 7.6.6. 7.6.7. 7.6.8. 7.6.9. 7.6.10. 7.6.11. 7.6.12. 7.6.13. 7.7. 7.7.1. 7.7.2. 7.7.3. 7.7.4. 7.7.5. 7.7.6. 7.7.7. 7.7.8. 7.7.9. 7.8. 7.8.1. 7.8.2. 7.8.3. 7.8.4. 7.8.5. 7.8.6. 7.8.7. 7.8.8. 7.8.9. PHY 5 REGISTERS ....................................................................................................................................................55 PHY 5 Register 0: Control..................................................................................................................................55 PHY 5 Register 1: Status ....................................................................................................................................55 PHY 5 Register 4: Auto-Negotiation Advertisement...........................................................................................55 PHY 5 Register 5: Auto-Negotiation Link Partner Ability..................................................................................55 PHY 5 Register 6: Auto-Negotiation Expansion.................................................................................................55 PHY 5 Register 16: MII Port Control 0..............................................................................................................56 PHY 5 Register 17: MII Port Control 1 & VLAN Entry [I]................................................................................57 PHY 5 Register 18: VLAN Entry [I] ...................................................................................................................57 PHY 5 Register 19: CPU Port & WAN Port.......................................................................................................57 PHY 5 Register 22: Port 5 Control 0..................................................................................................................58 PHY 5 Register 23: Port 5 Control 1..................................................................................................................58 PHY 5 Register 24: Port 5 Control 2 & VLAN Entry [F]...................................................................................58 PHY 5 Register 25: VLAN Entry [F] ..................................................................................................................58 PHY 6 REGISTERS ....................................................................................................................................................59 PHY 6 Register 0: Control..................................................................................................................................59 PHY 6 Register 1: Status ....................................................................................................................................59 PHY 6 Register 4: Auto-Negotiation Advertisement...........................................................................................59 PHY 6 Register 5: Auto-Negotiation Link Partner Ability..................................................................................59 PHY 6 Register 6: Auto-Negotiation Expansion.................................................................................................59 PHY 6 Register 22: Port 6 Control 0..................................................................................................................59 PHY 6 Register 23: Port 6 Control 1..................................................................................................................59 PHY 6 Register 24: Port 6 Control 2 & VLAN Entry [G] ..................................................................................60 PHY 6 Register 25: VLAN Entry [G]..................................................................................................................60 PHY 7 REGISTERS ....................................................................................................................................................61 PHY 7 Register 0: Control..................................................................................................................................61 PHY 7 Register 1: Status ....................................................................................................................................61 PHY 7 Register 4: Auto-Negotiation Advertisement...........................................................................................61 PHY 7 Register 5: Auto-Negotiation Link Partner Ability..................................................................................61 PHY 7 Register 6: Auto-Negotiation Expansion.................................................................................................61 PHY 7 Register 16: indirect Access Control.......................................................................................................61 PHY 7 Register 17~20: Indirect Access Data.....................................................................................................62 PHY 7 Register 22: Port 7 Control 0..................................................................................................................62 PHY 7 Register 23: Port 7 Control 1..................................................................................................................62 Single-Chip 9-Port 10/100Mbps Switch Controller viii Track ID: JATR-1076-21 Rev. 1.4 RTL8309SB Datasheet 7.8.10. 7.8.11. 7.9. 7.9.1. 7.9.2. 7.9.3. 7.9.4. 7.9.5. 8. PHY 7 Register 24: Port 7 Control 2 & VLAN Entry [H] ..................................................................................62 PHY 7 Register 25: VLAN Entry [H]..................................................................................................................63 PHY 8 REGISTERS ....................................................................................................................................................63 PHY 8 Register 0: Control..................................................................................................................................63 PHY 8 Register 1: Status ....................................................................................................................................64 PHY 8 Register 4: Auto-Negotiation Advertisement...........................................................................................64 MII Port NWay Mode .........................................................................................................................................65 MII Port Force Mode .........................................................................................................................................65 FUNCTIONAL DESCRIPTION.......................................................................................................................................66 8.1. 8.1.1. 8.1.2. 8.1.3. 8.1.4. 8.1.5. 8.1.6. 8.1.7. 8.1.8. 8.1.9. 8.2. 8.2.1. 8.2.2. 8.2.3. 8.2.4. 8.2.5. 8.2.6. 8.3. 8.3.1. 8.3.2. 8.3.3. 8.3.4. 8.3.5. 8.3.6. 8.3.7. 8.3.8. PHYSICAL LAYER TRANSCEIVER FUNCTIONAL OVERVIEW .......................................................................................66 Auto Negotiation for UTP ..................................................................................................................................66 100Base-Tx Transmit Function ..........................................................................................................................66 100Base-Tx Receive Function ............................................................................................................................66 10Base-T Transmit Function ..............................................................................................................................67 10Base-T Receive Function ................................................................................................................................67 Link Monitor.......................................................................................................................................................67 Power Saving Mode............................................................................................................................................67 Power-Down Mode.............................................................................................................................................67 Auto Crossover Detection...................................................................................................................................68 SWITCH CORE FUNCTIONAL OVERVIEW....................................................................................................................68 Address Search, Learning, and Aging ................................................................................................................68 Flow Control ......................................................................................................................................................69 Half Duplex Operation .......................................................................................................................................69 Backpressure ......................................................................................................................................................70 UTP Port Status Configuration ..........................................................................................................................70 MII Port (The 9th Port) ......................................................................................................................................70 ADVANCED FUNCTIONALITY OVERVIEW ...................................................................................................................74 Port-Based VLAN ...............................................................................................................................................74 802.1Q Tagged-VID based VLAN.......................................................................................................................76 QoS Operation....................................................................................................................................................77 Insert/Remove VLAN Priority Tag......................................................................................................................78 Port VID (PVID) ................................................................................................................................................79 Port Trunking .....................................................................................................................................................79 ISP MAC Address Translation ............................................................................................................................79 Lookup Table Access...........................................................................................................................................81 ix Track ID: JATR-1076-21 Rev. 1.4 Single-Chip 9-Port 10/100Mbps Switch Controller RTL8309SB Datasheet 8.3.9. 8.3.10. 8.3.11. 8.3.12. 8.3.13. 8.3.14. 8.3.15. 8.3.16. 8.3.17. 9. Serial Management Interface (SMI) ...................................................................................................................81 Broadcast Storm Control ....................................................................................................................................82 Broadcast In/Out Drop .......................................................................................................................................82 EEPROM Configuration Interface .....................................................................................................................83 24LC02 Device Operation..................................................................................................................................83 Head-of-Line Blocking .......................................................................................................................................84 MII Port Diagnostic Loopback...........................................................................................................................85 Loop Detection ...................................................................................................................................................86 LEDs (Light Emitting Diodes)............................................................................................................................87 CHARACTERISTICS .......................................................................................................................................................90 9.1. 9.2. 9.3. 9.4. 9.5. 9.6. ABSOLUTE MAXIMUM RATINGS................................................................................................................................90 OPERATING RANGE ...................................................................................................................................................90 DC CHARACTERISTICS .............................................................................................................................................90 AC CHARACTERISTICS .............................................................................................................................................91 DIGITAL TIMING CHARACTERISTICS .........................................................................................................................92 THERMAL CHARACTERISTICS ...................................................................................................................................94 SYSTEM APPLICATIONS ...........................................................................................................................................95 DESIGN AND LAYOUT GUIDE..................................................................................................................................96 MECHANICAL DIMENSIONS ...................................................................................................................................99 NOTES FOR 128-PIN LQFP DIMENSIONS ................................................................................................................100 10. 11. 12. 12.1. Single-Chip 9-Port 10/100Mbps Switch Controller x Track ID: JATR-1076-21 Rev. 1.4 RTL8309SB Datasheet List of Tables Table 1. Pin Assignments.............................................................................................................................6 Table 2. Media Connection Pins ..................................................................................................................7 Table 3. MII Port MAC Interface Pins ........................................................................................................7 Table 4. Miscellaneous Pins.........................................................................................................................9 Table 5. Port LED Pins ................................................................................................................................9 Table 6. Serial EEPROM and SMI Pins ....................................................................................................11 Table 7. Strapping Pins ..............................................................................................................................12 Table 8. Power Pins ...................................................................................................................................16 Table 9. Global Control Register0 .............................................................................................................17 Table 10. Global Control Register1 .............................................................................................................17 Table 11. Global Control Register2 .............................................................................................................18 Table 12. Global Control Register3 .............................................................................................................18 Table 13. Global Control Register4 .............................................................................................................19 Table 14. Global Control Register5 .............................................................................................................19 Table 15. Global Control Register6 .............................................................................................................19 Table 16. Global Control Register7 .............................................................................................................19 Table 17. Port 0 Control 0............................................................................................................................20 Table 18. Port 0 Control 1............................................................................................................................20 Table 19. Port 0 Control 2............................................................................................................................21 Table 20. Port 0 Control 3............................................................................................................................21 Table 21. Port 0 Control 4............................................................................................................................21 Table 22. IP Address ....................................................................................................................................22 Table 23. Port 1 Control 0............................................................................................................................23 Table 24. Port 1 Control 1............................................................................................................................23 Table 25. Port 1 Control 2............................................................................................................................24 Table 26. Port 1 Control 3............................................................................................................................24 Table 27. Port 1 Control 4............................................................................................................................24 Table 28. IP Mask ........................................................................................................................................25 Table 29. Port 2 Control 0............................................................................................................................25 Table 30. Port 2 Control 1............................................................................................................................26 Table 31. Port 2 Control 2............................................................................................................................26 Table 32. Port 2 Control 3............................................................................................................................26 Table 33. Port 2 Control 4............................................................................................................................27 Single-Chip 9-Port 10/100Mbps Switch Controller xi Track ID: JATR-1076-21 Rev. 1.4 RTL8309SB Datasheet Table 34. Switch MAC Address ..................................................................................................................27 Table 35. Port 3 Control 0............................................................................................................................28 Table 36. Port 3 Control 1............................................................................................................................28 Table 37. Port 3 Control 2............................................................................................................................29 Table 38. Port 3 Control 3............................................................................................................................29 Table 39. Port 3 Control 4............................................................................................................................29 Table 40. ISP MAC Address........................................................................................................................30 Table 41. Port 4 Control 0............................................................................................................................30 Table 42. Port 4 Control 1............................................................................................................................30 Table 43. Port 4 Control 2............................................................................................................................31 Table 44. Port 4 Control 3............................................................................................................................31 Table 45. Port 4 Control 4............................................................................................................................31 Table 46. MII Port Control 0 .......................................................................................................................32 Table 47. MII Port Control 1 .......................................................................................................................32 Table 48. MII Port Control 2 .......................................................................................................................33 Table 49. CPU Port and WAN Port..............................................................................................................33 Table 50. Port 5 Control 0............................................................................................................................34 Table 51. Port 5 Control 1............................................................................................................................34 Table 52. Port 5 Control 2............................................................................................................................35 Table 53. Port 5 Control 3............................................................................................................................35 Table 54. Port 5 Control 4............................................................................................................................35 Table 55. Port 6 Control 0............................................................................................................................36 Table 56. Port 6 Control 1............................................................................................................................36 Table 57. Port 6 Control 2............................................................................................................................36 Table 58. Port 6 Control 3............................................................................................................................37 Table 59. Port 6 Control 4............................................................................................................................37 Table 60. Port 7 Control 0............................................................................................................................38 Table 61. Port 7 Control 1............................................................................................................................38 Table 62. Port 7 Control 2............................................................................................................................38 Table 63. Port 7 Control 3............................................................................................................................39 Table 64. Port 7 Control 4............................................................................................................................39 Table 65. PHY 0 Register 0: Control ...........................................................................................................40 Table 66. PHY 0 Register 1: Status .............................................................................................................41 Table 67. PHY 0 Register 4: Auto-Negotiation Advertisement...................................................................42 Table 68. PHY 0 Register 5: Auto-Negotiation Link Partner Ability ..........................................................42 Single-Chip 9-Port 10/100Mbps Switch Controller xii Track ID: JATR-1076-21 Rev. 1.4 RTL8309SB Datasheet Table 69. PHY 0 Register 6: Auto-Negotiation Expansion .........................................................................43 Table 70. PHY 0 Register 16: Global Control 0 ..........................................................................................43 Table 71. PHY 0 Register 17: Global Control 1 ..........................................................................................45 Table 72. PHY 0 Register 18: Global Control 2 ..........................................................................................46 Table 73. PHY 0 Register 19: Global Control 3 ..........................................................................................46 Table 74. PHY 0 Register 22: Port 0 Control 0 ...........................................................................................46 Table 75. PHY 0 Register 23: Port 0 Control 1 ...........................................................................................48 Table 76. PHY 0 Register 24: Port 0 Control 2 & VLAN Entry [A]...........................................................48 Table 77. PHY 0 Register 25: VLAN Entry [A]..........................................................................................48 Table 78. PHY 1 Register 16~17: IP Priority Address [A] ..........................................................................49 Table 79. PHY 1 Register 18~19: IP Priority Address [B] ..........................................................................49 Table 80. PHY 1 Register 24: Port 1 Control 2 & VLAN Entry [B] ...........................................................50 Table 81. PHY 1 Register 25: VLAN Entry [B] ..........................................................................................50 Table 82. PHY 2 Register 16~17: IP Priority Mask [A] ..............................................................................51 Table 83. PHY 2 Register 18~19: IP Priority Mask [B] ..............................................................................51 Table 84. PHY 2 Register 24: Port 2 Control 2 & VLAN Entry [C] ...........................................................52 Table 85. PHY 2 Register 25: VLAN Entry [C] ..........................................................................................52 Table 86. PHY 3 Register 16~18: Switch MAC Address ............................................................................53 Table 87. PHY 3 Register 24: Port 3 Control 2 & VLAN Entry [D]...........................................................53 Table 88. PHY 3 Register 25: VLAN Entry [D]..........................................................................................53 Table 89. PHY 4 Register 16~18: ISP MAC Address .................................................................................54 Table 90. PHY 4 Register 24: Port 4 Control 2 & VLAN Entry [E] ...........................................................55 Table 91. PHY 4 Register 25: VLAN Entry [E] ..........................................................................................55 Table 92. PHY 5 Register 16: MII Port Control 0 .......................................................................................56 Table 93. PHY 5 Register 17: MII Port Control 1 & VLAN Entry [I] ........................................................57 Table 94. PHY 5 Register 18: VLAN Entry [I] ...........................................................................................57 Table 95. PHY 5 Register 19: CPU Port & WAN Port ................................................................................57 Table 96. PHY 5 Register 24: Port 5 Control 2 & VLAN Entry [F] ...........................................................58 Table 97. PHY 5 Register 25: VLAN Entry [F] ..........................................................................................58 Table 98. PHY 6 Register 24: Port 6 Control 2 & VLAN Entry [G]...........................................................60 Table 99. PHY 6 Register 25: VLAN Entry [G]..........................................................................................60 Table 100. PHY 7 Register 16: Indirect Access Control .............................................................................61 Table 101. PHY 7 Register 17~20: Indirect Access Data ............................................................................62 Table 102. PHY 7 Register 24: Port 7 Control 2 & VLAN Entry [H].........................................................62 Table 103. PHY 7 Register 25: VLAN Entry [H]........................................................................................63 Single-Chip 9-Port 10/100Mbps Switch Controller xiii Track ID: JATR-1076-21 Rev. 1.4 RTL8309SB Datasheet Table 104. PHY 8 Register 0: Control .........................................................................................................63 Table 105. PHY 8 Register 1: Status............................................................................................................64 Table 106. PHY 8 Register 4: Auto-Negotiation Advertisement.................................................................64 Table 107. MII Port NWay Mode ................................................................................................................65 Table 108. MII Port Force Mode .................................................................................................................65 Table 109. 802.1Q VLAN Tag Frame Format .............................................................................................78 Table 110. IPv4 Frame Format ....................................................................................................................78 Table 111. SMI Read/Write Cycles..............................................................................................................81 Table 112. Loop Frame Format ...................................................................................................................86 Table 113. Speed and Bi-Color Link/Act Truth Table .................................................................................88 Table 114. Absolute Maximum Ratings.......................................................................................................90 Table 115. Operating Range ........................................................................................................................90 Table 116. DC Characteristics .....................................................................................................................90 Table 117. AC Characteristics......................................................................................................................91 Table 118. Digital Timing Characteristics ...................................................................................................93 Table 119. Thermal Operating Range ..........................................................................................................94 Table 120. Thermal Resistance....................................................................................................................95 Single-Chip 9-Port 10/100Mbps Switch Controller xiv Track ID: JATR-1076-21 Rev. 1.4 RTL8309SB Datasheet List of Figures Figure 1. Block Diagram .............................................................................................................................4 Figure 2. Pin Assignments ...........................................................................................................................5 Figure 3. MII Port Application ..................................................................................................................71 Figure 4. MII Port Operating Mode Overview..........................................................................................72 Figure 5. VLAN Grouping Example .........................................................................................................75 Figure 6. Tagged and Untagged Packet Forwarding When 802.1Q Tag Aware VLAN is Disabled .........76 Figure 7. ISP MAC Outbound Process ......................................................................................................80 Figure 8. ISP MAC Inbound Process.........................................................................................................80 Figure 9. Input Drop vs. Output Drop .......................................................................................................82 Figure 10. Start and Stop Definition ............................................................................................................83 Figure 11. Output Acknowledge ..................................................................................................................84 Figure 12. Random Read .............................................................................................................................84 Figure 13. Sequential Read..........................................................................................................................84 Figure 14. MII Port Loopback .....................................................................................................................85 Figure 15. Loop Example ............................................................................................................................86 Figure 16. Floating and Pull-down of LED Pins .........................................................................................87 Figure 17. Two-Pin Bi-Color LED for SPD Floating or Pull-high..............................................................88 Figure 18. Two-Pin Bi-Color LED for SPD Pull-down...............................................................................88 Figure 19. Bi-Color LED Reference Schematic ..........................................................................................89 Figure 20. Reception Data Timing of MII/SNI/SMI Interface ....................................................................92 Figure 21. Transmission Data Timing of MII/SNI/SMI Interface...............................................................92 Figure 22. Cross-section of 128-Pin PQFP..................................................................................................94 Figure 23. Application for Transformer with Connected Central Tap .........................................................97 Figure 24. Bob Smith Termination ..............................................................................................................98 Single-Chip 9-Port 10/100Mbps Switch Controller xv Track ID: JATR-1076-21 Rev. 1.4 RTL8309SB Datasheet 1. General Description The RTL8309SB is a 128-pin, ultra low power, high-performance 8-port Fast Ethernet single-chip switch with one extra MII port for specific applications. It integrates all the functions of a high speed switch system—including SRAM for packet buffering, non-blocking switch fabric, address management, one general use MII interface, eight 10/100Base-TX transceivers, and nine Media Access Controllers—into a single 0.18µm CMOS device. It provides compatibility with all industry standard Ethernet and Fast Ethernet devices. Only a 25MHz crystal is required; the EEPROM is optional to save BOM costs. The embedded packet storage SRAM in the RTL8309SB features superior memory management technology to efficiently utilize the memory space. An integrated 1024-entry look-up table stores MAC address and associated information in a 10-bit direct mapping scheme. The table provides read/write access from the SMI interface, and each of the entries can be configured as a static entry. A static entry indicates that this entry is controlled by the external management processor and automatic aging and learning of the entry will not take place. To prevent MAC address mapping collisions, the embedded 16entry Content-Addressable Memory (CAM) offers another memory space for recording the MAC address when the mapped entry in the lookup table is occupied. For each incoming packet, the RTL8309SB searches the entries in the lookup table and the 16-entry CAM simultaneously. Then it obtains the correct destination port information to determine which output port the packet should be forwarded to. The aging time of the RTL8309SB is around 300 seconds (this may be sped up to 800µs via EEPROM configuration). The ninth port of the RTL8309SB implements a MAC module without a PHY transceiver to provide an MII interface for connection with an external PHY or MAC in specific applications. This MII interface may be set to MII PHY mode, SNI PHY mode, or MII MAC mode to work with an external MAC module in a routing engine application, PHY module in a HomePNA application, or other physical layer transceivers. In order to operate correctly, both sides of the connection must be configured to the same speed, duplex, and flow control settings. Four pins are used for the ninth port to force the link status. This interface should be 2.5V or 3.3V compatible depending on the voltage supplied to the power pin VDDIO of this interface. The RTL8309SB is capable of preventing broadcast storms by setting strapping pins upon system reset. When this function is enabled, it will drop broadcast packets after receiving 64 continuous broadcast packets. This counter will be reset to 0 every 800ms or when the RTL8309SB receives a non-broadcast packet. The RTL8309SB displays the port status via four LED indicators (with optional blinking time setting). These LEDs blink for diagnostic purposes at system reset time. The RTL8309SB provides various type of Single-Chip 9-Port 10/100Mbps Switch Controller 1 Track ID: JATR-1076-21 Rev. 1.4 RTL8309SB Datasheet LED combinations to fit different applications. Eight combinations of link, activity, speed, duplex, and collision, are available. Bi-color LED mode is also supported on the Link/Act LED. The RTL8309SB supports standard 802.3x flow control frames for full duplex, and optional backpressure for half duplex. It determines when to invoke the flow control mechanism by checking the availability of system resources, including the packet buffers and transmitting queues. If one of the forwarding ports is blocked, or system resources are unavailable, broadcast frames will be dropped according to the system configuration. The RTL8309SB support two types of dropping methods. The input dropping method will not forward broadcast packets to any output ports and will drop these packets directly. The output dropping method will forward broadcast packets to non-blocked ports only. To improve real-time and multimedia networking applications, the RTL8309SB supports four types of QoS (Quality of Service). These are based on (1) Port-based priority, (2) 802.1p/Q VLAN priority tag, (3) TOS field in IPv4 header, (4) Specific IP address. Each output port supports a weighted ratio of highpriority and low-priority queues to fit bandwidth requirements in different applications. The RTL8309SB provides 802.1Q port-based VLAN operation to separate logical connectivity from physical connectivity. Each port may be set to any topology via EEPROM upon reset or SMI after reset. The RTL8309SB also provides options to meet special application requirements. The first option is the ARP VLAN function, which is used to select to broadcast ARP frames to all VLANs or only forward ARP frames to the originating VLAN. The second option is the Leaky VLAN function, which is used to select to send unicast frames to other VLANs or only forward unicast frames to the originating VLAN. The VLAN tags can be inserted or removed on a per-port basis. In router applications, the router may want to know which input port this packet came from. The RTL8309SB supports Port VID (PVID) for each port to insert a PVID in the VLAN tag on egress. In this function, the VID information carried in the VLAN tag will be changed to PVID. The RTL8309SB also provides an option to admit VLAN tagged packet with a specific PVID only. If this function is enabled, it will drop non-tagged packets and packets with an incorrect PVID. Each physical layer channel consists of a 4B5B encoder/decoder, Manchester encoder/decoder, transmit output driver, scrambler/descrambler, output wave shaping, filters, digital adaptive equalizer, PLL circuit, and DC restoration circuit for clock/data recovery. This integrated chip benefits from low power consumption and offers advanced functions with flexible configuration for a small workgroup switch, multimedia, or real-time traffic mixed with other data type traffic, and other applications. Single-Chip 9-Port 10/100Mbps Switch Controller 2 Track ID: JATR-1076-21 Rev. 1.4 RTL8309SB Datasheet 2. Features Integrates eight 10/100 transceivers and nine MAC units for 10Base-T and 100Base-TX. Embedded SRAM for packet storage. On-chip 1024-entry look-up table in direct mapping mode. Embedded 16-entry CAM for hash collision mapping. Provides read/write access to look-up table entries via SMI interface. Provides non-blocking wire speed reception and transmission. Flow control fully supported: Half-duplex: backpressure flow control. Full-duplex: IEEE 802.3x flow control. Support for 4 LEDs per-port in various combinations for comprehensive applications. Optional loop detection function with an LED to indicate the existence of a loop. Supports MII loopback. LEDs blink upon reset for LED diagnostics. Flexible system configuration by strapping pins, EEPROM, or SMI interface. Optional crossover detection and auto correction for plug-and-play. Fully compliant with IEEE 802.3/802.3u. Optional Forwarding/Filtering reserved control frames (DID= 0180C2000003~0180C200000F). Optional Broadcast Input/Output Drop flow control. Optional maximum packet length 1536/1552 Bytes. Supports two Power Reduction methods: Power saving mode (automatic cable detection). Power down mode (via PHY register 0.11). Supports QoS function: QoS based on: (1) Port-based priority (2) 802.1p VLAN tag (3) DiffServ/TOS field in TCP/IP header (4) IP address. Supports two-level priority queues with various weighting ratios. Queue service rate based on weighted round robin algorithm. Optional auto turn off Flow Control for 1~2 sec to avoid head-of-line blocking. Supports MII interface connection to external MAC or PHY via 3 modes. PHY mode MII for router applications. PHY mode SNI for router applications. MAC mode MII for HomePNA or other PHY applications. Flexible 802.1Q port/tag-based VLAN. Optional 802.1Q tag-VID aware function. Optional VLAN Ingress Tag Admit Control. Optional VLAN Ingress Member set filtering. Optional ARP VLAN for broadcast packet. Optional Leaky VLAN for unicast packet. Optional 802.1P/Q tag insertion or removal on per-port basis (egress). 25MHz crystal input. 0.18µm, CMOS technology. 128-pin PQFP package. 1.8V core voltage. Independent power options for 2.5V or 3.3V MII interface. Single-Chip 9-Port 10/100Mbps Switch Controller 3 Track ID: JATR-1076-21 Rev. 1.4 RTL8309SB Datasheet 3. Block Diagram IBREF Waveform Shaping RX+-[0] TX+-[0] 10Base-T or 100Base-TX PHYceiver 10/100 MAC 0 Flow Control TX/RX FIFO RTL8309SB RX+-[1] TX+-[1] 10Base-T or 100Base-TX PHYceiver 10/100 MAC 1 Flow Control TX/RX FIFO RX+-[2] TX+-[2] 10Base-T or 100Base-TX PHYceiver 10/100 MAC 2 Flow Control TX/RX FIFO Look-up Table (1024-entries) Switch Fabric, VLAN, QoS, Trunking RX+-[3] TX+-[3] 10Base-T or 100Base-TX PHYceiver 10/100 MAC 3 Flow Control TX/RX FIFO Queue Management RX+-[4] TX+-[4] 10Base-T or 100Base-TX PHYceiver 10/100 MAC 4 Flow Control TX/RX FIFO Flow Control TX/RX FIFO RX+-[5] TX+-[5] 10Base-T or 100Base-TX PHYceiver 10/100 MAC 5 Buffer Management RX+-[6] TX+-[6] 10Base-T or 100Base-TX PHYceiver 10/100 MAC 6 Flow Control TX/RX FIFO Packet Buffer RX+-[7] TX+-[7] 10Base-T or 100Base-TX PHYceiver 10/100 MAC 7 Flow Control TX/RX FIFO EEPROM Interface MII Signal 13 / MAC Mode Inter face 10/100 MAC 8 Flow Control TX/RX FIFO Control Registers PHY Mode Mode Select P8MODE[1:0] Figure 1. Block Diagram Single-chip 9-port 10/100Mbps Switch Controller 4 Track ID: JATR-1076-21 Rev. 1.4 4. En_AutoXover/P1_LED[3] En_ANEG/P1_LED[2] En_FCTRL/P1_LED[1] En_BKPRS/P1_LED[0] VDDD VSSD Force_Duplex/P0_LED[3] Force_Speed/P0_LED[2] En_BRD_CTRL/P0_LED[1] En_RST_BLNK/P0_LED[0] EnEEPROM/LoopLED# VDDD VSSD Test pin VSSPLL X1 X2 VDDPLL Test Pin IBREF VDDA TXON[0] TXOP[0] VSSA RXIP[0] RXIN[0] Pin Assignments 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 Single-chip 9-port 10/100Mbps Switch Controller Figure 2. Pin Assignments 5 RTL8309SB VDDA VSSA TXON[1] TXOP[1] VSSA RXIP[1] RXIN[1] VDDA RXIN[2] RXIP[2] VSSA TXOP[2] TXON[2] VDDA TXON[3] TXOP[3] VSSA RXIP[3] RXIN[3] VDDA RXIN[4] RXIP[4] VSSA TXOP[4] TXON[4] VDDA TXON[5] TXOP[5] VSSA RXIP[5] RXIN[5] VDDA RXIN[6] RXIP[6] VSSA TXOP[6] TXON[6] VDDA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 MCOL/PCOL VSSIO VDDIO MTXD[3]/PRXD[3] MTXD[2]/PRXD[2] MTXD[1]/PRXD[1] MTXD[0]/PRXD[0] MTXEN/PRXDV MTXC/PRXC SDA_MDIO SCL_MDC VSSD VDDD MII_LNK_STA# MII_DUP_STA MII_SPD_STA MII_FCTRL_STA RESET# NC Test Pin VDDA TXON[7] TXOP[7] VSSA RXIP[7] RXIN[7] P2_LED[0]/MII_MODE[0] P2_LED[1]/MII_MODE[1] P2_LED[2]/LED_MODE[0] P2_LED[3]/LED_MODE[1] P3_LED[0]/LED_MODE[2] P3_LED[1]/Dis_Trunk VSSD VDDD P3_LED[2]/En_Forward P3_LED[3]/En_Defer P4_LED[0]/En_48pass1 P4_LED[1]/En_Agrs_Back P4_LED[2]/Max_Pkt_Len P4_LED[3]/Max_Pause_Count VSSD VDDD P5_LED[0]/Sel_PortPri[0] P5_LED[1]/Sel_PortPri[1] P5_LED[2]/Dis_VLAN_Pri P5_LED[3]/Dis_DS_Pri P6_LED[0]/QWeight[0] P6_LED[1]/QWeight[1] VSSD VDDD P6_LED[2]/Dis_VLAN P6_LED[3]/Dis_LeakyVLAN P7_LED[0]/Dis_ARPVLAN P7_LED[1]/LED_BLNK_TIME P7_LED[2]/Port_LED_LOC P7_LED[3]/Dis_FC_AutoOff VSSD VDDD MRXD[3]/PTXD[3] MRXD[2]/PTXD[2] MRXD[1]/PTXD[1] MRXD[0]/PTXD[0] MRXDV/PTXEN MRXC/PTXC Track ID: JATR-1076-21 Rev. 1.4 RTL8309SB Datasheet RTL8309SB Datasheet Codes used in the following tables: ‘A’ stands for analog; ‘D’ stands for digital, ‘I’ stands for input; ‘O’ stands for output. Table 1. Pin Assignments Name VDDA, VSSA, TXON[1], TXOP[1], VSSA, RXIP[1], RXIN[1], VDDA, RXIN[2], RXIP[2], VSSA, TXOP[2], TXON[2], VDDA, TXON[3], TXOP[3], VSSA, RXIP[3], RXIN[3], VDDA, RXIN[4], RXIP[4], VSSA, TXOP[4], TXON[4], VDDA, TXON[5], TXOP[5], VSSA, RXIP[5], RXIN[5], VDDA, RXIN[6], RXIP[6], VSSA, TXOP[6], TXON[6], VDDA, RXIN[7], RXIP[7], VSSA, TXOP[7], TXON[7], VDDA, NC, NC RESET# MII_FCTRL_STA, MII_SPD_STA, MII_DUP_STA, MII_LNK_STA#, VDDD, VSSD, SCL_MDC, SDA_MDIO, MTXC/PRXC, MTXEN/PRXDV, MTXD[0]/PRXD[0], MTXD[1]/PRXD[1], MTXD[2]/PRXD[2], MTXD[3]/PRXD[3], VDDIO, VSSIO, MCOL/PCOL Pin No. 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64 Type AVDD AGND AO AO AGND AI AI AVDD AI AI AGND AO AO AVDD AO AO AGND AI AI AVDD AI AI AGND AO AO AVDD AO AO AGND AI AI AVDD AI AI AGND AO AO AVDD AI AI AGND AO AO AVDD Name MRXC / PTXC MRXDV / PTXDV, MRXD[0] / PTXD[0], MRXD[1] / PTXD[1], MRXD[2] / PTXD[2], MRXD[3] / PTXD[3], VDDD, VSSD, P7_LED[3] / Dis_FC_AutoOff, P7_LED[2] / Port_LED_LOC, P7_LED[1] / LED_BLNK_TIME, P7_LED[0] / Dis_ARPVLAN, P6_LED[3] / Dis_LeakyVLAN, P6_LED[2] / Dis_VLAN, VDDD, VSSD, P6_LED[1] / QWeight[1], P6_LED[0] / QWeight[0], P5_LED[3] / Dis_DS_Pri, P5_LED[2] / Dis_VLAN_Pri, P5_LED[1] / Sel_PortPri[1], P5_LED[0] / Sel_PortPri[0], VDDD, VSSD, P4_LED[3] / Max_Pause_Count, P4_LED[2] / Max_Pkt_Len, P4_LED[1] / En_Agrs_Back, P4_LED[0] / En_48pass1, P3_LED[3] / En_Defer, P3_LED[2] / En_Forward, VDDD, VSSD P3_LED[1] / Dis_Trunk, P3_LED[0] / LED_MODE[2], P2_LED[3] / LED_MODE[1], P2_LED[2] / LED_MODE[0], P2_LED[1] / MII_MODE[1], P2_LED[0] / MII_MODE[0], P1_LED[3] / En_AutoXover, P1_LED[2] / En_ANEG, P1_LED[1] / En_FCTRL P1_LED[0] / En_BKPRS, VDDD, VSSD P0_LED[3] / Force_Duplex, P0_LED[2] / Force_Speed, P0_LED[1] / En_BRD_CTRL, P0_LED[0] / En_RST_BLNK, LoopLED#,/EnEEPROM VDDD, VSSD, NC, VSSPLL, X1, X2, VDDPLL, NC, IBREF, VDDA, TXON[0], TXOP[0], VSSA, RXIP[0], RXIN[0], Pin No 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128 Type I/O I I I I I DVDD DGND I/O I/O I/O I/O I/O I/O DVDD DGND I/O I/O I/O I/O I/O I/O DVDD DGND I/O I/O I/O I/O I/O I/O DVDD DGND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O DVDD DGND I/O I/O I/O I/O I/O DVDD DGND AGND I O AVDD AO AVDD AO AO AGND AI AI I I I I I DVDD DGND I/O I/O I/O O I/O I/O I/O I/O DVDD DGND I/O Single-chip 9-port 10/100Mbps Switch Controller 6 Track ID: JATR-1076-21 Rev. 1.4 RTL8309SB Datasheet 5. Pin Descriptions “Type” codes used in the following tables: ‘A’ stands for analog; ‘D’ stands for digital, ‘I’ stands for input; ‘O’ stands for output, ‘Ipu’ stands for input with internal pull-up. Upon reset: defined as a short time after the end of a hardware reset. After reset: defined as the time after the specified “Upon Reset” time. 5.1. Media Connection Pins Table 2. Media Connection Pins Pin Name RXIP[7:0] RXIN[7:0] Pin No. 40, 34, 30, 22, 18, 10, 6, 127, 39, 33, 31, 21, 19, 9, 7, 128 42, 36, 28, 24, 16, 12, 4, 125, 43, 37, 27, 25, 15, 13, 3, 124 Type AI Description Differential Receive Data Input shared by 100Base-TX, 10Base-T for connection to a transformer. Default TXOP[7:0] TXON[7:0] AO Differential Transmit Data Output shared by 100Base-TX, 10Base-T for connection to a transformer. 5.2. MII Port MAC Interface Pins The external device can be either 2.5V or 3.3V compatible depending on the power supplied to VDDIO. The input and input/output pins listed below do not implement an internal pull-high resistor. An external pull-high resistor is required for these floating input pins to reduce power consumption. Table 3. MII Port MAC Interface Pins Pin Name MRXD[3:0] /PTXD[3:0] Pin No. 70, 69, 68, 67 Type I Description For MII MAC mode, these pins are MRXD[3:0], MII receive data nibble. For MII PHY mode, these pins are PTXD[3:0], MII transmit data nibble. For SNI PHY mode, PTXD[0] is serial transmit data. For MII MAC mode, this pin represents MRXDV, MII receive data valid. For MII PHY mode, this pin represents PTXEN, MII transmit enable. For SNI PHY mode, this pin represents PTXEN, transmit enable. Default MRXDV/PTXEN 66 I Single-chip 9-port 10/100Mbps Switch Controller 7 Track ID: JATR-1076-21 Rev. 1.4 RTL8309SB Datasheet Pin Name MRXC/PTXC Pin No. 65 Type I/O Description Default For MII MAC mode, this pin represents MRXC/MII receive clock (acts as input). For MII/SNI PHY mode, this pin represent PTXC/MII transmit clock (acts as output). For MII MAC mode, this pin represents MCOL, MII collision detect (acts as input). For MII/SNI PHY mode, this pin represents PCOL, MII collision detect (acts as output). Output after reset. For MII MAC mode, these pins are MTXD[3:0], MII transmit data of MAC. For MII PHY mode, these pins are PRXD[3:0], MII receive data of MAC. For SNI PHY mode, PRXD[0] is SNI serial receive data. PRXD[3:1] are unused. For MII MAC mode, this pin represents MTXEN, MII transmit enable. For MII PHY mode, this pin represents PRXDV, MII receive data valid. For SNI PHY mode, this pin represents PRXDV, SNI receive data valid. For MII MAC mode, this pin represents MTXC, MII transmit clock (acts as input). For MII/SNI PHY mode, this pin represents MRXC, MII/SNI receive clock (acts as output). Input upon reset = Select MII port (9th port) operating mode. 11 11=Tristate MII output. 10=MII MAC mode. 01=MII PHY mode. 00=SNI PHY mode. Provides MII port (9th port) Link Status for MAC module at MII 1 MAC/MII PHY/SNI PHY operation mode in real time. This pin sets the link status of the MII port MAC module in real-time. Provides MII port (9th port) duplex status for MAC module at MII 1 MAC/MII PHY/SNI PHY operation mode in real time. 1: MII port operates in full duplex mode 0: MII port operates in half duplex mode Provides MII port (9th port) speed status for MAC module at MII 1 MAC/MII PHY/SNI PHY operation mode in real time. 1: MII port operates at 100Mbps speed 0: MII port operates at 10Mbps speed In an application outlined below, this pin should be left floating: For HomePNA (MII MAC mode), speed is determined by RXC and TXC from PHY of HomePNA running at 1Mbps. For SNI PHY mode, speed is fixed at 10MHz clock rate. Provides MII port (9th port) flow control status for MAC module at MII MAC/MII PHY/SNI PHY operation mode in real time. 1: MII port has flow control ability 0: MII port does not have flow control ability MCOL/PCOL 64 I/O MTXD[3:0] /PRXD[3:0] 61, 60, 59, 58 O MTXEN/PRXDV 57 O MTXC/PRXC 56 I/O MII_MODE[1:0] /P2_LED[1:0] 101, 102 Ipu MII_LNK_STA# 51 Ipu MII_DUP_STA 50 Ipu MII_SPD_STA 49 Ipu MII_FCTRL_STA 48 Ipu 1 Single-chip 9-port 10/100Mbps Switch Controller 8 Track ID: JATR-1076-21 Rev. 1.4 RTL8309SB Datasheet 5.3. Miscellaneous Pins Table 4. Miscellaneous Pins Pin Name X1 X2 RESET# Pin No. 118 119 47 Type I O I Description 25MHz crystal input. The clock tolerance is +-50ppm. 25MHz crystal output. Active low reset signal. To complete the reset function, this pin must be asserted for at least 10ms. After reset, about 30ms is needed for the RTL8309SB to complete the internal test function and initialization. Note: This pin is a Schmitt input pin. Control transmit output waveform Vpp. This pin should be grounded through a 2.0K ohm resistor. Not Connected – Floating in normal operation. Default IBREF NC 122 45, 46, 116, 121 A 5.4. Port LED Pins Each port supports four LED pins for status indication. The indicated status of these four LED pins may be changed by setting different values for strapping pin LED_MODE[2:0]. Note 1: All LED statuses are represented as active-low or high depending on input strapping, except Bi-color Link/Act in Bi-color LED mode, whose polarity depends on Bi-color Speed status. Note 2: Those pins are dual function pins: output for LED and input for strapping. Table 5. Port LED Pins Pin Name P0_LED[0] P1_LED[0] P2_LED[0] P3_LED[0] P4_LED[0] P5_LED[0] P6_LED[0] P7_LED[0] Pin No. Type 112, 106, Ipu/O 102, 98, 92, 86, 82, 76 Description Output after reset = used for the 1st LED. Mode 7: Speed (On =100 Mbps, Off =10Mbps) Mode 6: Activity (Flash=Tx or Rx activity) Mode 5: Speed (On =100 Mbps, Off =10Mbps) Mode 4: Collision (Flash=Collision) Mode 3: Reserved for internal use Mode 2: RxAct+10/100 (Flash every 120ms=10Mbps Rx activity, Flash every 43ms = 100Mbps Rx activity). Mode 1: Duplex+Collision (On=Full, Off=Half with no collision, Flash = Collision) Mode 0: Bi-color Speed. Polarity depends on Bi-color Link+Activity LED status. Refer to section 8.3.17 LEDs, page 87, for detailed information. Default 1 1 1 1 1 1 1 1 Single-chip 9-port 10/100Mbps Switch Controller 9 Track ID: JATR-1076-21 Rev. 1.4 RTL8309SB Datasheet Pin Name P0_LED[1] P1_LED[1] P2_LED[1] P3_LED[1] P4_LED[1] P5_LED[1] P6_LED[1] P7_LED[1] Description nd Ipu/O Output after reset = used for the 2 LED. Mode 7: Duplex+Collision (On=Full, Off=Half with no collision, Flash = Collision) Mode 6: Speed (On =100 Mbps, Off =10Mbps) Mode 5: Duplex (On=Full, Off=Half) Mode 4: Duplex (On=Full, Off=Half) Mode 3: Duplex+Collision (On=Full, Off=Half with no collision, Flash = Collision) Mode 2: TxAct+10/100 (Flash every 120ms = 10Mbps Tx activity, Flash every 43ms = 100Mbps Tx activity) Mode 1: 10Link+Act (On=Link on 10Mbps, Off=No link on 10Mbps, Flash=10Mbps Tx or Rx activity) Mode 0: Duplex+Collision (On=Full, Off=Half with no collision, Flash = Collision) 110, 104, Ipu/O Output after reset = used for the 3rd LED. Mode 7: Link+Act (On=Link, Off=No link, Flash=Tx or Rx activity) 100, 94, Mode 6: Link (On=Link, Off=No link) 90, 84, Mode 5: Link+Act (On=Link, Off=No link, Flash=Tx or Rx activity) 78, 74, Mode 4: Link+Act+Speed (On=Link, Off=No link, Flash every 120ms=10Mbps activity, flash every 43ms=100Mbps) Mode 3: Link+Act+Speed (On=Link, Off=No link, Flash every 120ms=10Mbps activity, flash every 43ms=100Mbps) Mode 2: Link (On=Link, Off=No link) Mode 1: 100Link+Act (On=Link on 100Mbps, Off=No link on 100Mbps, Flash=100Mbps Tx or Rx activity) Mode 0: Bi-color Speed. Polarity depends on Bi-color Link+Activity LED status. Refer to section 8.3.17 LEDs, page 87, for detailed information. 109, 103, Ipu/O Output after reset = used for the 4th LED. Mode 7: Reserved for internal use 99, 93, Mode 6: Reserved for internal use 89, 83, Mode 5: Reserved for internal use 77, 73 Mode 4: Reserved for internal use Mode 3: 10/100 (On =100 Mbps, Off =10Mbps) Mode 2: Reserved for internal use Mode 1: Reserved for internal use Mode 0: Reserved for internal use 98, I/O Input upon reset = Select LED display mode upon reset. 99, LED_MODE[2:0]=111 -> Mode 7: 100 Speed, Duplex+Collision, Link+Act, Reserved LED_MODE[2:0]=110 -> Mode 6: Activity, Speed, Link, Reserved LED_MODE[2:0]=101 -> Mode 5: Speed, Duplex, Link+Act, Reserved LED_MODE[2:0]=100 -> Mode 4: Collision, Duplex, Link+Act+Speed, Reserved LED_MODE[2:0]=011 -> Mode 3: Reserved, Duplex+Collision, Link+Act+Speed, 10/100 LED_MODE[2:0]=010 -> Mode 2: RxAct+10/100, TxAct+10/100, Link, Reserved LED_MODE[2:0]=001 -> Mode 1: Duplex+Collision, 10Link+Act, 100Link+Act, Reserved. LEDM_ODE[2:0]=000 -> Mode 0: Bi-color Speed, Duplex+Collision, Bi-color Link+Act, Reserved 10 Pin No. 111, 105, 101, 97, 91, 85, 81, 75 Type Default 1 1 1 1 1 1 1 1 P0_LED[2] P1_LED[2] P2_LED[2] P3_LED[2] P4_LED[2] P5_LED[2] P6_LED[2] P7_LED[2] 1 1 1 1 1 1 1 1 P0_LED[3] P1_LED[3] P2_LED[3] P3_LED[3] P4_LED[3] P5_LED[3] P6_LED[3] P7_LED[3] LED_MODE[2] /P3_LED[0] LED_MODE[1] /P2_LED[3] LED_MODE[0] /P2_LED[2] 1 1 1 1 1 1 1 1 111 Single-chip 9-port 10/100Mbps Switch Controller Track ID: JATR-1076-21 Rev. 1.4 RTL8309SB Datasheet Pin Name Port_LED_LOC /P7_LED[2] Pin No. 74 Description Ipu/O Input upon reset = Per port LED pin location reversed. 1: For designs where LEDs are placed at the opposite side to the phone jack Port 0 LEDs are assigned at pins 109~112 Port 1 LEDs are assigned at pins 103~106 Port 2 LEDs are assigned at pins 99~102 Port 3 LEDs are assigned at pins 93, 94, 97, 98 Port 4 LEDs are assigned at pins 89~92 Port 5 LEDs are assigned at pins 83~86 Port 6 LEDs are assigned at pins 77, 78, 80, 81 Port 7 LEDs are assigned at pins 73~76 0: Suitable for designs where LEDs are placed on the same side as the phone jack Port 0 LEDs are assigned at pins 73~76 Port 1 LEDs are assigned at pins 77, 78, 80, 81 Port 2 LEDs are assigned at pins 83~86 Port 3 LEDs are assigned at pins 89~92 Port 4 LEDs are assigned at pins 93, 94, 97, 98 Port 5 LEDs are assigned at pins 99~102 Port 6 LEDs are assigned at pins 103~106 Port 7 LEDs are assigned at pins 109~112 Ipu/O Output after reset = LoopLED# used for LED. If Loop detection is enabled, this pin indicates whether a Network loop is detected or not. Otherwise, this pin has no function. Note: The LED statuses are represented as active-low or high depending on input strapping. => If Input=1: Output 0=Network loop is detected. 1=No loop. => If Input=0: Output 1=Network loop is detected. 0= No loop. Type Default 1 LoopLED# /EnEEPROM 113 1 5.5. Serial EEPROM and SMI Pins Table 6. Serial EEPROM and SMI Pins Pin Name EnEEPROM /LoopLED# SCL_MDC Pin No. 113 Type Ipu/O Description Input upon reset = Enable loading of serial EEPROM upon reset. 1: Enable Serial EEPROM load upon reset 0: Disable Serial EEPROM load upon reset EEPROM Serial Clock or MDC. This pin is three state when pin RESET#=0. When the RTL8309SB detects an EEPROM connected to it, this pin becomes SCL (output) to load the serial EEPROM upon reset. Then the pin changes to MDC (input) after reset. In this case, this pin should be pulled high (VDDIO 2.5V/3.3V) by external register. When the RTL8309SB does not detect an EEPROM connected to it, this pin is MDC (input). In this case, it needs an external pull-high resistor, unless it is floated. Default 1 54 I/O - Single-chip 9-port 10/100Mbps Switch Controller 11 Track ID: JATR-1076-21 Rev. 1.4 RTL8309SB Datasheet Pin Name SDA_MDIO Pin No. 55 Type I/O Description EEPROM Serial Data Input/Output or MDIO. This pin is three state when pin RESET#=0. When the RTL8309SB detects an EEPROM connected to it, this pin becomes SDA (input/output) to load the serial EEPROM upon reset. The pin changes to MDIO (input/output) after reset. When the RTL8309SB does not detect an EEPROM connected to it, this pin is MDIO (input/output). It should be pulled high by an external resistor. Default - 5.6. Strapping Pins Note: All strapping pins are dual function pins: output for LED and input for strapping. The table below covers strapping only. See Port LED Pins, on page 9, for LED pin settings. Table 7. Strapping Pins Pin Name En_ANEG /P1_LED[2] Pin No. 104 Type Ipu Description Input upon reset = Enable Auto-negotiation function. 1: Enable the auto-negotiation function (NWay mode) and set PHY register 0.12 0: Disable the auto-negotiation function (force mode) and deselect PHY register 0.12 Output after reset = used for LED. Input upon reset = Enable flow control ability in full duplex mode. 1: In NWay mode, this pin sets PHY register 4.10, but the flow control function is finally enabled based on the auto negotiation result. In force mode, this pin will always enable the flow control function 0: Disable the flow control function Output after reset = used for LED. Input upon reset = Enable backpressure ability in half duplex mode. 1: Enable backpressure 0: Disable backpressure Output after reset = used for LED. Force duplex mode. This pin sets PHY Reg.0.8 and influences the contents of PHY Reg.4. 1: Force full duplex if auto-negotiation is disabled 0: Force half duplex if auto-negotiation is disabled Output after reset = used for LED. Force operating speed. This pin sets PHY Reg.0.13 and influences the contents of PHY Reg.4. 1: Force 100Mbps speed if auto-negotiation is disabled 0: Force 10Mbps speed if auto-negotiation is disabled Output after reset = used for LED. Default 1 En_FCTRL /P1_LED[1] 105 Ipu 1 En_BKPRS /P1_LED[0] 106 Ipu 1 Force_Duplex /P0_LED[3] 109 Ipu 1 Force_Speed /P0_LED[2] 110 Ipu 1 Single-chip 9-port 10/100Mbps Switch Controller 12 Track ID: JATR-1076-21 Rev. 1.4 RTL8309SB Datasheet Pin Name En_BRD_CTRL /P0_LED[1] Pin No. 111 Type Ipu Description Input upon reset = Disable Broadcast Storm Control. 1: Disable Broadcast Storm Control 0: Enable Broadcast Storm Control Default 1 En_RST_BLNK /P0_LED[0] 112 Ipu Output after reset = used for LED. Input upon reset = Enable blinking of LEDs upon reset. 1: Enable power-on LED blinking for diagnosis 0: Disable power-on LED blinking Output after reset = used for LED. Input upon reset = Enable Auto crossover detection. 1: Enable auto crossover detection 0: Disable auto crossover detection. MDI only Output after reset = used for LED. Disable auto turn off of flow control ability. 1: Disable 0: Enable auto turn off flow control ability on the low priority queue for 1~2 seconds whenever the port receives a high priority frame. The flow control ability will be re-enabled if this port does not receive another high priority frame during this 1~2 second duration Output after reset = used for LED. Input upon reset = Enable forwarding of 802.1D specified reserved group MAC address frames. 1: Forward reserved control packets with DID=01-80-C2-00-00-03 to 01-80-C2-00-00-0F 0: Filter reserved control packets with DID=01-80-C2-00-00-03 to 01-80-C2-00-00-0F Output after reset = used for LED. Input upon reset = Enable carrier sense defering function. 1: Enable carrier sense deferring function for half duplex backpressure 0: Disable carrier sense deferring function for half duplex backpressure Output after reset = used for LED. Enable 48 pass 1 mechanism. 1: 48 pass 1. Continuously collides 48 input packets then passes 1 packet to retain system resources and avoid repeater partition when buffer is full 0: Continuously collides input packets to avoid packet loss when buffer is full Output after reset = used for LED. Input upon reset = Enable aggressive back-off mechanism. 1: Enable more aggressive back-off mechanism in half duplex mode for performance enhancement. The back-off limitation will become 3 in this mode (default is 10) 0: Disable aggressive back-off mechanism in half duplex mode Output after reset = used for LED. 1 En_AutoXover /P1_LED[3] 103 Ipu 1 Dis_FC_AtuoOff /P7_LED[3] 73 Ipu 1 En_Forward /P3_LED[2] 94 Ipu 1 En_Defer /P3_LED[3] 93 Ipu 1 En_48pass1 /P4_LED[0] 92 Ipu 1 En_Agrs_Back /P4_LED[1] 91 Ipu 1 Single-chip 9-port 10/100Mbps Switch Controller 13 Track ID: JATR-1076-21 Rev. 1.4 RTL8309SB Datasheet Pin Name Max_Pkt_Len /P4_LED[2] Pin No. 90 Type Ipu Description Input upon reset = Select maximum frame length. 1: 1536 bytes 0: 1552 bytes Output after reset = used for LED. Input upon reset = Select the max Pause frame count during a congested event. 1: Generates maximum of 32 pause frames, even if congestion still exists 0: Continuously generates pause frames until congestion is resolved Output after reset = used for LED. Disable Two Port Trunking function. 1: Disable two port trunking function 0: Port 0 and port 1 are combined as one trunk Output after reset = used for LED. Input upon reset = Select high priority port for port-based priority QoS. 11: Disable port-based priority function 10: Select port 0 as high priority port 01: Select port 2 as high priority port 00: Select port 3 as high priority port Output after reset = used for LED. Input upon reset = Disable 802.1p VLAN tag priority based QoS. 1: Disable 802.1p priority classification for ingress packets on each port 0: Enable 802.1p priority classification for ingress packets on each port. A User priority field in the VLAN tag greater or equal to 4 will be considered a high priority packet Output after reset = used for LED. Input upon reset = Disable Diffserv priority based QoS. 1: Disable diffserv priority classification for ingress packets on each port 0: Enable diffserv priority classification for ingress packets on each port Output after reset = used for LED. Input upon reset = Weighted round robin ratio priority queue. The frame service ratio between the high priority queue and low priority queue is: 11=16:1 10=Always high priority queue first 01=8:1 00=4:1 Output after reset = used for LED. Default 1 Max_Pause_Count /P4_LED[3] 89 Ipu 1 Dis_Trunk /P3_LED[1] 97 Ipu 1 Sel_PortPri[1:0] /P5_LED[1:0] 85, 86 Ipu 1 Dis_VLAN_Pri /P5_LED[2] 84 Ipu 1 Dis_DS_Pri /P5_LED[3] 83 Ipu 1 QWeight[1:0] /P6_LED[1:0] 81, 82 Ipu 1 Single-chip 9-port 10/100Mbps Switch Controller 14 Track ID: JATR-1076-21 Rev. 1.4 RTL8309SB Datasheet Pin Name Dis_VLAN /P6_LED[2] Pin No. 78 Type Ipu Description Input upon reset = Disable VLAN. 1: Disable VLAN 0: Enable VLAN. The default VLAN membership configuration is MII port overlapped with all the other ports to form 8 individual VLANs. The default membership configuration may be modified by setting internal registers via the SMI interface or EEPROM Output after reset = used for LED. Input upon reset = Disable Leaky VLAN. 1: Disable forwarding of unicast frames to other VLANs 0: Enable forwarding of unicast frames to other VLANs Note: Broadcast and multicast frames adhere to the VLAN configuration. Output after reset = used for LED. Input upon reset = Disable ARP broadcast to all VLANs. 1: Disable broadcast of ARP broadcast packets to all VLANs 0: Enable broadcast of ARP broadcast packets to all VLANs Output after reset = used for LED. Input upon reset = Select blinking speed of activity and collision LED. 1: On 43ms then Off 43ms 0: On 120ms then Off 120ms Note: This pin only affects LEDs that are configured in LED mode 1, 5, and 7. Output after reset = used for LED. Default 1 Dis_LeakyVLAN /P6_LED[3] 77 Ipu 1 Dis_ARPVLAN /P7_LED[0] 76 Ipu 1 LED_BLNK_TIME /P7_LED[1] 75 Ipu 1 Single-chip 9-port 10/100Mbps Switch Controller 15 Track ID: JATR-1076-21 Rev. 1.4 RTL8309SB Datasheet 5.7. Power Pins Table 8. Power Pins Pin Name VDDD Pin No. 52, 71, 79, 87, 95,107, 114 53, 72, 80, 88, 96, 108, 115 62 63 120 117 1, 8, 14, 20, 26, 32, 38, 44, 123 2, 5, 11, 17, 23, 29, 35, 41, 126 Type P Description 1.8V digital power. Default VSSD G Digital ground. VDDIO VSSIO VDDPLL VSSPLL VDDA P G P G P 2.5/3.3V digital VDD for MII interface. Digital ground for MII interface. 1.8V analog power for PLL. 1.8V analog ground for PLL. 1.8V analog power (Used for transmitters and equalizers). VSSA G Analog ground. Single-chip 9-port 10/100Mbps Switch Controller 16 Track ID: JATR-1076-21 Rev. 1.4 RTL8309SB Datasheet 6. EEPROM Register Description 6.1. Global Control Registers 6.1.1. Global Control Register0 Table 9. Global Control Register0 Name EEPROM existence Accept Error disable IEEE 802.3x transmit flow control enable IEEE 802.3x receive flow control enable Broadcast input or output drop Aging enable Fast aging enable Byte.bit 0.7 0.6 0.5 Description 1: EEPROM does not exist 0: EEPROM exists 1: Filter bad packets in normal operation 0: Switch all packets including bad ones 1: Invoke transmit flow control based on auto-negotiation result 0: Switch will not enable transmit flow control 1: When the switch receives a pause control frame, it has the ability to stop the next transmission of a normal frame until the timer has expired based on the auto negotiation result 0: Receive flow control not enabled 1: Broadcast input drop is selected 0: Broadcast output drop is selected 1: Enable aging function in the switch 0: Disable aging function in the switch 1: An entry learned in the lookup table will be aged out if it is not updated within an 800µs period 0: Disable fast aging function. The normal aging time of the RTL8309SB is around 200~300 seconds 1: Enable ISP MAC Address Translation 0: Disable ISP MAC Address Translation Default 0 1 1 0.4 1 0.3 0.2 0.1 1 1 0 Enable ISP MAC Address Translation 0.0 0 6.1.2. Global Control Register1 Table 10. Global Control Register1 Byte.bit 1.7~1.5 Description Default 111 -> Mode 7: Speed, Duplex+Collision, Link+Act, SQI 111 110 -> Mode 6: Activity, Speed, Link, SQI 101 -> Mode 5: Speed, Duplex, Link+Act, SQI 100 -> Mode 4: Collision, Duplex, Link+Act+Speed, SQI 011 -> Mode 3: SQI, Duplex+Collision, Link+Act+Speed,10/100 010 -> Mode 2: RxAct+10/100, TxAct+10/100, Link, SQI 001 -> Mode 1: Duplex+Collision, 10Link+Act, 100Link+Act, SQI 000 -> Mode 0: Duplex+Collision, Bi-color Speed, Bi-color Link+Act, SQI 1 1: Disable VLAN 1 0: Enable VLAN 1: Disable the 802.1Q tagged-VID Aware function 0 0: Use tagged-VID VLAN mapping for tagged frames but still use Port-Based VLAN mapping for priority-tagged and untagged frame Name LED Mode Reserved Disable VLAN Disable 802.1Q tag aware VLAN 1.4 1.3 1.2 Single-chip 9-port 10/100Mbps Switch Controller 17 Track ID: JATR-1076-21 Rev. 1.4 RTL8309SB Datasheet Name Disable VLAN member set ingress filtering Disable VLAN tag admit control Byte.bit 1.1 Description 1: The switch will not drop the received frame if the ingress port of this packet is not included in the matched VLAN member set 0: The switch will drop the received frame if the ingress port of this packet is not included in the matched VLAN member set 1: The switch accepts all frames received 0: The switch will only accept tagged frames and will drop untagged frames Default 1 1.0 1 6.1.3. Global Control Register2 Table 11. Global Control Register2 Byte.bit 2.7 Description 1: The default DiffServ code point listed below will be considered a high priority code point if DiffServ priority function is enabled EF – 101110 AF – 001010, 010010, 011010, 100010 Network Control – 111000, 110000 0: The default DiffServ code point will be considered low priority Default 1 Name Enable default high priority DiffServ code point Reserved 2.6~2.0 1111 111 6.1.4. Global Control Register3 Table 12. Global Control Register3 Byte.bit 3.7~3.5 Description Used to classify priority for incoming 802.1Q packets when 802.1p priority classification is enabled. “User priority” compares against this value. >=: Classify as high priority Mode 7: Speed, Duplex+Collision, Link+Act, SQI 110 -> Mode 6: Activity, Speed, Link, SQI 101 -> Mode 5: Speed, Duplex, Link+Act, SQI 100 -> Mode 4: Collision, Duplex, Link+Act+Speed, SQI 011 -> Mode 3: SQI, Duplex+Collision, Link+Act+Speed,10/100. 010 -> Mode 2: RxAct+10/100, TxAct+10/100, Link, SQI 001 -> Mode 1: Duplex+Collision, 10Link+Act, 100Link+Act, SQI 000 -> Mode 0: Duplex+Collision, Bi-color Speed, Bi-color Link+Act, SQI. 1: Soft reset. This bit is self-clearing If this bit is set to 1, the RTL8309SB will reset all registers in it except PHY registers and will not load configurations from EEPROM or strapping pins. Software reset is designed to provide a convenient way for users to change the configuration via SMI. After changing register values in the RTL8309SB (except PHY registers) via SMI, the external device must execute a soft reset in order to update the configuration by setting this bit to 1. 43 Default 111 Reg.bit Name 16.[15:13] LED Mode 16.12 Software Reset RW/ SC 0 Single-chip 9-port 10/100Mbps Switch Controller Track ID: JATR-1076-21 Rev. 1.4 RTL8309SB Datasheet Reg.bit 16.11 Name Disable VLAN Mode RW Description 1: Disable VLAN 0: Enable VLAN. The default VLAN membership configuration by internal register is MII port overlapped with all the other ports to form 8 individual VLANs. This default membership configuration may be modified by setting internal registers via the SMI interface or EEPROM. 1: Disable 802.1Q tagged-VID Aware function. The RTL8309SB will not check the tagged VID on received frames to perform tagged-VID VLAN mapping. Under this configuration, the RTL8309SB only uses the per port VLAN index register to perform Port-Based VLAN mapping 0: Enable the Member Set Filtering function of VLAN Ingress Rule. The RTL8309SB checks the tagged VID on received frames with the VIDA[11:0]~VIDH[11:0] to index to a member set, then performs VLAN mapping. The RTL8309SB uses tagged-VID VLAN mapping for tagged frames but still uses port-based VLAN mapping for priority-tagged and untagged frames 1: The switch will not drop a received frame if the ingress port of this packet is not included in the matched VLAN member set. It will still forward the packet to the VLAN members specified in the matched member set. This setting works on both port-based and tag-based VLAN configurations 0: The switch will drop the received frame if the ingress port of this packet is not included in the matched VLAN member set 1: The switch accepts all frames it receives whether tagged or untagged 0: The switch will only accept tagged frames and will drop untagged frames 1: EEPROM does not exist (pin EnEEPROM=0 or pin EnEEPROM=1 but EEPROM does not exist) 0: EEPROM exists (pin EnEEPROM=1 and EEPROM exists) 1: Filter bad packets in normal operation 0: Switch all packets including bad ones. This bit is intended for debugging purposes only 1: Determines when to invoke flow control based on auto negotiation results 0: Will not enable transmit flow control no matter what the auto negotiation result is 1: When the RTL8309SB receives a pause control frame, it has the ability to stop the next transmission of a normal frame until the timer is expired based on the auto negotiation result 0: Will not receive flow control no matter what the auto negotiation result is 1: Broadcast input drop is selected 0: Broadcast output drop is selected 1: Enable aging function 0: Disable aging function. The addresses learned in the lookup table will not be aged out. If the table is full, the last entry in the table will be deleted to make room for the new entry Default 1 16.10 Disable 802.1Q tag aware VLAN RW 0 16.9 Disable VLAN member set ingress filtering RW 1 16.8 Disable VLAN tag admit control RW 1 16.7 EEPROM existence Accept Error disable IEEE 802.3x transmit flow control enable IEEE 802.3x receive flow control enable RO 0 16.6 RW 1 16.5 RW 1 16.4 RW 1 16.3 16.2 Broadcast input or output drop Aging enable RW RW 1 1 Single-chip 9-port 10/100Mbps Switch Controller 44 Track ID: JATR-1076-21 Rev. 1.4 RTL8309SB Datasheet Reg.bit 16.1 Name Fast aging enable Mode RW Description 1: Enable fast aging function. The entry learned in the lookup table will be aged out if it is not updated within an 800µs period 0: Disable fast aging function 1: Enable ISP MAC Address Translation function 0: Disable ISP MAC Address Translation function Default 0 16.0 Enable ISP MAC Address Translation RW 0 7.1.7. PHY 0 Register 17: Global Control 1 Table 71. PHY 0 Register 17: Global Control 1 Mode RW Description Classifies priority for incoming 802.1Q packets, if 802.1p priority classification is enabled. ‘User priority’ is compared against this value. >=: Classify as high priority