S3076

® DEVICE SPECIFICATION MULTI-RATE SONET/SDH CLOCK RECOVERY UNIT MULTI-RATE SONET/SDH CLOCK RECOVERY UNIT BiCMOS PECL CLOCK GENERATOR GENERAL DESCRIPTION S3076 S3076 FEATURES • • SiGe BiCMOS technology Complies with Bellcore and ITU-T specifications for jitter tolerance, jitter transfer and jitter generation On-chip high frequency PLL with internal loop filter for clock recovery Supports clock recovery for: OC-48 (2488.32 Mbps) (with FEC) Fibre Channel (2125 Mbps) (with FEC) OC-24 (1244.16 Mbps) (with FEC) Gigabit Ethernet (1250 Mbps) (with FEC) Fibre Channel (1062.5 Mbps) (with FEC) OC-12 (622.08 Mbps) (with FEC) OC-3 (155.52 Mbps) (with FEC) NRZ data Selectable reference frequencies 19.44 MHz or 155.52 MHz (or equivalent Fibre Channel/ Gigabit Ethernet frequencies) Lock detect—monitors frequency of incoming data Low-jitter serial interface +3.3 V supply Compact 48 pin TQFP TEP package Typical power 620 mW Available in Die form also • • The function of the S3076 clock recovery unit is to derive high speed timing signals for SONET/SDHbased equipment. The S3076 is implemented using AMCC’s proven Phase Locked Loop (PLL) technology. Figure 1 shows a typical network application. The S3076 receives an OC-48, OC-24, OC-12, OC-3, Fibre Channel or Gigabit Ethernet scrambled NRZ signal with FEC capability up to 8 bytes per 255-byte block and recovers the clock from the data. The chip outputs a differential bit clock and retimed data. The S3076 utilizes an on-chip PLL which consists of a phase detector, a loop filter, and a Voltage Controlled Oscillator (VCO). The phase detector compares the phase relationship between the VCO output and the serial data input. A loop filter converts the phase detector output into a smooth DC voltage, and the DC voltage is input to the VCO whose frequency is varied by this voltage. A block diagram is shown in Figure 2. • • • • • • • Figure 1. System Block Diagram Network Interface Processor 16 OTX S3057 ORX S3076 S3057 16 16 16 S3076 ORX OTX October 23, 2000 / Revision A Network Interface Processor 1 S3076 S3076 OVERVIEW MULTI-RATE SONET/SDH CLOCK RECOVERY UNIT Suggested Interface Devices Sumitomo OC-48 Optical Receiver AMCC S3057 OC-48 Transceiver The S3076 supports clock recovery for the OC-48, Fibre Channel (2125 Mbps), OC-24, Gigabit Ethernet, Fibre Channel (1062.5 Mbps), OC-12 or OC-3 data rate with FEC capabilty up to 8 bytes per 255-byte block. Differential serial data is input to the chip at the specified rate, and clock recovery is performed on the incoming data stream. An external oscillator is required to minimize the PLL lock time, and provide a stable output clock source in the absence of serial input data. Retimed data and clock are output from the S3076. Figure 2. S3076 Functional Block Diagram CAP 1,2 2 LOOP FILTER VCO TESTOUT REFCLKP/N TESTCLK RATESEL[1:0] REFSEL TESTEN LCKREFN 2 CLOCK DIVIDER REFCMP LOCK DETECTOR LOCKDET SERCLKOP/N RST PHASE DETECTOR SERDATOP/N SDN SERDATIP/N BYPASS 2 October 23, 2000 / Revision A MULTI-RATE SONET/SDH CLOCK RECOVERY UNIT S3076 FUNCTIONAL DESCRIPTION The S3076 clock recovery device performs the clock recovery function for SONET OC-48, Fibre Channel (2125 Mbps), OC-24, Gigabit Ethernet, Fibre Channel (1062.5 Mbps), OC-12 or OC-3 serial data links with FEC capabilty up to 8 bytes per 255-byte block. The chip extracts the clock from the serial data inputs and provides retimed clock and data outputs. A 155.52/19.44 MHz (156.25/19.53 MHz for Gigabit Ethernet and 132.81/16.60 MHz for Fibre Channel) reference clock is required for phase locked loop start up and proper operation under loss of signal conditions. An integral prescaler and phase locked loop circuit is used to multiply this reference to the nominal bit rate. The input data rate is selected by the RATESEL inputs. (See Table 1.) Clock Recovery Clock recovery, as shown in the block diagram in Figure 2, generates a clock that is at the same frequency as the incoming data bit rate at the serial data input. The clock is phase aligned by a PLL so that it samples the data in the center of the data eye pattern. The phase relationship between the edge transitions of the data and those of the generated clock are compared by a phase/frequency discriminator. Output pulses from the discriminator indicate the required direction of phase corrections. These pulses are smoothed by an integral loop filter. The output of the loop filter controls the frequency of the Voltage Controlled Oscillator (VCO), which generates the recovered clock. S3076 Frequency stability without incoming data is guaranteed by an alternate reference input (REFCLK) that the PLL locks onto when data is lost. If the frequency of the incoming signal varies by a value greater than that stated in Table 7 with respect to REFCLKP/N, the PLL will be declared out of lock, and the PLL will lock to the reference clock. The assertion of SDN will also cause an out of lock condition. The loop filter transfer function is optimized to enable the PLL to track the jitter, yet tolerate the minimum transition density expected in a received SONET data signal. The total loop dynamics of the clock recovery PLL yield a jitter tolerance which exceeds the minimum tolerance proposed for SONET equipment by the Bellcore TA-NWT-000253 standard, shown in Figure 3. Lock Detect The S3076 contains a lock detect circuit which monitors the integrity of the serial data inputs. If the received serial data fails the frequency test, the PLL will be forced to lock to the local reference clock. This will maintain the correct frequency of the recovered clock output under loss of signal or loss of lock conditions. If the recovered clock frequency deviates from the local reference clock frequency by more than that stated in Table 7, the PLL will be declared out of lock. The lock detect circuit will poll the input data stream in an attempt to reacquire lock to data. If the recovered clock frequency is determined to be within that stated in Table 7, the PLL will be declared in lock and the lock detect output will go active. The assertion of SDN will also cause an out of lock condition. Table 1. Data Rate Select RATESEL0 0 0 1 1 1 1 1 RATESEL1 0 1 0 1 0 0 1 Operating Mode OC-3 OC-12 OC-24 OC-48 Gigabit Ethernet Fibre Channel (1062.5 Mbps) Fibre Channel (2125 Mbps) REFCLK Frequency 155.52/19.44 155.52/19.44 155.52/19.44 155.52/19.44 156.25/19.53 132.81/16.60 132.81/16.60 Table 2. Reference Frequency Select Reference Frequency for Data Rates with FEC Capability of X bytes per 255–Byte Block (For OC-3/12/24/48 Rates Only) REFSEL X=0 X=3 X=4 X=5 X=6 X=7 X=8 0 1 19.44 MHz 155.52 MHz 19.99 MHz 20.15 MHz 20.31 MHz 20.48 MHz 20.65 MHz 20.83 MHz 166.63 MHz 159.91MHz 161.21 MHz 162.53 MHz 163.87 MHz 165.26 MHz October 23, 2000 / Revision A 3 S3076 SONET JITTER CHARACTERISTICS Performance MULTI-RATE SONET/SDH CLOCK RECOVERY UNIT Figure 3. Input Jitter Tolerance Specification The S3076 PLL complies with the jitter specifications proposed for SONET/SDH equipment defined by the Bellcore Specifications: GR-253-CORE, Issue 2, December 1995 and ITU-T Recommendations: G.958 document, when used as specified. Input Jitter Tolerance Input jitter tolerance is defined as the peak to peak amplitude of sinusoidal jitter applied on the input signal that causes an equivalent 1 dB optical/electrical power penalty. SONET input jitter tolerance requirements are shown in Figure 3. Jitter Transfer The jitter transfer function is defined as the ratio of jitter on the output OC-N/STS-N signal to the jitter applied on the input OC-N/STS-N signal versus frequency. Jitter transfer requirements are shown in Figure 4. The measurement condition is that input sinusoidal jitter up to the mask level in Figure 4 be applied. Jitter Generation The jitter of the serial clock and serial data outputs shall not exceed the value specified in Table 7. when a serial data input with no jitter is presented to the serial data inputs. (See Table 7.) Sinusodal Input Jitter Amplitude (UI p-p) 15 1.5 0.15 f0 f1 f2 f3 ft Frequency OC/STS Level 48 243 12 3 10 10 30 30 300 300 25 6.5 250 65 f0 (Hz) 10 f1 (Hz) 600 f2 (Hz) 6000 f3 (kHz) 100 ft (kHz) 1000 Figure 4. Jitter Transfer Specification P slope = -20 dB/decade Jitter Transfer Acceptable Range fc Frequency OC/STS Level1,2 48 243 12 3 fc (kHz) 2000 P (dB) 0.1 500 130 0.1 0.1 1. Bellcore Specifications: GR-253- CORE, Issue 2, December 1995. 2. ITU-T Recommendations: G.958. 3. Not specified in GR-253 or G.958. 4 October 23, 2000 / Revision A MULTI-RATE SONET/SDH CLOCK RECOVERY UNIT FIBRE CHANNEL JITTER CHARACTERISTICS Performance The S3076 PLL complies with the jitter specifications proposed for Fibre Channel equipment defined by the fibre channel methodology for Jitter specification. Input Jitter Tolerance Input jitter tolerance is defined as the peak to peak amplitude of sinusoidal jitter applied on the input signal that causes an equivalent 1 dB optical/electrical power penalty. Fibre Channel input jitter tolerance requirements are shown in Table 3. Jitter Generation The jitter of the serial clock and serial data outputs shall not exceed the value specified in Table 4 when a serial data input with no jitter is presented to the serial data inputs. tRJ tTJ tFDJ S3076 Table 3. Input Jitter Tolerance Specification at node αR Parameters Description Frequency Dependent Jitter Tolerance (637 kHz to ≥ 5 MHz) Deterministic Jitter Tolerance (637 kHz – 531 MHz) Random Jitter (637 kHz – 531 MHz) Total Jitter Min 0.10 Max – Units UI p-p tDJ 0.38 0.22 0.70 – – – UI p-p UI p-p UI p-p Table 4. Total Jitter Generation Specification at node αT Parameters DJ TJ Description Deterministic Jitter Total Jitter Min Max 0.08 0.23 Units UI p-p UI p-p Figure 5. Fibre Channel System Node Definition Componet Receiver Node = αR αT = Component Transmitter Node SYSTEM HOST ADAPTOR SERDES SYSTEM STORAGE DISK DRIVE SERDES BACKPLANE PBC REPEAETERS CABLES CONNECTORS October 23, 2000 / Revision A 5 S3076 Table 5. Pin Assignment and Descriptions Pin Name SERDATIP SERDATIN BYPASS Level Diff. CML LVTTL I/O Pin# 3 2 46 MULTI-RATE SONET/SDH CLOCK RECOVERY UNIT Description Serial Data In. Clock is recovered from the transitions on these inputs. Internally biased and terminated. (See Figure 10.) Active High. Used to bypass the PLL. It allows transmission of data input without clock recovery. Signal Detect. Active Low. A single-ended 10K PECL input to be driven by the external optical receiver module to indicate a loss of received optical power. When SDN is inactive, the data on the Serial Data In (SERDATIP/N) pins will be internally forced to a constant zero, and the PLL will be forced to lock to the REFCLK inputs. When SDN is active, data on the SERDATIP/N pins will be processed normally. Reference Clock. 155.52/19.44 MHz (or equivalent Fibre Channel or Gigabit Ethernet frequency) input used to establish the initial operating frequency of the clock recovery PLL and also used as a standby clock in the absence of data, during reset or when SDN is inactive. Internally biased. Loop Filter Capacitor. The external loop filter capacitor and resistors are connected to these pins. (See Figure 14.) Lock to Reference. Active Low. When active, the serial clock output will be forced to lock to the local reference clock input [REFCLK]. Rate Select. Selects the operating mode (See Table 1.) Test Clock. Test input signal used for production test. Connect to Ground for normal operation. This input is internally pulled High. Selects the reference frequency (See Table 2.) Reset Input. Active High. Resets lock detect circuit and VCO divideby-N circuit for production test. Test Enable. Active High. Bypasses the VCO for production test. Connect to Ground for normal operation. This input is internally pulled High. Serial Data Out. This signal is the delayed version of the incoming data stream (SERDATIP/N) updated on the falling edge of Serial Clock Out (SERCLKOP/N). Serial Clock Out. This signal is phase aligned with Serial Data Out (SERDATO). (See Figure 8.) Lock Detect. Clock recovery indicator. Set high when the internal clock recovery has locked onto the incoming data stream. LOCKDET is an asynchronous output. I I SDN Single Ended LVPECL I 45 REFCLKP REFCLKN Internally Biased Diff. LVPECL I 6 7 CAP1 CAP2 LCKREFN RATESEL0 RATESEL1 TESTCLK REFSEL RST LVTTL I 40 39 17 20 19 15 18 16 I LVTTL LVTTL LVTTL LVTTL I I I I TESTEN LVTTL I 47 SERDATOP SERDATON SERCLKOP SERCLKON LOCKDET Diff. CML Diff. CML LVTTL O 28 27 34 33 10 O O 6 October 23, 2000 / Revision A MULTI-RATE SONET/SDH CLOCK RECOVERY UNIT Table 5. Pin Assignment and Descriptions (Continued) Pin Name Level I/O Pin# Description S3076 TESTOUT O 23 37 42 Test Output. Leave open for normal operation. AVCC +3.3 V I Analog power supply. AGND GND I 38, 41, 43 Analog GND connection. 1, 5, 9, 21, 24, Power Supply. 26, 29, 32, 35, 48 4, 8, 11, 12, 13, 14, 22, Ground connection. 25, 30, 31, 36, 44 VCC +3.3 V I GND GND I Pad Assignment Pad # 1 2 3 4 5 6 7 8 9 10 11 12 13 Pad Center (756.900, 72.425) (861.900, 72.425) (966.900, 72.425) (1806.900, 72.425) (1911.900, 72.425) (2016.900, 72.425) (2121.900, 72.425) (2226.900, 72.425) (2331.900, 72.425) (2436.900, 72.425) (2541.900, 72.425) (3171.900, 72.425) (3751.375, 756.900) Pin Name VCC TESTOUT GND VCC RATESEL0 RATESEL1 REFSEL LCKREFN RST TESTCLK GND GND GND Pad # 14 15 16 17 18 19 20 21 22 23 24 25 26 Pad Center (3751.375, 868.900) (3751.375, 973.900) (3751.375, 1078.900) (3751.375, 1603.900) (3751.375, 1708.900) (3751.375, 1813.900) (3751.375, 1918.900) (3751.375, 2758.900) (3751.375, 2863.900) (3751.375, 2968.900) (3751.375, 3073.900) (3171.900, 3871.375) (3066.900, 3871.375) Pin Name GND LOCKDET VCC GND REFCLKN REFCLKP VCC GND SERDATIP SERDATIN VCC VCC TESTEN October 23, 2000 / Revision A 7 S3076 MULTI-RATE SONET/SDH CLOCK RECOVERY UNIT Table 5. Pin Assignment and Descriptions (Continued) Pad Assignment (Continued) Pad # 27 28 29 30 31 32 33 34 35 36 37 38 39 Pad Center (2961.900, 3871.375) (2856.900, 3871.375) (2751.900, 3871.375) (2436.925, 3871.375) (2226.900, 3871.375) (2121.900, 3871.375) (2016.900, 3871.375) (1911.900, 3871.375) (1386.900, 3871.375) (1281.900, 3871.375) (966.900, 3871.375) (861.900, 3871.375) (756.900, 3871.375) Pin Name BYPASS SDN GND AGND AVCC AVCC AGND AGND CAP1 CAP2 AGND AGND AVCC Pad # 40 41 42 43 44 45 46 47 48 49 50 51 52 Pad Center (651.900, 3871.375) (72.425, 3287.900) (72.425, 3182.900) (72.425, 3077.900) (72.425, 2972.900) (72.425, 2867.900) (72.425, 2762.900) (72.425, 1610.400) (72.425, 1505.400) (72.425, 1400.400) (72.425, 1295.400) (72.425, 1190.400) (72.425, 1085.400) Pin Name AVCC GND VCC SERCLKOP SERCLKON VCC GND GND VCC SERDATOP SERDATON VCC GND 8 October 23, 2000 / Revision A MULTI-RATE SONET/SDH CLOCK RECOVERY UNIT Figure 6. S3076 48 Pin TQFP/TEP Pinout TESTEN BYPASS AGND AGND AVCC CAP1 CAP2 AGND AVCC S3076 48 47 VCC SDN GND 46 45 44 43 VCC SERDATIN SERDATIP GND VCC REFCLKP REFCLKN GND VCC LOCKDET GND GND 1 2 3 4 5 6 7 42 41 38 37 40 39 S3076 48 Pin TQFP/TEP Top View 36 35 34 33 32 31 30 29 28 27 26 25 GND VCC SERCLKOP SERCLKON VCC GND GND VCC SERDATOP SERDATON VCC GND 8 9 10 11 12 19 13 14 15 16 17 18 20 21 22 RATESEL0 VCC LCKREFN REFSEL October 23, 2000 / Revision A RATESEL1 GND TESTOUT VCC GND GND TESTCLK RST 23 24 9 S3076 Figure 7. 48 Pin TQFP/TEP Package MULTI-RATE SONET/SDH CLOCK RECOVERY UNIT TOP VIEW Die Width – 156.7 mils Die Length – 161.5 mils Table 6. Thermal Management Device S3076 Package Max Power 850 mW Θja 50˚ C/W 10 October 23, 2000 / Revision A MULTI-RATE SONET/SDH CLOCK RECOVERY UNIT Table 7. Performance Specifications Parameter VCO Operating Frequency Data Output Jitter with VCO locked to SERDATIP/N OC-48 OC-24 OC-12 OC-3 Reference Clock Frequency Tolerance Acquisition Lock Time (OC-48) 19.44 MHz REFCLK 155.52 MHz REFCLK -100 0.002 0.002 0.005 0.005 +100 UI (rms) UI (rms) ppm Min 2.125 Ty p 2.488 Max 2.67 Units GHz Condition S3076 0.0038 0.005 UI (rms) rms jitter Not specified in GR-253 rms jitter rms jitter 1800 250 µsec Minimum transition density of 20%. Guaranteed but not tested. With device already powered up and valid ref. clk. Reference Clock Input Duty Cycle Reference Clock Rise & Fall Times CML Output Rise & Fall Times Frequency difference at which the PLL goes out of lock (REFCLK compared to the divided down VCO clock) Frequency difference at which the receive PLL goes into lock (REFCLK compared to the divided down VCO clock) tSU OC-48/Fibre Channel (2125 Mbps) OC-24/Fibre Channel (1062.5 Mbps) OC-12 OC-3 tH OC-48/Fibre Channel (2125 Mbps) OC-24/Fibre Channel (1062.5 Mbps) OC-12 OC-3 40 60 1.5 60 120 770 % of UI ns ps ppm 20% to 80% of amplitude. 20% to 80%, 50 Ω load, 1 pF cap. 450 600 220 300 390 ppm 100 250 500 2500 ps See Figure 8. 100 250 500 2500 ps See Figure 8. October 23, 2000 / Revision A 11 S3076 MULTI-RATE SONET/SDH CLOCK RECOVERY UNIT Figure 8. Receiver Output Timing Diagram SERCLKOP tSU 50% tH SERDATOP/N Note: Output propagation delay time of high speed CML outputs is the time in pico seconds from the cross-over point of the reference signal to the cross-over point of the output. Table 8. Jitter Tolerance Specifications Parameter Jitter Tolerance STS-48 Jitter Tolerance STS-24 Jitter Tolerance STS-12 Jitter Tolerance STS-3 0.4 0.6 UI 250 kHz < f < 5 MHz Data Pattern = 27-1 PRBS 65 kHz < f < 1 MHz Data Pattern = 27-1 PRBS Min 0.4 Typ 0.5 Max Units Conditions UI 1 MHz < f < 5 MHz Data Pattern = 27-1 PRBS 0.4 0.8 UI Table 9. Gigabit Ethernet Jitter Specifications Parameter tJ Total Input Jitter Tolerance tDJ Deterministic Input Jitter Tolerance Min 599 370 Typ Max Units Conditions ps ps As specified in IEEE 802.3z. As specified in IEEE 802.3z. 12 October 23, 2000 / Revision A MULTI-RATE SONET/SDH CLOCK RECOVERY UNIT Table 10. Recommended Operating Conditions Parameter Ambient Temperature Under Bias (Industrial) Voltage on VCC with respect to GND Voltage on any LVTTL Input Pin Voltage on any LVPECL Input Pin ICC Supply Current1 1. Outputs open. S3076 Min -40 3.135 0 0 Typ Max +85 Units ˚C V V V mA 3.3 3.465 VCC VCC 187 245 Table 11. Absolute Maximum Ratings Parameter Storage Temperature Voltage on VCC with respect to GND Voltage on any LVTTL Input Pin Voltage on any LVPECL Input Pin LVTTL Output Sink Current LVTTL Output Source Current Min -65 -0.5 -0.5 0 Typ Max +150 3.465 VCC VCC 8 8 Units ˚C V V V mA mA Electrostatic Discharge (ESD) Ratings The S3076 is rated to the following voltages based on the human body model: 1. All pins are rated 1500 Volts except pin # 24(VCC), 37(AVCC), 38(AGND), 41(AGND), 42(AVCC), and 43(AGND). Pins 24, 37, 38, 41, 42, and 43 are rated at 100 volts. Adherence to standards for ESD protection should be taken during the handling of the devices to ensure that the devices are not damaged. The standards to be used are defined in ANSI standard ANSI/ESD S20.20-1999, "Protection of Electrical and Electronic Parts, Assemblies and Equipment." Contact your local FAE or sales representative for applicable ESD application notes. October 23, 2000 / Revision A 13 S3076 Table 12. CML Input DC Characteristics Parameter ∆VINDIFF ∆VINSINGLE RDIFF Description MULTI-RATE SONET/SDH CLOCK RECOVERY UNIT Min 300 150 80 Typ Max 1900 950 Units mV mV Ω Conditions See Figure 9. See Figure 9. Differential Input Voltage Swing Single-ended Input Voltage Swing Differential Input Resistance 100 120 Table 13. CML Output DC Characteristics Parameter VOL (Data) VOH (Data) ∆VOUTDIFF (Data) ∆VOUTSINGLE (Data) VOL (Clock) VOH (Clock) ∆VOUTDIFF (Clock) ∆VOUTSINGLE (Clock) Description CML Output Low Voltage CML Output High Voltage CML Serial Output Differential Voltage Swing CML Serial Output Single-ended Voltage Swing CML Output Low Voltage CML Output High Voltage CML Serial Output Differential Voltage Swing CML Serial Output Single-ended Voltage Swing Min VCC -1.0 VCC -0.35 800 400 VCC -1.5 VCC -0.5 800 400 Typ Max VCC -0.65 VCC -0.2 1600 80 0 VCC -0.85 VCC -0.25 1800 900 Units V V mV mV V V mV mV Conditions 100 Ω line-to-line. 100 Ω line-to-line. 100 Ω line-to-line. See Figure 9. 100 Ω line-to-line at 2.5 Gbps. See Figure 9. 100 Ω line-to-line. 100 Ω line-to-line. 100 Ω line-to-line. See Figure 9. 100 Ω line-to-line at 2.5 GHz. See Figure 9. Table 14. LVTTL Input/Output DC Characteristics Parameter VIH VIL IIH IIL VOH Description Input High Voltage Input Low Voltage Input High Current Input Low Current Output High Voltage -500 2. 4 Min 2.0 0.0 Typ Max 3.465 0.8 50 Unit V V µA µA V Conditions TTL VCC = Max TTL VCC = Max VIN = 2.4 V VIN = 0.5 V VIH = Min VIL = Max IOH = -100 µA VIH = Min VIL = Max IOL = 1.0 mA VOL Output Low Voltage 0.5 V Note: All parameters are specified with respect to the source termination and ground with VTTL = Max. = 3.465 V. 14 October 23, 2000 / Revision A MULTI-RATE SONET/SDH CLOCK RECOVERY UNIT Table 15. Single Ended LVPECL Input DC Characteristics Parameter VIL VIH IIL IIH Description Input Low Voltage Input High Voltage Input Low Current Input High Current Min VCC -2.00 VCC -1.2 -100 +50 Typ Max VCC -1.4 VCC -0.5 0 350 Units V V µA µA S3076 Conditions Table 16. Internally Biased Differential LVPECL Input AC Characteristics Parameter VIL VIH IIL IIH ∆VINDIFF ∆VINSINGLE Description Input Low Voltage Input High Voltage Input Low Current Input High Current Differential Input Voltage Swing Single-ended Input Voltage Swing Min VCC -2.00 VCC -1.2 -300 -50 300 150 Typ Max VCC -1.4 VCC -0.5 0 100 1200 600 Units V V µA µA mV mV VIL = VCC -2 VIH = VCC -0.5 See Figure 9. See Figure 9. Conditions Figure 9. Differential Voltage Measurement V(+) VSWING V(–) V(+) – V(-) VD = 2 X VSWING 0.0 V Note: V(+) – V(-) is the algebraic difference of the input signals. October 23, 2000 / Revision A 15 S3076 MULTI-RATE SONET/SDH CLOCK RECOVERY UNIT Figure 10. +5 V Differential PECL Driver to S3076 Differential CML Input AC Coupled Termination +5 V 0.01 µF 330 Ω 330 Ω 0.01 µF Zo=50 Ω Vcc -0.5 V S3076 SERDATIP/N Zo=50 Ω Vcc -0.5 V +3.3 V 100 Ω Figure 11. S3076 Differential CML Output to S3057/S3067 Terminations +3.3 V Zo=50 Ω Vcc -0.5 +3.3 V 100 Ω Zo=50 Ω S3076 SERDATOP/N SERCLKOP/N Vcc -0.5 S3057/S3067 SERDATIP/N SERCLKIP/N Figure 12. +5 V Differential PECL Driver to S3076 Reference Clock Input AC Coupled Termination +5 V 0.01 µF 330 Ω 330 Ω 0.01 µF Zo=50 Ω Zo=50 Ω 100 Ω Vcc -0.5 V +3.3 V Vcc -0.5 V S3076 REFCLKP/N 155 MHz OSCILLATOR 16 October 23, 2000 / Revision A MULTI-RATE SONET/SDH CLOCK RECOVERY UNIT Figure 13. +3 V Differential LVPECL Driver to S3076 Reference Clock Input DC Coupled Termination S3076 +3 V Zo=50 Ω 150 Ω 150 Ω Zo=50 Ω 100 Ω Vcc -0.5 V +3.3 V Vcc -0.5 V S3076 REFCLKP/N 155 MHz OSCILLATOR/ 155MCK from S3057 Figure 14. Loop Filter Capacitor Connections 56 Ω CAP1 10 µF CAP2 56 Ω S3076 October 23, 2000 / Revision A 17 S3076 Ordering Information PREFIX MULTI-RATE SONET/SDH CLOCK RECOVERY UNIT DEVICE PACKAGE S – Integrated Circuit 3076 TT – 48 Pin TQFP/TEP DI – Die X Prefix XXXX Device XX Package IS O 900 RT IFI Applied Micro Circuits Corporation • 6290 Sequence Dr., San Diego, CA 92121 Phone: (858) 450-9333 • (800)755-2622 • Fax: (858) 450-9885 http://www.amcc.com AMCC reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current. AMCC does not assume any liability arising out of the application or use of any product or circuit described herein, neither does it convey any license under its patent rights nor the rights of others. AMCC reserves the right to ship devices of higher grade in place of those of lower grade. AMCC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. AMCC is a registered trademark of Applied Micro Circuits Corporation. Copyright ® 2000 Applied Micro Circuits Corporation D53/R82 E D 1 CE 18 October 23, 2000 / Revision A