SCG9832

SCG9832 8-BIT MICROCONTROLLER SCG9832 Microcontroller Specification FEATURE SUMMARY Technology − CMOS technology. I/O ports − − 2 8-bit programmable I/O ports. 1 7-bit output port. CPU − − 8-bit CPU core. 126 powerful and easy-to-use instruction set Timer − − − 2 8-bit pre-scalar auto reload timers which can be cascaded to form one 16-bit timer. 1 real time timer. 1 watch dog timer. Memory − − − Internal ROM: 32K x 8 Internal RAM: 128 x 8 Memory is organized as 16K-byte page. Operating Voltage − 2.4V to 5.5V. I/O structure − Memory mapped I/O structure. Oscillation Frequency − − RC Oscillator for the main system clock up to 4MHz, instruction cycle ~0.5us. Subsystem clock frequency of 32.768kHz for real time timer. Power Down − Stop mode (Stop oscillation) Interrupts − − − − 2 timer interrupts. 1 real time interrupt. 1 external event interrupt. 1 software interrupt. Score Concept Semiconductor Ltd. 1 Sept 2000 SCG9832 8-BIT MICROCONTROLLER Function Overview Program Memory Map RAM Area: Address $00-$0F $10-$7F $80-$FF Description H/W registers and I/Os Reserved Data memory and Stack Figure 1. Memory map in RAM area ROM Area: Physical Address $0000-$3BFF $3C00-$3FFF $4000-$FFBF $8000-$FFBF $FFC0-$FFFF Page 0 Program Reset address at $0000 IC Test Program Page 1 Reserved Page 3 Software interrupt at $FFC0 External interrupt at $FFD0 Timer 1 interrupt at $FFE0 Timer 0/RTC interrupt at $FFF0 Figure 2. Memory map in ROM area Description Score Concept Semiconductor Ltd. 2 Sept 2000 SCG9832 8-BIT MICROCONTROLLER CPU core An 8-bit accumulator based CPU core can directly address up to 64 x 16K byte addressing space. Most of the instructions are executed in two cycles. Instruction is generally one byte and will have an extra byte for some addressing modes. CPU Registers: Program Counter (PC) The 14-bit Program Counter stores address for instruction fetch during program execution. It makes up a page size of 16K bytes. Together with the Program Page Register (iPAGE), it becomes a 20-bit address that can access up to 1,048,576 bytes. When the CPU resets, the content of the iPAGE:PC will be 00:0000. If interrupt occurs, the type of interrupt will then determine its content. PC will automatically be incremented to the next instruction after an instruction fetch. Table 1. Different types of interrupt Interrupt Timer 0 / RTC Interrupt Timer 1 Interrupt External Interrupt Software Interrupt Page Register (PAGE) An 8-bit Page Register to change the program flow. The most significant two bits are always set to zero. Data Bank Register (BANK) An 8-bit Bank Register to access data memory. The most significant two bits are always set to zero. Program Page Register (iPAGE) An 8-bit Program Page Register is combined with PC for instruction fetch. The most significant two bits are always set to zero. Accumulator (A) An 8-bit Accumulator for arithmetic, logical and data movement operation. Temporary Register (B) An 8-bit temporarily storage for accumulator. Index Registers (X, Y) These two 8-bit registers can be used for general registers and index registers of the indirect addressing mode. They can also be used as pointer for table read and memory write instructions. IPAGE:PC 3H:3FF0H 3H:3FE0H 3H:3FD0H 3H:3FC0H Score Concept Semiconductor Ltd. 3 Sept 2000 SCG9832 8-BIT MICROCONTROLLER Stack Register (SP) A 7-bit Stack Register (SP) stores the address for stack operation. After CPU resets, the value is $00. The SP has to be initialized at $FF by software. This means the stack frame starts from the highest address memory location. Program Status (PS) This is an 8-bit Program Status Register. However only 4-bit is used for controlling ALU operations and instruction execution sequences. Program Status Bit 7 6 5 4 3 2 1 0 Sign Zero Carry Interrupt Mask Reserved Figure 3. 8-bit Program Status Carry Flag (C) Whenever there is a carry or borrow occurs after an arithmetic operation, carry flag is set to 1. Otherwise, it is cleared to 0. Besides, the “Rotate” instructions can also change the carry flag which value is a bit shifted out of the specified source operand. Executing single instruction of “SETC” or “CLRC” can also alter this flag. Upon returning from an interrupt service routine, this flag will be restored. Zero Flag (Z) For arithmetic and logical operations, Zero flag will be set to 1 if the result is zero. Besides, for operation that involves moving source operand to accumulator, zero flag will also be set to 1 if the content of the source operand is zero. Upon returning from an interrupt service routine, this flag will be restored. Sign Flag (N) Sign flag stores the most significant bit of a result after the following operations: a. Arithmetic b. Logic c. Move from source operand to accumulator This flag will also be restored upon returning from an interrupt service routine. Score Concept Semiconductor Ltd. 4 Sept 2000 SCG9832 8-BIT MICROCONTROLLER Interrupt Mask Flag (I) The flag will be set to 1 when entering an interrupt service routine. By that time, all other interrupt events will be pending. After exiting from the interrupt service routine, this interrupt mask flag will be cleared to 0. Then interrupt handling will be resumed. Memory There are 32K bytes internal ROM with each page size is 16K bytes. Besides, an extra 64 bytes area are for interrupt vector addressing space. Regarding the instruction pointer, it is organized as iPAGE:PC for instruction fetch. Change of program flow between pages is by modifying the PAGE register and then followed by executing a JMP or CALL instruction. These two instructions will load the PAGE register to iPAGE and change the content in PC for long JMP or CALL instruction. It does not need to change the PAGE register if it is a short JMP/CALL (JMP/CALL within page) because the PAGE register is normally the same as the iPAGE register. To exit a subroutine, long or short return type must be specified for long or short CALL respectively. The microcontroller has 128 bytes internal RAM data storage of address $80-$FF. This area includes stack frame and data memory. The stack frame is usually initialized at the highest RAM address location, i.e. $FF. Oscillation Circuits Main system and subsystem oscillation circuitry generates the internal clock signal for the CPU and other hardware timings. The main system clock uses the RC oscillation source. The operating frequency is up to 4 MHz. This clock is for CPU and the two timers. The subsystem clock is for the real time signals. It uses 32.768 kHz crystal. It has to be tied to a voltage level, either HIGH or LOW, if the real time timer and the watch dog timer are not used. Power Down The microcontroller supports power down mode for saving power. Executing a STOP instruction will stop the main system oscillation to save most of microcontroller power. Only an external interrupt will release the microcontroller from STOP mode. Interrupts The MICROCONTROLLER has 2 timer interrupts, one real time interrupt, one external event interrupt and one software interrupt. When interrupt occurs, the content of PC, iPAGE and PS are pushed onto the stack in sequence. And then, the corresponding interrupt vector is loaded into iPAGE:PC. Upon executing a RTI instruction, the registers are popped out of the stack in the reversed order. The preference of interrupt priority is Timer 0 / RTC interrupt, Timer 1 interrupt and then external interrupt. Score Concept Semiconductor Ltd. 5 Sept 2000 SCG9832 8-BIT MICROCONTROLLER I/O ports The microcontroller has one 7-bit output port and two software controllable 8-bit I/O ports. For I/O port 0, there is a pull-low resistor when it is configured as in input mode, and this resistor is disabled when it is in output mode. For I/O port 1, it is floating when in input mode. For Port 2, it is a 7-bit output port only. Timers The microcontroller has two programmable 8-bit timers (T0 and T1) for system timing. It has also a real time timer and a watch dog timer when subsystem clock is employed. All the timers can be enabled or disabled by configuring an internal register, TCONG. At CPU resets, all of them are disabled. T0 and T1 are up-counters and can be configured as either two 8-bit pre-scalar auto reload timer or as a 16-bit pre-scalar auto reload timer. The timer overflow flag will be set if the timer overflows. Then an interrupt will be generated if the corresponding interrupt enable bit is set to 1. The real time timer provides 0.5 sec interrupt for RTC functions. Watch dog timer will overflow in ~1 sec and then will reset the CPU. Score Concept Semiconductor Ltd. 6 Sept 2000 SCG9832 8-BIT MICROCONTROLLER BLOCK DIAGRAM P0 INTERRUPT CONTROL RTC P1 WATCH DOG P1 OUTPUT LATCH P0 OUTPUT LATCH CONTROL XTAL ALU P2 A B X Y SP PS P2 OUTPUT LATCH TIMER0 PC iPAGE TIMER1 PAGE OSC BANK CPU CORE ADDRESS BUS & CONTROL DATA BUS INTERNAL ROM 32Kx 8 INTERNAL RAM 128x8 Figure 4. Block diagram of SCG9832 Score Concept Semiconductor Ltd. 7 Sept 2000 SCG9832 8-BIT MICROCONTROLLER PIN DESCRIPTIONS Table 2. Pin Description Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 Name P_CLK CLK320 CLK32I GND P0RW0 P0RW1 P0RW2 P0RW3 VDD P0RW4 P0RW5 P0RW6 P0RW7 GND P1RW0 P1RW1 P1RW2 P1RW3 VDD P1RW4 P1RW5 P1RW6 P1RW7 GND P2W0 P2W1 P2W2 P2W3 VDD P2W4 P2W5 P2W6 PWMP PWMM GND VDD TEST RESET EXT_INT Type I/P O/P I/P Power I/O I/O I/O I/O Power I/O I/O I/O I/O Power I/O I/O I/O I/O Power I/O I/O I/O I/O Power O/P O/P O/P O/P Power O/P O/P O/P O/P O/P Power Power I/P I/P I/P Description RC Oscillator for the Main System clock 32.768KHz RTC 32.768KHz RTC Ground (optional) Port 0 Port 0 Port 0 Port 0 Supply voltage Port 0 Port 0 Port 0 Port 0 Ground (optional) Port 0 Port 1 Port 1 Port 1 Supply Voltage (optional) Port 1 Port 1 Port 1 Port 1 Ground (optional) Port 2 Port 2 Port 2 Port 2 Supply Voltage (optional) Port 2 Port 2 Port 2 Speaker + Speaker Ground Supply Voltage Test pin, no connection Reset pin External Interrupt pin Pad Type Pad type 5 Pad type 6 Pad type 6 Pad type 1 Pad type 1 Pad type 1 Pad type 1 Pad type 1 Pad type 1 Pad type 1 Pad type 1 Pad type 1 Pad type 1 Pad type 1 Pad type 1 Pad type 1 Pad type 1 Pad type 1 Pad type 1 Pad type 2 Pad type 2 Pad type 2 Pad type 2 Pad type 2 Pad type 2 Pad type 2 Pad type 2 Pad type 2 Pad type 4 Pad type 3 Pad type 4 Note: The Optional pins for VDD and GND can be left open as NC pins. Score Concept Semiconductor Ltd. 8 Sept 2000 SCG9832 8-BIT MICROCONTROLLER data in bond pad Schmitt input data out output enable tristate control Figure 5. Pad type 1 (bi-directional pad) data out bond pad tristate control output enable Figure 6. Pad type 2 (output pad) Reset Schmitt input Figure 7. Pad type 3 ( Reset ) Score Concept Semiconductor Ltd. 9 Sept 2000 SCG9832 8-BIT MICROCONTROLLER INT Schmitt input Figure 8. Pad type 4 (external interrupt) Test Test=1 Test=0 RC circuitry Clock out RC pad enable Figure 9. Pad type 5 (RC oscillation pad) 20pF CLK32I 10M Ω 32.768k Hz CLK32O 20pF Figure 10. Pad type 6 (Clock circuit) Score Concept Semiconductor Ltd. 10 Sept 2000 SCG9832 8-BIT MICROCONTROLLER Control Registers Summary Table 3. Summary of Control Registers Hex 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH Mnemonic P0DIR P0RW P1DIR P1RW P2W TCONG INTR TFLAG T0VAL T1VAL SPHEN Control Registers Name Port 0 Direction Control Register (Reserved) Port 0 Read/Write Port Port 1 Direction Control Register Port 1 Read/Write Port Port 2 Output Port (Reserved) (Reserved) (Reserved) Timer Configuration Port Interrupt Control Register Timer Flag Status Register/Watch-dog Reset Timer 0 Preset Value Register Timer 1 Preset Value Register D/A Output Control Register (Reserved) R/W W R/W W R/W W W W R/W W W W - Descriptions P0DIR and P1DIR Bit R/W 7 W 6 W 5 W 4 W 3 W 2 W 1 W 0 W 0 : Input mode 1 : Output mode Figure 11. Port 0 and Port 1 Direction Control Registers P0RW and P1RW Bit R/W 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 R/W Write to output latch. Read from input pin. Read value of Output pin will be the output latch value. Figure 12. Port 0 and Port 1 Read/Write Port Score Concept Semiconductor Ltd. 11 Sept 2000 SCG9832 8-BIT MICROCONTROLLER P2W Bit R/W 7 6 W 5 W 4 W 3 W 2 W 1 W 0 W Reserved Write to output latch Figure 13. Port 2 Output Port TCONG Bit R/W 7 6 5 4 W 3 W 2 W 1 W 0 W Reserved Watch dog timer 0 : disable 1 : enable 000 : disable T0 and T1 0x1 : enable T0 01x : enable T1 1xx : cascade T0:T1 as 16-bit timer Real time timer 0 : disable 1 : enable Figure 14. Timer Configuration Port Score Concept Semiconductor Ltd. 12 Sept 2000 SCG9832 8-BIT MICROCONTROLLER INTR Bit R/W 7 6 5 4 3 2 W 1 W 0 W Reserved External interrupt 0 : disable 1 : enable T1 interrupt 0 : disable 1 : enable T0/RTC (half second) interrupt 0 : disable 1 : enable Figure 15. Interrupt Control Register TFLAG Bit R/W 7 6 5 4 3 R 2 R 1 R 0 R Reserved CLK32I Input 0 : T0 not overflow 1 : T0 overflow 0 : T1 not overflow 1 : T1 overflow Note : Read will reset all flags. Any write operation to TFLAG will reset the watch dog timer. 0 : not half second 1 : half second Figure 16. Timer Flag Status Register/Watch-dog Reset Score Concept Semiconductor Ltd. 13 Sept 2000 SCG9832 8-BIT MICROCONTROLLER T0VAL and T1VAL Bit R/W 7 W 6 W 5 W 4 W 3 W 2 W 1 W 0 W Write timer 0 and timer 1 preset value Time frequency = system clock 1 × 2 counter value For either T0 or T1, Maximum counter value = 255 Minimum frequency ≈ 7840Hz For T0:T1, Maximum counter value = 65535 Minimun frequency ≈ 30Hz Figure 17. Timer 0 and Timer 1 Preset Value Register SPHEN Bit R/W 7 6 5 4 3 2 1 W 0 W Reserved 0 : single channel 1 : dual channels 0 : disable D/A output 1 : enable D/A output Figure 18. D/A Output Control Register Score Concept Semiconductor Ltd. 14 Sept 2000 SCG9832 8-BIT MICROCONTROLLER INSTRUCTION SUMMARY There are 126 instructions. All instructions are one or two byte instructions. The followings are the notations used: A B C Z N X Y SP STACK BANK PAGE iPAGE PC PS I (X) (Y) label (label) ADDR14 ADDR 8 #CONSTANT Accumulator B Register Carry bit Zero bit Negative bit X Index Register Y Index Register Stack Pointer Register Stack Data Bank Register Page Register The page register for PC19-PC14 Program Counter PC13-0 Program Status Interrupt flag RAM pointed by X RAM pointed by Y A 8-bit RAM/Register label RAM pointed by the label A 14-bit address A 8-bit address A 8-bit constant Score Concept Semiconductor Ltd. 15 Sept 2000 SCG9832 8-BIT MICROCONTROLLER INSTRUCTION SET 1. ADC Code Operation Flags A 0100 0000 A + A + C→A N, Z, C 9. AND X Code Operation Flags 0100 1010 X Λ A→A N,Z 2. ADC X Code Operation Flags 0100 0010 X + A + C→A N, Z, C 10. AND Y Code Operation Flags 0100 1011 Y Λ A→A N,Z 3. ADC Y Code Operation Flags 0100 0011 Y + A + C→A N, Z, C 11. AND (X) Code Operation Flags 0100 1110 (X) Λ A→A N,Z 4. ADC (X) Code Operation Flags 0100 0110 (X) + A + C→A N, Z, C 12. AND (Y) Code Operation Flags 0100 1111 (Y) Λ A→A N,Z 5. ADC (Y) Code Operation Flags 0100 0111 (Y) + A + C→A N, Z, C 13. AND label Code Operation Flags 0100 1100 zzzz zzzz (zzzz zzzz)ΛA→A N,Z 6. ADC label Code Operation Flags 0100 0100 zzzz zzzz (zzzz zzzz)+A+C→A N, Z, C 14. AND #CONSTANT Code Operation Flags 0100 1001 zzzz zzzz Zzzz zzzz Λ A →A N,Z 7. ADC #CONSTANT Code Operation Flags 0100 0001 zzzz zzzz Zzzz zzzz +A+C→A N, Z, C 15. BRA ADDR8 Code Operation Flags 0011 0010 zzzz zzzz Zzzz zzzz → PC0-7 ----- 8. AND A Code Operation Flags 0100 1000 A Λ A→A N,Z Score Concept Semiconductor Ltd. 16 Sept 2000 SCG9832 24. 16. CALL ADDR14 Code Operation 8-BIT MICROCONTROLLER CMP #CONSTANT Code 11zz zzzz zzzz zzzz PC →(SP);SP-2→SP ADDR14 →PC[13:0] If PAGE ≠ iPAGE IPAGE→(SP);SP-1→SP PAGE →iPAGE 25. CMP label Code Operation Flags 0000 0101 zzzz zzzz A ∀ (zzzz zzzz) Z Operation Flags 0000 0001 zzzz zzzz A ∀ zzzz zzzz Z Flags ----- 17. CLR A Code Operation Flags 0010 1000 0 →A N,Z 26. CPMX #CONSTANT Code Operation Flags 0000 1001 zzzz zzzz (X) ∀ zzzz zzzz Z 18. CLR X Code Operation Flags 0010 1010 0 →X ----27. CPMX label Code Operation Flags 0000 1101 zzzz zzzz (X) ∀ zzzz zzzz Z 19. CLR Y Code Operation Flags 0010 1011 0 →Y ----28. CPX #CONSTANT Code Operation Flags 0001 0001 zzzz zzzz X ∀ zzzz zzzz Z 20. CLR (X) Code Operation Flags 0010 1110 0 →(X) ----29. CPX label Code Operation Flags 0001 0101 zzzz zzzz X ∀ (zzzz zzzz) Z 21. CLR (Y) Code Operation Flags 0010 1111 0 →(Y) ----30. CPY #CONSTANT Code Operation Flags 0001 1001 zzzz zzzz Y ∀ zzzz zzzz Z 22. CLR label Code Operation Flags 0010 1100 0 →(zzzz zzzz) ----31. CPY label Code Operation Flags 0001 1101 zzzz zzzz Y ∀ (zzzz zzzz) Z 23. CLRC Code Operation Flags 0110 0001 0 →C C Score Concept Semiconductor Ltd. 17 Sept 2000 SCG9832 41. 32. DEC A Code Operation Flags 0110 1000 A – 1 →A N, Z, C 42. 33. DEC X Code Operation Flags 0110 1010 X – 1 →X N, Z, C 43. 34. DEC Y Code Operation Flags 0110 1011 Y – 1 →Y N, Z, C 44. 35. DEC (X) Code Operation Flags 0110 1110 (X) – 1 →(X) N, Z, C 45. 36. DEC (Y) Code Operation Flags 0110 1111 (Y) – 1 →(Y) N, Z, C 46. 37. DEC label Code Operation Flags 0110 1100 zzzz zzzz (zzzz zzzz)-1 →(zzzzzzzz) N, Z, C 47. 38. EOR X Code Operation Flags 0101 1010 X ∀ A →A N, Z 48. 39. EOR Y Code Operation Flags 0101 1011 Y ∀ A →A N, Z INC (Y) Code Operation Flags INC (X) Code Operation Flags INC Y Code Operation Flags INC X Code Operation Flags INC A Code Operation Flags EOR #CONSTANT Code Operation Flags EOR label Code Operation Flags EOR (Y) Code Operation Flags 8-BIT MICROCONTROLLER 0101 1111 (Y) ∀ A →A N, Z 0101 1100 zzzz zzzz (zzzz zzzz)∀ A →A N, Z 0101 1001 zzzz zzzz zzzz zzzz ∀ A →A N, Z 0110 0000 A + 1 →A N, Z, C 0110 0010 X + 1 →X N, Z, C 0110 0011 Y + 1 →Y N, Z, C 0110 0110 (X) + 1 →X N, Z, C 0110 0111 (Y) + 1 →Y N, Z, C 40. EOR (X) Code Operation Flags 0101 1110 (X) ∀ A →A N, Z Score Concept Semiconductor Ltd. 18 Sept 2000 SCG9832 55. 49. INC label Code Operation Flags 0110 0100 zzzz zzzz (zzzz zzzz) + 1 → (zzzz zzzz) 8-BIT MICROCONTROLLER MOV A, (X) Code Operation Flags 0000 0110 A →(X) ----- N, Z, C 56. MOV A, (Y) Code 0011 0110 PC LOW → (SP), SP-1 → SP PCHIGH→(SP), SP-1 → SP IPAGE → (SP), SP-1 → SP PS → (SP), SP-1 → SP 1→I 3FC0H → PC 3 → iPAGE,PAGE 58. MOV X, A Code Operation Flags 0001 0000 X →A N, Z 57. MOV A label Code Operation Flags 0000 0100 zzzz zzzz A →(zzzz zzzz) ----Operation Flags 0000 0111 A →(Y) ----- 50. INT Code Operation Flags I 51. JA Code Operation Flags 0111 0001 A →PC[7:0] ----- 59. MOV X, Y Code Operation Flags 0001 0011 X →Y ----- 52. JUMP ADDR14 Code Operation 10zz zzzz zzzz zzzz ADDR14 →PC[13:0] If PAGE≠iPAGE PAGE →iPAGE Flags ----- 60. MOV X, (Y) Code Operation Flags 0001 0111 X →(Y) ----- 61. MOV X, label Code 0001 0100 zzzz zzzz X →(zzzz zzzz) ----- 53. MOV A, X Code Operation Flags 0000 0010 A →X ----62. Operation Flags MOV Y, A Code 0001 1000 Y →A N, Z 54. MOV A, Y Code Operation Flags 0000 0011 A →Y ----- Operation Flags Score Concept Semiconductor Ltd. 19 Sept 2000 SCG9832 72. 63. MOV Y, X Code Operation Flags 0001 1010 Y →X ----73. 64. MOV Y, (X) Code Operation Flags 65. MOV Y, label Code Operation Flags 0001 1100 zzzz zzzz Y →(zzzz zzzz) ----75. 66. MOV (X), A Code Operation Flags 0011 0000 (X) →A N, Z 76. 67. MOV (X), Y Code Operation Flags 0011 0011 (X) →Y ----77. 68. MOV (X), (Y) Code Operation Flags 0011 0111 (X) →(Y) ----78. 69. MOV (X), label Code Operation Flags 0011 0100 zzzz zzzz (X) →(zzzz zzzz) ----79. 70. MOV (Y), A Code Operation Flags 0011 1000 (Y) →A N, Z 80. 71. MOV (Y), X Code Operation Flags 0011 1010 (Y) →X ----MOV #CONSTANT, X MOV #CONSTANT, A 8-BIT MICROCONTROLLER MOV (Y), (X) Code Operation Flags 0011 1110 (Y) →(X) ----- MOV (Y), label Code 0011 1100 zzzz zzzz (Y) →(zzzz zzzz) ----- 0001 1110 Y →(X) ----74. Operation Flags MOV label, A Code Operation Flags 0010 0000 zzzz zzzz (zzzz zzzz) →A N, Z MOV label, X Code Operation Flags 0010 0010 zzzz zzzz (zzzz zzzz) →X ----- MOV label, Y Code Operation Flags 0010 0011 zzzz zzzz (zzzz zzzz) →Y ----- MOV label, (X) Code Operation Flags 0010 0110 zzzz zzzz (zzzz zzzz) →(X) ----- MOV label, (Y) Code Operation Flags 0010 0111 zzzz zzzz (zzzz zzzz) →(Y) ----- Code Operation Flags 0000 1000 zzzz zzzz Zzzz zzzz →A N, Z Code Operation Flags 0000 1010 zzzz zzzz Zzzz zzzz →X ----- Score Concept Semiconductor Ltd. 20 Sept 2000 SCG9832 90. 81. MOV #CONSTANT, Y 8-BIT MICROCONTROLLER OR #CONSTANT Code 0000 1011 zzzz zzzz Zzzz zzzz →Y ----91. POP Code 0000 1110 zzzz zzzz Zzzz zzzz →(X) ----Flags Operation 0011 1111 SP+1→SP (SP)→A ----Operation Flags 0101 0001 zzzz zzzz Zzzz zzzzV A→A N, Z Code Operation Flags 82. MOV #CONSTANT, (X) Code Operation Flags 83. MOV #CONSTANT, (Y) 92. 0000 1111 zzzz zzzz zzzz zzzz →(Y) ----- PSHPAGE Code Operation Flags 0110 1101 PAGE→ (SP); SP-1→SP ----- Code Operation Flags 84. NOP Code Operation Flags 0000 0000 No operation ----- 93. PUSH Code Operation Flags 0110 1001 A→(SP),SP-1→SP ----- 85. OR X Code Operation Flags 0101 0010 X V A→A N, Z 94. ROL A Code Operation Flags 0111 0000 C←A←C N, Z, C 86. OR Y Code Operation Flags 0101 0011 Y V A→A N, Z 95. ROL X Code Operation Flags 0111 0010 C←X←C N, Z, C 87. OR (X) Code Operation Flags 0101 0110 (X) V A→A N, Z 96. ROL Y Code Operation Flags 0111 0011 C←Y←C N, Z, C 88. OR (Y) Code Operation Flags 0101 0111 (Y) V A→A N, Z 97. ROL (X) Code Operation Flags 0111 0110 C←(X)←C N, Z, C 89. OR label Code Operation Flags 0101 0100 zzzz zzzz (zzzz zzzz)V A→A N, Z Score Concept Semiconductor Ltd. 21 Sept 2000 SCG9832 107. 98. ROL (Y) Code Operation Flags 0111 0111 C←(Y)←C N, Z, C 108. 99. ROL label Code Operation Flags 0111 0100 zzzz zzzz C←(zzzz zzzz)←C N, Z, C 109. 100. ROM A Code Operation Flags 0111 1101 ROM (BANK,X,A)→A ----RTI Code Operation ROR label Code Operation Flags ROR (Y) Code Operation Flags 8-BIT MICROCONTROLLER 0111 1111 C→(Y)→C N, Z, C 0111 1100 zzzz zzzz C→(zzzz zzzz)→C N, Z, C 0100 0101 SP+1→SP (SP)→PS;SP+1→1 (SP)→IPAGE,PAGE; SP+1→SP (SP)¡PCHIGH; 101. ROM Y Code Operation Flags 0111 1001 ROM (BANK,X,Y)→A ----110. RTL Code 0001 0010 ROM (BANK,X,Y)→B ROM (BANK,X,Y+1)→A Operation Flags SP+1¡SP (SP)→PCLOW ----- 102. ROMDBL Code Operation 0100 1101 SP+1→SP (SP)→iPAGE,PAGE; SP+1→SP (SP)→PCHIGH SP+1→SP 103. ROR A Code Operation Flags 0111 1000 C¡A¡C N, Z, C 111. RTS Code 0111 1010 C→X→C N, Z, C Operation Flags (SP)→PCLOW ----- 104. ROR X Code Operation Flags 0101 0101 SP+1→SP (SP)→PCHIGH; SP+1→SP (SP)→PCLOW 105. ROR Y Code Operation Flags 0111 1011 C→Y→C N, Z, C 112. Flags ----- SETC Code Operation 0110 0101 1→C C 106. ROR (X) Code Operation Flags 0111 1110 C→(X)→C N, Z, C Flags Score Concept Semiconductor Ltd. 22 Sept 2000 SCG9832 8-BIT MICROCONTROLLER 113. SETZ Code Operation Flags 0101 1000 1→Z,0→A, N, Z 120. STOP Code Operation Flags 0010 0100 Stop ------ 114. SKIPC Code Operation Flags 0011 0001 PC+2→PC if C = 1 ----- 121. TAPAGE Code Operation 0111 0101 A→PAGE 122. 115. SKIPMI Code Operation Flags 0001 0110 PC+2→PC if N = 1 ----- TZ Code Operation 0101 0000 Z=1 if A = 0 Z=0 if A ≠ 0 Flags N, Z 116. SKIPNC Code Operation Flags 0011 1001 PC+2→PC if C = 0 ----- 123. XB Code Operation Flags 0010 0101 B↔A ----- 117. SKIPNZ Code Operation Flags 0010 1001 PC+2→PC if Z = 0 ----- 124. XBANK Code Operation Flags 0011 0101 BANK↔A ----- 118. SKIPPL Code Operation Flags 0001 1111 PC+2→PC if N = 0 ----- 125. XSP Code Operation Flags 0011 1101 SP↔A ----- 119. SKIPZ Code Operation Flags 0010 0001 PC+2→PC if Z = 1 ----- 126. XST Code Operation Flags 0010 1101 PS↔A N, Z, C, I Score Concept Semiconductor Ltd. 23 Sept 2000 SCG9832 8-BIT MICROCONTROLLER ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings: 1. 2. 3. 4. 5. VDD VIH VIL Operating Temperature Storage Temperature 7.0V VDD + 0.3V GND - 0.3V 0°C to + 60°C -50°C to + 150°C Recommended Operating: MIN 2.4 TYP 3.0 4.0 MAX 5.5 Unit V MHz 1. Operating Voltage (VDD) 2. Operating Frequency (Fosc) 3. Input Voltage 3.1 VDD = 2.4V 3.2 VDD = 3.0V 3.3 VDD = 5.5V VIH VIL VIH VIL VIH VIL 1.6 0 2.0 0 3.6 0 2.0 0.4 2.4 0.6 4.0 1.5 2.4 0.8 3.0 1.0 5.5V 1.8V V V V V V V 4. Output Voltage 4.1 VDD = 2.4V @1mA 4.2 VDD = 3.0V @2mA 4.3 VDD = 5.5V @10mA 5. Input Current VIH = VDD VIL = OV VOH VOL VOH VOL VOH VOL 2.0 2.4 4.0 - - 0.4 0.6 1.5 V V V V V V µA (through pull-low resistor) µA (leakage) IH IL - - 150 0.3 6. Output Current 6.1 VDD = 2.4V, 6.2 6.3 VDD = 3.0V, VDD = 5.5V, IOH@VOH =2.0V IOL@VOL =0.4V IOH@VOH =2.4V IOL@VOL =0.6V IOH@VOH =4.0V IOL@VOL =1.5V 1.0 2.0 1.5 3.0 8 16 1.5 3.0 3.5 7.0 10 20 - mA mA mA mA mA mA 7. Current Dissipation 7.1 Operating Current @4MHz, 3.0V & Output Pad Load = 50pF 7.2 Operating Current @4MHz, 5.0V & Output Pad Load = 50pF 7.3 Standby Current (OFF mode) 1.0 2.0 - 1.5 3.0 5.0 4.5 9.0 30.0 mA mA µA Score Concept Semiconductor Ltd. 24 Sept 2000 SCG9832 8-BIT MICROCONTROLLER PAD Co-ordinates EXT_INT RESET- TEST 37 39 1 2 3 4 5 6 7 8 9 10 11 12 13 P_CLK CLK32O CLK32I VSS P0RW0 38 36 VDD 35 Y VSS PWMM PWMP P2W6 P2W5 P2W4 VDD P2W3 P2W2 P0RW1 P0RW2 (0,0) X 34 33 32 31 30 29 28 27 14 VSS 15 P1RW0 16 P1RW1 17 P1RW2 18 P1RW3 19 VDD 20 P1RW4 21 P1RW5 22 P1RW6 23 P1RW7 24 VSS 25 P2W0 26 P2W1 P0RW3 VDD P0RW4 P0RW5 P0RW6 P0RW7 The substrate of IC should be connected to VSS Score Concept Semiconductor Ltd. 25 Sept 2000 SCG9832 8-BIT MICROCONTROLLER Pad No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Pad Name P_CLK CLK32O CLK32I VSS P0RW0 P0RW1 P0RW2 P0RW3 VDD P0RW4 P0RW5 P0RW6 P0RW7 VSS P1RW0 P1RW1 P1RW2 P1RW3 VDD X -1193.600 -1193.600 -1193.600 -1193.600 -1193.600 -1193.600 -1193.600 -1193.600 -1193.600 -1193.600 -1193.600 -1193.600 -1193.600 -984.000 -824.000 -664.000 -504.000 -344.000 -184.000 Y 955.000 795.000 635.000 475.000 315.000 155.000 -5.000 -165.000 -325.000 -485.000 -645.000 -805.000 -965.000 -1174.600 -1174.600 -1174.600 -1174.600 -1174.600 -1174.600 Pad No 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 Pad Name P1RW4 P1RW5 P1RW6 P1RW7 VSS P2W0 P2W1 P2W2 P2W3 VDD P2W4 P2W5 P2W6 PWMP PWMM VSS VDD TEST RESET EXT_INT X -24.000 136.000 296.000 456.000 616.000 776.000 936.000 1193.600 1193.600 1193.600 1193.600 1193.600 1193.600 1193.600 1193.600 1193.600 -504.000 -664.000 -824.000 -984.000 Y -1174.600 -1174.600 -1174.600 -1174.600 -1174.600 -1174.600 -1174.600 -965.000 -805.000 -645.000 -485.000 -325.000 -165.000 -5.000 155.000 315.000 1174.600 1174.600 1174.600 1174.600 Score Concept Semiconductor Ltd. 26 Sept 2000 SCG9832 8-BIT MICROCONTROLLER Application Circuit VCC U1 1 2 3 R2 100K 5 6 7 8 10 11 12 13 15 16 17 18 20 21 22 23 P_CLK CLK32O CLK32I P0RW0 P0RW1 P0RW2 P0RW3 P0RW4 P0RW5 P0RW6 P0RW7 P1RW0 P1RW1 P1RW2 P1RW3 P1RW4 P1RW5 P1RW6 P1RW7 SCG9832 32768 R1 RESET EXT_INT TEST 38 39 37 R3 47K C4 0.1u OPTIONAL Y1 P2W0 P2W1 P2W2 P2W3 P2W4 P2W5 P2W6 25 26 27 28 30 31 32 D1 LED D2 LED D3 LED D4 LED 1M C1 C2 SCORE CONCEPT SEMICONDUCTOR LIMITED Title SCG9832 application circuit Size A Date: Document Number SCG9832 Thursday, September 14, 2000 Sheet 1 of 1 Rev 1 Score Concept Semiconductor Ltd. 27 Sept 2000