SED1351
SED1351
GRAPHICS LCD CONTROLLER
s DESCRIPTION The SED1351F is a graphics LCD controller capable of controlling medium to large resolution displays. It transfers data from MPU to external frame buffer RAM and converts this data to display signals for LCD drivers. The SED1351F can display images with 4 gray shades and support display duty cycle as high as 1/ 1024. The SED1351F is designed to achieve high efficiency and data throughput to the LCD. It has a cycle steal mode which allows MPU to access frame buffer RAM without interfering with the display operation. The SED1351F can directly interface with up to eight 64K-bit SRAMs or two 256K-bit SRAMs. The SED1351F can operate with either 5V or 3V power supply. The 5V version chip is the SED1351F0A and the 3V version chip is the SED1351FLB.
s FEATURES
• Low-power CMOS technology • 8-bit or 16-bit MPU data interface • Direct interface with 80xx, Z80 and 68xxx MPU 8-bit panel • 4- or bus for dualdata bus for single panel and 4-bit panel Support logical OR of layers and panel division • • Smooth vertical scrolling • Virtual screen display up to 1024 mode • Binaryimages (on/off only) generates black & white mode • Grayimages(on/off4and two gray steps) generates with gray shades
s SYSTEM BLOCK DIAGRAM
• Maximum number of rows • • •
Binary mode ............ 2048 Gray mode .............. 1024 Maximum number of rows: Single panel ............ 1024 Dual panel ............... 2048 Maximum display sizes when 64K-byte SRAMs are used: Binary mode ............ 2048 × 256 / 1024 × 512 Gray mode .............. 1024 × 256 / 512 × 512 Available models: SED1351F0A ............ 5V, QFP5-100 pin SED1351FLB ............ 3V,QFP15-100 pin
CLOCK
DATA CONTROL
MPU
80xx Z80 68xxx
SED1351F
MONO LCD
ADDRESS
8 of 8K × 8 or 2 of 32K × 8
SRAM
197
SED1351
s INTERFACE WITH 8-BIT MPU (Z-80) AND 64K-BIT SRAM (8 of 8K x 8)
Z80
A0~A15 DECODER MMU DECODER MEMRQ IOREQ
SED1351F
A0~A15 IOCS MPUSEL
UD0~UD3,LD0~LD3 YD LP XSCL FR MONO LCD
MEMCS
VA0~VA12 VD0~VD7 VCS0~VCS7 VWE
A0~A12 I/O1~I/O8 CS(0) WE A0~A12 I/O1~I/O8 CS(1) WE A0~A12 I/O1~I/O8 CS(2) WE A0~A12 I/O1~I/O8 CS(3) WE
8K × 8
D0~D7 RD WR
DB0~DB7 IORD IOWR MEMRD MEMWR
A0~A12 I/O1~I/O8 CS(4) WE A0~A12 I/O1~I/O8 CS(5) WE A0~A12 I/O1~I/O8 CS(6) WE A0~A12 I/O1~I/O8 CS(7) WE
WAIT RESET CLK
READY RESET MPULCK
Note: Example implementation, actual may vary.
198
SED1351
s INTERFACE WITH 16-BIT MPU (8086) AND 64K-BIT SRAM (8 of 8K x 8)
8086 (Maximum Mode) 8288
MPUCLK CLK S2 CLK S2 S1 S0 DEN DT/R RDY RESET ALE VCS2 RESET MRDC AMWC IORC AIOWC +5V MPUSEL MEMRD MEMWR IORD IOWR VA0~VA12 VD0~VD7 VCS0 WE A0~A12 I/O1~I/O8 CS(0) WE A0~A12 I/O1~I/O8 CS(2) WE A0~A12 I/O1~I/O8 CS(4) WE A0~A12 I/O1~I/O8 CS(6) WE 8K × 8
SED1351
UD0~UD3,LD0~LD3 YD LP XSCL FR
MONO LCD
8284A
CLK S1 S0 READY READY
8282
M/IO BHE A16~A19 AD0~AD15 BHE A16~A19 A0~A15 STB OE
Decoder
MEMCS
VCS4 BHE
AB0~AB15
VCS6
Decoder
IOCS VD8~VD15 VCS1
A0~A12 I/O1~I/O8 CS(1) WE A0~A12 I/O1~I/O8 CS(3) WE A0~A12 I/O1~I/O8 CS(5) WE A0~A12 I/O1~I/O8 CS(7) WE
8286
D0~D15 T MIN/MAX OE VCS5 DB0~DB15 VCS3
RESET READY VCS7
Note: Example implementation, actual may vary.
199
SED1351
s INTERFACE WITH 16-BIT MPU (68000) AND 256K-BIT SRAM (2 of 32K x 8)
68000
DACK Q D READY
UD0~UD3,LD0~LD3 YD LP XSCL CK FR MONO LCD
VA1~VA15 FC0,1,2 A[16–23] AS Decoder MEMCS IOCS VD0~VD7 VCS0 VWE
A0~A14 I/O1~I/O8 32K × 8 CS(0) WE
MEMRD R/W IORD A0~A14 VD8~VD15 MEMWR IOWR A[1–15] LDS UDS AB1–AB15 AB0 BHE VCS1 I/O1~I/O8 32K × 8 CS(1) WE
Note: Example implementation, actual may vary.
200
SED1351
s SUPPORTED RESOLUTIONS Display RAM 8K 16K 24K 32K Maximum Display Size Monochrome 4 Grayscale X Y X Y 256 × 256 256 × 128 512 × 256 256 × 256 512 512 × × 384 512 384 512 × × 256 256 SRAM Type 1 of 8K × 8 2 of 8K × 8 3 of 8K × 8 4 of 8K × 8 1 of 32K × 8 6 of 8K × 8 7 of 8K × 8 8 of 8K × 8 2 of 32K × 8 CPU Interface 8 bit 8 bit 16 bit 8 bit 8 bit 16 bit 8 bit 8 bit 16 bit 8 bit 8 bit 16 bit 8 bit 16 bit SRAM Interface 8 bit 8 bit 16 bit 8 bit 8 bit 16 bit 8 bit 8 bit 16 bit 8 bit 8 bit 16 bit 8 bit 16 bit
48K 56K 64K
768 896 1024
× × ×
512 512 512
512 512 512
× × ×
384 448 512
s BLOCK DIAGRAM
READY
RESET MPUSEL, MPUCLK
IOCS,LOWR, IORD MEMCS, MEMWR, MEMRD
I/O Control
Control Register
R1 to R15
LCDENB
AB0 ~ AB15 BHE
Address Buffer
Display Timing Control
XSCL LP YD WF
DB0 ~ DB15
Data Buffer
16 Bits
Basic Training Generation
Refresh Address Counter
VRAM Control
Display Data Control
UD0 ~ UD3 LD0 ~ LD3
Oscillator
MPX
MPX
OSC1
OSC2
VA0 ~ VA15 VCS0 ~ VCS4
VWE
VD0 ~ VD15
201
SED1351
s ELECTRICAL CHARACTERISTICS SED1351F0A Absolute Maximum Ratings
• •
(VSS = 0V) Symbol VDD VI VO IO PD IDD/ISS Tstg Tsol Ratings VSS–0.3 to 7.0 VSS–0.3 to VDD+0.3 VSS–0.3 to VDD+0.3 ±10 200 ±40 –65 to 150 260°C, 10s (at lead) Unit V V V mA mW mA °C —
Parameter Supply voltage Input voltage Output voltage Output current/pin Power dissipation Supply current Storage temperature Soldering temperature and time
•
Recommended Operating Conditions (VSS = 0V) Parameter Supply voltage Input voltage Operating temperature Symbol VDD VI Topr Condition Min 4.5 VSS –20 Typ 5.0 — — Max 5.5 VDD 75 Unit V V °C
202
SED1351
°
DC Characteristics (F0A) Parameter Static current Symbol IDDS Condition VIN = VDD, VDD = Max, VSS, IOH = IOL = 0 VDD = 5.5V, VIH = VDD, VIL = VSS VDD = 5.5V VDD = 4.5V VDD = 5.5V VDD = 4.5V VDD = 5.5V VDD = 4.5V VDD = 5V VDD = 4.5V IOH = –2mA IOL = 6mA VDD = 4.5V IOH = –50µA IOL = 50µA Min — –10 3.5 — 2.0 — 4.0 — 0.3 VDD – 0.4 — VDD – 0.4 —
(Ta = –20 to 75°C) Typ — — — — — — — — — — — — — Max 100 10 — 1.0 — 0.8 — 0.8 — — VSS + 0.4 — VSS + 0.4 Unit µA µA V V V V V V V V V V V
Input leakage current (Type 1) High level input voltage 1 (OSC1) Low level input voltage 1 (OSC1) High level input voltage 2 (Type 2) Low level input voltage 2 (Type 2) High level input voltage 3 (Type 3) Low level input voltage 3 (Type 3) Hysteresis voltage (Type 3) High level output voltage 1 (Type 4) Low level output voltage 1 (Type 4) High level output voltage 2 (OSC2) Low level output voltage 2 (OSC2)
ILI VIH1 VIL1 VIH2 VIL2 VT+ VT– VH VOH1 VOL1 VOH2 VOL2
Note: Type 1. MEMCS, MEMWR, MEMRD, IOCS, IOWR, IORD, MPUCLK, AB0 ~ AB15, BHE, MPUSEL, RESET, OSC Type 2. MEMCS, MEMWR, MEMRD, IOCS, IOWR, IORD, MPUCLK, AB0 ~ AB15, BHE, DB0 ~ DB15, VD0 ~ VD15 Type 3. MPUSEL, RESET Type 4. DB0 ~ DB15, READY, VA0 ~ VA15, VCS0 ~ VCS4, VD0 ~ VD15, VWE, XSCL, LP, WF, YD, UD0 ~ UD3, LD0 ~ LD3, LCDENB
203
SED1351
• •
SED1351FLA Absolute Maximum Ratings Parameter Supply voltage Input voltage Output voltage Output current/pin Power dissipation Supply current Storage temperature Symbol VDD VI VO IO PD IDD/ISS Tstg Ratings VSS–0.3 to 7.0 VSS–0.3 to VDD+0.5 VSS–0.3 to VDD+0.5 ±24 200 ±40 –65 to 150
(VSS = 0V) Unit V V V mA mW mA °C
•
Recommended Operating Conditions (VSS = 0V) Parameter Supply voltage Input voltage Operating temperature Symbol VDD VI Topr Condition Min 2.7 VSS –20 Typ — — — Max 3.6 VDD 75 Unit V V °C
204
SED1351
°
DC Characteristics (FLB) Parameter Static current Symbol IDDS Condition VIN = VDD or VSS, VDD = MAX, IOH = IOL = 0 VDD = MAX, VIH = VDD, VIL = VSS VDD = MAX VDD = MIN VDD = MAX VDD = MIN VDD = MAX VDD = MIN VDD = TYP VDD = MIN IOH = –1.5mA IOL = 3mA VDD = MIN IOH = –50µA IOL = 50µA Min —
(Ta = –20 to 75°C) Typ — Max 30 Unit µA
Input leakage current (Type 1) High level input voltage 1 (OSC1) Low level input voltage 1 (OSC1) High level input voltage 2 (Type 2) Low level input voltage 2 (Type 2) High level input voltage 3 (Type 3) Low level input voltage 3 (Type 3) Hysteresis voltage (Type 3) High level output voltage 1 (Type 4) Low level output voltage 1 (Type 4) High level output voltage 2 (OSC2) Low level output voltage 2 (OSC2)
IL VIH1 VIL1 VIH2 VIL2 VT+ VT– VH VOH1 VOL1 VOH2 VOL2
–1 0.7VDD — 0.7VDD — 0.8VDD — 0.3 VDD – 0.3 — VDD – 0.4 —
— — — — — — — — — — — —
1 — 0.2VDD — 0.2VDD — 0.2VDD — — VSS + 0.3 — VSS + 0.4
µA V V V V V V V V V V V
Note: Type 1. MEMCS, MEMWR, MEMRD, IOCS, IOWR, IORD, MPUCLK, AB0 ~ AB15, BHE, MPUSEL, RESET, OSC Type 2. MEMCS, MEMWR, MEMRD, IOCS, IOWR, IORD, MPUCLK, AB0 ~ AB15, BHE, DB0 ~ DB15, VD0 ~ VD15 Type 3. MPUSEL, RESET Type 4. DB0 ~ DB15, READY, VA0 ~ VA15, VCS0 ~ VCS4, VD0 ~ VD15, VWE, XSCL, LP, WF, YD, UD0 ~ UD3, LD0 ~ LD3, LCDENB
205
SED1351
s PIN CONFIGURATION (F0A)
VD11 VD12 VD13 VD14 VD15 LCDENB XSCL LP WF YD UD0 UD1 UD2 UD3 LD0 LD1 LD2 LD3 OSC1 OSC2
s PIN CONFIGURATION (FLB)
VD8 VD9 VD10 VD11 VD12 VD13 VD14 VD15 LCDENB XSCL LP WF YD UD0 UD1 UD2 UD3 LD0 LD1 LD2 LD3 OSC1 OSC2 VSS VDD
100 1
80 81
76
82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99
100 75 1 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99
SED1351FOA
SED1351FLB
206
49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 25 51 26 50
IOCS IOWR IORD MEMCS MEMWR MEMRD READY MPUCLK RESET MPUSEL BHE AB0 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52
VD7 VD6 VD5 VD4 VD3 VD2 VD1 VD0 VCS0 VCS1 VCS2 VCS3 VCS4 VA15 VA14 VA13 VA12 VA11 VA10 VA9 VA8 VA7 VA6 VA5 VDD
VSS VDD IOCS IOWR IORD MEMCS MEMWR MEMRD READY MPUCLK RESET MPUSEL BHE AB0 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 DB0 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52
49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
VSS VDD VD10 VD9 VD8 VD7 VD6 VD5 VD4 VD3 VD2 VD1 VD0 VCS0 VCS1 VCS2 VCS3 VCS4 VA15 VA14 VA13 VA12 VA11 VA10 VA9 VA8 VA7 VA6 VA5 VA4
31 30
51 50
VSS VA4 VA3 VA2 VA1 VA0 VWE DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 AB15 AB14
VA3 VA2 VA1 VA0 VWE DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1
SED1351
s PIN DESCRIPTION 1. System Connector Terminals (at MPU) Pin Name DB0 to DB15 Type I/O F0A Pin No. 30 to 45 FLB Pin No. 28 to 43 Drv Description These pins are interfaced with the MPU data bus. When using an 8-bit MPU, connect DB8 to DB15 to VDD. These pins are interfaced with the MPU address bus. If multiplexed address signals are used, connect them via latch circuits. A control register is selected by AB0 to AB3. Correspondence of the MPU address bus to the VRAM address bus is such that ABi = VAi (where i is a pin number). This signal is a bus high enable signal where a 16-bit MPU is used. It goes “L” (low) when an odd address is encountered. When using an 8-bit MPU configuration, connect the BHE pin to VDD. This pin selects a control register contained in the SED1351. It is “L” active, and must be assigned to MPU I/O space. This signal is used for writing data into a control register contained in the SED1351. It is “L” active, and must go “L” when it encounters an OUT instruction from the MPU. This signal is used for reading data from a control register contained in the SED1351. It is “L” active, and must go “L” when it encounters an IN instruction from the MPU. This signal is used for selecting VRAM. It is “L” active, and must be assigned to MPU memory space. This signal is used for writing data to the VRAM. It is “L” active, and must go “L” when it encounters a memory write instruction from the MPU. This signal is used for reading data from the VRAM. It is “L” active, and must go “L” when it encounters a memory read instruction from the MPU. This signal requests the MPU to wait. It goes “L” by the falling edge of IOCS or MEMCS. It goes “H” by the rising edge of MPUCLK after completion of the SED1351 internal processing. Since READY is not a tri-state pin, it needed not be pulled up and must be connected directly to the READY (WAIT) terminal of the MPU. This pin accepts an MPU clock. The MPU wait state is cleared by the rising edge of MPUCLK. This signal is connected to either VDD or VSS for selection of an MPU. MPUSEL = VSS 8-bit MPU (e.g., Z80, V20, i8088) MPUSEL = VDD 16-bit MPU (e.g., V30, i8086) The MPU reset signal comes to this pin. It is “H” active, and initializes a control register.
AB0 to AB15
I
14 to 29
12 to 27
BHE
I
13
11
IOCS
I
3
1
IOWR
I
4
2
IORD
I
5
3
MEMCS MEMWR
I I
6 7
4 5
MEMRD
I
8
6
READY
O
9
7
MPUCLK MPUSEL
I I
10 12
8 10
RESET
I
11
9
207
SED1351
Combinations of Control Pins IOCS 1 0 0 1 1 IOWR * 0 1 1 1 IORD * 1 0 1 1 MEMCS 1 1 1 0 0 MEMWR * 1 1 0 1 MEMRD * 1 1 1 0 Operation Invalid Write to control register Read from control register Write to VRAM Read from VRAM
Note: Any combination other than those listed above will cause a system error. 1 = “H” (high) 0 = “L” (low) * = Don’t care
2. VRAM Connector Terminals Pin Name VD0 to VD15 Type I/O F0A Pin No. 68 to 78, 81 to 85 FLB Pin No. 68 to 83 Drv Description These pins are interfaced with the VRAM data bus. For a 16-bit MPU configuration, VD0 to VD7 must be connected to even addresses, and VD8 to VD15 to odd addresses. For an 8-bit configuration, VD8 to VD15 must be connected to VDD. These pins are interfaced with the VRAM address bus and chip select pins. The SED1351 has chip select pins that can directly control eight 64K SRAMs (8K bytes each) or two 256K SRAMs (32K bytes) in the 64K VRAM space. See Technical Manual for details. This signal is used for writing data to the VRAM. It is “L” active, and must be connected to the WE pin of the VRAM.
VA0 to VA12 VA13/VCS7 to VA15/VCS5 VCS0 to VCS4 VWE
O O O O
47 to 59 60 to 62 67 to 63 46
45 to 49, 52 to 59 60 to 62 67 to 63 44
3. Oscillator Terminals Pin Name OSC1 OSC2 Type I O F0A Pin No. 99 100 FLB Pin No. 97 98 Drv Description The OSC1 (input) and OSC2 (output) pins generate clocks for internal operation. They allow crystal oscillation and external clock input.
4. Power Terminals Pin Name VDD VSS Type — — F0A Pin No. 2, 79 1, 80 FLB Pin No. 51, 100 50, 99 Drv Description The power supply pins include two VDDs and two VSSs. Apply +5V or +3V to VDD and 0V to VSS. A capacitor (4.7 µF or more) must be connected near each pair of VDD/VSS pins.
208
SED1351
5. LCD Connector Terminals Pin Name UD0 to UD3 LD0/UD4 to LD3/UD7 Type I/O O F0A Pin No. 91 to 94 95 to 98 FLB Pin No. 89 to 92 93 to 96 Drv Description LCD display data. UD0 to UD3 are the upper panel display data in the signal panel or double panel drive panel mode. LD0/UD4 to LD3/UD7 are the lower panel display data in the double panel drive mode. UD0 to UD3, and LD0/UD4 to LD3/UD7 are used for 8bit data transfer in the single panel drive mode. This single is a shift clock for display data transfer. Take the UD0 to UD3, LD0/UD4 to LD3/UD7 display data into LCDs by the falling edge of XSCL. This pin provides both a display data latch pulse and a scan signal transfer clock. Upon completion of transferring the LCD data on one line, display data can be latched or a scan signal transferred by the falling edge of LP. This pin provides a frame signal used for LCD AC driving. This pin provides a scanning line start pulse. The signal is “H” active. Allow the scanning line drive IC to take in YD by the falling edge of LP. The SED1351 has two lines of retracing; if two scanning line drive ICs are cascade-connected for the upper and lower panels in the double panel drive mode, two lines must be provided between the upper and lower scanning line drive outputs. This pin provides the data which is set in bit 1 (D1) of the mode register (R1). LCDENB goes “L” when the system is reset; it can be effectively used for LCD power control.
XSCL
O
87
85
LP
O
88
86
WF YD
O O
89 90
87 88
LCDENB
O
86
84
209
SED1351
Illustrated below are the display data which are output from the UD0 to UD3, LD0/UD4 to LD3/UD7 and the display on the panel:
UD3
UD2
UD1
UD0
...
UD3
UD2
UD1
UD0
LD3
LD2
LD1
LD0
...
Dual Panel — Top
LD3 LD2 LD1 LD0
...
8-bit Single Panel
Dual Panel — Bottom
UD3
UD2
UD1
UD0
UD3
UD2
UD1
UD0
...
4-bit Single Panel
s LCD PANEL PIXELS
640 DOTS 1-1 2-1 1-2 2-2 1 - 639 2 - 639 1 - 640 2 - 640
240 LINES
UPPER LCD PANEL
240 - 1 241 - 1
240 - 2 241 - 2 (TOP VIEW)
240- 639 240- 640 241- 639 241- 640
240 LINES
LOWER LCD PANEL
480 - 1
480 - 2
480- 639 480- 640
210
SED1351
s MONOCHROME LCD PANEL INTERFACE 8-Bit Dual Monochrome Panel (i.e. 640 × 480)
LP : 242 PULSES YD LP WF UD[3:0], LD[3:0]
LINE 1/241 LINE 2/242 LINE 3/243 LINE 4/244 LINE 239/479 LINE 240/480 LINE 1/241 LINE 2/242
LP WF XSCL: 160 CLOCKS XSCL UD3 UD2 UD1 UD0 LD3 LD2 LD1 LD0
1–1 1–2 1–3 1–4 241–1 241–2 241–3 241–4 1–5 1–6 1–7 1–8 241–5 241–6 241–7 241–8 1–637 1–638 1–639 1–640 241–637 241–638 241–639 241–640
211
SED1351
s MONOCHROME LCD PANEL INTERFACE 4-Bit Single Monochrome Panel (i.e. 320 × 480)
LP : 482 PULSES YD LP WF UD[3:0]
LINE 1 LINE 2 LINE 3 LINE 4 LINE 479 LINE 480 LINE 1 LINE 2
LP WF XSCL: 80 CLOCKS XSCL UD3 UD2 UD1 UD0
1–1 1–2 1–3 1–4 1–5 1–6 1–7 1–8 1–317 1–318 1–319 1–320
8-Bit Single Monochrome Panel (i.e. 640 × 480)
LP : 482 PULSES YD LP WF UD[3:0], LD[3:0]
LINE 1 LINE 2 LINE 3 LINE 4 LINE 479 LINE 480 LINE 1 LINE 2
LP WF XSCL: 80 CLOCKS XSCL UD3 UD2 UD1 UD0 LD3 LD2 LD1 LD0
1–1 1–2 1–3 1–4 1–5 1–6 1–7 1–8 1–9 1–10 1–11 1–12 1–13 1–14 1–15 1–16 1–633 1–634 1–635 1–636 1–637 1–638 1–639 1–640
212
SED1351
s PACKAGE DIMENSIONS
•
SED1351F0A QFP5-100pin
25.6 ± 0.4 20 ± 0.1 80 51
Unit: mm
81
50
Index
100
31
1
0.15± 0.05 2.7 ± 0.1
30 0.65 ± 0.1 0.30 ± 0.1
19.6 ± 0.4
14 ± 0.1
0 ~12°
1.5 ±0.3
2.8
Actual Size
•
SED1351FLB QFP15-100pin
16.0 ± 0.4 14.0 ± 0.1 75 76 51 50
Unit: mm
14.0 ± 0.1 26 25 0.18 ± 0.1
Index
100 1 0.125 ± 0.05 1.4 ± 0.1 0.5 ± 0.1
16.0 ± 0.4 0 ~ 12°
0.5 ± 0.2
1.0
Actual Size
213
SED1351
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