SG-XA3XXXX

CRYSTAL CLOCK OSCILLATORS HF/UHF SMD TCVCXO Data Sheet 0631B Rev. A SG-XA3XXXX Series Description The SG-XA3XXXX Series of SMD temperature compensated, voltage controlled crystal oscillators (TCVCXO) provides High and Ultra High Frequency with excellent temperature stability, extremely low phase noise and jitter with variety of different output types in a small surface mount FR4 based package. Applications and Features • Ultra High Frequency - up to 1GHz • Small, Low Profile SMD Package • Very Low Phase Jitter and Phase Noise • Excellent Frequency Stability • CMOS, Sine-wave, Differential PECL or LVDS outputs available • Stratum 3 available Creating a Part Number SG - X A3 X X X X - FREQ Package Code SG 7 pad 1.0"x0.87" SMD Input Voltage 0 5.0V±5% A 3.3V±5% TCXO/TCVCXO Option T No V. Control V With V Control Output Type C CMOS P PECL S Sine-wave L LVDS Temp Frequency Stability, ppm 1 ±1.0 2 ±2.5 3 ±0.28 Temperature Range, °C B 0 to 70 C -20 to 70 D -40 to 85 E -10 to 60 9 Customer specific 357 Beloit Street, P.O. Box 457, Burlington, WI 53105-0457 U.S.A. Phone 262/763-3591 FAX 262/763-2881 Email: nelsales@nelfc.com www.nelfc.com CRYSTAL CLOCK OSCILLATORS SG-XA3XXXX Series Continued HF/UHF SMD TCVCXO Parameter Input Break Down Voltage Storage Temperature Control Voltage Sym Vcc Ts Vc Data Sheet 0631B Rev. A Absolute Maximum Ratings Condition Min -0.5 -40 -1 Typ Max 5.5 105 9 Unit V ºC V Note Electrical Parameters Parameter Frequency Range Input Voltage Input current Frequency Stability Frequency Stability Sym F Vcc Icc ∆F/F ∆F/F Conditions CMOS Sine-wave PECL,LVDS Code 0 Code A CMOS,Sine PECL, Sine,LVDS Overall, available vs Temperature vs Vcc Aging As shipped, 25°C CMOS Sinewave PECL LVDS At 50 % 20 to 80% CMOS CMOS PECL PECL Differential amplitude Amplitude error Offset Voltage Offset Voltage error Sinewave Into 50 Ohm 1 sigma PECL, LVDS, Sine CMOS, Sine Sine-wave @10 Hz @100 Hz @1 KHz @10KHz @100KHz @10 Hz @100 Hz @1 KHz @10KHz @100KHz Vc MB Vc=0V to 3.3V, 25°C 0 100Hz ±5 ±7 MIN 30 30 30 4.75 3.135 TYP MAX 200 1,000 1,000 5.25 3.465 30 100 ±4.6 ±1 Unit MHz V mA @100MHz, 3.3V @622MHz, 3.3V 20 years See Chart First Year 10 years Note 5.0 3.3 Calibration Load ∆F/F Duty Cycle Rise/Fall Time Logic “1" level Logic “0" level Logic “1" level Logic “0" level Output Levels LVDS Tr/Tf Voh Vol Voh Vol Vod ±0.5 ppm ±0.1 ppm/V ±1 ppm/year ±3.5 ppm ±0.5 ±1 ppm 15pf/10KOhmOhm Internally AC-coupled 50 Ohm 50 Ohm to Vcc-2V or Thevenin equivalent 100 Ohm between the outputs, receiving end 45/55 50/50 55/45 % 3 ns 0.35 0.9Vcc V 0.1Vcc V Vcc-0.96 Vcc-0.81 V Vcc-1.85 Vcc-1.65 V 247 330 454 mV 50 1.375 50 10 1 0.4 -40 none -60 -25 mV V mV dBm ms ps dBc dBc dBc dBc/Hz CMOS, PECL, LVDS CMOS PECL, LVDS 100K available 100K available Vof Output power Start up Time Phase jitter Sub-harmonics Spurious Harmonics SSB Phase Noise P Ts 1.125 4 1.25 37 2 0.4 0.2 -45 -30 -80 -110 -140 -155 -160 -60/-60 -90/-90 -120/-120 -140/-145 -145/-150 > 10 K Ohm 3.3V 5.0V 100Hz to 20MHz 12kHz to 20MHz F>250MHz F