SI5320-X-BC

Si5320 SONET/SDH P R E C I S I O N C L O C K M U L T I P L I E R I C Features Ultra-low-jitter clock output with jitter generation as low as 0.3 psRMS No external components (other than a resistor and standard bypassing) Input clock ranges at 19, 39, 78, 155, 311, and 622 MHz Output clock ranges at 19, 155, or 622 MHz Digital hold for loss of input clock Support for forward and reverse FEC clock scaling Selectable loop bandwidth Loss-of-signal alarm output Low power Small size (9x9 mm) Si5320 Si5320 Applications SONET/SDH line/port cards Optical modules Core switches Digital cross connects Terabit routers Ordering Information: See page 29. Description The Si5320 is a precision clock multiplier designed to exceed the requirements of high-speed communication systems, including OC-192/OC-48 and 10 GbE. This device phase locks to an input clock in the 19, 39, 78, 155, 311, or 622 MHz frequency range and generates a frequency-multiplied clock output that can be configured for operation in the 19, 155, or 622 MHz range. Silicon Laboratories’ DSPLL™ technology delivers all PLL functionality with unparalleled performance while eliminating external loop filter components, providing programmable loop parameters, and simplifying design. FEC rates are supported with selectable 255/ 238 or 238/255 scaling of the clock multiplication ratios. The Si5320 establishes a new standard in performance and integration for ultra-low-jitter clock generation. It operates from a single 3.3 V supply. Functional Block Diagram REXT VSEL33 V DD GND Biasing & Supply Regulation FXDDELAY CLKIN+ CLKIN– 2 CAL_ACTV ÷ Signal Detect 3 M DSPLLT DH_ACTV ÷ Calibration VALTIME LOS 2 CLKOUT+ CLKOUT– FRQSEL[1:0] RSTN/CAL 2 2 INFRQSEL[2:0] FEC[1:0] DBLBW BWSEL[1:0] Rev. 2.3 4/05 Copyright © 2005 by Silicon Laboratories Si5320 S i5320 NOTES: 2 Rev. 2.3 S i5320 TA B L E O F C O N T E N TS Section Page 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.1. DSPLL™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 2.2. Clock Input and Output Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 2.3. PLL Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.4. Digital Hold of the PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.5. Hitless Recovery from Digital Hold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 2.6. Loss-of-Signal Alarm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 2.7. Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.8. PLL Self-Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.9. Bias Generation Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 2.10. Differential Input Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.11. Differential Output Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.12. Power Supply Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.13. Design and Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3. Pin Descriptions: Si5320 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 4. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6. 9x9 mm CBGA Card Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Rev. 2.3 3 S i5320 1. Electrical Specifications Table 1. Recommended Operating Conditions Parameter Ambient Temperature Si5320 Supply Voltage3 When Using 3.3 V Supply Symbol TA VDD33 Test Condition Min1 –202 3.135 Typ 25 3.3 Max1 85 3.465 Unit °C V Notes: 1. All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise stated. 2. The Si5320 is guaranteed by design to operate at –40° C. All electrical specifications are guaranteed for an ambient temperature of –20 to 85° C. 3. The Si5320 specifications are guaranteed when using the recommended application circuit (including component tolerance) of Figure 5 on page 15. 3.3 V operation uses an on-chip voltage regulator and is recommended. 4 Rev. 2.3 S i5320 C LKIN + C LKIN – V IS A. O peration with Single-Ended C lock Input N ote: W hen using single-ended clock sources, the unused clock input on the Si5320 m ust be ac-coupled to ground. C LKIN + C LKIN – 0.5 V ID (C LKIN+) – (C LKIN –) V ID B. O peration with D ifferential C lock Input N ote: Transm ission line term ination, when required, m ust be provided externally. Figure 1. CLKIN Voltage Characteristics 80% 20% tF tR Figure 2. Rise/Fall Time Measurement (C L K IN + ) – (C L K IN – ) 0V tLOS Figure 3. Transitionless Period on CLKIN for Detecting a LOS Condition Rev. 2.3 5 S i5320 Table 2. DC Characteristics, VDD = 3.3 V (VDD33 = 3.3 V ±5%, TA = –20 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit Supply Current 1 Supply Current 2 Power Dissipation Using 3.3 V Supply Clock Output Common Mode Input Voltage (CLKIN) 1,2,3 IDD IDD PD VICM VIS VID RIN VOD VOCM ISC(–) ISC(+) VIL VIH IIL IIH Ipd RIN VOL VOH Clock in = 622.08 MHz Clock out = 19.44 MHz Clock in = 19.44 MHz Clock out = 622.08 MHz Clock in = 19.44 MHz Clock out = 622.08 MHz — — — 1.0 141 135 445 1.5 — — 80 906 1.8 — 15 — — — — — — — — 155 145 479 2.0 5004 5004 — 1100 2.2 — — 0.8 — 50 50 50 — 0.4 — mA mA mW V mVPP mVPP kΩ mVPP V mA mA V V µA µA µA Single-Ended Input Voltage2,3,4 (CLKIN) Differential Input Voltage Swing2,3,4 (CLKIN) Input Impedance (CLKIN+, CLKIN–) Differential Output Voltage Swing (CLKOUT) Output Common Mode Voltage (CLKOUT) Output Short to GND (CLKOUT) Output Short to VDD25 (CLKOUT) Input Voltage Low (LVTTL Inputs) Input Voltage High (LVTTL Inputs) Input Low Current (LVTTL Inputs) Input High Current (LVTTL Inputs) Internal Pulldowns (All LVTTL Inputs) Input Impedance (LVTTL Inputs) Output Voltage Low (LVTTL Outputs) Output Voltage High (LVTTL Outputs) Notes: See Figure 1A See Figure 1B 200 200 — 100 Ω Load Line-to-Line 100 Ω Load Line-to-Line 816 1.4 –60 — — 2.0 — — — 50 kΩ V V IO = .5 mA IO = .5 mA — 2.0 1. The Si5320 device provides weak 1.5 V internal biasing that enables ac-coupled operation. 2. Clock inputs may be driven differentially or single-endedly. When driven single-endedly, the unused input should be ac coupled to ground. 3. Transmission line termination, when required, must be provided externally. 4. Although the Si5320 device can operate with input clock swings as high as 1500 mVPP, Silicon Laboratories recommends maintaining the input clock amplitude below 500 mVPP for optimal performance. 6 Rev. 2.3 S i5320 Table 3. AC Characteristics (VDD33 = 3.3 V ±5%, TA = –20 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit Input Clock Frequency (CLKIN) FEC[1:0] = 00 (non FEC) INFRQSEL[2:0] = 001 INFRQSEL[2:0] = 010 INFRQSEL[2:0] = 011 INFRQSEL[2:0] = 100 INFRQSEL[2:0] = 101 INFRQSEL[2:0] = 110 Input Clock Frequency (CLKIN) FEC[1:0] = 01 (forward FEC) INFRQSEL[2:0] = 001 INFRQSEL[2:0] = 010 INFRQSEL[2:0] = 011 INFRQSEL[2:0] = 100 INFRQSEL[2:0] = 101 INFRQSEL[2:0] = 110 Input Clock Frequency (CLKIN) FEC[1:0] = 10 (reverse FEC) INFRQSEL[2:0] = 001 INFRQSEL[2:0] = 010 INFRQSEL[2:0] = 011 INFRQSEL[2:0] = 100 INFRQSEL[2:0] = 101 INFRQSEL[2:0] = 110 Input Clock Rise Time (CLKIN) Input Clock Fall Time (CLKIN) Input Clock Duty Cycle CLKOUT Frequency FRQSEL[1:0] = 00 (no output) FRQSEL[1:0] = 01 FRQSEL[1:0] = 10 FRQSEL[1:0] = 11 CLKOUT Rise Time CLKOUT Fall Time Output Clock Duty Cycle RSTN/CAL Pulse Width Range* fCLKIN No FEC Scaling 19.436 38.872 77.744 155.48 310.97 621.95 — — — — — — 21.685 43.369 86.738 173.48 346.95 693.90 MHz fCLKIN 255/238 FEC Scaling 18.142 36.284 72.568 145.13 290.27 580.54 — — — — — — 20.239 40.478 80.955 161.91 323.82 647.64 MHz fCLKIN 238/255 FEC Scaling 20.826 41.652 83.305 166.61 333.22 666.44 — — — — — — — — 50 — — — — 213 191 — — 23.234 46.465 92.934 185.87 371.74 743.47 11 11 60 — 21.685 173.48 693.90 260 260 52 — MHz tR tF CDUTY_IN Figure 2 Figure 2 — — 40 — 19.436 155.48 621.95 ns ns % fO_19 fO_155 fO_622 tR tF CDUTY_OUT tRSTN Figure 2; single-ended; after 3 cm of 50 Ω FR4 stripline Figure 2; single-ended; after 3 cm of 50 Ω FR4 stripline Differential: (CLKOUT+) – (CLKOUT–) MHz — — 48 20 ps ps % ns *Note: The Si5320 provides a 1/32, 1/16, 1/8, 1/4, 1/2, 1, 2, 4, 8, 16, or 32x clock frequency multiplication function with an option for additional frequency scaling by a factor of 255/238 or 238/255 for FEC rate compatibility. Rev. 2.3 7 S i5320 Table 3. AC Characteristics (Continued) (VDD33 = 3.3 V ±5%, TA = –20 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit Transitionless Period Required on CLKIN for Detecting a LOS Condition. INFRQSEL[2:0] = 001 INFRQSEL[2:0] = 010 INFRQSEL[2:0] = 011 INFRQSEL[2:0] = 100 INFRQSEL[2:0] = 101 INFRQSEL[2:0] = 110 Recovery Time for Clearing an LOS Condition VALTIME = 0 VALTIME = 1 tLOS Figure 3 16 24/ /fo_622 12 /fo_622 10/ fo_622 9 /fo_622 9 /fo_622 tVAL Measured from when a valid reference clock is applied until the LOS flag clears fo_622 — — — — — — 32 /fo_622 32 /fo_622 32/ fo_622 32 /fo_622 32 /fo_622 32/ fo_622 s 0.09 12.0 — — 0.22 14.1 s *Note: The Si5320 provides a 1/32, 1/16, 1/8, 1/4, 1/2, 1, 2, 4, 8, 16, or 32x clock frequency multiplication function with an option for additional frequency scaling by a factor of 255/238 or 238/255 for FEC rate compatibility. 8 Rev. 2.3 S i5320 Table 4. AC Characteristics (PLL Performance Characteristics) (VDD33 = 3.3 V ±5%, TA = –20 to 85 °C) Parameter Wander/Jitter at 800 Hz Bandwidth (BWSEL[1:0] = 10 and DBLBW = 0) Symbol Test Condition Min Typ Max Unit Jitter Tolerance (see Figure 7) JTOL(PP) f = 8 Hz f = 80 Hz f = 800 Hz 1000 100 10 — — — — — — — — — — — — — 0.87 0.26 0.85 0.26 7.3 3.7 7.2 3.8 800 0.0 — — — 1.2 0.35 1.2 0.35 10.0 5.0 10.0 5.0 — 0.05 ns ns ns ps ps ps ps ps ps ps ps Hz dB CLKOUT RMS Jitter Generation FEC[1:0] = 00 CLKOUT RMS Jitter Generation FEC[1:0 = 01, 10 CLKOUT Peak-Peak Jitter Generation FEC[1:0 = 00 CLKOUT Peak-Peak Jitter Generation FEC[1:0 = 01, 10 Jitter Transfer Bandwidth (see Figure 6) Wander/Jitter Transfer Peaking Wander/Jitter at 1600 Hz Bandwidth (BWSEL[1:0] = 10 and DBLBW = 1) JGEN(RMS) JGEN(RMS) JGEN(PP) JGEN(PP) FBW JP 12 kHz to 20 MHz 50 kHz to 80 MHz 12 kHz to 20 MHz 50 kHz to 80 MHz 12 kHz to 20 MHz 50 kHz to 80 MHz 12 kHz to 20 MHz 50 kHz to 80 MHz BW = 800 Hz < 800 Hz Jitter Tolerance (see Figure 7) f = 16 Hz f = 160 Hz f = 1600 Hz 500 50 5 — — — — — — — — — 0.78 0.25 7.0 3.8 1600 0.00 — — — 1.2 0.35 9.0 5.0 — 0.05 ns ns ns ps ps ps ps Hz dB CLKOUT RMS Jitter Generation FEC[1:0] = 00 CLKOUT Peak-Peak Jitter Generation FEC[1:0] = 00 Jitter Transfer Bandwidth (see Figure 6) Wander/Jitter Transfer Peaking JGEN(RMS) JGEN(PP) FBW JP 12 kHz to 20 MHz 50 kHz to 80 MHz 12 kHz to 20 MHz 50 kHz to 80 MHz BW = 1600 Hz < 1600 Hz Notes: 1. Higher PLL bandwidth settings provide smaller clock output wander with temperature gradient. 2. For reliable device operation, temperature gradients should be limited to 10 °C/min. 3. Telcordia GR-1244-CORE requirements specify maximum phase transient slope during clock rearrangement in terms of nanoseconds per millisecond. The equivalent ps/µs unit is used here since the maximum phase transient magnitude for the Si5320 (tPT_MTIE) never reaches one nanosecond. Rev. 2.3 9 S i5320 Table 4. AC Characteristics (PLL Performance Characteristics) (Continued) (VDD33 = 3.3 V ±5%, TA = –20 to 85 °C) Parameter Wander/Jitter at 1600 Hz Bandwidth (BWSEL[1:0] = 01 and DBLBW = 0) Symbol Test Condition Min Typ Max Unit Jitter Tolerance (see Figure 7) JTOL(PP) f = 16 Hz f = 160 Hz f = 1600 Hz 1000 100 10 — — — — — — — — — — — — — 0.82 0.26 0.79 0.26 7.3 3.8 7.1 4.3 1600 0.0 — — — 1.0 0.35 1.0 0.35 10.0 5.0 10.0 5.0 — 0.1 ns ns ns ps ps ps ps ps ps ps ps Hz dB CLKOUT RMS Jitter Generation FEC[1:0] = 00 CLKOUT RMS Jitter Generation FEC[1:0] = 01, 10 CLKOUT Peak-Peak Jitter Generation FEC[1:0] = 00 CLKOUT Peak-Peak Jitter Generation FEC[1:0] = 01, 10 Jitter Transfer Bandwidth (see Figure 10) Wander/Jitter Transfer Peaking Wander/Jitter at 3200 Hz Bandwidth (BWSEL[1:0] = 01 and DBLBW = 1) JGEN(RMS) JGEN(RMS) JGEN(PP) JGEN(PP) FBW JP 12 kHz to 20 MHz 50 kHz to 80 MHz 12 kHz to 20 MHz 50 kHz to 80 MHz 12 kHz to 20 MHz 50 kHz to 80 MHz 12 kHz to 20 MHz 50 kHz to 80 MHz BW = 1600 Hz < 1600 Hz Jitter Tolerance (see Figure 7) f = 32 Hz f = 320 Hz f = 3200 Hz 500 50 5 — — — — — 0.72 0.24 — — — 0.9 0.3 ns ns ns ps ps CLKOUT RMS Jitter Generation FEC[1:0] = 00 JGEN(RMS) 12 kHz to 20 MHz 50 kHz to 80 MHz Notes: 1. Higher PLL bandwidth settings provide smaller clock output wander with temperature gradient. 2. For reliable device operation, temperature gradients should be limited to 10 °C/min. 3. Telcordia GR-1244-CORE requirements specify maximum phase transient slope during clock rearrangement in terms of nanoseconds per millisecond. The equivalent ps/µs unit is used here since the maximum phase transient magnitude for the Si5320 (tPT_MTIE) never reaches one nanosecond. 10 Rev. 2.3 S i5320 Table 4. AC Characteristics (PLL Performance Characteristics) (Continued) (VDD33 = 3.3 V ±5%, TA = –20 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit CLKOUT Peak-Peak Jitter Generation FEC[1:0] = 00 Jitter Transfer Bandwidth (see Figure 6) Wander/Jitter Transfer Peaking Wander/Jitter at 3200 Hz Bandwidth (BWSEL[1:0] = 00 and DBLBW = 0) JGEN(PP) FBW JP 12 kHz to 20 MHz 50 kHz to 80 MHz BW = 3200 Hz < 3200 Hz — — — — 6.8 3.7 3200 0.05 10.0 5.0 — 0.1 ps ps Hz dB Jitter Tolerance (see Figure 7) JTOL(PP) f = 32 Hz f = 320 Hz f = 3200 Hz 1000 100 10 — — — — — — — — — — — — — 0.86 0.29 0.79 0.28 7.7 3.9 7.2 4.0 3200 0.05 — — — 1.2 0.4 1.2 0.4 10.0 5.0 10.0 5.0 — 0.1 ns ns ns ps ps ps ps ps ps ps ps Hz dB CLKOUT RMS Jitter Generation FEC[1:0] = 00 CLKOUT RMS Jitter Generation FEC[1:0] = 01, 10 CLKOUT Peak-Peak Jitter Generation FEC[1:0] = 00 CLKOUT Peak-Peak Jitter Generation FEC[1:0] = 01, 10 Jitter Transfer Bandwidth (see Figure 6) Wander/Jitter Transfer Peaking Wander/Jitter at 6400 Hz Bandwidth (BWSEL[1:0] = 00 and DBLBW = 1) JGEN(RMS) JGEN(RMS) JGEN(PP) JGEN(PP) FBW JP 12 kHz to 20 MHz 50 kHz to 80 MHz 12 kHz to 20 MHz 50 kHz to 80 MHz 12 kHz to 20 MHz 50 kHz to 80 MHz 12 kHz to 20 MHz 50 kHz to 80 MHz BW = 3200 Hz < 3200 Hz Jitter Tolerance (see Figure 7) f = 64 Hz f = 640 Hz f = 6400 Hz 500 50 5 — — — — — — — 0.7 0.25 6.6 3.8 — — — 1.0 0.3 9.0 5.0 ns ns ns ps ps ps ps CLKOUT RMS Jitter Generation FEC[1:0] = 00 CLKOUT Peak-Peak Jitter Generation FEC[1:0] = 00 JGEN(RMS) JGEN(PP) 12 kHz to 20 MHz 50 kHz to 80 MHz 12 kHz to 20 MHz 50 kHz to 80 MHz Notes: 1. Higher PLL bandwidth settings provide smaller clock output wander with temperature gradient. 2. For reliable device operation, temperature gradients should be limited to 10 °C/min. 3. Telcordia GR-1244-CORE requirements specify maximum phase transient slope during clock rearrangement in terms of nanoseconds per millisecond. The equivalent ps/µs unit is used here since the maximum phase transient magnitude for the Si5320 (tPT_MTIE) never reaches one nanosecond. Rev. 2.3 11 S i5320 Table 4. AC Characteristics (PLL Performance Characteristics) (Continued) (VDD33 = 3.3 V ±5%, TA = –20 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit Jitter Transfer Bandwidth (see Figure 6) Wander/Jitter Transfer Peaking Wander/Jitter at 6400 Hz Bandwidth (BWSEL[1:0] = 11 and DBLBW = 0) FBW JP BW = 6400 Hz < 6400 Hz — — 6400 0.05 — 0.1 Hz dB Jitter Tolerance (see Figure 7) (1/1 Scaling) JTOL(PP) f = 64 Hz f = 640 Hz f = 6400 Hz 1000 100 10 — — — — — — — — — — — — — 1.0 0.38 0.94 0.41 9.4 4.7 8.3 4.6 6400 0.05 — — — 1.4 0.5 1.4 0.6 12.0 5.5 12.0 5.5 — 0.1 ns ns ns ps ps ps ps ps ps ps ps Hz dB CLKOUT RMS Jitter Generation FEC[1:0] = 00 (1/1 Scaling) CLKOUT RMS Jitter Generation FEC[1:0] = 01, 10 (255/238, 238/255 scaling) CLKOUT Peak-Peak Jitter Generation FEC[1:0] = 00 (1/1 Scaling) CLKOUT Peak-Peak Jitter Generation FEC[1:0] = 01, 10 (255/238, 238/255 scaling) Jitter Transfer Bandwidth (see Figure 6) Wander/Jitter Transfer Peaking Wander/Jitter at 12800 Hz Bandwidth (BWSEL[1:0] = 11 and DBLBW = 1) JGEN(RMS) JGEN(RMS) JGEN(PP) JGEN(PP) FBW JP 12 kHz to 20 MHz 50 kHz to 80 MHz 12 kHz to 20 MHz 50 kHz to 80 MHz 12 kHz to 20 MHz 50 kHz to 80 MHz 12 kHz to 20 MHz 50 kHz to 80 MHz BW = 6400 Hz < 6400 Hz Jitter Tolerance (see Figure 7) f = 128 Hz f = 1280 Hz f = 12800 Hz 500 50 5 — — — — — — — — — 0.74 0.30 6.9 4.0 12800 0.05 — — — 1.0 0.4 9.0 5.0 — 0.1 ns ns ns ps ps ps ps Hz dB CLKOUT RMS Jitter Generation FEC[1:0] = 00 (1/1 Scaling) CLKOUT Peak-Peak Jitter Generation FEC[1:0] = 00 (1/1 Scaling) Jitter Transfer Bandwidth (see Figure 6) Wander/Jitter Transfer Peaking JGEN(RMS) JGEN(PP) FBW JP 12 kHz to 20 MHz 50 kHz to 80 MHz 12 kHz to 20 MHz 50 kHz to 80 MHz BW = 12,800 Hz < 12,800 Hz Notes: 1. Higher PLL bandwidth settings provide smaller clock output wander with temperature gradient. 2. For reliable device operation, temperature gradients should be limited to 10 °C/min. 3. Telcordia GR-1244-CORE requirements specify maximum phase transient slope during clock rearrangement in terms of nanoseconds per millisecond. The equivalent ps/µs unit is used here since the maximum phase transient magnitude for the Si5320 (tPT_MTIE) never reaches one nanosecond. 12 Rev. 2.3 S i5320 Table 4. AC Characteristics (PLL Performance Characteristics) (Continued) (VDD33 = 3.3 V ±5%, TA = –20 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit Acquisition Time TAQ RSTN/CAL high to CAL_ACTV low, with valid clock input and VALTIME = 0 Stable Input Clock; Temperature Gradient