SSD1858Z

TABLE OF CONTENTS 1 2 3 4 5 6 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.10 6.11 6.12 6.13 6.14 6.15 6.16 6.17 6.18 GENERAL DESCRIPTION................................................................................................................. 1 FEATURES ........................................................................................................................................ 2 ORDERING INFORMATION .............................................................................................................. 2 BLOCK DIAGRAM ............................................................................................................................. 3 DIE ARRANGEMENT ........................................................................................................................ 4 PIN DESCRIPTION ............................................................................................................................ 9 RES#............................................................................................................................................ 9 PS0 .............................................................................................................................................. 9 PS1 .............................................................................................................................................. 9 CS# .............................................................................................................................................. 9 D/C#............................................................................................................................................. 9 R/W(WR#).................................................................................................................................... 9 E(RD#) ......................................................................................................................................... 9 D0 -D7 ........................................................................................................................................... 9 VDD ............................................................................................................................................... 9 RVSS ........................................................................................................................................... 10 CVSS ........................................................................................................................................... 10 VSS ............................................................................................................................................. 10 VCI .............................................................................................................................................. 10 Vout ............................................................................................................................................. 10 VL5, VL4, VL3 and VL2 ................................................................................................................... 10 COM0 – COM63 ........................................................................................................................ 10 ICONS........................................................................................................................................ 10 COL0 – COL103........................................................................................................................ 10 i 6.19 6.20 6.21 6.22 6.23 6.24 6.25 6.26 6.27 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 CL .............................................................................................................................................. 10 M ................................................................................................................................................ 11 MID0~MID2................................................................................................................................ 11 SYNC ......................................................................................................................................... 11 MODE ........................................................................................................................................ 11 TEST_IN0~1 .............................................................................................................................. 11 TEST0~14.................................................................................................................................. 11 N/C............................................................................................................................................. 11 Dummy...................................................................................................................................... 11 FUNCTIONAL BLOCK DESCRIPTIONS ........................................................................................ 12 Command Decoder and Command Interface........................................................................ 12 MPU Parallel 6800-series Interface ........................................................................................ 12 MPU Parallel 8080-series Interface ........................................................................................ 12 MPU Serial 4-wire Interface..................................................................................................... 13 MPU Serial 3-wire interface..................................................................................................... 13 Graphic Display Data RAM (GDDRAM).................................................................................. 13 Oscillator Circuit ...................................................................................................................... 13 LCD Driving Voltage Generator and Regulator .................................................................... 14 169 Bit Latch ............................................................................................................................ 14 Level selector ........................................................................................................................... 14 HV Buffer Cell (Level Shifter).................................................................................................. 14 Default Setting after Reset...................................................................................................... 15 LCD Panel Driving Waveform ................................................................................................. 16 COMMAND TABLE .................................................................................................................................... 20 7.14 7.15 8 Read Status Byte ..................................................................................................................... 25 Data Read / Write ..................................................................................................................... 25 COMMAND DESCRIPTIONS .......................................................................................................... 26 ii 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.10 8.11 8.12 8.13 8.14 8.15 8.16 8.17 8.18 8.19 8.20 8.21 8.22 8.23 8.24 8.25 8.26 8.27 8.28 Set Display On/Off ................................................................................................................... 26 Set Display Start Line.............................................................................................................. 26 Set Page Address .................................................................................................................... 26 Set Higher Column Address ................................................................................................... 26 Set Lower Column Address.................................................................................................... 26 Set Temperature Coefficient (TC) Value................................................................................ 26 Set Segment Re-map............................................................................................................... 26 Set Normal/Reverse Display ................................................................................................... 26 Set Entire Display On/Off ........................................................................................................ 26 Set LCD Bias ............................................................................................................................ 26 Software Reset ......................................................................................................................... 27 Set COM Output Scan Direction............................................................................................. 27 Set Power Control Register .................................................................................................... 27 Set Internal Regulator Resistors Ratio.................................................................................. 27 Set Contrast Control Register ................................................................................................ 28 Set frame frequency ................................................................................................................ 29 Set Multiplex Ratio................................................................................................................... 29 Set Power Save Mode.............................................................................................................. 29 Exit Power Save Mode............................................................................................................. 29 Set N-line Inversion ................................................................................................................. 29 Exit N-line Inversion ................................................................................................................ 29 Set DC-DC Converter Factor................................................................................................... 29 Set Icon Enable ........................................................................................................................ 29 Start Internal Oscillator ........................................................................................................... 29 Set Display Data Length.......................................................................................................... 29 Set Test Mode .......................................................................................................................... 29 Status register Read................................................................................................................ 30 Set Gray Scale Mode (White/Light Gray/Dark Gray/Black).................................................. 30 iii 8.29 Set PWM and FRC.................................................................................................................... 30 EXTENDED COMMANDS..................................................................................................................... 30 8.30 8.31 9 10 11 12 OTP setting and programming ............................................................................................... 31 Enable External Oscillator Input ............................................................................................ 33 M AXIMUM RATINGS ....................................................................................................................... 34 DC CHARACTERISTICS ................................................................................................................. 35 AC CHARACTERISTICS ................................................................................................................. 37 APPLICATION EXAMPLES ............................................................................................................ 44 iv TABLE OF FIGURES Figure 1 - Block Diagram .............................................................................................................................. 3 Figure 2 – SSD1858 Pin Assignment ........................................................................................................... 4 Figure 3 – Display Data Read with the insertion of Dummy Read.............................................................. 12 Figure 4 - Oscillator Circuitry....................................................................................................................... 13 Figure 5 - SSD1858 Graphic Display Data RAM (GDDRAM) Address Map (with vertical scroll value 30H & MODE=L) ............................................................................................................................................. 17 Figure 6 - SSD1858 Graphic Display Data RAM (GDDRAM) Address Map (with vertical scroll value 30H & MODE=H) ............................................................................................................................................ 18 Figure 7 - LCD Display Example “0” ........................................................................................................... 19 Figure 8 - LCD Driving Signal from SSD1858............................................................................................. 19 o Figure 9 - Contrast Control Voltage Range Curve (TC=-0.14%/ C; VDD=2.775V; VCI=3.5V) ..................... 28 Figure 10 - Contrast Control Flow ............................................................................................................... 28 Figure 11 - OTP programming circuitry....................................................................................................... 31 Figure 12 - Flow chart of OTP program ...................................................................................................... 32 o Figure 13 - Frame Frequency at different VDD( Temp = 25 C).................................................................. 37 Figure 14 – Parallel 6800-series Interface Timing Characteristics (PS0 = H, PS1 = H)............................. 38 Figure 15 - Parallel 6800-series Interface Timing Characteristics (PS0 = H, PS1 = H) ............................. 39 Figure 16 - Parallel 8080-series Interface Timing Characteristics (PS0 = H, PS1 = L) .............................. 40 Figure 17 - Parallel 8080-series Interface Timing Characteristics (PS0 = H, PS1 = L) .............................. 41 Figure 18- Serial Timing Characteristics (PS0 = L) .................................................................................... 42 Figure 19 - Serial Timing Characteristics (PS0 = L) ................................................................................... 43 LIST OF TABLE Table 1 - Ordering Information ...................................................................................................................... 2 Table 2 - SSD1858 Series Die Pad Coordinates .......................................................................................... 5 Table 3 - PS0 & PS1 Interface ...................................................................................................................... 9 Table 4 - Vout > VL5 > VL4 > VL3 > VL2 > VSS Relationship ............................................................................ 10 Table 5 – Mode setting................................................................................................................................ 11 Table 6 -Modes of Operation ...................................................................................................................... 13 Table 7 - COMMAND TABLE...................................................................................................................... 20 Table 8 – Extended Command Table ......................................................................................................... 24 Table 9 - Read Status Byte ......................................................................................................................... 25 Table 10 - Address Increment Table........................................................................................................... 25 Table 11 - Commands Required for R/W (WR#) Actions on RAM ............................................................. 25 Table 12 - Maximum Ratings (Voltage Referenced to VSS) ........................................................................ 34 Table 13 - DC Characteristics (Unless otherwise specified, Voltage Referenced to VSS, VDD = 1.8 to 3.3V, TA = -40 to 85°C).................................................................................................................................. 35 Table 14 - AC Characteristics (Unless otherwise specified, Voltage Referenced to VSS, VDD, VCI = 2.7V, TA = -40 to 85°C) ...................................................................................................................................... 37 Table 15 – Parallel Timing Characteristics (TA = -40 to 85°C, VDD = 1.8V, VSS =0V) ................................. 38 Table 16 – Parallel Timing Characteristics (TA = -40 to 85°C, VDD = 2.7, VSS =0V).................................... 39 Table 17 - Parallel Timing Characteristics (TA = -40 to 85°C, VDD = 1.8V, VSS =0V) .................................. 40 Table 18 - Parallel Timing Characteristics (TA = -40 to 85°C, VDD = 2.7V, VSS =0V) .................................. 41 Table 19 – Serial Timing Characteristics (TA = -40 to 85°C, VDD = 2.7V, VSS =0V) .................................... 42 Table 20 – Serial Timing Characteristics (TA = -40 to 85°C, VDD = 1.8V, VSS =0V) .................................... 43 v SOLOMON SOLOMON SYSTECH LIMITED SEMICONDUCTOR TECHNICAL DATA SSD1858 Advanced Information LCD Segment / Common Driver with Controller CMOS 1 General Description SSD1858 is a single-chip CMOS 4 gray scale LCD driver with controller for liquid crystal dot-matrix graphic display system. SSD1858 consists of 169 high voltage driving output pins for driving maximum 104 Segments, 64 Commons and 1 icon driving Commons. SSD1858 supports two display modes 96x65 or 104x65 by pin select. SSD1858 displays data directly from its internal 104x65x2 bits Graphic Display Data RAM (GDDRAM). Data/Commands are sent from general MCU through a hardware selectable 6800-/8080series compatible Parallel Interface or 3/4 wires Serial Peripheral Interface. SSD1858 embeds a DC-DC Converter, a LCD Voltage Regulator, an On-Chip Bias Divider, integrated bias capacitors, integrated booster capacitors and an On-Chip oscillator which reduce the number of external components. With the special design on minimizing power consumption and die/package layout, SSD1858 is suitable for any portable battery-driven applications requiring a long operation period and a compact size. This document contains information on a new product. Specifications and information herein are subject to change without notice. Copyright  2002 SOLOMON Systech Limited Rev 1.1 09/2002 2 FEATURES 104x64 4 gray scale levels Graphic Display with an Icon Line Programmable Multiplex ratio (partial display) [16Mux - 65Mux] Single Supply Operation, 1.8 V - 3.3V Low Current Sleep Mode ( VL5 > VL4 > VL3 > VL2 > VSS Table 4 - Vout > VL5 > VL4 > VL3 > VL2 > VSS Relationship 1 : a bias VL5 VL4 VL3 (a-1)/a * Vout (a-2)/a * Vout 2/a * Vout VL2 1/a * Vout a is equals to 9 at POR. 6.16 COM0 – COM63 These pins provide the row driving signal COM0 - COM63 to the LCD panel. See figure 5 and figure 6 about the COM signal mapping in different multiplex ratio N. 6.17 ICONS This pin is the special icons line COM signal output. 6.18 COL0 – COL103 These pins provide the LCD column driving signal. Their voltage level is VSS during sleep mode. 6.19 CL This pin is the external clock input for the device which is enabled by using an extended command. Under normal operation, this pin should be left opened and internal oscillator will be used after power on reset. SSD1858 Rev 1.1 09/2002 SOLOMON 10 6.20 M This pin is used for cascade purpose only. Under normal operation, it should be left open. 6.21 MID0~MID2 These pins are used for setting the ID code of LCD panel manufacturer. These pins should be connected to VSS or VDD when NOT IN USE. 6.22 SYNC This pin is used for cascade purpose only. Under normal operation, it should be left open. 6.23 MODE This pin is used for setting the display size. Table 5 – Mode setting MODE H L Remarks: SSD1858 96x65 display mode SSD1858 104x65 display mode 6.24 TEST_IN0~1 These pins is used for internal only and should be connected to Vss. 6.25 TEST0~14 These pins is used for internal only and should be left open, any connection is not allowed. 6.26 N/C These No Connection pins should NOT be connected to any signal pins nor shorted together. They should be left open. 6.27 Dummy There are the floating dummy pads without any internal circuitry connection. 11 SSD1858 Rev 1.1 09/2002 SOLOMON 7 7.1 FUNCTIONAL BLOCK DESCRIPTIONS Command Decoder and Command Interface This module determines whether the input data is interpreted as data or command. Data is directed to this module based upon the input of the D/C# pin. If D/C# is high, data is written to Graphic Display Data RAM (GDDRAM). If D/C# is low, the input at D0 -D7 is interpreted as a command and it will be decoded and written to the corresponding command register. Reset is of the same function as Power ON Reset (POR). Once RES# receives a negative reset pulse of about 1us, all internal circuitry will be back to its initial status. Refer to Command Description section for more information. 7.2 MPU Parallel 6800-series Interface The parallel interface consists of 8 bi-directional data pins (D0 - D7), R/W(WR#), D/C#, E(RD#) and CS#. R/W(WR#) input High indicates a read operation from the Graphic Display Data RAM (GDDRAM) or the status register. R/W(WR#) input Low indicates a write operation to Display Data RAM or Internal Command Registers depending on the status of RS input. The E(RD#) and CS# input serves as data latch signal (clock) when they are high and low respectively. Refer to Figure 14 of parallel timing characteristics for Parallel Interface Timing Diagram of 6800-series microprocessors. In order to match the operating frequency of display RAM with that of the microprocessor, some pipeline processing is internally performed which requires the insertion of a dummy read before the first actual display data read. This is shown in Figure 3 below. R/W (WR) E(RD ) data bus N writ e column address dummy read n data read1 n+1 data read 2 n+2 data read 3 Figure 3 – Display Data Read with the insertion of Dummy Read 7.3 MPU Parallel 8080-series Interface The parallel interface consists of 8 bi-directional data pins (D0 - D7), R/W(WR#), E(RD#), D/C# and CS#. The CS# input serves as data latch signal (clock) when it is low. Whether it is display data or status register read is controlled by D/C#. R/W(WR#) and E(RD#) input indicates a write or read cycle when CS# is low. Refer to Figure 16 of parallel timing characteristics for Parallel Interface Timing Diagram of 8080-series microprocessor. Similar to 6800-series interface, a dummy read is also required before the first actual display data read. SSD1858 Rev 1.1 09/2002 SOLOMON 12 7.4 MPU Serial 4-wire Interface The serial interface consists of serial clock SCK, serial data SDA, D/C# and CS#. SDA is shifted into an 8-bit shift register on every rising edge of SCL in the order of D7, D6, ... D0. D/C# is sampled on every eighth clock and the data byte in the shift register is written to the Display Data RAM or command register in the same clock. No extra clock or command is required to end the transmission. 7.5 MPU Serial 3-wire interface Operation is similar to 4-wire serial interface while D/C# is not been used. The Display Data Length instruction is used to indicate that a specified number display data byte(s) (1-256) are to be transmitted. Next byte after the display data string is handled as a command. It should be noted that if there is a signal glitch at SCK that causing an out of synchronization in the serial communication, a hardware reset pulse at RES# pin is required to initialize the chip for re-synchronization. Table 6 -Modes of Operation 6800 Parallel Data Read Data Write Yes Yes 8080 Parallel Yes Yes Status only Yes No Yes No Yes Serial Command Read Status only Command Write Yes 7.6 Graphic Display Data RAM (GDDRAM) The GDDRAM is a bit mapped static RAM holding the bit pattern to be displayed. The size of the RAM is 104 x 65 x 2 = 13,520bits. Figure 5 is a description of the GDDRAM address map. For mechanical flexibility, re-mapping on both Segment and Common outputs are provided. For vertical scrolling of display, an internal register storing the display start line can be set to control the portion of the RAM data mapped to the display. Figure 5 shows the case in which the display start line register is set at 30H. For those GDDRAM out of the display common range, they could still be accessed, for either preparation of vertical scrolling data or even for the system usage. 7.7 Oscillator Circuit This module is an On-Chip low power RC oscillator circuitry (Figure 4). The oscillator generates the clock for the DC-DC voltage converter. This clock is also used in the Display Timing Generator. Oscillator enable enable Oscillation Circuit enable Buffer (CL) Internal Resistor OSC1 OSC2 Figure 4 - Oscillator Circuitry 13 SSD1858 Rev 1.1 09/2002 SOLOMON 7.8 LCD Driving Voltage Generator and Regulator This module generates the LCD voltage needed for display output. It takes a single supply input and generates necessary bias voltages. It consists of: 1. 2X, 3X, 4X and 5X DC-DC voltage converter 2. Bias Divider If the output op-amp buffer option in Set Power Control Register command is enabled, this circuit block will divide the regulator output (Vout) to give the LCD driving levels (VL2 - VL5). The divider does not require external capacitors to reduce the external hardware and pin counts. 3. Contrast Control Software control of 64 voltage levels of LCD voltage. 4. Bias Ratio Selection circuitry Software control of 1/4 to 1/9 bias ratio to match the characteristic of LCD panel. 5. Self adjust temperature compensation circuitry Provide 5 different compensation grade selections to satisfy the various liquid crystal temperature grades. The grading can be selected by software control. Defaulted temperature coefficient (TC) value is -0.14%/°C. 7.9 169 Bit Latch A register carries the display signal information. In 104 X 65 display-mode, data will be fed to the HV-buffer Cell and level-shifted to the required level. 7.10 Level selector Level Selector is a control of the display synchronization. Display voltage can be separated into two sets and used with different cycles. Synchronization is important since it selects the required LCD voltage level to the HV Buffer Cell, which in turn outputs the COM or SEG LCD waveform. 7.11 HV Buffer Cell (Level Shifter) HV Buffer Cell works as a level shifter, which translated the low voltage output signal to the required driving voltage. The output is shifted out with an internal FRM clock, which comes from the Display Timing Generator. The voltage levels are given by the level selector, which is synchronized with the internal M signal. SSD1858 Rev 1.1 09/2002 SOLOMON 14 7.12 Default Setting after Reset W hen RES input is low, the chip is initialized to the following: Register Default Value Descriptions Page address 0 Column address 0 Display ON/OFF 0 Display OFF Display Start Line 0 GDDRAM page 0,D0 Display Offset 0 COM0 is mapped to ROW0 Mux Ratio 40H 64 Mux Normal/Reverse Display 0 Normal Display N-line Inversion 0 No N-line Inversion Entire Display 0 Entire Display is OFF DC-DC booster 0 3X booster is selected Internal Resistor Ratio 0 Gain = 2.84 (IR0) Contrast 20H LCD Bias Ratio 5 1/9 Bias Ratio Scan direction of COM 0 Normal Scan direction Segment Re-map 0 Segment re-map is disabled Internal oscillator 0 Internal oscillator is OFF Power save mode 0 Power save mode is OFF Data display length 0 FRC, PWM Mode 0 4FRC, 9PWM W hite Palette (0, 0, 0, 0) Light Gray Palette (9, 0, 0, 0) Dark Gray Palette (9, 9, 9, 0) Black Palette (9, 9, 9, 9) Test mode 0 Test mode is OFF o Temperature coefficient 4 PTC4 (-0.14%/ C) Icon display 0 Icon display line is OFF 8 Frame frequency = 157.5Hz (typical) Power control 0,0,0 Booster, regulator & divider are both disabled W hen RESET command is issued, the following parameters are initialized only: Register Default Value Descriptions Page address 0 Column address 0 Display Start Line 0 GDDRAM page 0,D0 Internal Resistor Ratio 0 Gain = 2.84 (IR0) Contrast 20H Data display length 0 FRC, PWM Mode 0 4FRC, 9PWM W hite Palette (0, 0, 0, 0) Light Gray Palette (9, 0, 0, 0) Dark Gray Palette (9, 9, 9, 0) Black Palette (9, 9, 9, 9) 15 SSD1858 Rev 1.1 09/2002 SOLOMON 7.13 LCD Panel Driving Waveform The following is an example of how the Common and Segment drivers may be connected to a LCD panel. The waveforms shown in Figure 7 and Figure 8 illustrate the desired multiplex scheme with N-line inversion feature is disabled (default). SSD1858 Rev 1.1 09/2002 SOLOMON 16 (MSB) First Byte Page Address D3 D2 D2 D0 D D D D D D D D D D D D D D D D 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 (LSB) Second Byte Normal ……….. ……….. ……….. ……….. ……….. ……….. ……….. ……….. ……….. ……….. ……….. ……….. ……….. ……….. ……….. ……….. Line Address 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 Remapped COM47 COM46 COM45 COM44 COM43 COM42 COM41 COM40 COM39 COM38 COM37 COM36 COM35 COM34 COM33 COM32 Page 0 0 0 0 0 Page 1 0 0 0 1 …………… …………… …………… …………… …………… …………… …………… Page 6 1 1 1 0 Page 7 1 1 1 1 Page 8 0 0 0 0 D D D D D D D D D D D D D D D D D 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 ……….. ……….. ……….. ……….. ……….. ……….. ……….. ……….. ……….. ……….. ……….. ……….. ……….. ……….. ……….. ……….. 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 4 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 ICONS COM63 COM62 COM61 COM60 COM59 COM58 COM57 COM56 COM55 COM54 COM53 COM52 COM51 COM50 COM49 COM48 ICONS CC CD CA CB CE Internal Column Address SEG Re-map = 0 SEG Re-map = 1 SEG Outputs 00 67 SEG0 01 66 SEG1 02 65 SEG2 03 64 SEG3 64 03 SEG100 65 02 SEG101 66 01 SEG102 67 00 SEG103 Figure 5 - SSD1858 Graphic Display Data RAM (GDDRAM) Address Map (with vertical scroll value 30H & MODE=L) 17 CF C8 C9 00 01 02 03 04 05 06 07 SSD1858 Rev 1.1 09/2002 SOLOMON …………… (MSB) First Byte Page Address D3 D2 D2 D0 D D D D D D D D D D D D D D D D 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 (LSB) Second Byte Normal ……….. ……….. ……….. ……….. ……….. ……….. ……….. ……….. ……….. ……….. ……….. ……….. ……….. ……….. ……….. ……….. Line Address 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 Remapped COM47 COM46 COM45 COM44 COM43 COM42 COM41 COM40 COM39 COM38 COM37 COM36 COM35 COM34 COM33 COM32 Page 0 0 0 0 0 Page 1 0 0 0 1 …………… …………… …………… …………… …………… …………… …………… Page 6 1 1 1 0 Page 7 1 1 1 1 Page 8 0 0 0 0 D D D D D D D D D D D D D D D D D 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 00 01 02 03 04 05 06 07 ……….. ……….. ……….. ……….. ……….. ……….. ……….. ……….. ……….. ……….. ……….. ……….. ……….. ……….. ……….. ……….. 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 4 BC BD BA BB BE BF B8 B9 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 ICONS COM63 COM62 COM61 COM60 COM59 COM58 COM57 COM56 COM55 COM54 COM53 COM52 COM51 COM50 COM49 COM48 ICONS Internal Column Address SEG Re-map = 0 SEG Re-map = 1 SEG Outputs 00 5F SEG0 01 5E SEG1 02 5D SEG2 03 5C SEG3 5C 03 SEG92 5D 02 SEG93 5E 01 SEG94 5F 00 SEG95 Figure 6 - SSD1858 Graphic Display Data RAM (GDDRAM) Address Map (with vertical scroll value 30H & MODE=H) …………… SSD1858 Rev 1.1 09/2002 SOLOMON 18 COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 SEG 0 SEG 1 SEG 2 SEG 3 SEG 4 Figure 7 - LCD Display Example “0” TIME SLOT 123456789 .. . * N1 2 3 4 5 6 7 8 9 . .. * N123456789 .. . * N1 2 3 4 5 6 7 8 9 .. . * N V o ut V L5 COM0 V L4 V L3 V L2 VS S V o ut V L5 COM1 V L4 V L3 V L2 VS S V o ut V L5 SEG0 V L4 V L3 V L2 VS S V o ut V L5 SEG1 V L4 V L3 V L2 VS S M * Note : N is the number of multiplex ratio including Icon line if it is enabled, N is equal to 64 on POR . Figure 8 - LCD Driving Signal from SSD1858 19 Rev 1.1 09/2002 SOLOMON SSD1858 COMMAND TABLE Table 7 - COMMAND TABLE Bit Pattern 0000 C3C2C1C0 0001 0C6C5C4 0010 0R2R1R0 Command Set Column LSB Set Column MSB Set Internal Resistor Ratio Description Set the lower nibble of the column address pointer for RAM access. The pointer is reset to 0 after reset. Set the upper nibble of the column address pointer for RAM access. The pointer is reset to 0 after reset. The internal regulator gain (1+R2/R1) Vout increases as R2R1R0 is increased from 000b to 111b. The factor, 1+R2/R1, is given by: R2R1R0 = 000: 2.84 (POR) R2R1R0 = 001: 3.71 R2R1R0 = 010: 4.57 R2R1R0 = 011: 5.44 R2R1R0 = 100: 6.30 R2R1R0 = 101: 7.16 R2R1R0 = 110: 8.03 R2R1R0 = 111: 8.89 (Refer to 8.14) VC=0: turn OFF the internal voltage booster (POR) VC=1: turn ON the internal voltage booster & regulator VR=0: turn OFF the internal regulator (POR) VR=1: turn ON the internal regulator & voltage booster VF=0: turn OFF the output op-amp buffer (POR) VF=1: turn ON the output op-amp buffer This command set the Temperature Coefficient T2T1T0: o 000: -0.01%/ C o 001: -0.035%/ C o 010: -0.05%/ C o 011: -0.083%/ C o 100: -0.14%/ C(POR) The second command specifies the row address pointer (0-63) of the RAM data to be displayed in COM0. This command has no effect on ICONS. The pointer is set to 0 after reset. The second command specifies the mapping of first display line (COM0) to one of ROW0~63. This command has no effect on ICONS. COM0 is mapped to ROW0 after reset. 0010 1VC VR VF Set Voltage Control 0011 1T2T1T0 Set TC value 0100 00XX XL6L5L4 L3L2L1L0 0100 01XX XXC5C4 C3C2C1C0 Set Initial Display Line Set Initial COM0 SSD1858 Rev 1.1 09/2002 SOLOMON 20 Bit Pattern 0100 10XX XD6D5D4 D3D2D1D0 Command Set Multiplex Ratio 0100 11XX XXXN4 N3N2N1N0 Set N-line Inversion 0101 0B2B1B0 Set LCD Bias 0110 01B1B0 Set Boost Level 1000 0001 XXC5C4 C3C2C1C0 Set Contrast Level Description The second command specifies the number of lines, excluding ICONS, to be displayed. With Icon is disabled (POR), 16~64 Mux could be selected. With Icon enabled, the available Mux are 17~ 65. Mux(icon disable) Mux(icon enable) D6 – D0 000000 invalid invalid … 0001111 invalid invalid 0010000 16 17 0010001 17 18 … 1000000 64 65 1000001 invalid invalid 1000010 invalid invalid … 1111111 invalid invalid The second command sets the n-line inversion register from 3 to 33 lines to reduce display crosstalk. Register values from 00001b to 11111b are mapped to 3 lines to 33 lines respectively. Value 00000b disables the N-line inversion, which is the POR value. To avoid a fix polarity at some lines, it should be noted that the total number of Mux (including the icon line) should NOT be a multiple of the lines of inversion (n). n-line inversion N4 – N0 00000 Exit n-line inversion 00001 3 lines 00010 4 lines … 11101 31 lines 11110 32 lines 11111 33 lines Sets the LCD bias from 1/4 ~ 1/9 according to B2B1B0: 000: 1/4 bias 001: 1/5 bias 010: 1/6 bias 011: 1/7 bias 100: 1/8 bias 101: 1/9 bias (POR) 110: 1/9 bias 111: 1/9 bias Set the DC-DC multiplying factor from 2X to 5X B1B0: 00: 3X (POR) 01: 4X 10: 5X 11: 2X The second command sets one of the 64 contrast levels. The darkness increase as the contrast level increase. 21 SSD1858 Rev 1.1 09/2002 SOLOMON 1000 1000 W B3WB2WB1WB0 W A3WA2WA1WA0 1000 1001 W D3WD2WD1WD0 W C3WC2WC1WC0 1000 1010 LB3LB2LB1LB0 LA3LA2LA1LA0 1000 1011 LD3LD2LD1LD0 LC3LC2LC1LC0 1000 1100 DB3DB2DB1DB0 DA3DA2DA1DA0 1000 1101 DD3DD2DD1DD0 DC3DC2DC1DC0 1000 1110 BB3BB2BB1BB0 BA3BA2BA1BA0 1000 1111 BD3BD2BD1BD0 BC3BC2BC1BC0 Set White Mode, nd st Frame 2 & 1 Set White Mode, th rd Frame 4 & 3 Set Light Gray Mode, nd st Frame 2 & 1 Set Light Gray Mode, th rd Frame 4 & 3 Set Dark Gray Mode, nd st Frame 2 & 1 Set Dark Gray Mode, th rd Frame 4 & 3 Set Black Mode, nd st Frame 2 & 1 Set Black Mode, th rd Frame 4 & 3 Set gray scale mode and register. These are two-byte commands used to specify the contrast levels for the gray scale, 4 levels available. After power on reset: WA0~3 = WB0~3 = WC0~3 = WD0~3 = 0000 LA0~3 = 1001 LB0~3 = LC0~3 = LD0~3 = 0000 DA0~3 = DB0~3 = DC0~3 = 1001 DD0~3 = 0000 BA0~3 = BB0~3 = BC0~3 = BD0~3 = 1001 Memory Content 1 Byte 0 0 1 1 st 2 nd Byte 0 1 0 1 Gray Mode W hite Light Gray Dark Gray Black SSD1858 Rev 1.1 09/2002 SOLOMON 22 Bit Pattern 1001 0 FRC PWM1 PWM0 Command Set PWM and FRC 1010 000S0 Set Segment Re-map 1010 001C0 1010 010E0 Icon Control Register ON/OFF Entire Display Select 1010 011R0 Invert Display Select 1010 1001 Power Save Mode 1010 1011 1010 111D0 Start Internal Oscillator Display On/Off 1011 P3P2P1P0 1100 S0XXX 1110 0001 1110 0010 1110 0100 1110 1000 D7D6D5D4 D3D2D1D0 Set Page Address Set COM Scan Direction Exit Power-save Mode Reset Release N-line Inversion Mode Display Data Length Description Set PWM and FRC for gray-scale operation. FRC = 0 : 4-frame (POR) FRC = 1 : 3-frame PWM = 00 & 01 : 9-levels (POR) PWM = 10 : 12-levels PWM = 11 : 15-levels MODE=0 S0=0: column address 00H is mapped to SEG0 (POR) S0=1: column address 67H is mapped to SEG0 MODE=1 S0=0: column address 00H is mapped to SEG0 (POR) S0=1: column address 5FH is mapped to SEG0 C0=0: Disable icon row (Mux = 16 to 64, POR) C0=1: Enable icon row (Mux = 17 to 65) E0=0: Normal display (display according to RAM contents, POR) E0=1: All pixels are ON regardless of the RAM contents *Note: This command will override the effect of “Set Normal/Invert Display” R0=0: Normal display (display according to RAM contents, POR) R0=1: Invert display (ON and OFF pixels are inverted) *Note: This command will not affect the display of the icon lines Sleep Mode: Oscillator: OFF LCD Power Supply: OFF COM/SEG Outputs: VSS This command starts the internal oscillator. Note that the oscillator is OFF after reset, so this instruction must be executed for initialization Turn the display on and off without modifying the content of the RAM. (0: off, 1: on) This command has priority over Entire Display On/Off and Invert Display On/Off. Commands are accepted while the display is off, but the visual state of the display does not change. Select the page of display RAM to be addressed. Pages 0-8 are valid. Set the COM (row) scanning direction. (0: COM0 →COM63, 1: COM63 →COM0) Return the driver/controller from the sleep mode. Reset some functions of the driver/controller. See Reset Section below for more details. Release the driver/controller from N-line inversion mode. This command is used in 3-line SPI mode (without RS line) to specify that the controller is about to send display data to the display RAM. Eight bits are used to specify the number of bytes to be sent (1 to 256 bytes). The second command received after the display data is transmitted is assumed to be command data. 23 SSD1858 Rev 1.1 09/2002 SOLOMON Bit Pattern 1101 1F2F1F0 Command Set Frame Frequency Description This command is used to set the frame frequency. F2F1F0 Frame Frequency (typical) 000 70 001 78.5 010 88.5 011 100 100 115 101 130 110 140 111 157.5(POR) Table 8 – Extended Command Table Bit Pattern 1000 0010 0001X3X2X1X0 Comment Set the desired Vout voltage value: 0000: original contrast 0001: original contrast +1 step 0010: original contrast +2 steps 0011: original contrast +3 steps 0100: original contrast +4 steps 0101: original contrast +5 steps 0110: original contrast +6 steps 0111: original contrast +7 steps 1000: original contrast -8 steps 1001: original contrast -7 steps 1010: original contrast -6 steps 1011: original contrast -5 steps 1100: original contrast -4 steps 1101: original contrast -3 steps 1110: original contrast -2 steps 1111: original contrast -1 step OTP programming This command start program LCD driver with OTP offset value. This command only execute once. No effect on the second run. Detail of OTP programming procedure on P.31 Enable external oscillator input Select external oscillator input form CL pin. X0 = 0 : (POR) internal RC oscillator X0 = 1 : external square wave Reserved Command OTP setting 1000 0011 1111 0010 000X0 0000 Other than above SSD1858 Rev 1.1 09/2002 SOLOMON 24 7.14 Read Status Byte An 8 bits status byte will be placed to the data bus if a read operation is performed if D/C# is low. The status byte is defined as follow. Table 9 - Read Status Byte Bit Pattern Command BUSY ON RES# MF2 Read Status MF1 MF0 DS1 DS0 Comment BUSY=0: Chip is idle BUSY=1: Chip is executing instruction ON=0: Display is OFF ON=1: Display is ON RES#=0: Chip is idle RES#=1: Chip is executing reset MF2-MF0: Manufacturer device ID DS1,DS0 : 0 0 : 64-row driver 0 1 : 80-row driver 1 0 : 128-row,4 G/S driver 7.15 Data Read / Write To read data from the GDDRAM, input High to R/W(WR#) pin and D/C# pin for 6800-series parallel mode. Low to E(RD#) pin and High to RS pin for 8080-series parallel mode. No data read is provided for serial mode. In normal mode, GDDRAM column address pointer will be increased by one automatically after each data read. Also, a dummy read is required before the first data is read. See Figure 3 in Functional Description. To write data to the GDDRAM, input Low to R/W(WR#) pin and High to D/C# pin for 6800-series parallel mode. For serial interface, it will always be in write mode. GDDRAM column address pointer will be increased by one automatically after each data write. The address will be reset to 0 in next data read/write operation is executed when it is 95. Remarks: Only read data on Page 0 to Page 7 of the GDDRAM. The data on Icon page (page 8) cannot be read. Table 10 - Address Increment Table RS 0 0 1 1 R/W (WR) 0 1 0 1 Comment W rite Command Read Status W rite Data Read Data Address Increment No No Yes Yes Address Increment is done automatically after data read/write. The column address pointer of GDDRAM is also affected. It will be reset to 0 in next data read/write operation is executed when it is 95. Table 11 - Commands Required for R/W (WR#) Actions on RAM R/W (WR) Actions on RAMs Read/write Data from/to GDDRAM Commands Required Set GDDRAM Page Address Set GDDRAM Column Address Read/Write Data (1011X3X2X1X0)* (0001X3X2X1X0)* (0000X3X2X1X0)* (X7X6X5X4X3X2X1X0) * No need to resend the command again if it is set previously. The read / write action to the Display Data RAM does not depend on the display mode. This means the user can change the RAM content whether the target RAM content is being displayed or not. 25 SSD1858 Rev 1.1 09/2002 SOLOMON 8 8.1 COMMAND DESCRIPTIONS Set Display On/Off This command turns the display on/off, by the value of the LSB. 8.2 Set Display Start Line This command is to set Display Start Line register to deter-mine starting address of display RAM to be displayed by selecting a value from 0 to 63. With value equals to 0, D0 of Page 0 is mapped to COM0. With value equals to 1, D1 of Page0 is mapped to COM0. The display start line values of 0 to 63 are assigned to Page 0 to 7. 8.3 Set Page Address This command positions the page address to 0 to 8 possible positions in GDDRAM. Refer to Figure 5. 8.4 Set Higher Column Address This command specifies the higher nibble of the 7-bit column address of the display data RAM. The column address will be incremented by each data access after it is pre-set by the MCU and returning to 0 once overflow (>95 when MODE=1 OR >103 when MODE=0). 8.5 Set Lower Column Address This command specifies the lower nibble of the 7-bit column address of the display data RAM. The column address will be incremented by each data access after it is pre-set by the MCU and returning to 0 once overflow (>95 when MODE=1 OR >103 when MODE=0). 8.6 Set Temperature Coefficient (TC) Value This command is to set 1 out of 5 different temperature coefficients in order to match various liquid crystal temperature grades (-0.14% / °C – POR). 8.7 Set Segment Re-map This commands changes the mapping between the display data column address and segment driver. It allows flexibility in layout during LCD module assembly. Refer to Figure 5. 8.8 Set Normal/Reverse Display This command sets the display to be either normal/reverse. In normal display, a RAM data of 1 indicates an “ON” pixel while in reverse display; a RAM data of 0 indicates an “ON” pixel. The icon line is not affected by this command. 8.9 Set Entire Display On/Off This command forces the entire display, including the icon row, to be “ON” regardless of the contents of the display data RAM. This command has priority over normal/reverse display. To execute this command, Set Display On command must be sent in advance. 8.10 Set LCD Bias This command selects a suitable bias ratio (1/4 to 1/9) required for driving the particular LCD panel in use. The POR is set to 1/9 bias. 26 SSD1858 Rev 1.1 09/2002 SOLOMON 8.11 Software Reset This command causes some of the internal status of the chip to be initialized: Register Default Value Descriptions Page address 0 Column address 0 Display Start Line 0 GDDRAM page 0,D0 Internal Resistor Ratio 0 Gain = 2.84(IR0) Contrast 20H Data display length 0 FRC, PWM Mode 0 4FRC, 9PWM W hite Palette (0, 0, 0, 0) Light Gray Palette (9, 0, 0, 0) Dark Gray Palette (9, 9, 9, 0) Black Palette (9, 9, 9, 9) 8.12 Set COM Output Scan Direction This command sets the scan direction of the COM output allowing layout flexibility in LCD module assembly. 8.13 Set Power Control Register This command turns on/off the various power circuits associated with the chip. There are three power relating sub-circuits could be turned on/off by this command. Internal voltage booster is used to generate the highest positive voltage supply internally from the voltage input (VCI -VSS). Internal regulator is used to generate the LCD driving volt-age. Vout, from the booster output (internal use only). Output op-amp buffer is the internal divider for dividing the different voltage levels (VL2, VL3, VL4, VL5) from the internal regulator output, Vout. External voltage sources should be fed into this driver if this circuit is turned off. 8.14 Set Internal Regulator Resistors Ratio This command is to enable any one of the eight internal resistor (IRS) settings for different regulator gains when using internal regulator resistor network. The Contrast Control Voltage Range curves is referred to the following formula:  R Vout = 1 + 2  *Vcon  R 1   63 − α  Vcon = 1 −  * Vref 210   , where Vref = 1.7V 27 SSD1858 Rev 1.1 09/2002 SOLOMON Contrast Cruve Vout[V] 16 14 12 10 8 6 4 2 Contrast[0~63] 0 10 20 30 40 50 60 70 IR0 IR1 IR2 IR3 IR4 IR5 IR6 IR7 Figure 9 - Contrast Control Voltage Range Curve (TC=-0.14%/ C; VDD=2.775V; VCI=3.5V) o 8.15 Set Contrast Control Register This command adjusts the contrast of the LCD panel by changing Vout of the LCD drive voltage provided by the On-Chip power circuits. Vout is set with 64 steps (6-bit) contrast control register. It is a compound commands: Set Contrast Control Register Contrast Level Data No Changes Complete? Yes Figure 10 - Contrast Control Flow SSD1858 Rev 1.1 09/2002 SOLOMON 28 8.16 Set frame frequency This command specifies the frame frequency so as to minimize the flickering due to the ac main frequency. The frequency is set to 157.5Hz (typical) at 64 Mux after POR. 8.17 Set Multiplex Ratio This command switches default 64 multiplex modes to any multiplex from 16 to 64, if Icon is disabled (POR). When Icon is set enable, the corresponding multiplex ratio setting will be mapped to 17 to 65. The chip pads ROW0-ROW63 will be switched to corresponding COM signal output as specified in Table 2. 8.18 Set Power Save Mode This command can force the chip to enter Standby or Sleep Mode. LSB of the command will define which mode will be entered. 8.19 Exit Power Save Mode This command releases the chip from Sleep Mode and return to normal operation. 8.20 Set N-line Inversion Number of line inversion is set by this command for reducing crosstalk noise. 3 to 33-line inversion operations could be selected. At POR, this operation is disabled. It should be noted that the total number of mux (including the icon line) should NOT be a multiple of the inversion number (n). Or else, some lines will not change their polarity during frame change. 8.21 Exit N-line Inversion This command releases the chip from N-line inversion mode. The driving waveform will be inverted once per frame after issuing this command. 8.22 Set DC-DC Converter Factor Internal DC-DC converter factor is set by this command. For SSD1858, 2X to 5X multiplying factors could be selected. 2X to 5X factors are selected using this command. 8.23 Set Icon Enable This command enable/disable the Icon display. 8.24 Start Internal Oscillator After POR, the internal oscillator is OFF. It should be turned ON by sending this command to the chip. 8.25 Set Display Data Length This two-bytes command only valid when 3-wire SPI configuration is set by H/W input (PS0=PS1=L). The second 8-bit is used to indicate that a specified number display data byte(s) (1-256) are to be transmitted. Next byte after the display data string is handled as a command. 8.26 Set Test Mode This command forces the driver chip into its test mode for internal testing of the chip. Under normal operation, user should NOT use this command. 29 SSD1858 Rev 1.1 09/2002 SOLOMON 8.27 Status register Read This command is issued by setting D/C# Low during a data read (refer to Figure 14 and Figure 16 parallel interface waveform). It allows the MCU to monitor the internal status of the chip. No status read is provided for serial mode. 8.28 Set Gray Scale Mode (White/Light Gray/Dark Gray/Black) Command 84(hex) to 8F(hex) are used to specify the four gray levels’ pulse width at the four possible frames. The four gray levels are called white, light gray, dark gray and black. Each level is defined by 4 registers for 4 consecutive frames. For example, WA is a 4-bit register to st nd define the pulse width of the 1 frame in White mode. WB is a register for 2 frame in White mode etc. Each command specifies two registers. For 4 FRC, Memory Content st nd 1 Byte 2 Byte 0 0 0 1 1 0 1 1 For 3 FRC, Memory Content st nd 1 Byte 2 Byte 0 0 0 1 1 0 1 1 Gray Mode FRAME 1 WA LA DA BA st Gray Mode FRAME 1 WA LA DA BA st W hite Light Gray Dark Gray Black 2 WB LB DB BB nd 3 WC LC DC BC rd 4 WD LD DD BD th W hite Light Gray Dark Gray Black 2 WB LB DB BB nd 3 WC LC DC BC rd 4 (No use) WD (XX) LD (XX) DC (XX) BC (XX) th 8.29 Set PWM and FRC This command selects the number of frames in frame rate control, or the number of levels in the pulse width modulation. EXTENDED COMMANDS These commands are used, in addition to basic commands, to trigger the enhanced features, on top of general ones, designed for the chip. SSD1858 Rev 1.1 09/2002 SOLOMON 30 8.30 OTP setting and programming OTP (One Time Programming) is a method to adjust Vout. In order to eliminate the variations of LCD module in term of contrast level, OTP can be used to achieve the best contrast of every LCD modules. OTP setting and programming should include two major steps of (1) Find the OTP offset and (2) OTP programming as following, Step 1. Find OTP offset (1) (2) (3) (4) (5) Hardware Reset (sending an active low reset pulse to RES# pin) Send original initialization routines Set and display any test patterns Adjust the contrast value (0x81, 0x00~0x3F) until there is the best visual contrast OTP setting steps = Contrast value of the best visual contrast - Contrast value of original initialization Example 1: Contrast value of original initialization = 0x20 Contrast value of the best visual contrast = 0x24 OTP setting steps = 0x24 - 0x20 = +4 OTP setting commands should be (0x82, 0x14) Example 2: Contrast value of original initialization = 0x20 Contrast value of the best visual contrast = 0x1B OTP setting steps = 0x1B - 0x20 = -5 OTP setting commands should be (0x82, 0x1B) Step 2. OTP programming (6) Hardware Reset (sending an active low reset pulse to RES# pin) (7) Enable Oscillator (0xAB) (8) Connect an external Vout (see diagram below) (9) Send OTP setting commands that we find in step 1 (0x82, 0x10~0x1F) (10)Send OTP programming command (0x83) (11)Wait at least 2 seconds (12)Hardware Reset Verify the result by repeating step 1. (2) – (3) (8) R Vout +C GND (1) & (6) & (12) GND SSD1858 16.5-17.5V RES# Note: R = 1K ~ 10k ohm C = 1u ~ 4.7u F Figure 11 - OTP programming circuitry 31 SSD1858 Rev 1.1 09/2002 SOLOMON Start Step 2 Step 1 i) Hardware reset ii) Send original initialization routines iii) Set and display any test patterns i) Hardware reset ii) Enable oscillator Adjust the contrast level to the best visual level Connect an external voltage (16.5-17.5V) on Vout pins Accept the contrast level on panel? No i) Send OTP setting commands ii) Send OTP programming command iii) Wait > 2 sec iv) Hardware reset Yes OTP setting steps = Adjusted contrast value – Original contrast value i) Send original initialization routines ii) Set and display any test patterns iii) Inspect the contrast END Figure 12 - Flow chart of OTP program SSD1858 Rev 1.1 09/2002 SOLOMON 32 OTP Example program Find the OTP offset: 1. 2. Hardware reset by sending an active low reset pulse to RES# pin COMMAND(0XAB) COMMAND(0X2F) 3. COMMAND(0X48) COMMAND(0X40) COMMAND(0X55) 4. COMMAND(0X81) COMMAND(0X2D) COMMAND(0X24) 5. COMMAND(0XB0) COMMAND(0x00) COMMAND(0X10) DATA(…) COMMAND(0XAF) 6. 7. 8. 9. \\Enable oscillator \\ Turn on the internal voltage booster, internal regulator and output op-amp buffer; Select booster level \\ Set Duty ratio \\ 64Mux \\ Set Biasing ratio (1/9 BIAS) \\ Set target gain and contrast. \\ Contrast = 45 \\ Gain = 6.3 \\ Set page address \\ Set lower nibble column address \\ Set higher nibble column address \\ Write test patterns to GDDRAM \\ Set Display On \\ Set target display contents OTP offset calculation… target OTP offset value is +3 Hardware reset by sending an active low reset pulse to RES# pin COMMAND(0XAB) \\ Enable Oscillator \\ Set OTP offset value to +3 (0011) \\ 0001 X3X2X1X0 , where X3X2X1X0 is the OTP offset value \\ Send the OTP programming command. Connect an external Vout (16.5V-17.5V) COMMAND(0X13) OTP programming: 10. COMMAND(0X82) 11. COMMAND(0X83) 12. Wait at least 2 seconds for programming wait time. 13. Hardware reset by sending an active low reset pulse to RES# pin 14. Verify the result: 15. After OTP programming, procedure 2 to 5 are repeated for inspection of the contrast on the panel 8.31 Enable External Oscillator Input This command enables the external clock input from CL pin and expected external square wave is 726kHz. 33 SSD1858 Rev 1.1 09/2002 SOLOMON 9 MAXIMUM RATINGS Parameter Value -0.3 to 5.5 VSS -0.3 to VSS +12.0 VDD to +5.5 VSS -0.3 to VDD +0.3 25 -40 to +85 -65 to +150 Unit V V V V mA °C °C Table 12 - Maximum Ratings (Voltage Referenced to VSS) Symbol VDD VCC VCI Vin I TA Tstg Supply Voltage Booster Supply Voltage Input Voltage Current Drain Per Pin Excluding VDD and VSS Operating Temperature Storage Temperature Range * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the limits in the Electrical Characteristics tables or Pin Description section. This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions to be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation it is recommended that Vin and Vout be constrained to range VSS < or = (Vin or Vout) < or = VDD. Reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (e.g. either VSS or VDD). Unused outputs must be open. This device may be light sensitive. Caution should be taken to avoid exposure of this device any light source during normal operation. This device is not radiation protected. SSD1858 Rev 1.1 09/2002 SOLOMON 34 10 DC CHARACTERISTICS Table 13 - DC Characteristics (Unless otherwise specified, Voltage Referenced to VSS, VDD = 1.8 to 3.3V, TA = -40 to 85°C) Symbol VDD Parameter Logic Circuit Supply Voltage Range Booster Voltage Supply Pin Test Condition (Absolute value referenced to VSS) (Absolute value referenced to VSS) Internal Reference Voltage Source Enabled (REF pin pulled High), VEXT pin NC. VDD = 2.7V, Voltage Generator On, 5X DC-DC Converter Enabled, Write accessing, Tcyc =3.3MHz, Frame Freq.=157.5Hz, Display On. VDD =VCI = 2.7V, Voltage Generator ON, internal Divider Enabled. Read/Write Halt, Frame Freq. = 157.5Hz, Display On, Vout = 10.0V. VDD = VCI = 1.8V, Voltage Generator OFF, DC-DC Converter Disabled, Internal Divider Disable. Read/Write Halt, Frame Freq. = 157.5Hz, Display On, Vout = 8.0V, no panel loading. Min 1.8 Typ 2.7 Max 3.3 Unit V VCI VREF IAC VDD - 1.7 0.9 3.6 2 V V mA Internal Reference Voltage o o (25 C, -0.14%/ C) Access Mode Supply Current Drain (VDD Pins) IDP1 Display Mode Supply Current Drain (VDD & VCI Pins) - 220 300 µA IDP2 Display Mode Supply Current Drain (VDD &VCI Pins) - 75 150 µA IVCI Operating Current (VCI Pin) o o (25 C, -0.14%/ C) ISLEEP Vout Sleep Mode Supply Current Drain (VDD Pins) LCD Driving Voltage Generator Output (Vout Pin) VDD=VCI=2.75V, Voltage Generator On, 4X DC-DC Converter Enabled, Internal Divider Enabled. Read/Write Halt, Frame Freq. = 157.5Hz, Display On, Vout = 7.5V, no panel loading, checker board pattern. VDD = 2.7V, LCD Driving Waveform Off, Oscillator Off, Read/Write halt. Display On, Voltage Generator Enabled, DC/DC Converter Enabled, Regulator Enabled, Frame Freq.=157.5Hz, 80uA panel loading Voltage Generator Disabled Iout = +500µA Iout = -500µA Regulator Enabled (Vout voltage depends on Internal contrast Control) 220 300 µA 4.0 1.2 - 2.5 12.0 µA V DC-DC Converter Efficiency VLCD VOH1 VOL1 Vout LCD Driving Voltage Input (Vout Pin) Output High Voltage (D0-D7) Out Low Voltage (D0-D7) LCD Driving Voltage Source (Vout Pin) 4.0 0.8*VDD 0 VDD 85 - 12.0 VDD 0.2*VDD 12.0 % V VLCD V V 35 SSD1858 Rev 1.1 09/2002 SOLOMON Symbol Vout VIH1 VIL1 Vout VL5 VL4 VL3 VL2 Vout VL5 VL4 VL3 VL2 IOH IOL IOZ IIL /IIH Parameter LCD Driving Voltage Source (Vout Pin) Input high voltage (RES#, PS0, PS1, CS#, D/C#, R/W(WR#), D0-D7) Input low voltage (RES#, PS0, PS1, CS#, D/C#, R/W(WR#), D0-D7) LCD Display Voltage Output Test Condition Regulator Disable Min - Typ Floating Max - Unit V 0.8*VDD 0 - VDD 0.2*VDD - V V Bias Divider Enabled, 1:a bias ratio - Vout (a-1)/a*Vout (a-2)/a*Vout 2/a* Vout 1/a* Vout - V V V V V V (Vout, VL5, VL4, VL3, VL2 Pins) LCD Display Voltage Input (Vout, VL5, VL4, VL3, VL2 Pins) Voltage reference to VSS, External Voltage Generator, Bias Diver Disabled VL5 VL4 VL3 VL2 VSS 50 -1 -1 CIN ∆Vout Vref Output High Current Source (D0-D7) Output Low Current Drain (D0-D7) Output Tri-state Current Source (D0-D7) Input Current (RES#, PS0, PS1, CS# , E(RD#), D/C#, R/W(WR#), D0-D7) Input Capacitance (all logic pins) Variation of Vout Output (1.8V < VDD < 3.3V) Reference Voltage (T= 25ºC) Reference Voltage (T= -20ºC) Reference Voltage (T= 70ºC) Temperature Coefficient Compensation Flat Temperature Coefficient Temperature Coefficient 1* Temperature Coefficient 2* Temperature Coefficient 3* Temperature Coefficient 4* (POR) Output Voltage=V DD -0.4V Output Voltage = 0.4V Vout VL5 VL4 VL3 -50 1 1 V V V V µA µA µA µA Regulator Enabled, Internal Contrast Control Enabled, Set Contrast Control Register = 0 1.68 1.76 1.54 Voltage Regulator Enabled Voltage Regulator Enabled Voltage Regulator Enabled Voltage Regulator Enabled Voltage Regulator Enabled 0 -0.025 -0.04 -0.07 -0.126 5 ±2 1.7 1.81 1.59 -0.01 -0.035 -0.05 -0.083 -0.14 7.5 1.72 1.86 1.64 -0.02 -0.045 -0.06 -0.096 -0.154 PF % V V V % % % % % PTC0 PTC1 PTC2 PTC3 PTC4 * The formula for the temperature coefficient is: TC(%)= Vout 50ºC – Vout at 0ºC 50ºC – 0ºC X 1 X100% Vout at 25ºC SSD1858 Rev 1.1 09/2002 SOLOMON 36 11 AC CHARACTERISTICS Table 14 - AC Characteristics (Unless otherwise specified, Voltage Referenced to VSS, VDD, VCI = 2.7V, TA = -40 to 85°C) Symbol FFRM Parameter Frame Frequency Test Condition Display ON, Set 104 x 64 Graphic Display Mode, Icon Line Disabled (POR) Display ON, Set 104 x 64 Graphic Display Mode, Icon Line Disabled Min Typ Max Unit - 157.5 726 - Hz kHz Fosc Oscillator frequency Frame Frequency at diff Vdd 180.0 160.0 140.0 Frame Frequency[Hz] D8 D9 DA DB DC DD DE DF 120.0 100.0 80.0 60.0 40.0 1.5 2 2.5 3 o 3.5 VDD [V] Figure 13 - Frame Frequency at different VDD( Temp = 25 C). 37 SSD1858 Rev 1.1 09/2002 SOLOMON Table 15 – Parallel Timing Characteristics (TA = -40 to 85°C, VDD = 1.8V, VSS =0V) Symbol tcycle tAS tAH tDSW tDHW tDHR tOH tACC PW CSL PW CSH tR tF Parameter Clock Cycle Time (write cycle) Address Setup Time Address Hold Time W rite Data Setup Time W rite Data Hold Time Read Data Hold Time Output Disable Time Access Time (RAM) Access Time (command) Chip Select Low Pulse Width (read RAM) Chip Select Low Pulse Width (read Command) Chip Select Low Pulse Width (write) Chip Select High Pulse Width (read) Chip Select High Pulse Width (write) Rise Time Fall Time Min 200 0 0 40 10 10 15 15 500 500 100 200 100 - Typ 1000 - Max 25 50 40 10 10 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns R/ W D/C tA S E t cycle tAH PW CSL CS tF tDSW D0 -D7 (Write data to driv er) tA CC D 0-D 7 (Read data f rom driv er) Valid Data PW CSH tR tDHW t DHR Valid Data tOH Figure 14 – Parallel 6800-series Interface Timing Characteristics (PS0 = H, PS1 = H) SSD1858 Rev 1.1 09/2002 SOLOMON 38 Table 16 – Parallel Timing Characteristics (TA = -40 to 85°C, VDD = 2.7, VSS =0V) Symbol tcycle tAS tAH tDSW tDHW tDHR tOH tACC PW CSL PW CSH tR tF Parameter Clock Cycle Time (write cycle) Address Setup Time Address Hold Time W rite Data Setup Time W rite Data Hold Time Read Data Hold Time Output Disable Time Access Time (RAM) Access Time (command) Chip Select Low Pulse Width (read RAM) Chip Select Low Pulse Width (read Command) Chip Select Low Pulse Width (write) Chip Select High Pulse Width (read) Chip Select High Pulse Width (write) Rise Time Fall Time Min 100 0 0 30 5 10 15 15 250 250 50 100 50 - Typ 500 - Max 25 50 40 10 10 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns R/ W D/C tA S E t cycle tAH PW CSL CS tF tDSW D0 -D7 (Write data to driv er) tA CC D 0-D 7 (Read data f rom driv er) Valid Data PW CSH tR tDHW t DHR Valid Data tOH Figure 15 - Parallel 6800-series Interface Timing Characteristics (PS0 = H, PS1 = H) 39 SSD1858 Rev 1.1 09/2002 SOLOMON Table 17 - Parallel Timing Characteristics (TA = -40 to 85°C, VDD = 1.8V, VSS =0V) Symbol tcycle tAS tAH tDSW tDHW tDHR tOH tACC PW CSL PW CSH tR tF Parameter Clock Cycle Time (write cycle) Address Setup Time Address Hold Time W rite Data Setup Time W rite Data Hold Time Read Data Hold Time Output Disable Time Access Time (RAM) Access Time (command) Chip Select Low Pulse Width (read RAM) Chip Select Low Pulse Width (read Command) Chip Select Low Pulse Width (write) Chip Select High Pulse Width (read) Chip Select High Pulse Width (write) Rise Time Fall Time Min 200 0 0 40 10 10 15 15 500 500 100 200 100 - Typ 1000 - Max 25 50 40 10 10 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns D/C tAH tAS WR ( R/W ) RD ( E) tcycl e PWCSL CS tF tD SW D0-D7 (Write dat a to driver) tAC C D0 -D7 (Read data from driver) Valid Data PW CSH tR t DH W t D HR Valid Data tOH Figure 16 - Parallel 8080-series Interface Timing Characteristics (PS0 = H, PS1 = L) SSD1858 Rev 1.1 09/2002 SOLOMON 40 Table 18 - Parallel Timing Characteristics (TA = -40 to 85°C, VDD = 2.7V, VSS =0V) Symbol tcycle tAS tAH tDSW tDHW tDHR tOH tACC PW CSL PW CSH tR tF Parameter Clock Cycle Time (write cycle) Address Setup Time Address Hold Time W rite Data Setup Time W rite Data Hold Time Read Data Hold Time Output Disable Time Access Time (RAM) Access Time (command) Chip Select Low Pulse Width (read RAM) Chip Select Low Pulse Width (read Command) Chip Select Low Pulse Width (write) Chip Select High Pulse Width (read) Chip Select High Pulse Width (write) Rise Time Fall Time Min 100 0 0 30 5 10 15 15 250 250 50 100 50 - Typ 500 - Max 25 50 40 10 10 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns D/C tAH tAS WR ( R/W ) RD ( E) tcycl e PWCSL CS tF tD SW D0-D7 (Write dat a to driver) tAC C D0 -D7 (Read data from driver) Valid Data PW CSH tR t DH W t D HR Valid Data tOH Figure 17 - Parallel 8080-series Interface Timing Characteristics (PS0 = H, PS1 = L) 41 SSD1858 Rev 1.1 09/2002 SOLOMON Table 19 – Serial Timing Characteristics (TA = -40 to 85°C, VDD = 2.7V, VSS =0V) Symbol Parameter tcycle tAS tAH tCSS tCSH tDSW tOHW tCLKL tCLKH tR tF Clock Cycle Time Address Setup Time Address Hold Time Chip Select Setup Time Chip Select Hold Time W rite Data Setup Time W rite Data Hold Time Clock Low Time Clock High Time Rise Time Fall Time Min 58.8 10 5 30 29.4 30 30 29.4 29.4 - Typ - Max 10 10 Unit ns ns ns ns ns ns ns ns ns ns ns D/C (Required if PS1 = H) tAS CS tCSS t c ycle tC L KH tAH tCS H tC LK L SCK tF tDSW SDA Valid Data tR tDHW CS SCK SDA D7 D6 D5 D4 D3 D2 D1 D0 Figure 18- Serial Timing Characteristics (PS0 = L) SSD1858 Rev 1.1 09/2002 SOLOMON 42 Table 20 – Serial Timing Characteristics (TA = -40 to 85°C, VDD = 1.8V, VSS =0V) Symbol Parameter tcycle tAS tAH tCSS tCSH tDSW tOHW tCLKL tCLKH tR tF Clock Cycle Time Address Setup Time Address Hold Time Chip Select Setup Time Chip Select Hold Time W rite Data Setup Time W rite Data Hold Time Clock Low Time Clock High Time Rise Time Fall Time Min 111 15 10 60 55.5 60 60 55.5 55.5 - Typ -- Max -- 10 10 Unit ns ns ns ns ns ns ns ns ns ns ns D/C (Required if PS1 = H) tAS CS tCSS t c ycle tC L KH tAH tCS H tC LK L SCK tF tDSW SDA Valid Data tR tDHW CS SCK SDA D7 D6 D5 D4 D3 D2 D1 D0 Figure 19 - Serial Timing Characteristics (PS0 = L) 43 SSD1858 Rev 1.1 09/2002 SOLOMON 12 APPLICATION EXAMPLES ICONS COM0 : : COM10 COM11 : : COM30 COM31 DISPLAY PANEL SIZE 96 X 64 + 1 ICON LINE COM32 COM33 : : : : : COM63 Remapped COM SCAN Direction [Command: C8] Remapped COM SCAN Direction [Command: C8 SEG95…………………………………………….………….SEG0 : : : : COM33 COM32 : : : : : COM0 COL99………………………………………………………………………COL4 Remapped COM SCAN Direction [Command: C8 : : : : COM62 COM63 ICONS SSD1858 IC 64 MUX (DIE FACE IP) : : : : : COM30 COM31 Remapped COM SCAN Direction [Command: C8 C1 C2 RES# CS# SDA SCL VCI VDD VOUT VSS where VDD&VCI=2.775V; C1~C2 = 0.47uF~4.7uF, Logic pin connections not specified above: Pins connected to VDD: E(RD#);R/W(WR#);MODE; D/C; D0~D5 Pins connected to VSS: TEST_IN0;TEST_IN1;PS0;PS1;RVSS;CVSS Figure 20 - Typical Application (3-wires SPI mode) SSD1858 Rev 1.1 09/2002 SOLOMON 44 Solomon Systech reserves the right to make changes without further notice to any products herein. Solomon Systech makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Solomon Systech assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different applications. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Solomon Systech does not convey any license under its patent rights nor the rights of others. Solomon Systech products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Solomon Systech product could create a situation where personal injury or death may occur. Should Buyer purchase or use Solomon Systech products for any such unintended or unauthorized application, Buyer shall indemnify and hold Solomon Systech and its offices, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Solomon Systech was negligent regarding the design or manufacture of the part. 45 SSD1858 Rev 1.1 09/2002 SOLOMON