TTS3816B4E-6

M.tec 2M x 16Bit x 4 Banks synchronous DRAM TTS3816B4E GENERAL DESCRIPTION The TTS3816B4E is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 8 x 1,048,576 words by 16 bits, fabricated with M’tec high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. FEATURES • JEDEC standard 3.3V power supply • LVTTL compatible with multiplexed address • Four-banks operation • MRS cycle with address key programs -. CAS latency (2 & 3) -. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave) • All inputs are sampled at the positive going edge of the system clock. • Burst read single-bit write operation • DQM for masking • Auto & self refresh • 64ms refresh period (4K cycle) ORDERING INFORMATION Part No. TTS3816B4E-7 TTS3816B4E-6 TTS3816B4E-6A TTS3816B4E-6B TTS3816B4E-6C TTS3816B4E-6D TTS3816B4E-6E Max Freq. 100MHz 2-2-2 133MHz 3-3-3 100MHz 2-3-3 133MHz 2-3-2 133MHz 2-2-2 150MHz 3-3-3 166MHz 3-3-3 LVTTL 54 TSOP(II) Interface Package Revision_1.1 1 TwinMOS Technologies Inc. Sep. 2000 M.tec PIN CONFIGURATION (Top View) TTS3816B4E 54Pin TSOP (II) (400mil x 875mil) (0.8 mm Pin pitch) Revision_1.1 2 TwinMOS Technologies Inc. Sep. 2000 M.tec PIN FUNCTION DESCRIPTION Pin Name A0~ A11 BS0, BS1 DQ0 ~DQ15 /CS /RAS /CAS /WE UDQM/LDQM CLK CKE Vcc Vss Vcc Vss NC Address Bank Data Input / Output Chip Select Row Address Strobe Column Address Strobe Write Enable Input /output mask Clock Input Clock Enable Power (+3.3 V) Ground TTS3816B4E Function Description Multiplexed pins for row and column address Row address: A0 ~ A11. Column address: A0 ~ A8. Select bank to activate during row address latch time, or bank to read/write during address latch time. Multiplexed pins for data output and input. Disable or enable the command decoder. When command decoder is disabled, new command is ignored and previous operation continues. Command input. When sampled at the rising edge of the clock, /RAS, /CAS and /WE define the operation to be executed. Referred to /RAS Referred to /RAS The output buffer is placed at Hi-Z (with latency of 2) when DQM is sampled high in read cycle. In write cycle, sampling DQM high will block the write operation with zero latency. System clock used to sample inputs on the rising edge of clock. CKE controls the clock activation and deactivation. When CKE is low, Power Down mode, Suspend mode, or Self Refresh mode is entered. Power for input buffers and logic circuit inside DRAM. Ground for input buffers and logic circuit inside DRAM. Q Power (+ 3.3 V) for I/O Separated power from VCC , used for output buffers to improve noise. buffer Q Ground for I/O buffer No Connection Separated ground from VSS , used for output buffers to improve noise. No connection Revision_1.1 3 TwinMOS Technologies Inc. Sep. 2000 M.tec BLOCK DIAGRAM TTS3816B4E Bank Select Data Input Sse AMP Address ADD Buffer Row Decoder & Refresh Counter 2MX16 2MX16 2MX16 2MX16 Column Decoder Output Buffer DQ Column Buffer /CS / RAS / CAS / WE CLK CKE Latency & Burst Length Commend Decoder & Clock Buffer Programming Register Revision_1.1 4 TwinMOS Technologies Inc. Sep. 2000 M.tec ABSOLUTE MAXIMUM RATING Parameter Voltage on any pin relative to VSS Voltage on VCC supply relative to VSS Storage temperature Power dissipation Short circuit current TTS3816B4E Symbol VIN, VOUT VCC, VCCQ TSTG PD IOS Value -1.0 ~ 4.6 -1.0 ~ 4.6 -55 ~ +150 1 50 Unit V V ℃ W mA Note: Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to the recommended operating conditions. Exposure to higher voltage than recommended for extended periods of time could affect device reliability. DC OPERATING CONDITIONS Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70°C) Parameter Supply voltage Input logic high voltage Input logic low voltage Output logic high voltage Output logic low voltage Input leakage current (Input) Input leakage current (I/O pins) Symbol VCC, VCCQ VIH VIL VOH VOL IIL IIL Min 3.0 2.0 -0.3 2.4 -1 -1.5 Typ 3.3 3.0 0 - Max 3.6 VCCQ+0.3 0.8 0.4 1 1.5 Unit V V V V V uA uA Note 1 2 IOH=-2mA IOL=2mA 3 3,4 Notes: 1. VIH (max) = 5.6V AC. The overshoot voltage duration is ≦ 3ns. 2. VIL (min) = -2.0V AC. The undershoot voltage duration is ≦ 3ns. 3. Any input 0V ≦ VIN ≦ VCCQ, Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs. 4. Dout is disabled, 0V ≦ Vout ≦ VCCQ Revision_1.1 5 TwinMOS Technologies Inc. Sep. 2000 M.tec DC CHARACTERISTICS (Recommended operating condition unless otherwise noted, TA = 0 to 70°C) TTS3816B4E Parameter Operating current (One bank active) Symbol Test Condition Burst length = 1 tRC≧tRC(min) IOL = 0mA CKE≦VIL(max), tCC = 15 ns TTS3816B4E Unit Note ICC1 100 mA 1 ICC2P Pre-charge standby current in power- down mode ICC2PS 2 mA CKE&CLK≦VIL(max), tCC = ∞ CKE≧VIH(min), /CS≧VIH(min) , tCC = 15ns Input signals are stable CKE≧VIH(min), CLK≦VIL(Max) , tCC = ∞ Input signals are stable CKE≦VIL(max), tCC = 15 ns 2 ICC2N Pre-charge standby current in non power-down mode ICC2NS 30 mA 10 ICC3P Active standby current in power-down mode ICC3PS 5 mA CKE&CLK≦VIL(max), tCC = ∞ CKE≧VIH(min), /CS≧VIH(min) , tCC = 15ns Input signals are stable CKE≧VIH(min), CLK≦VIL(Max) , tCC = ∞ Input signals are stable IOL=0 mA Page burst 2Banks activated tCCD = 2CLKS tRC≧tRC(min) CL = 3 CL = 2 5 Active standby current in non power-down mode (One bank active) ICC3N 40 mA 20 150 mA 140 mA 2 1 ICC3NS Operating current (Burst mode) ICC4 Refresh current ICC5 160 Self refresh current ICC6 CKE≦0.2V 1 mA Note: 1.Measured with outputs open. 2.Refresh period is 64 ms. Revision_1.1 6 TwinMOS Technologies Inc. Sep. 2000 M.tec AC CHARACTERISTICS AND OPERATING (Vcc=3.3V±0.3V, Ta=0° to 70°C) Parameter Row active to row active delay /RAS to /RAS delay Row pre-charge time Row active time Row cycle time Col. Address to col. Address delay W rite Recovery Time CLK Cycle Time CLK High Level width CLK Low Level width Access Time from CLK Output Data Hold Time Data-in Set-up Time Data-in Hold Time Address Set-up Time Address Hold Time CKE Set-up Time CKE Hold Time Command Set-up Time Command Hold Time Refresh Time Mode register Set Cycle Time TTS3816B4E Symbol tRRD tRCD tRP tRAS tRC tCCD tWR tCK tCH tCL tAC tOH tDS tDH tAS tAH tCKS tCKH tCMS tCMH tREF tRSC CL=2 CL=3 -7 -6 -6A -6B -6C -6D -6E Min Max Min Max Min Max Min Max Min Max Min Max Min Max 20 20 20 48 70 1 20 100K Unit ns ns ns 15 20 20 45 67.5 100K 20 30 30 48 70 1 20 1000 1000 100K 14 20 15 45 63 1 14 1000 1000 100K 14 15 15 45 63 1 14 1000 1000 100K 14 20 20 45 63 1 13 1000 1000 100K 12 18 18 42 60 1 12 1000 100K ns ns CLK ns ns 1 15 1000 1000 CL=2 10 CL=3 8 3 3 10 7.5 2.5 2.5 10 8 3 3 7.5 7.5 2.5 2.5 7.5 7.5 2.5 2.5 6.5 2 2 6 2 2 1000 ns ns 5 ns ns ns ns ns ns ns ns ns ns 64 ms 6 6 3 2 1 2 1 2 1 2 1 64 20 15 2.7 1.5 1 1.5 1 1.5 1 1.5 1 6 5.4 3 2 1 2 1 2 1 2 1 64 20 8 6 2.7 1.5 1 1.5 1 1.5 1 1.5 1 64 14 5.4 5.4 2.7 1.5 1 1.5 1 1.5 1 1.5 1 64 14 5.4 5.4 2.5 1.5 1 1.5 1 1.5 1 1.5 1 64 12 5.4 2 1.5 1 1.5 1 1.5 1 1.5 1 64 12 ns Revision_1.1 7 TwinMOS Technologies Inc. Sep. 2000 M.tec 54PIN PLASTIC TSOP(II) (400mil) 54 28 TTS3816B4E detail of lead end F P E 1 2 A H G I 7 J C D NOTE N M L K B ITEM A B C D E F G H I J K L M N P MILLIMETERS 22.62 MAX. 0.91 MAX. 0.80 (T.P.) 0.32 +0.08 –0.07 0.10±0.05 1.20 MAX. 1.00 11.76±0.20 10.16±0.10 0.80±0.20 0.145 +0.025 –0.015 0.50±0.10 0.13 0.10 3 +7° ° –3 ° INCHES 0.891 MAX. 0.036 MAX. 0.031 (T.P.) 0.013±0.003 0.004±0.002 0.048 MAX. 0.039 0.463±0.008 0.400±0.004 0.031 +0.009 –0.008 0.006±0.001 0.020 +0.004 –0.005 0.005 0.004 ° 3 ° +7° –3 M Each lead centerline is located within 0.13 mm (0.005 inch) of its true position (T.P.) at maximum material condition. Revision_1.1 8 TwinMOS Technologies Inc. Sep. 2000