UT51C164MC-50

 UTRON Rev 1.4 UT51C164 256K X 16 BIT EDO DRAM FEATURES RAS access time: 35, 40, 50, 60 2 CAS Byte/Word Read/Write operation CAS - before – RAS refresh capability RAS only and Hidden refresh capability Early write or output enable controlled write Extended Data Out operation Package : 40 pin 400mil SOJ 40 / 44 pin 400mil TSOP-Ⅱ Single +5V+10% power supply TTL compatible inputs and outputs 512 refresh cycles /8ms Speed tRAC tCAA tPC tCAC tRC -35 35ns 18ns 14ns 11ns 70ns -40 40ns 20ns 15ns 12ns 75ns -50 50ns 24ns 19ns 14ns 90ns -60 60ns 30ns 27ns 15ns 110ns GENERAL DESCRIPTION The UT51C164 is high speed 5V EDO DRAMs organized as 256K bit X 16 I/O and fabricated with the CMOS process. The UT51C164 offers a combination of unique features including : EDO Page Mode operation for higher bandwidth with Page Mode cycle time as short as 14ns. All inputs are TTL compatible. Input and output capacitance is significantly lowered to increase performance and minimize loading. These features make the UT51C164 suited for wide variety of high performance computer systems and peripheral applications UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 P90005 1  UTRON Rev 1.4 UT51C164 256K X 16 BIT EDO DRAM PIN DESCRIPTION SYMBOL A0-A8 RAS UCAS LCAS WE OE DQ0-DQ15 VDD Vss NC DESCRIPTION Address Inputs Row Address Strobe Column Address Strobe / Upper Byte Control Column Address Strobe / Lower Byte Control Write enable Output enable Data Inputs, Data Outputs +5V Supply 0V Supply No Connect PIN CONFIGURATIONS UT51C164 40- pin SOJ V DD DQ0 DQ1 DQ2 DQ3 V DD DQ4 DQ5 DQ6 DQ7 NC NC WE RAS NC A0 A1 A2 A3 V DD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 UT51C164 40- pin TSOP - Ⅱ Vss DQ15 DQ14 DQ13 DQ12 Vss DQ11 DQ10 DQ9 DQ8 NC LCAS UCAS OE A8 A7 A6 A5 A4 Vss VDD DQ0 DQ1 DQ2 DQ3 VDD DQ4 DQ5 DQ6 DQ7 1 2 3 4 5 6 7 8 9 10 40 39 38 37 36 35 34 33 32 31 Vss DQ15 DQ14 DQ13 DQ12 Vss DQ11 DQ10 DQ9 DQ8 NC NC WE RAS NC A0 A1 A2 A3 VDD 11 12 13 14 15 16 17 18 19 20 30 29 28 27 26 25 24 23 22 21 NC LCAS UCAS OE A8 A7 A6 A5 A4 Vss UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 P90005 2  UTRON Rev 1.4 UT51C164 256K X 16 BIT EDO DRAM FUNCTION BLOCK DIAGRAM V SS V UCAS LCAS WE RAS OE DD A0 A1 A8 Y0 – Y8 Address Buffers & Predecoders . A7 . . . X512 CS GENERATOR Refresh Counter X0 – X8 Control Circuit VBB 9 V BB Row Control Circuit Row Decoder Column Decoder 512 x 512 x 16 Sense Amp 3 FSA & Write in Circuit Input & Output Buffer x16 DQ[0,15] UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 Cell Array x16 x16 P90005  UTRON Rev 1.4 UT51C164 256K X 16 BIT EDO DRAM ABSOLUTE MAXIMUM RATINGS PARAMETER Voltage on any pin relative to Vss Supply voltage relative to VSS Short circuit output current Power dissipation Operating temperature Storage temperature SYMBOL VT VDD IOUT PD TA TSTG VALUE -1.0 to +7 -1.0 to +7 50 1.0 0 to + 70 -55 to +125 UNIT V V mA W ºC ºC Notes: Permanent device damage may occur if absolute maximum ratings are exceed. RECOMMENDED DC OPERATING CONDITIONS (TA = 0℃ to 70ºC) PARAMETER Supply voltage Input high voltage Input low voltage Notes: 1. All Voltage referred to Vss SYMBOL VDD Vss VIH VIL 5.0V MIN 4.5 0 2.4 -0.3 MAX 5.5 0 VDD +1V 0.8 UNIT V V V V NOTES 1 1 1 CAPACITANCE (TA = 25ºC, VDD= 5V±0.5V，f=1MHz) PARAMETER Input capacitance (A0-A8) Input Capacitance ( RAS , UCAS , LCAS , WE , OE ) Output capacitance(DQ0-DQ15) SYMBOL CIN1 CIN2 CDQ TYP 3 4 5 MAX 4 5 7 UNIT pF pF pF UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 P90005 4  UTRON Rev 1.4 UT51C164 256K X 16 BIT EDO DRAM DC CHARACTERISTICS (TA = 0℃ to 70ºC, VDD = 5.0 V ± 0.5 V, Vss = 0 V) SYMBOL PARAMETER Operating Current, VDD Supply Standby Current (TTL Input) RAS Only Current EDO Page Current Refresh SPEED (tRAC) -35 -40 -50 -60 -35 -40 -50 -60 -35 -40 -50 -60 -35 -40 -50 -60 UT51C164 Min Max 190 180 170 160 4.5 -10 -10 -1 2.4 2.4 3 190 180 170 160 220 200 190 180 190 180 170 160 2 5.5 10 10 0.8 VDD +1 UNIT TEST CONDITION IDD1 mA tRC = tRC (min.) RAS = UCAS = LCAS =VIH tRC = tRC (min.) IDD2 mA IDD3 mA IDD4 Mode mA tPC = tPC (min.) IDD5 CBR Refresh Current mA tRC = tRC (min.) RAS ≧ VDD-0.2V CAS ≧ VDD-0.2V All other inputs≧ VSS VSS≦ VIN ≦VDD VSS≦ VOUT ≦VDD RAS = CAS = VIH IDD6 VDD ILI ILO VIL VIH VOL VOH Standby Current (CMOS Input) Power Supply Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage mA V uA uA V V V V 0.4 - IOI = 2mA IOH = 2mA Notes: IDD1, IDD3, IDD4, IDD5 are dependent on output loading and cycle rates. Specified values are obtained with the output open. IDD is specified as an average current. In IDD1, IDD3, and IDD5 address can be changed maximum once while RAS =VIL. In IDD4, address can be changed maximum once within one EDO page cycle time, tPC. UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 P90005 5  UTRON Rev 1.4 UT51C164 256K X 16 BIT EDO DRAM AC CHARACTERISTICS (TA = 0℃ to 70°C) Test condition: VDD = 5.0V±0.5V, VIH / VIL=3V / 0V, VOH / VOL=2.0 / 0.8) SYMBOL PARAMETER 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 35 40 50 60 UNIT NOTE Min. Max. Min. Max. Min. Max. Min. Max. 35 70 25 35 8 13 0 0 6 0 6 10 5 0 0 7 11 11 35 18 0 0 25 10 1.5 8 0 5 5 17 50 5 0 0 30 12 1.5 10 0 6 6 20 50 6 24 75K 40 75 25 40 8 17 0 0 7 0 7 12 5 0 0 8 12 12 40 20 0 0 40 14 1.5 10 0 7 7 26 50 8 28 75K 50 90 30 50 10 19 0 0 9 0 9 14 5 0 0 10 14 14 50 24 0 0 50 15 1.5 10 0 10 10 30 50 10 36 75K 60 110 40 60 10 20 0 0 10 0 10 15 5 0 0 10 15 15 60 30 45 75K ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns *9,10 *8 *12 *9 *3,4,11 *3,5,6 *3,4,7 *13 *13 *2 *2 *1 tRAS tRC tRP tCSH tCAS tRCD tRCS tASR tRAH tASC tCAH tRSH tCRP tRCH tRRH tROH tOAC tCAC tRAC tCAA tLZ tHZ tAR tRAD tT tCWL tWCS tWCH tWP RAS Pulse Width Read or Write Cycle Time RAS Precharge Time CAS Hold Time CAS Pulse Width RAS to CAS Delay Read Command Setup Time Row Address Setup Time Row Address Hold Time Column Address Setup Time Column Address Hold Time RAS to CAS Hold Time CAS to RAS Precharge Time Read Command Hold Time Reference CAS Read Command Hold Time Reference RAS RAS Hold Time Referenced to OE Access Time from OE Access Time from CAS Access Time from RAS Access Time From Column Address OE or CAS to Low-Z Output OE or CAS to High-Z Output Column Address Hold Time from RAS RAS to Column Address Delay Time Transition Time Write Command to CAS Lead Time Write Command Setup Time Write Command Hold time Write Pulse Width UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 P90005 6  UTRON Rev 1.4 UT51C164 256K X 16 BIT EDO DRAM AC CHARACTERISTICS ( continued ) SYMBOL PARAMETER 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 35 40 50 60 UNIT NOTE Min. Max. Min. Max. Min. Max. Min. Max. 25 11 0 5 5 5 30 12 0 6 6 6 110 75 30 58 48 38 15 5 20 20 25 8 0 8 55 3 3 5 8 8 30 10 0 9 60 3 4 6 10 8 23 40 10 0 12 70 3 6 8 14 8 40 14 0 7 8 8 130 85 34 68 52 42 19 7 24 27 50 10 0 15 85 3 8 10 18 8 50 15 0 10 10 10 170 105 40 85 65 58 27 10 30 34 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms *14 *4 *9 *9 *9 *11 *11 *11 *11 tWCR tRWL tDS tDH tWOH tOED tRWC tRRW tCWD tRWD tCRW tAWD tPC tCP tCAR tCAP tDHR tCSR tRPC tCHR tPCM tCOH tOES tOEH tOEP tREF Write Command Hold Time from RAS Write Command to RAS Lead Time Data in Setup Time Data in Hold Time Write to OE Hold time OE to Data Delay Time Read-Modify-Write Cycle Time 105 Read-Modify-Write Cycle Time 70 RAS Pulse Width CAS to WE Delay in ReadModify-Write Cycle RAS to WE Delay in ReadModify-Write Cycle CAS pulse Width in RMW Column Address to WE Delay Time EDO Page Mode Read or Write Cycle Time 28 54 46 35 14 4 18 CAS Precharge Time Column Address to RAS Setup Time Access Time from Column Precharge Data in Hold Time Referenced to RAS CAS Setup Time in CBR Refresh RAS to CAS Precharge Time CAS Hold Time in CBR Refresh EDO Page Mode Cycle Time in RMW Output Hold After CAS Low OE Low to CAS High Setup Time OE Hold Time from WE in RMW Cycle OE Pulse Width Refresh Interval (512 Cycles) UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 P90005 7  UTRON Rev 1.4 UT51C164 256K X 16 BIT EDO DRAM Notes: 1. tRCD (Max.) is specified for reference only. Operation within tRCD (Max.) limits insures that tRAC (Max.) and tCAA (Max.) can be met. If tRCD is greater than the specified tRCD (Max.), the access time is controlled by tCAA and tCAC. 2. Either tRRH or tRCH must be satisfied for Read Cycle to occur. 3. Measured with a load equivalent to one TTL input and 50pF. 4. Access time is determined by the longest of tCAA , tCAC and tCAP . 5. Assumes that tRAD ≦ tRAD (Max.). If tRCD is greater than tRCD (Max.), tRAC will increase by the amount that tRCD exceeds tRCD (Max.) 6. Assumes that tRCD ≦ tRCD (Max.). If tRCD is greater than tRCD (Max.), tRAC will increase by the amount that tRAD exceeds tRAD (Max.) 7. Assumes that tRAD ≧ tRAD (Max.). 8. Operation within the tRAD (Max.) limits ensures that tRA can be met. tRAD (Max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (Max.), the access time is controlled by tCAA and tCAC. 9. tWCS , tRWD , tAWD and tCWD are not restrictive operating parameters. 10. tWCS (min.) must be satisfied in an Early Write Cycle. 11. tDS and tDH are referenced to the latter occurrence of CAS or WE . 12. tT is measured between VIH (min.) and VIL (max.). AC-measurements assume tT = 3ns. 13. Assumes a tri-state test load (5pF and a 500Ohm Thevenin equivalent). 14.An initial pause of 200us is required after power-up followed by any 8 CBR or ROR cycles before device operation is achieved. UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 P90005 8  UTRON Rev 1.4 UT51C164 256K X 16 BIT EDO DRAM TRUTH TABLE FUNCTION Standby Read: Word Read: Lower Byte Read: Upper Byte Write: Word L L (Early-Write) Write: Lower Byte L L (Early-Write) Write: Upper Byte L H (Early-Write) Read-Write L L EDO Page-Mode H→ L L Read EDO Page-Mode H→ L L Write EDO Page –Mode H→ L L Read-Write Hidden Refresh L→ H → L L Read RAS Only L H Refresh CBR Refresh H→ L L RAS H L L L LCAS H L L H UCAS H L H L L H L L H→ L H→ L H→ L L H L WE X H H H OE X L L L X X X ADDRESS DQ(0-7) DQ(8-15) NOTE X ROW/COL ROW/COL ROW/COL ROW/COL High-Z High-Z DQ-OUT DQ-OUT High-Z High-Z DQ-OUT DQ-IN High-Z DQ-IN *1,2 *2 *2 *1,2 *2 L L L H→ L H L H→ L H X X ROW/COL DQ-IN ROW/COL High-Z L→H ROW/COL DQ-OUT,DQ-IN COL DQ-OUT L X L→ H L X X COL COL DQ-IN DQ-OUT,DQ-IN ROW/COL DQ-OUT ROW X High-Z High-Z Notes: 1. Byte Write cycles LCAS or UCAS active. 2. Byte Read cycles LCAS or UCAS active. UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 P90005 9  UTRON Rev 1.4 UTRON EDO Mode, X16 (2CAS) Device Timing Diagram ― UT51C164 256K X 16 BIT EDO DRAM Waveforms of Read Cycle t RAS(1) t RC(2) t RP(3) V RAS IH － V IL － t CRP(13) t RCD(6) t RAD(24) t RAH(9) t AR(23) t CSH(4) t t CRP(13) RSH(12) UCAS, V IH － LCAS V IL － t ASR(8) t CAS(5) t t ASC(10) ROW ADDRESS CAH(11) V IH － Address V IL － COLUMN ADDRESS t CAR(24) t RCH(14) t RRH(15) tRCS (7) WE V IH － V IL － t CAA(20) t ROH(16) OE V IH － V IL － t RAC(19) t CAC(18) t OAC(17) t OES(52) t HZ(22) t HZ(22) DQ V OH － V OL － t LZ(21) VALID DATA - OUT Don't care Undefined UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 P90005 10  UTRON Rev 1.4 UTRON EDO Mode, X16 (2CAS) Device Timing Diagram ― UT51C164 256K X 16 BIT EDO DRAM Waveforms of Early Write Cycle t RAS(1) t RC(2) t RP(3) V RAS IH － V IL － t CRP(13) t AR(23) t CSH(4) t RCD(6) t RSH(12) t CAS(5) t CRP(13) UCAS, V IH － LCAS V IL － t ASR(8) t RAH(9) t CAH(11) t ASC(10) t CAR(44) Address V IH － V IL － ROW ADDRESS t RAD(24) COLUMN ADDRESS t WCH(28) t CWL(26) WE V IH － V IL － t WCS (27) t WP(29) tWCR (30) t RWL (31) OE V IH － V IL － t DHR(46) t DS(32) t DH(33) DQ V IH － V IL － VALID DATA - IN HIGH-Z Don't Care Undefined UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 P90005 11  UTRON Rev 1.4 UTRON EDO Mode, X16 (2CAS) Device Timing Diagram Waveforms of OE-Contrilled Write Cycle t RC(2) t RAS(1) UT51C164 256K X 16 BIT EDO DRAM t RP(3) V RAS IH － V IL － t CRP(13) t RCD(6) t RAD(24) t RAH(9) tASR(8) t AR(23) t CSH(4) t RSH(12) t CAS(5) t CRP(13) UCAS, V IH － LCAS V IL － t ASC(10) t CAH(11) t CAR(44) Address V IH － V IL － ROW ADDRESS COLUMN ADDRESS tCWL (26) tRWL(31) WE V IH － V IL － tWP (29) tWOH (34) OE V IH － V IL － tOED (35) tDS (32) tDH(33) DQ V IH － V IL － VALID DATA -IN Don' t Care Undefined UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 P90005 12  UTRON Rev 1.4 UTRON EDO Mode, X16 (2CAS) Device Timing Diagram ― Waveforms of Read -Modify-Write Cycle t RWC(36) UT51C164 256K X 16 BIT EDO DRAM t RRW(37) t RP(3) RAS V IH － V IL － t CRP(13) t AR(23) t CSH(4) t RCD(6) t CRW(40) t RAH(9) t ASR(8) t t RSH(12) t CRP(13) UCAS, V IH － LCAS V IL － t CAH(11) ASC(10) V－ Address IH V IL － ROW ADDRESS t RAD(24) COLUMN ADDRESS tAWD (41) tCWL(26) tRWL(31) t ACS tRWD (39) t CAA (20) tCWD (38) tWP(29) WE V IH － V IL － tOAC (17) OE V IH － V IL － t RAC(19) tCAC (18) t OEH tOED (35) (53) t HZ (22) t DS (32) tDH (33) DQ V IH VOH－ V IL VOL－ t LZ(21) VALID DATA-OUT VALID DATA -IN Don't Care Undefined UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 P90005 13  UTRON Rev 1.4 UTRON EDO Mode, X16 (2CAS) Device Timing Diagram ― EDO Page Mode Read Cycle UT51C164 256K X 16 BIT EDO DRAM V RAS IH － V IL － t AR(23) t RCD(6) t RAS(1) t RP(3) ⌇ ⌇ t PC(42) t CRP(13) t CAS(5) t CP(43) t CAS(5) t RSH(12) ⌇ ⌇ t CAS(5) t CRP(13) UCAS, V IH － LCAS V IL － t RAH(9) t ASR(8) t CSH(4) t t ASC(10) ⌇ ⌇ t CAR(44) t ASC(10) CAH(11) t CAH(11) Address V IH － V IL － ROW ADDRESS t RCS(7) COLUMN ADDRESS t t CAH(11) RCH(14) COLUMN ADDRESS ⌇ ⌇ t RCS(7) ⌇ ⌇ COLUMN ADDRESS t RCS(7) t RCH(14) WE V IH － V IL － t CAA(20) t CAP(45) t CAA(20) t RRH(15) t OAC(17) t OAC(17) ⌇ ⌇ t OES(52) OE V IH － V IL － t RAC(19) t CAC(18) t LZ(21) t CAC(18) t COH(5) ⌇ ⌇ t OEP(54) t HZ(22) t CAC(18) t HZ(22) t HZ(22) t HZ(22) DQ V OH － V OL － VALID DATA OUT VALID DATA OUT t LZ VALID DATA OUT Don' t Care Undefined UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 P90005 14  UTRON Rev 1.4 UTRON EDO Mode, X16 (2CAS) Device Timing Diagram ― EDO Page Mode Write Cycle tAR(23) RAS V IH － V IL － t CRP(13) t RCD(6) t PC(42) t CAS(5) t RAS(1) UT51C164 256K X 16 BIT EDO DRAM t RP(3) ⌇ ⌇ t RSH(12) t CP(43) t CRP(13) UCAS, V LCAS t CAS(5) ⌇ ⌇ t CAS(5) IH － V IL － t ASR(8) t RAH(9) t CSH(4) t CAH (11) t ASC (10) t CAH(11) ROW ADDRESS t RAD(24) t WCS(27) COLUMN ADDRESS t CWL(26) t WCH(28) t WP(29) t t t COLUMN ADDRESS ⌇ ⌇ t CWL(26) t CAR(44) t ASC (10) ⌇ ⌇ COLUMN ADDRESS t CWL(26) t CAH (11) Address V IH － V IL － WCS(27) WCH(28) WP(29) t WCS(27) ⌇ ⌇ t t WCH(28) RWL(31) WE V － IH V IL － ⌇ ⌇ t WP(29) OE V V ⌇ ⌇ IH IL － － t DS(32) t DH (33) OPEN VALID DATA IN ⌇ ⌇ t DS (32) tDH (33) VALID DATA IN t DS (32) t DH (33) DQ VIH V IL － － VALID DATA IN OPEN Don't care Undefined UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 P90005 15  UTRON Rev 1.4 UTRON EDO Mode, X16 (2CAS) Device Timing Diagram ― UT51C164 256K X 16 BIT EDO DRAM EDO Page Mode Read-Write Cycle V IH － V IL － t RCD(6) RAS t RAS(1) t RP(3) t CSH(4) t PCM(50) t CAS(5) t CP(43) t CAS(5) t RSH(12) t CRP(13) t CAS(5) UCAS, V IH － LCAS V IL － t RAD(24) t ASC(10) t RAH(9) t ASC(10) tCAH(11) tCAH (11) t ASC(10) t CAH (11) t CAR(44) t ASR(8) Address V IH － V IL － ROW ADD COLUMN ADDRESS t RWD(39) t CWD(38) COLUMN ADDRESS t CWD(38) tCWL(26) tCWL(26) COLUMN ADDRESS t CWD(38) t CWL (26) t RWL (31) WE V IH － V IL － t AWD(41) t CAA (20) tWP (29) tOAC(17) t AWD(41) t WP (29) tOAC(17) tOEH(35) t CAP (45) t AWD(41) t WP (29) tOAC(17) OE V IH － V IL － t OED(35) t HZ(22) t RAC(19) tCAC (18) t DH(33) tCAA (20) t OED(35) t HZ(22) t CAC (18) tCAP(45) tCAA(20) tDH(33) tDS (32) t OED(35) tHZ(22) tCAC(18) tDH(33) t DS (32) tDS(32) DQ V I/OH － V I/OL － OUT t LZ(21) IN OUT tLZ(21) IN OUT t LZ(21) IN Don' t Care Undefined UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 P90005 16  UTRON Rev 1.4 UTRON EDO Mode, X16 (2CAS) Device Timing Diagram ― Waveforms UT51C164 256K X 16 BIT EDO DRAM of RAS - Only Refresh Cycle t RC(2) t RAS(1) t RP(3) RAS V IH － V IL － tCRP(13) UCAS, V IH － LCAS V IL － tASR(8) tRAH(9) Address V IH － V IL － ROW ADD Note: WE, OE = Don't care Don't care Undefined UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 P90005 17  UTRON Rev 1.4 UTRON EDO Mode, X16 (2CAS) Device Timing Diagram ― UT51C164 256K X 16 BIT EDO DRAM Waveforms of CAS - before - RAS Refresh Counter Test Cycle t RP(3) t RAS(1) RAS V IH － V IL － t CSR(47) t CHR(49) t CP(43) t RSH(12) t CAS(5) UCAS, V IH － LCAS V IL － Address V IH － V IL － Read Cycle WE I/O V IH － V IL － V OH － V OL － t t RCS(7) RRH(15) t RCH(14) t LZ(21) t HZ(22) t RWL(31) DOUT t CWL(26) Write Cycle WE V IH － V IL － t WCS(27) t WCH(28) OE V IH － V IL － t DS(32) t DH(33) DQ V IH － V IL － D IN Don't Care Undefined UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 P90005 18  UTRON Rev 1.4 UTRON EDO Mode, X16 (2CAS) Device Timing Diagram ― UT51C164 256K X 16 BIT EDO DRAM Waveforms of CAS - before - RAS Refresh Cycle t RC(2) t RP(3) t RAS(1) t RP(3) V RAS IH － V IL － t RPC(48) t CP(43) t CSR(47) t CHR(49) UCAS, V IH － LCAS V IL － t HZ(22) DQ V OH － V OL － Note: WE, OE = A 0 - A 8 = Don't care Don't care Undefined UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 P90005 19  UTRON Rev 1.4 UTRON EDO Mode, X16 (2CAS) Device Timing Diagram Waveforms of Hidden Refresh Cycle (Read) t RC(2) t RC(2) t RP(3) t RAS(1) UT51C164 256K X 16 BIT EDO DRAM ― t V RAS IH － V IL － t RCD(6) t CRP(13) t RAS(1) t AR(23) t RSH(12) RP(3) t CHR(49) t CRP(13) UCAS, V IH － LCAS V IL － t ASR(8) t RAD(24) t ASC(10) t RAH(9) t CAH(11) Address V IH － V IL － ROW ADD COLUMN ADDRESS t RRH(15) t RCS(7) WE V IH － V IL － t CAA(20) OE V IH － V IL － t CAC(18) t OAC(17) t RAC(19) t LZ(21) t HZ(22) t HZ(22) DQ V OH － V OL － VALID DATA Don't Care Undefined UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 P90005 20  UTRON Rev 1.4 UTRON EDO Mode, X16 (2CAS) Device Timing Diagram ― Waveforms of Hidden Refresh Cycle (Write) t RC(2) UT51C164 256K X 16 BIT EDO DRAM t t RP(3) RC(2) RAS VIH － VIL － t t CRP(13) t t RCD(6) t t RAS(1) RAS(1) RP(3) AR(23) t RSH(12) t CHR(49) t CRP(13) UCAS, VIH － LCAS VIL － tASR(8) t RAD(24) t ASC(10) t RAH(9) t CAH(11) Address VIH － VIL － ROW ADD t WCS(27) COLUMN ADDRESS t WCH(28) WE VIH － VIL － － OE VIH VIL － t DS(32) t DH(33) DQ VIH － VIL － VALID DATA -IN t DHR(46) don't care Undefined UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 P90005 21  UTRON Rev 1.4 UTRON EDO Mode, X16 (2CAS) Device Timing Diagram ― UT51C164 256K X 16 BIT EDO DRAM Waveforms of EDO-Page-Mode Read-Early-Write Cycle (Pseudo Read-Modify-Write) t RAS t RP V IH － RAS V － IL t t CRP t CSH t t CAS PC t t CP PC t t CP t RSH RCD t CAS CAS t CP UCAS V IH － LCAS V IL － t ASR t AR t RAD t t CAH CAR t RAH ROW ADD tASC t ASC t CAH t ASC t CAH Address V IH － V IL － COLUMN ADDRESS t COLUMN ADDRESS t RCH COLUMN ADDRESS RCS t WCS t WCH WE V IH － V IL － t RAC t CAA t CAC t OE t CAP t CAA t CAC OE V IH － V IL － t DS t DH t COH DQ V OH － VOL － VALID DATA -OUT VALID DATA -OUT VALID DATA -IN Don't care Undefined UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 P90005 22  UTRON Rev 1.4 UT51C164 256K X 16 BIT EDO DRAM PACKAGE OUTLINE DIMENSION 40 pin 400mil SOJ Package Outline Dimension UNIT：MIL SYMBOLS A A1 A2 D E H MIN. 130 0.24 106 430 NOR. 134 110 1025 BSC. 400 BSC. 440 MAX. 138 114 450 UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 P90005 23  UTRON Rev 1.4 40 pin 400mil TSOP-Ⅱ Package Outline Dimension UT51C164 256K X 16 BIT EDO DRAM UNIT SYMBOL MM(BASE) 1.20(MAX) 0.10± 0.05 1.00± 0.05 0.30~0.45 0.13(TYP) 18.41± 0.10 10.16± 0.10 11.76± 0.20 0.80(TYP) 0.50± 0.10 0.80(REF) 0° ~8° A A1 A2 b t D E1 E e L L1 θ UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 P90005 24  UTRON Rev 1.4 UT51C164 256K X 16 BIT EDO DRAM ORDERING INFORMATION PART NO. UT51C164JC-35 UT51C164JC-40 UT51C164JC-50 UT51C164JC-60 UT51C164MC-35 UT51C164MC-40 UT51C164MC-50 UT51C164MC-60 ACCESS TIME (ns) 35 40 50 60 35 40 50 60 PACKAGE 40-PIN SOJ 40-PIN SOJ 40-PIN SOJ 40-PIN SOJ 40-PIN TSOP-Ⅱ 40-PIN TSOP-Ⅱ 40-PIN TSOP-Ⅱ 40-PIN TSOP-Ⅱ UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 P90005 25  UTRON Rev 1.4 UT51C164 256K X 16 BIT EDO DRAM REVISION HISTORY REVISION Rev. 1.0 Rev. 1.1 Rev. 1.2 Rev. 1.3 Rev. 1.4 DESCRIPTION Original. Add 40 pin TSOP-II Package. Add 3.3V range. Revised Datasheet name to be UT51C164/UT51L164. 1. Separated VDD=5V and VDD=3.3V version. 2. Revise symbols “RAS#、CAS#、OE#、WE#” to be “ RAS 、 CAS 、 OE 、 WE ”. DATE Apr 30 ,1999 Jun 7 ,1999 Jul 30,1999 Sep 22,2000 Jan 23,2002 UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 P90005 26