UT54ACTS220

UT54ACTS220 Clock and Wait-State Generation Circuit FEATURES • 1.2µ radiation-hardened CMOS - Latchup immune • High speed • Low power consumption • Single 5-volt supply • Available QML Q or V processes • Flexible package - 14-pin DIP - 14-lead flatpack DESCRIPTION The UT54ACTS220 is designed to be a companion chip to UTMC’s UT69151 SµMMIT family for the purpose of generating clock and wait-state signals. The device contains a divide by two circuit that accepts TTL input levels and drives CMOS output buffers. The chip accepts a 48MHz clock and generates a 24MHz clock. The 48MHz clock can have a duty cycle that varies by ± 20%. The UT54ACT220 generates a 24MHz clock with a ± 5% duty cycle variation. The wait-state circuit generates a single wait-state by delaying the falling edge of DTACK into the S µMMIT. The clock/timing device generates DTACK from the falling edge of input RCS which is synchronized by the falling edge of 24MHz. The S µMMIT drives inputs RCS and DMACK. The devices are characterized over full military temperature range of -55°C to +125°C. LOGIC SYMBOL MRST 48MHz RCS DMACK (10) (6) (9) (8) S CTR1 SRG2 1D S (11) (12) DTACK (13) PINOUTS 14-Pin DIP Top View NC CLKOUT CLKOUT CLKIN NC 48MHz VSS 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VDD 24MHz DTACK TEST MRST RCS DMACK 14-Lead Flatpack Top View NC CLKOUT CLKOUT CLKIN NC 48MHz VSS 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VDD 24MHz DTACK TEST MRST RCS DMACK 24MHz TEST (2) CLKIN (4) (3) CLKOUT CLKOUT Note: 1. Logic symbol in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. 145 RadHard MSI Logic UT54ACTS220 PIN DESCRIPTION Pin Number 2 3 4 6 8 9 10 11 12 13 Pin Name CLKOUT CLKOUT CLKIN 48MHz DMACK RCS MRST TEST DTACK 24MHz Buffered version of CLKIN. Inverted version of CLKIN. Clock Input. This signal can be any arbitrary signal that the user wishes to buffer. 48MHz Clock. The 24MHz clock is created by dividing this signal by two. DMA Acknowledge. This input is generated by the SµMMIT. When high, this signal will cause DTACK output to be forced high. RAM Chip Select. This input is generated by the SµMMIT. Master Reset. This input can be used to preset 24MHz, DTACK and TEST. For normal operation tie MRST to VDD through a resistor. Test output signal. Data Transfer Acknowledge. This signal can be used to drive the DTACK signal of the SµMMIT if the user requires one wait state during the memory transfer. 24MHz Clock. This output runs at half the frequency of the 48MHz input. The falling edge of 24MHz is the signal that latches the DTACK outputs. 24MHz is forced high whenever MRST is low. Properly loaded, 24MHz will have a 50% duty cycle ± 5%. Description FUNCTIONAL TIMING: Single SµMMIT Wait-State For both read and write memory cycles, DTACK is an input to the SµMMIT E and S µMMIT LXE/DXE. A non-wait state memory requires two clock cycles, T1 and T2 of figure 1. For accessing slower memory devices, the UT54ACTS220 holds DTACK to a logical “1”. This results in the stretching of memory cycles by one clock to three clock cycles, T W of figure 1. The SµMMIT E and S µMMIT LXE/DXE samples the DTACK on the rising edge of the 24 MHz clock. If DTACK is not generated before the rising edge of the clock, the SµMMIT E and SµMMIT LXE/DXE extends the memory cycle. 48MHz 24MHz T1 TW T2 DMACK RCS DTACK Figure 1. Functional Timing RadHard MSI Logic 146 UT54ACTS220 LOGIC DIAGRAM 24MHz D Q D Q DTACK 48MHz MRST RCS CK Q RST CK Q PRE D CK Q PRE Q TEST DMACK CLKIN CLKOUT CLKOUT 147 RadHard MSI Logic UT54ACTS220 RADIATION HARDNESS SPECIFICATIONS PARAMETER Total Dose SEU Threshold 1 SEL Threshold Neutron Fluence 2 Notes: 1. Device storage elements are immune to SEU affects. 2. Not tested, inherent of CMOS technology. LIMIT 1.0E6 80 >120 1.0E14 UNITS rad(Si) MeV-cm2/mg MeV-cm2/mg n/cm2 ABSOLUTE MAXIMUM RATINGS SYMBOL VDD VI/O TSTG TJ TLS ΘJC II PD PARAMETER Supply voltage Voltage any pin Storage Temperature range Maximum junction temperature Lead temperature (soldering 5 seconds) Thermal resistance junction to case DC input current Maximum power dissipation LIMIT -0.3 to 7.0 -0.3 to V DD +0.3 -65 to +150 +175 +300 20 ±10 1 UNITS V V °C °C °C °C/W mA W Note: 1.Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS SYMBOL VDD VIN TC 48MHz PARAMETER Supply voltage Input voltage any pin Temperature range Duty Cycle LIMIT 4.5 to 5.5 0 to VDD -55 to + 125 50 ± 20% UNITS V V °C MHz RadHard MSI Logic 148 UT54ACTS220 DC ELECTRICAL CHARACTERISTICS 7 (VDD = 5.0V ±10%; V SS = 0V 6, -55°C < TC < +125°C) SYMBOL VIL VIH IIN VOL1 PARAMETER Low-level input voltage 1 TTL High-level input voltage 1 TTL Input leakage current TTL Low-level output voltage 3 Except CLKOUT/CLKOUT VOH1 VOL2 VOH2 IOS High-level output voltage 3 Except CLKOUT/CLKOUT CLKOUT/CLKOUT Low-level output voltage 3 CLKOUT/CLKOUT High-level output voltage 3 Short-circuit output current 2 ,4 IOL = 100µA IOH = -100µA VO = V DD and VSS VDD = 5.5V IOL1 Output current 10 (Sink), Except CLKOUT/CLKOUT IOH1 Output current 10 (Source), Except CLKOUT/CLKOUT IOL2 CLKOUT/CLKOUT output current10 (Sink) IOH2 CLKOUT/CLKOUT output current10 (Source) IIH Input current high VIN = VDD or VSS VOL = 0.4V VIN = VDD or VSS VOH = V DD - 0.4V VIN = VDD or VSS VOL = 0.4V VIN = VDD or VSS VOH = V DD - 0.4V VIN = VDD or VSS VIN = 5.5V IIL Input current low VIN = VDD or VSS VIN = V SS Ptotal IDDQ Power dissipation 2, 8, 9 Quiescent Supply Current CL = 50pF VDD = 5.5V VIN = VDD or V SS 1.0 10 mW/ MHz µA -1.0 µA +1.0 µA -12 mA 12 mA -8 mA 8 mA 4.25 V +300 mA 0.25 V VDD = 5.5V VIN = VDD or VSS IOL = 8mA, VDD = 4.5V IOL = 100µA IOH = -8mA, V DD = 4.5V 3.15 V 2.25 1 0.4 0.25 CONDITION MIN MAX 0.8 UNIT V V µA V -1 149 RadHard MSI Logic UT54ACTS220 ∆IDDQ Quiescent Supply Current Delta 1.6 mA For input under test VIN = VDD - 2.1V For all other inputs VIN = VDD or VSS VDD = 5.5V ƒ = 1MHz @ 0V ƒ = 1MHz @ 0V CIN COUT Input capacitance 5 Output capacitance 5 15 15 pF pF Notes: 1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: V IH = VIH(min) + 20%, - 0%; V IL = VIL(max) + 0%, - 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are guaranteed to VIH (min) and V IL (max). 2. Supplied as a design limit but not guaranteed or tested. 3. Per MIL-PRF-38535, for current density ≤5.0E5 amps/cm 2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pF/MHz. 4. Not more than one output may be shorted at a time for maximum duration of one second. 5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at frequency of 1MHz and a signal amplitude of 50mV rms maximum. 6. Maximum allowable relative shift equals 50mV. 7. All specifications valid for radiation dose ≤ 1E6 rads(Si). 8. Power does not include power contribution of any TTL output sink current. 9. Power dissipation specified per switching output. 10. This value is guaranteed based on characterization data, but not tested. RadHard MSI Logic 150 UT54ACTS220 AC ELECTRICAL DIAGRAM 48MHz 24MHz RCS T1 TW TW T2 tSUR DTACK tSU tH CLKIN CLKOUT or CLKOUT tPHL or tPLH 151 RadHard MSI Logic UT54ACTS220 AC ELECTRICAL CHARACTERISTICS 2 (VDD = 5.0V ±10%; V SS = 0V1, -55°C < TC < +125°C) SYMBOL tPHL1 tPLH1 tPHL2 tPLH2 tPLH3 tPLH4 tPHL5 tPLH5 tPHL6 tPLH6 tSU 3 tH3 tSUR tWM tWC fMAX PARAMETER 48MHz ↑ to 24MHz ↓ 48MHz ↑ to 24MHz ↑ 24MHz ↓ to DTACK ↓ 24MHz ↓ to DTACK ↑ DMACK ↑ to DTACK ↑ MRST ↓ to 24MHz ↑, DTACK ↑ CLKIN ↓ to CLKOUT ↓ CLKIN ↑ to CLKOUT ↑ CLKIN ↑ to CLKOUT ↓ CLKIN ↓ to CLKOUT ↑ DTACK ↓ to 24MHz ↑, setup time 24MHz ↑ to DTACK ↑, hold time Setup time from RCS ↓ to 24MHz ↓ MRST pulse width low CLKIN pulse width Maximum CLKIN frequency MINIMUM 0 0 0 0 3 3 0 0 0 0 12 20 7 5 12 40 MAXIMUM 15 15 7 6 16 16 11 11 11 11 UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz Notes: 1. Maximum allowable relative shift equals 50mV. 2. All specifications valid for radiation dose ≤ 1E6 rads(Si). 3. Guaranteed by design but not tested. RadHard MSI Logic 152