UT62L25616BS-55LLI

 UTRON Rev. 1.1 256K X 16 BIT LOW POWER CMOS SRAM GENERAL DESCRIPTION The UT62L25616(I) is a 4,194,304-bit low power CMOS static random access memory organized as 262,144 words by 16 bits. The UT62L25616(I) operates from a single 2.7V ~ 3.6V power supply and all inputs and outputs are fully TTL compatible. The UT62L25616(I) is designed for low power system applications. It is particularly suited for use in high-density high-speed system applications. UT62L25616(I) FEATURES Fast access time : 55/70/100 ns CMOS Low operating power Operating current: 45/35/25mA (Icc max) Standby current: 20 uA(TYP.) L-version 3 uA(TYP.) LL-version Single 2.7V~3.6V power supply Operating temperature: Industrial : -40℃~85℃ All inputs and outputs TTL compatible Fully static operation Three state outputs Data retention voltage: 1.5V (min) Data byte control : LB (I/O1~I/O8) UB (I/O9~I/O16) Package : 44-pin 400mil TSOPⅡ 48-pin 6mm × 8mm TFBGA PIN DESCRIPTION SYMBOL A0 - A17 I/O1 - I/O16 CE WE OE LB UB VCC VSS NC DESCRIPTION Address Inputs Data Inputs/Outputs Chip Enable Input Write Enable Input Output Enable Input Lower-Byte Control High-Byte Control Power Supply Ground No Connection FUNCTIONAL BLOCK DIAGRAM A0 A1 A2 A3 A4 A8 A13 A14 A15 A16 A17 I/O1 I/O16 ROW DECODER . MEMORY ARRAY VCC VSS . . 2048 Rows x 128 Columns x 16 bits . . . . I/O CONTROL . . . . . . . . COLUMN I/O CE WE OE LOGIC CONTROL COLUMN DECODER LB UB A9 A10 A11 A12 A5 A6 A7 UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 P80054 1  UTRON Rev. 1.1 256K X 16 BIT LOW POWER CMOS SRAM UT62L25616(I) PIN CONFIGURATION A4 A3 A2 A1 A0 CE I/O1 I/O2 I/O3 I/O4 Vcc Vss I/O5 I/O6 I/O7 I/O8 WE 1 2 3 4 44 43 42 41 A5 A6 A7 OE UB A B C D E F G H LB I/O9 I/O10 OE UB I/O11 I/O12 I/O13 A0 A3 A5 A17 NC A14 A12 A9 A1 A4 A6 A7 A16 A15 A13 A10 A2 CE I/O2 I/O4 I/O5 I/O6 NC I/O1 I/O3 Vcc Vss I/O7 I/O8 NC UT62L25616(I) 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 LB I/O16 I/O15 I/O14 I/O13 Vss Vcc I/O12 I/O11 I/O10 I/O9 NC A8 A9 A10 A11 A12 Vss Vcc I/O15 I/O16 I/O14 NC A8 WE A11 NC A17 A16 A15 A14 A13 1 2 3 4 5 6 TFBGA TSOP II TRUTH TABLE MODE Standby Output Disable Read CE OE X X H X L L L X X X WE LB UB X H X H H L L H L L Write H X L L L L L L L L X X H X H H H L L L X H X H L H L L H L I/O OPERATION I/O1-I/O8 I/O9-I/O16 High – Z High – Z High – Z High – Z High – Z High – Z High – Z High – Z DOUT High – Z High – Z DOUT DOUT DOUT DIN High – Z High – Z DIN DIN DIN SUPPLY CURRENT ISB, ISB1 ISB, ISB1 ICC,ICC1,ICC2 ICC,ICC1,ICC2 ICC,ICC1,ICC2 Note: H = VIH, L=VIL, X = Don't care. UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 P80054 2  UTRON Rev. 1.1 256K X 16 BIT LOW POWER CMOS SRAM UT62L25616(I) ABSOLUTE MAXIMUM RATINGS* PARAMETER Terminal Voltage with Respect to VSS Operating Temperature Industrial Storage Temperature Power Dissipation DC Output Current Soldering Temperature (under 10 secs) SYMBOL VTERM TA TSTG PD IOUT Tsolder RATING -0.5 to 4.6 -40 to 85 -65 to +150 1 50 260 UNIT V ℃ ℃ W mA ℃ *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability. DC ELECTRICAL CHARACTERISTICS (VCC = 2.7V~3.6V, TA = -40℃ to 85℃(I)) PARAMETER SYMBOL Power Voltage VCC Input High Voltage VIH Input Low Voltage VIL Input Leakage Current ILI Output Leakage Current ILO Output High Voltage VOH Output Low Voltage VOL Operating Power ICC Supply Current Average Operation Current Icc1 Icc2 Standby Current (TTL) Standby Current (CMOS) ISB ISB1 MIN. TYP. MAX. UNIT 2.7 3.0 3.6 V 2.0 VCC+0.3 V -0.2 0.6 V -1 1 VSS ≦VIN ≦VCC µA -1 1 VSS ≦VI/O ≦VCC; Output Disabled µA IOH= -1mA 2.2 V IOL= 2.1mA 0.4 V Cycle time=min, 100%duty, 55 30 45 mA 70 25 35 mA I/O=0mA, CE =VIL ; 100 20 25 mA 4 5 mA Cycle time=1µs,100%duty,I/O=0mA, CE ≦0.2V,other pins at 0.2V or Vcc-0.2V, Cycle time=500ns,100%duty,I/O=0mA, 8 10 mA CE ≦0.2V,other pins at 0.2V or Vcc-0.2V, 0.3 0.5 mA CE =VIH, other pins =VIL or VIH, CE =VCC-0.2V, other pins at 0.2V or Vcc-0.2V, -L -LL 20 3 80 25 µA µA TEST CONDITION UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 P80054 3  UTRON Rev. 1.1 256K X 16 BIT LOW POWER CMOS SRAM UT62L25616(I) CAPACITANCE (TA=25℃, f=1.0MHz) PARAMETER Input Capacitance Input/Output Capacitance SYMBOL CIN CI/O MIN. - MAX 6 8 UNIT pF pF Note : These parameters are guaranteed by device characterization, but not production tested. AC TEST CONDITIONS Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Levels Output Load 0V to 3.0V 5ns 1.5V CL = 30pF, IOH/IOL = -1mA / 2.1mA AC ELECTRICAL CHARACTERISTICS (VCC =2.7V~3.6V, TA = -40℃ to 85℃(I)) (1) READ CYCLE SYMBOL UT62L25616(I)-55 UT62L25616(I)-70 UT62L25616(I)-100 UNIT MIN. MAX. MIN. MAX. MIN. MAX. Read Cycle Time tRC 55 70 100 ns Address Access Time tAA 55 70 100 ns Chip Enable Access Time tACE 55 70 100 ns Output Enable Access Time tOE 30 35 50 ns Chip Enable to Output in Low Z tCLZ* 10 10 10 ns Output Enable to Output in Low Z tOLZ* 5 5 5 ns Chip Disable to Output in High Z tCHZ* 20 25 30 ns Output Disable to Output in High Z tOHZ* 20 25 30 ns Output Hold from Address Change tOH 5 5 5 ns tBA 55 70 100 ns , UB Access Time LB tHZB 25 30 40 ns LB , UB to High-Z Output tLZB 0 0 0 ns LB , UB to Low-Z Output (2) WRITE CYCLE SYMBOL UT62L25616(I)-55 UT62L25616(I)-70 UT62L25616(I)-100 UNIT MIN. MAX. MIN. MAX. MIN. MAX. Write Cycle Time tWC 55 70 100 ns Address Valid to End of Write tAW 50 60 80 ns Chip Enable to End of Write tCW 50 60 80 ns Address Set-up Time tAS 0 0 0 ns Write Pulse Width tWP 45 55 70 ns Write Recovery Time tWR 0 0 0 ns Data to Write Time Overlap tDW 25 30 40 ns Data Hold from End of Write Time tDH 0 0 0 ns Output Active from End of Write tOW* 5 5 5 ns Write to Output in High Z tWHZ* 30 30 40 ns tBW 45 60 80 ns , UB Valid to End of Write LB *These parameters are guaranteed by device characterization, but not production tested. PARAMETER PARAMETER UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 P80054 4  UTRON Rev. 1.1 256K X 16 BIT LOW POWER CMOS SRAM UT62L25616(I) TIMING WAVEFORMS READ CYCLE 1 (Address Controlled) (1,2,4) tRC Address tAA tOH tOH DOUT Data Valid READ CYCLE 2 ( CE and OE Controlled) (1,3,5,6) t Address RC CE t AA t ACE t t BA LB , UB BLZ OE t t Dout HIGH-Z CLZ OE t t t OH CHZ OHZ t OLZ HIGH-Z Data Valid t BHZ Notes : 1. WE is HIGH for read cycle. 2. Device is continuously selected CE =VIL. 3. Address must be valid prior to or coincident with CE transition; otherwise tAA is the limiting parameter. 4. OE is LOW. 5. tCLZ, tOLZ, tCHZ and tOHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state. 6. At any given temperature and voltage condition, tCHZ is less than tCLZ, tOHZ is less than tOLZ. UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 P80054 5  UTRON Rev. 1.1 WRITE CYCLE 1 ( WE Controlled) (1,2,3,5) t WC Address t AW CE 256K X 16 BIT LOW POWER CMOS SRAM UT62L25616(I) t AS WE t CW t WP t WR LB , UB t WHZ Dout Din (4) t BW t OW High-Z (4) t DW Data Valid t DH WRITE CYCLE 2 ( CE Controlled) (1,2,5) t WC Address t AW CE WE t AS t CW t WP t WR LB , UB t WHZ Dout t BW High-Z t DW Din Notes : 1. Data Valid t DH WE or CE must be HIGH during all address transitions. 2. A write occurs during the overlap of a low CE and a low WE . 3. During a WE controlled with write cycle with OE LOW, tWP must be greater than tWHZ+tDW to allow the drivers to turn off and data to be placed on the bus. 4. During this period, I/O pins are in the output state, and input signals must not be applied. 5. If the CE LOW transition occurs simultaneously with or after WE high impedance state. 6. tOW and tWHZ are specified with CL = 5pF. LOW transition, the outputs remain in a Transition is measured ±500mV from steady state. P80054 UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 6  UTRON Rev. 1.1 256K X 16 BIT LOW POWER CMOS SRAM UT62L25616(I) DATA RETENTION CHARACTERISTICS (TA = -40℃ to 85℃(I)) PARAMETER Vcc for Data Retention Data Retention Current Chip Disable to Data Retention Time Recovery Time SYMBOL VDR IDR tCDR tR TEST CONDITION CE ≧ VCC-0.2V Vcc=1.5V CE ≧ VCC-0.2V See Data Retention Waveforms (below) MIN. 1.5 -L - LL 0 5 TYP. 1 0.5 MAX. 3.6 50 20 UNIT V µA µA ms ms DATA RETENTION WAVEFORM Data Retention Mode VCC 2.7V VDR ≧ 1.5V CE 2.7V tCDR tR VSS CE ≧ VCC -0.2V UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 P80054 7  UTRON Rev. 1.1 256K X 16 BIT LOW POWER CMOS SRAM UT62L25616(I) PACKAGE OUTLINE DIMENSION 44 pin 400mil TSOP-Ⅱ Package Outline Dimension SYMBOLS A A1 A2 b c D E E1 e L 2D y Θ DIMENSIONS IN MILLMETERS MIN NOM MAX. 1.00 1.20 0.05 0.15 0.95 1.00 1.05 0.30 0.35 0.45 0.12 0.21 18.313 18.415 18.517 11.854 11.836 11.838 10.058 10.180 10.282 0.800 0.40 0.50 0.60 0.805 0.00 0.076 o o 0 5 DIMENSIONS IN INCHS MIN. NOM. MAX. 0.039 0.047 0.002 0.006 0.037 0.039 0.041 0.012 0.014 0.018 0.0047 0.083 0.721 0.725 0.728 0.460 0.466 0.470 0.398 0.400 0.404 0.0315 0.0157 0.020 0.0236 0.0317 0.000 0.003 o o 0 5 UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 θ P80054 8  UTRON Rev. 1.1 48 pin 6mm×8mm TFBGA Outline Dimension 256K X 16 BIT LOW POWER CMOS SRAM UT62L25616(I) UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 P80054 9  UTRON Rev. 1.1 256K X 16 BIT LOW POWER CMOS SRAM UT62L25616(I) ORDERING INFORMATION INDUSTRIAL TEMPERATURE PART NO. UT62L25616MC-55LI UT62L25616MC-55LLI UT62L25616MC-70LI UT62L25616MC-70LLI UT62L25616BS-55LI UT62L25616BS-55LLI UT62L25616BS-70LI UT62L25616BS-70LLI ACCESS TIME (ns) 55 55 70 70 55 55 70 70 STANDBY CURRENT (µA) TYP. 20 3 20 3 20 3 20 3 PACKAGE 44 PIN TSOP-Ⅱ 44 PIN TSOP-Ⅱ 44 PIN TSOP-Ⅱ 44 PIN TSOP-Ⅱ 48 PIN TFBGA 48 PIN TFBGA 48 PIN TFBGA 48 PIN TFBGA UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 P80054 10  UTRON Rev. 1.1 256K X 16 BIT LOW POWER CMOS SRAM UT62L25616(I) REVISION HISTORY REVISION Preliminary Rev. 0.5 Rev. 1.0 DESCRIPTION Original. 1. The symbols CE# and OE# and WE# are revised as. CE and OE and WE . 2. Separate Industrial and Consumer SPEC. 3. Add access time 55ns range. 4. The power supply is revised: 3.3V 3.6V 1. Revised PIN CONFIGURATION : Rev 1.0 : No A17 pin typing error Rev 1.1 : add A17 pin. DATE Mar, 2001 Jul 4,2001 Rev. 1.1 Oct 18,2001 UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 P80054 11  UTRON Rev. 1.1 256K X 16 BIT LOW POWER CMOS SRAM UT62L25616(I) THIS PAGE IS LEFT BLANK INTENTIONALLY. UTRON TECHNOLOGY INC. 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919 P80054 12