VMX1C1020
Datasheet Rev 2.12
Versa Mix 8051 Mixed-Signal MCU
Overview
The VMX51C1020 is a fully integrated mixed-signal microcontroller that provides a “one-chip solution” for a broad range of signal conditioning, data acquisition, processing, and control applications. The VMX51C1020 is based on a powerful single-cycle, RISC-based, 8051 microprocessor with an enhanced MULT/ACCU unit that can be used to perform complex mathematical operations. On-chip analog peripherals such as: an A/D converter, PWM outputs (that can be used as D/A converters), a voltage reference, a programmable current source, an uncommitted operational amplifier, digital potentiometers and an analog switch makes the VMX51C1020 ideal for analog data acquisition applications. The inclusion of a full set of digital interfaces such as an enhanced fully configurable SPI, an I2C interface, UARTs and a J1708/RS-485/RS-422 compatible differential transceiver, enables total system integration.
Feature Set
o o o o o o o o o 8051 Compatible RISC performance Processor. Integrated Debugger 56KB Flash Program Memory 1280 Bytes of RAM MULT/ACCU unit including a Barrel Shifter o Provides DSP capabilities 2 UART Serial Ports 2 Baud Rate Generators for UARTs Differential Transceiver connected to UART1 J1708/RS-485/RS-422 compatible. Enhanced SPI interface (Master/Slave) o Fully Configurable o Controls up to 4 slave devices I2C interface 28 General Purpose I/Os 2 External Interrupt Inputs Interrupt on Port 1 pin change 3, 16-bit Timers/Counters 4 Compare & Capture Units with 3 Capture Inputs 4 PWM outputs, 8-bit / 16-bit resolution 4 ext. + 3 int. Channel 12-bit A/D Converter o Conversion rate up to 10kHz o 0-2.7 Volt Input range Continuous / One-Shot operation o Single or 4-channel automatic sequential conversions On-Chip Voltage Reference Programmable Current Source Operational Amplifier 2 Digital Potentiometers 1 Digitally Controlled Switch Power Saving Features + Clock Control Power-on Reset with Brown-Out Detect W atchdog Timer
o o o o o o o o
Applications
o o o o o Automotive Applications Industrial Controls / Instrumentation Consumer Products Intelligent Sensors Medical Devices o o o o o o o o
FIGURE 1: VMX51C1020 BLOCK DIAGRAM
8051 µPROCESSOR SINGLE CYCLE
I n- Circuit Debugging t h r o u g h U A R T0
FIGURE 2: VMX51C1020 QFP-64 PACKAGE PINOUT
Programmable Current Source 2 UARTs Serial Ports
P3.7 - SCL NC NC
4 8
1 2- BIT A / D CONVERTER
ISRCIN, ISRCOUT, OPOUT are internally connected to A /D Input Multiplexer
5 6 KB Program FLASH
( In -Circuit Programmable )
XTVREF Input
Band gap Reference
1280 Bytes RAM
PGA
(2 5 6 x 8 & 1 k X8 )
AGND INT0 PM RESISRCOUT – TA ISRCIN POT2A POT2B VDDA ADCI3 ADCI2 ADCI1 ADCI0 XTVREF AGND OPOUT
P 3. 6 – S DA V PP P 3. 5 – T1IN P 3.4 – CCU 1 P 3.3 – CCU 0 V DD P 3. 2 – T0IN P3.1 – R X0 P3.0 – TX0 OS C0 OS C1 P 1.7 P 1.6
33 32
A/D inp ut Mu x.
49
P1.5 P1.4 VDD P2.7 – SDI P2.6 – SDO P2.5 – SCK P2.4 – SSP2.3 – CS0P2.2 – CS1P2.1 – CS2P2.0 – CS3DGND INT1 CCU2 P1.3 PWM3 P1.2 PWM2
4 P4 4 WWWp uAs /A s WP 4 O uM M tD s MP P tD D /A M /s 8 / 1 6 bit Resolution
(C a n b e u s e d a s D /A s)
· · · · · ·
Operational Amplifier 1 DIGITALLY CONTROLLED SWITCH
2 Interrupt inputs 2 8 I /O s, Interrupt on P o r t1 c h a n g e 3 Timers , 2 Baud Rate Generators 4 CCU units [M U L T / A C C U] Unit with BARREL SHIFTER
VMX51C1020
+
I
2 DIGITAL POTENTIOMETERS SPI Interface
64 1 16
17
P 0. 1 – T2EX P0.2 – TX1 P0.3 – RX 1 RX 1D + TX1D+ RX 1D TX 1DS W1B S W1A P OT1B P OT1A OP IN + OP IN -
P1. 1 – P WM1 P1. 0 – P WM0 P0.0 – T2I N
J1 7 0 8 /R S 4 8 5 / R S 422 Compatible Transceiver
I ²C B u s Interface
XTAL
Clock Control Unit
Power On Reset Circuit + WatchDog Timer
Ramtron International Corporation 1850 Ramtron Drive Colorado Springs Colorado, USA, 80921
? ? ?
http://www.ramtron.com MCU customer service: 1-800-943-4625, 1-514-871-2447, ext. 208 1-800-545-FRAM, 1-719-481-7000
VMX51C1020
VMX51C1020 Pins Description
Table 1: Pin out description
PIN NAME FUNCTION PIN NAME FUNCTION
39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 I/O - Pulse Width Modulator output 1 I/O - Pulse Width Modulator output 2 I/O - Pulse Width Modulator output 3 Capture and Compare Unit 2 Input Interrupt Input 1 Digital Ground I/O - SPI Chip Enable Output (Master Mode) I/O - SPI Chip Enable Output (Master Mode) I/O - SPI Chip Enable Output (Master Mode) I/O - SPI Chip Enable Output (Master Mode) I/O - SPI Chip Enable Output (Slave Mode) I/O - SPI Clock (Input in Slave Mode) I/O - SPI Data Output Bus I/O - SPI Data Input Bus Digital Supply I/O I/O I/O I/O Oscillator Crystal Output Oscillator Crystal input/External Clock Source Input I/O - Asynchronous UART0 Transmitter Output I/O - Asynchronous UART0 Receiver Input
AGND INT0 PM RESISRCOUT – TA ISRCIN POT2A POT2B VDDA ADCI3 ADCI2 ADCI1 ADCI0 XTVREF AGND OPOUT
P3.2-T0IN VDD P3.3CCU0 P3.4CCU1 P3.5-T1IN VPP P3.6-SDA NC NC P3.7-SCL AGND INT0 PM RESISRCOUTTA ISRCIN POT2A POT2B VDDA ADCI3 ADCI2 ADCI1 ADCI0 XTVREF AGND OPOUT
I/O - Timer/Counter 0 Input 5V Digital I/O - Capture and Compare Unit 0 Input I/O - Capture and Compare Unit 1 Input I/O - Timer/Counter 1 Input Flash Programming Voltage Input I/O - I2C / Prog. Interface Bi-Directional Data Bus Not Connected, leave floating Not Connected I/O - I2C / Prog. Interface Clock Analog Ground External interrupt Input (Negative Level or Edge Triggered) Mode Control Input Hardware Reset Input (Active low) Programmable Current Source Analog Output Programmable Current Source Input Digitally Controlled Potentiometer 2A Digitally Controlled Potentiometer 2B Analog Supply Analog to Digital Converter ext. Input 3 Analog to Digital Converter ext. Input 2 Analog to Digital Converter ext. Input 1 Analog to Digital Converter ext. Input 0 External Reference Voltage Input Analog Ground Output of the Operational Amplifier
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
OPINOPIN+ POT1A POT1B SW1A SW1B TX1DRX1DTX1D+ RX1D+ P0.3-RX1 P0.2-TX1 P0.1T2EX P0.0-T2IN P1.0PWM0 P1.1PWM1 P1.2PWM2 P1.3PWM3 CCU2 INT1 DGND P2.0-CS3P2.1-CS2P2.2-CS1P2.3-CS0P2.4-SSP2.5-SCK P2.6-SDO P2.7-SDI VDD P1.4 P1.5 P1.6 P1.7 OSC1 OSC0 P3.0-TX0 P3.1-RX0
Inverting Input of the Operational Amplifier Non-inverting Input of the Operational Amplifier Digitally Controlled Potentiometer 1A Digitally Controlled Potentiometer 1B Digitally Controlled Switch 1A Digitally Controlled Switch 1B RS-485/RS422 compatible differential Transmitter, Negative side RS-485/RS422 compatible differential Receiver Negative side RS-485/RS422 compatible differential Transmitter, Positive side RS-485/RS422 compatible differential Receiver Positive side I/O - Asynchronous UART1 Receiver Input I/O - Asynchronous UART1 Transmitter Output I/O -Timer/Counter 2 Input I/O -Timer/Counter 2 Input I/O - Pulse Width Modulator output 0
59 60 61 62 63 64
FIGURE 3: VMX51C1020 PINOUT
NC P3.6 – SDA VPP P 3 .5 – T 1 IN P 3 .4 – C C U 1 P 3 .3 – C C U 0 VDD P 3 .2 – T 0 IN P 3 .7 - S C L NC P3.1 – RX0 P3.0 – TX0
38 37
48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 1
47
46
45
44
43
42 41
40
39
OSC0 OSC1 P1.7 P1.6
36 35 34 33 32 31 30 29 28 27
P1.5 P1.4 VDD P2.7 – SDI P2.6 – SDO P2.5 – SCK P2.4 – SSP2.3 – CS0P2.2 – CS1P2.1 – CS2P2.0 – CS3DGND INT1 CCU2 P1.3 PWM3 P1.2 PWM2
VMX51C1020
26 25 24 23 22 21 20 19 18 17
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
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POT1B POT1A O P IN + OPIN -
P 0 .2 – T X 1 P 0 .3 – R X 1 RX1D+ TX1D+ RX1DTX1DSW 1B SW 1A
P1.1 – PWM1 P1.0 – PWM0 P 0 .0 – T 2 IN
P0.1 – T2EX
VMX51C1020
VMX51C1020 Block Diagram
FIGURE 4: VMX51C1020 BLOCK DIAGRAM
8 051 µPROCESSOR SINGLE CYCLE
In-Circuit Debugging through UART0
Programmable Current Source
2 UARTs Serial Ports
A/ D input M ux.
12-BIT A/D CONVERTER
I SRCIN, ISRCOUT, OPOUT are internally connected to A/D Input Multiplexer
56KB Program FLASH
(In-Circuit Programmable )
XTVREF Input
Band gap Reference
1280 Bytes RAM
PGA
(256x8 & 1kX8)
4 PWM D/As 4 PWMPWM D/As 4 4 Outputs PWM D/As 8 / 16 bit Resolution
(Can be used as D/As)
· · · · · ·
Operational Amplifier 1 DIGITALLY CONTROLLED SWITCH
2 Interrupt inputs 28 I/Os, Interrupt on Port1 change 3 Timers, 2 Baud. rate generators 4 CCU units [MULT / ACCU] Unit with BARREL SHIFTER
+
I
2 DIGITAL POTENTIOMETERS SPI Interface
J1708/ RS485/RS422 Compatible Transceiver
I²C Bus Interface
XTAL
Clock Control Unit
Power On Reset Circuit + WatchDog Timer
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VMX51C1020
Absolute Maximum Ratings
VDD to DGND VDDA to DGND AGND to DGND VDD to VDDA ADCI (0-3) to AGND XTVREF to AGND Digital Input Voltage to DGND RS422/485 Minimum and Maximum Voltages –0.3V, +6V -0.3V, +6V –0.3V, +0.3V -0.3V, +0.3V -0.3V, VDDA+0.3V -0.3V, VDDA+0.3V -0.3V, VDD+0.3V -2V, +7V Digital Output Voltage to DGND VPP to DGND Power Dissipation § To +70°C Operating Temperature Range Storage Temperature Range Lead Temperature (soldering, 10sec) –0.3V, VDD+0.3V +13V 1000mW 0° to +70°C –65°C to +110°C +300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Electrical Characteristics
TABLE 2: ELECTRICAL CHARACTERISTICS
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS GENERAL CHARACTERISTICS (VDD = +5V, VDDA = +5V, T A = +25°C, 14.75MHz input clock, unless otherwise noted.) Power Supply Voltage VDD 4.75 5.0 5.5 V VDDA 4.5 5.0 5.5 V Power Supply Current IDD (14.75MHz) 5 45* mA *Depends on clock IDD (1MHz) 0.6 6* speed and peripheral
use and load
Flash Programming Voltage DIGITAL INPUTS Minimum High-Level input Maximum Low-Level input Input Current Input Capacitance DIGITAL OUTPUTS Minimum High-Level Output Voltage Maximum Low-Level Output Voltage Output Capacitance Tri-state Output Leakage Current
IDDA VPP VIH VIL IIN CIN VOH VOL COUT IOZ VDD = +5V VDD = +5V
0.1 11 2.0 0.8 ±0.05 5 4.2 0.2 10
5* 13
V V V µA pF V V
10
ISOURCE = 4mA ISINK = 4mA
15 0.25
Pf µA
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VMX51C1020
ANALOG INPUTS ADCI(0-3) Input Voltage Range ADCI(0-3) Input Resistance ADCI(0-3) Input Capacitance ADCI(0-3) Input Leakage Current Channel-to-Channel Crosstalk
VADCI RADCI CADCI IADCI
0 100 7 TBD
2.7
V Mohms (design) pF nA dB
(design)
-72 (12 bit)
ANALOG OUTPUT TA Output Drive Capabilities (Maximum Load Resistance) VTA=VADCI(0-3) Others 10 Requires buffering 25M 33 133 195 799 50 25 100 7 2.5 1000 100 66 500 205 803 µA (design) µA mV mV MOhms pF Mohms pF % PF pF kOhms
CURRENT SOURCE ISRC Current Drive REFISRC200 IISRC200 ISRC Current Drive REFISRC800 IISRC800 ISRC Feedback voltage 200mV REFISRC200 ISRC Feedback voltage 800mV REFISRC800 ISRC Output Resistance RISRC ISRC Output Capacitance CISRC ISRCIN Input Reference RRESIN Resistance ISRCIN Input Reference CRESIN Capacitance ISRC stability Drift Allowable sensor capacitance between ISRCIN & ISRCOUT Allowable capacitance between ISRCOUT & GND INTERNAL REFERENCE Bandgap Reference Voltage Bandgap Reference Tempco EXTERNAL REFERENCE Input Impedance RXTVREF PGA PGA Gain adjustment ANALOG TO DIGITAL CONVERTER
External Reference, TA=25C, Fosc = 14.75MHz
1.18
1.23V 100 150
1.28
V ppm/°C kOhms
2.11
2.29
ADC Resolution Differential Non linearity Integral Non linearity Full-Scale Error (Gain Error) Offset Error Channel-to-Channel Mismatch Sampling Rate
12 DNL INL ±1.5 +4 ±4 ±1 ±1 10k 2.5k +7 1 30 100mV
-1 All channels, ADCI(0-3) All channels, ADCI(0-3) All channels, ADCI(0-3) Single Channel 1 4 Channels 1 UART1 DIFFERENTIAL TRANSCEIVER COMPATIBLE TO J1708/ RS-485/RS-422 Common mode Input Voltage VcI -2 Input Impedance ZIN Output Drive Current Differential Input
Bits LSB LSB LSB LSB LSB Hz
V MOhms mA mV
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VMX51C1020
OPERATIONAL AMPLIFIER Output Impedance Input Resistance Voltage Gain Unit Gain Bandwidth Load Resistance to Ground Load Capacitance Slew rate Input Offset Voltage Input Voltage Range Common Mode Rejection Ratio Power Supply Rejection Ratio Output Voltage Swing (RL=10k) Short Circuit Current to ground DIGITAL POTENTIOMETERS Number of Steps (8-bit binary weighted) Maximum Resistance Minimum Resistance Step size Inter channel Matching Temperature Coefficient Allowable current (DC) Inherent Capacitance DIGITAL SWITCH Switch on Resistance Input capacitance Voltage range on Pin Allowable current (DC) BROWN OUT / RESET CIRCUIT Brown-out circuit Threshold RES- pin internal Pull-Up
Zout Zin Gv UGBW
20 36 100 5 1 40 7 +/- 2 DC Taken at 1kHz Taken at 1kHz (20dB/decade) 0 83 75 -75 (Vdd) 25mV 86 256 28k 485 105 30k 510 115 1 0.16 3 50 4 0 5 5 4.0 20 100 32k 535 130 -94 (Vss) 4.975 4 99
SR VIO VI® CMRRdc CMRR1kHz PSRR VO (P-P) IIC
mOhms GOhms dB MHz KOhms pF V/µs (Design) mV V (Design) dB dB Design) dB (Design) V mA (Design) steps Ohms Ohms Ohms % %/°C mA pF Ohms (+/-10%) pF V mA V KOhms
5
3.7
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VMX51C1020
Detailed Description
The following sections will describe VMX51C1020’s architecture and peripherals.
FIGURE 5: INTERFACE DIAGRAM FOR THE VMX51C1020
VERSA MIX
Memory Organization
the Figure 6 shows the memory organization of the VMX51C1020. At power-up/reset, the code is executed from the 56Kx8 Flash memory mapped into the processor’s internal Program space.
TIMERS
+5V Digital +5V Analog
VDD VDDA AGND DGND
T0IN T1IN T2IN T2EX
UART 0 EXTERNAL A/D INPUTS ADCI0 ADCI1 ADCI2 ADCI3
UART 0 INTERFACE UART 1 INTERFACE UART1 DIFF. TRANSCEIVER J1708/RS-485 / RS422 COMPARE AND CAPTURE UNITS INPUTS
UART 1
CURRENT SOURCE
ISRCOUT ISRCIN
DIFFERENTIAL TRANSCEIVER
DIGITAL SWITCH
SW1A SW1B
CCU0 CCU1 CCU2
A 1KB block of RAM is also mapped into the external data memory of the VMX51C1020. This block can be used as general-purpose scratch pad or storage memory. A 256 byte block of RAM is mapped to the internal data memory space. This block of RAM is broken into 2 sub-blocks, with the upper block accessible via indirect addressing and the lower block accessible via both direct and indirect addressing. The following figure describes the access to the lower block of 128 bytes.
FIGURE 7: LOWER 128 BYTES BLOCK INTERNAL MEMORY MAP
I/O RESET RESOPOUT OPINOPIN+ POT1A POT1B POT2A POT2B PWM0 PWM1 PWM2 PWM3 SCL SDA INT0 INT1 SDI SDO SCK SSCS0CS1CS2CS3-
I/Os
OP-AMP
I2C INTERFACE
EXTERNAL INTERRUPTS
POTENTIOMETERS
PWM OUTPUTS
SPI INTERFACE
LOWER 128 BYTES OF INTERNAL DATA MEMORY 7Fh DIRECT RAM 30h 2Fh REGISTER BANK SELECT The value of the RS1, RS0 bits of PSW SFR Register (D0h) defines the selected R0 -R7 Register Bank 20h 1Fh 18h 17h 10h 0Fh 08h 07h 00h BITADDRESSABLE REGISTERS 11h 10h 01h 00h BANK 3 BANK 2 BANK 1 BANK 0
OSC0 OSC1
FIGURE 6: MEMORY ORGANIZATION OF THE VMX51C1020
INTERNAL PROGRAM MEMORY SPACE DFFFh 56KB FLASH MEMORY 8051 COMPATIBLE µ-PROCESSOR FFh INTERNAL DATA MEMORY SPACE 128 Bytes SFR SPACE RAM PERIPHERALS (INDIRECT (DIRECT ADDRESSING ADDRESSING) FFh
0000h EXTERNAL DATA MEMORY SPACE 03FFh 1KB SRAM 0000h
80h 7Fh
80h
128 Bytes RAM (DIRECT & INDIRECT 00h ADDRESSING)
The SFR (Special Function Register) space is also mapped into the upper 128 bytes of internal data memory space. This SFR space is only accessible using direct-access. The SFR space provides the interface to all the on-chip peripherals. This interfacing is illustrated in Figure 8.
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VMX51C1020
FIGURE 8: SFR ORGANIZATION
ADC CONTROL SPI BUS DIFF TRANSCEIVER INTERNAL DATA MEMORY SPACE FFH SFR SPACE PERIPHERALS (DIRECT ADDRESSING) CLOCK CONTROL I2C BUS PERIPHERAL INTERRUPTS MAC I/O CONTROL 8051 PROCESSOR PERIPHERALS
TABLE 5: (DPH1) DATA POINTER HIGH 1 - SFR 85H
15 7
14 6
13 5
12 11 DPH1 [7:0] 4 3 DPL1 [7:0]
10 2
9 1
8 0
TABLE 6: (DPL1) DATA POINTER LOW 1 - SFR 84H
Bit 15-8 7-0 7 0 Bit 7-1 0
Mnemonic DPH1 DPL1 6 0 5 0
Function Data Pointer 1 MSB. Data Pointer 1 LSB. 4 0 3 0 2 0 1 0 0 SEL
80H
TABLE 7: (DPS) DATA POINTER SELECT REGISTER - SFR 86H
Mnemonic 0 SEL
Function Always zero 0 = DPTR0 is selected 1 = DPTR1 is selected Used to toggle between both data pointers
Dual Data Pointers The VMX51C1020 includes two data pointers. The first data pointer (DPTR0) is mapped into SFR locations 82h and 83h and the second data pointer (DPTR1) mapped into SFR locations 84h and 85h. The SEL bit in the data pointer select register, DPS (SFR 86h), selects which data pointer is active. When SEL = 0, instructions that use the data pointer will use DPL0 and DPH0. When SEL = 1, instructions that use the DPTR will use DPL1 and DPH1. SEL is located in bit 0 of the DPS (SFR location 86h - the remaining bits of SFR location 86h are un-used. All DPTR-related instructions use the currently selected data pointer. In order to switch the active pointer, toggle the SEL bit. The fastest way to do so is to use the increment instruction (INC DPS). The use of the two data pointers can significantly increase the speed of moving large blocks of data because only one instruction is needed to switch from a source address and destination address. The SFR locations and register representations related to the dual data pointers are outlined as follows:
TABLE 3: (DPH0) DATA POINTER HIGH 0 - SFR 83H
MPAGE Register The MPAGE register controls the upper 8 bits of the targeted address when the MOVX instruction is used for external RAM data transfer. This allows access to the entire external RAM content without using the Data Pointer.
TABLE 8: (MPAGE) MEMORY PAGE - SFR CF H
7
6
5
4
3 2 MPAGE [7:0]
1
0
User Flags The VMX51C1020 provides an SFR register that gives the user the ability to define software flags. Each bit of this register is individually addressable. This register may also be used as a generalpurpose storage location. Thus, the user flag feature allows the VMX51C1020 to better adapt to each specific application. This register is located at SFR address F8h
TABLE 9: (USERFLAGS) USER FLAG - SFR F8H
7 UF7
6 UF6
5 UF5
4 UF4
3 UF3
2 UF2
1 UF1
0 UF0
15
14
13
12 11 DPH0 [7:0] 4 3 DPL0 [7:0]
10
9
8
TABLE 4: (DPL0) DATA POINTER LOW 0 - SFR 82H
7
6
5
2
1
0
Bit 15-8 7-0
Mnemonic DPH0 DPL0
Function Data Pointer 0 MSB Data Pointer LSB.
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VMX51C1020
Instruction Set
All VMX51C1020 instructions are function and binary code compatible with the industry standard 8051. However, the timing of instructions may be different. The following two tables describe the instruction set of the VMX51C1020.
TABLE 10: LEGEND FOR INSTRUCTION SET TABLE Symbol Function A Accumulator Rn Register R0-R7 Direct Internal register address @Ri Internal register pointed to by R0 or R1 (except MOVX) rel Two's complement offset byte bit Direct bit address #data 8-bit constant #data 16 16-bit constant addr 16 16-bit destination address addr 11 11-bit destination address TABLE 11: VMX51C1020 INSTRUCTION SET
Mnemonic Arithmetic instructions ADD A, Rn ADD A, direct ADD A, @Ri ADD A, #data ADDC A, Rn ADDC A, direct ADDC A, @Ri ADDC A, #data SUBB A, Rn SUBB A, direct SUBB A, @Ri SUBB A, #data INC A INC Rn INC direct INC @Ri DEC A DEC Rn DEC direct DEC @Ri INC DPTR MUL AB DIV AB DA A Logical Instructions ANL A, Rn ANL A, direct ANL A, @Ri ANL A, #data ANL direct, A ANL direct, #data ORL A, Rn ORL A, direct ORL A, @Ri ORL A, #data ORL direct, A ORL direct, #data XRL A, Rn XRL A, direct XRL A, @Ri XRL A, #data XRL direct, A XRL direct, #data CLR A CPL A SWAP A RL A RLC A RR A RRC A AND register to A AND direct byte to A AND data memory to A AND immediate to A AND A to direct byte AND immediate data to direct byte OR register to A OR direct byte to A OR data memory to A OR immediate to A OR A to direct byte OR immediate data to direct byte Exclusive-OR register to A Exclusive-OR direct byte to A Exclusive-OR data memory to A Exclusive-OR immediate to A Exclusive-OR A to direct byte Exclusive-OR immediate to direct byte Clear A Compliment A Swap nibbles of A Rotate A left Rotate A left through carry Rotate A right Rotate A right through carry 1 2 1 2 2 3 1 2 1 2 2 3 1 2 1 2 2 3 1 1 1 1 1 1 1 1 2 2 2 3 4 1 2 2 2 3 4 1 2 2 2 3 4 1 1 1 1 1 1 1 Miscellaneous Instruction NOP No operation 1 1 Add register to A Add direct byte to A Add data memory to A Add immediate to A Add register to A with carry Add direct byte to A with carry Add data memory to A with carry Add immediate to A with carry Subtract register from A with borrow Subtract direct byte from A with borrow Subtract data mem from A with borrow Subtract immediate from A with borrow Increment A Increment register Increment direct byte Increment data memory Decrement A Decrement register Decrement direct byte Decrement data memory Increment data pointer Multiply A by B Divide A by B Decimal adjust A 1 2 1 2 1 2 1 2 1 2 1 2 1 1 2 1 1 1 2 1 1 1 1 1 1 2 2 2 1 2 2 2 1 2 2 2 1 2 3 3 1 2 3 3 1 5 5 1 Description Size (bytes) Instr. Cycles Mnemonic Data Transfer Instructions MOV A, Rn MOV A, direct MOV A, @Ri MOV A, #data MOV Rn, A MOV Rn, direct MOV Rn, #data MOV direct, A MOV direct, Rn MOV direct, direct MOV direct, @Ri MOV direct, #data MOV @Ri, A MOV @Ri, direct MOV @Ri, #data MOV DPTR, #data16 MOVC A, @A+DPTR MOVC A, @A+PC MOVX A, @Ri MOVX A, @DPTR MOVX @Ri, A MOVX @DPTR, A PUSH direct POP direct XCH A, Rn XCH A, direct XCH A, @Ri XCHD A, @Ri Branching Instructions ACALL addr 11 LCALL addr 16 RET RETI AJMP addr 11 LJMP addr 16 SJMP rel JC rel JNC rel JB bit, rel JNB bit, rel JBC bit, rel JMP @A+DPTR JZ rel JNZ rel CJNE A, direct, rel CJNE A, #data, rel CJNE Rn, #data, rel CJNE @Ri, #data, rel DJNZ Rn, rel DJNZ direct, rel Bit Operations CLR C CLR bit SETB C SETB bit CPL C CPL bit ANL C,bit ANL C, /bit ORL C,bit ORL C, /bit MOC c,bit MOV bit,C Clear carry flag Clear direct bit Set carry flag Set direct bit Complement carry Flag Complement direct bit Logical AND direct bit to carry flag Logical AND between /bit and carry flag Logical OR bit to carry flag Logical OR /bit to carry flag Copy direct bit location to carry flag Copy carry flag to direct bit location 1 2 1 2 1 2 2 2 2 2 2 2 1 3 1 3 1 3 2 2 2 2 2 3 Absolute call to subroutine Long call to subroutine Return from subroutine Return from interrupt Absolute jump unconditional Long jump unconditional Short jump (relative address) Jump on carry = 1 Jump on carry = 0 Jump on direct bit = 1 Jump on direct bit = 0 Jump on direct bit = 1 and clear Jump indirect relative DPTR Jump on accumulator = 0 Jump when accumulator not equal to 0 Compare A, direct JNE relative Compare A, immediate JNE relative Compare reg, immediate JNE relative Compare ind, immediate JNE relative Decrement register, JNZ relative Decrement direct byte, JNZ relative 2 3 1 1 2 3 2 2 2 3 3 3 1 2 2 3 3 3 3 2 3 6 6 4 4 3 4 3 3 3 4 4 4 2 3 3 4 4 4 4 3 4 Move register to A Move direct byte to A Move data memory to A Move immediate to A Move A to register Move direct byte to register Move immediate to register Move A to direct byte Move register to direct byte Move direct byte to direct byte Move data memory to direct byte Move immediate to direct byte Move A to data memory Move direct byte to data memory Move immediate to data memory Move immediate 16 bit to data pointer Move code byte relative DPTR to A Move code byte relative PC to A Move external data (A8) to A Move external data (A16) to A Move A to external data (A8) Move A to external data (A16) Push direct byte onto stack Pop direct byte from stack Exchange A and register Exchange A and direct byte Exchange A and data memory Exchange A and data memory nibble 1 2 1 2 1 2 2 2 2 3 2 3 1 2 2 3 1 1 1 1 1 1 2 2 1 2 1 1 1 2 2 2 2 4 2 3 3 4 4 3 3 5 3 3 3 3 3-10 3-10 4-11 4-11 4 3 2 3 3 3 Description Size (bytes) Instr. Cycles
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VMX51C1020
Special Function Registers
The Special Function Registers (SFRs) control several features of the VMX51C1020. Many of the VMX51C1020 SFRs are identical to the standard 8051 SFRs. However, there are additional SFRs that control the VMX51C1020’s specific peripheral features that are not available in the standard 8051.
TABLE 12: SPECIAL FUNCTION REGISTERS
SFR Register P0 SP DPL0 DPH0 DPL1 DPH1 DPS PCON TCON* TMOD TL0 TL1 TH0 TH1 Reserved Reserved
P1*
IRCON
ANALOGPWREN
SFR Adrs 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h
Bit 7 0 SMOD TF1 GATE1 -
Bit 6 0 TR1 CT1 -
Bit 5 0 TF0 M11 -
Bit 4 0 TR0 M01 -
Bit 3 0 GF1 IE1 GATE0 -
Bit 2 0 GF0 IT1 CT0 -
Bit 1 0 STOP IE0 M10 -
Bit 0 SEL IDLE IT0 M00 -
Reset Value 1111 1111b 0000 0111b 0000 0000b 0000 0000b 0000 0000b 0000 0000b 0000 0000b 0000 0000b 0000 0000b 0000 0000b 0000 0000b 0000 0000b 0000 0000b 0000 0000b 0000 0000b 0000 0000b 1111 1111b
0000 0000b
T2EXIF
T2IF
ADCIF/ COMPINT3
MACIF/ COMPINT2
I2CIF/ COMPINT1
SPIRXIF/ COMPINT0
SPITXIF
Reserved
DIGPWREN CLKDIVCTRL ADCCLKDIV S0RELL S0RELH S0CON* S0BUF IEN2 P0PINCFG P1PINCFG P2PINCFG P3PINCFG PORTIRQEN P2* PORTIRQSTAT ADCCTRL
ADCCONVRLOW ADCCONVRMED
ADCCONVRHIGH
ADCD0LO ADCD0HI IEN0* ADCD1LO ADCD1HI ADCD2LO ADCD2HI ADCD3LO ADCD3HI Reserved P3* Reserved Reserved BGAPCAL PGACAL INMUXCTRL OUTMUXCTRL SWITCHCTRL IP0* IP1 DIGPOT1
92h OPAMPEN DIGPOTEN ISRCSEL ISRCEN TAEN ADCEN PGAEN BGAPEN UART1DIFFEN UART1EN 93h T2CLKEN WDOGEN MACEN I2CEN SPIEN UART0EN IRQNORMSPD MCKDIV_3 MCKDIV_2 MCKDIV_1 MCKDIV_0 94h SOFTRST 95h 96h 97h 0 0 0 0 0 0 98h S0M0 S0M1 MPCE0 R0EN T0B8 R0B8 T0I R0I 99h 9Ah S1IE 9Bh P07IO P06IO P05IO P04IO P0.3/RX1INE P0.2/TX1OE P0.1/T2EXINE P0.0/T2INE P1.3/PWM3OE P1.2/PWM2OE P1.1/PWM1OE P1.0/PWM0OE 9Ch P1.7 P1.6 P1.5 P1.4 9Dh P2.7/SDIEN P2.6/SDOEN P2.5/SCKEN P2.4/SSEN P2.3/CS0EN P2.2/CS1EN P2.1/CS2EN P2.0/CS3EN 9Eh P3.7/MSCLEN P3.6/MSDAEN P3.5/T1INEN P3.4/CCU1EN P3.3/CCU0EN P3.2/T0INEN P3.1/RX0EN P3.0/TX0EN 9Fh P17IEN P16IEN P15IEN P14IEN P13IEN P12IEN P11IEN P10IEN A0h A1h P17ISTAT P16ISTAT P15ISTAT P14ISTAT P13ISTAT P12ISTAT P11ISTAT P10ISTAT A2h ADCIRQCLR XVREFCAP 1 ADCIRQ ADCIE ONECHAN CONT ONESHOT A3h A4h A5h A6h A7h ADCD0HI_3 ADCD0HI_2 ADCD0HI_1 ADCD0HI_0 A8h EA WDT T2IE S0IE T1IE INT1IE T0IE INT0IE A9h AAh ADCD1HI_3 ADCD1HI_2 ADCD1HI_1 ADCD1HI_0 ABh ACh ADCD2HI_3 ADCD2HI_2 ADCD2HI_1 ADCD2HI_0 ADh AEh ADCD3HI_3 ADCD3HI_2 ADCD3HI_1 ADCD3HI_0 AFh B0h B1h B2h B3h B4h ADCINSEL_2 ADCINSEL_1 ADCINSEL_0 AINEN_3 AINEN_2 AINEN_1 AINEN_0 B5h TAOUTSEL_2 TAOUTSEL_1 TAOUTSEL_0 B6h B7h SWITCH1_3 SWITCH1_2 SWITCH1_1 SWITCH1_0 B8h UF8 WDTSTAT IP0.5 IP0.4 IP0.3 IP0.2 IP0.1 IP0.0 B9h IP1.5 IP1.4 IP1.3 IP1.2 IP1.1 IP1.0 BAh -
0000 0000b 0000 0000b 0000 0000b 0000 1100b 11011001b 0000 0011b 0000 0000b 0000 0000b 0000 0000b 0000 0000b 0000 0000b 0000 0000b 0000 0000b 0000 0000b 1111 1111b 0000 0000b 0000 0000b 0000 0000b 0000 0000b 0000 0000b 0000 0000b 0000 0000b 0000 0000b 0000 0000b 0000 0000b 0000 0000b 0000 0000b 0000 0000b 0000 0000b 0000 0000b 1111 1111b 1101 0001b 0000 0000b Cal. Vector Cal. Vector
0000 0000b
0000 0000b 0000 0000b 0000 0000b 0000 0000b 0000 0000b
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VMX51C1020
SFR Register DIGPOT2 ISRCCAL1 ISRCCAL2 S1RELL S1RELH S1CON* S1BUF CCL1 CCH1 CCL2 CCH2 CCL3 CCH3 T2CON* CCEN CRCL CRCH TL2 TH2 Reserved MPAGE P SW* Reserved
U0BAUD WDTREL I2CCONFIG I2CCLKCTRL I2CCHIPID I2CIRQSTAT I2CRXTX Reserved ACC* SPIRX3TX0 SPIRX2TX1 SPIRX1TX2 SPIRX0TX3 SPICTRL SPICONFIG SPISIZE IEN1* SPIIRQSTAT Reserved
MACCTRL1
MACC0 MACC1 MACC2 MACC3 B* MACCTRL2 MACA0 MACA1 MACRES0 MACRES1 MACRES2 MACRES3 USERFLAGS* MACB0 MACB1
MACSHIFTCTRL
MACPREV0 MACPREV1 MACPREV2 MACPREV3 * Bit addressable
SFR Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Value Adrs BBh 0000 0000b BCh PGACAL0 ISRCCAL1_6 ISRCCAL1_5 ISRCCAL1_4 ISRCCAL1_3 ISRCCAL1_2 ISRCCAL1_1 ISRCCAL1_0 Cal. Vector BDh ISRCCAL2_6 ISRCCAL2_5 ISRCCAL2_4 ISRCCAL2_3 ISRCCAL2_2 ISRCCAL2_1 ISRCCAL2_0 Cal. Vector BEh 0000 0000b BFh 0000 0000b C0h S1M reserved MPCE1 R1EN T1B8 R1B8 T1I R1I 0000 0000b C1h 0000 0000b C2h 0000 0000b C3h 0000 0000b C4h 0000 0000b C5h 0000 0000b C6h 0000 0000b C7h 0000 0000b C8h T2PS T2PSM T2SIZE T2RM1 T2RM0 T2CM T2IN1 T2IN0 0000 0000b C9h COCAH3 COCAL3 COCAH2 COCAL2 COCAH1 COCAL1 COCAH0 COCAL0 0000 0000b CAh 0000 0000b CBh 0000 0000b CCh 0000 0000b CDh 0000 0000b CEh CFh 0000 0000b D0h CY AC F0 RS1 RS0 OV reserved P 0000 0001b D1h D1h-D4h =FFh D5h-D7h = 00h To D7 D8h BAUDSRC 0000 0000b D9h PRES WDTREL_6 WDTREL_5 WDTREL_4 WDTREL_3 WDTREL_2 WDTREL_1 WDTREL_0 0000 0000b DAh I2CMASKID I2CRXOVIE I2CRXDAVIE I2CTXEMPIE I2CMANACK I2CACKMODE I2CMSTOP I2CMASTER 0000 0010b DBh 0000 0000b DCh I2CID_6 I2CID_5 I2CID_4 I2CID_3 I2CID_2 I2CID_1 I2CID_0 I2CWID 0100 0010b I2CSDA DDh I2CGOTSTOP I2CNOACK I2CDATACK I2CIDLE I2CRXOV I2CRXAV I2CTXEMP 0010 1001b DEh 0000 0000b DFh 0000 0000b E0h 1110 0000b E1h 0000 0000b E2h 0000 0000b E3h 0000 0000b E4h 0000 0000b E5h SPICK_2 SPICK_1 SPICK_0 SPICS_1 SPICS_0 SPICKPH SPICKPOL SPIMA_SL 0000 0001b E6h SPICSLO FSONCS3 SPI LOAD SPIRXOVIE SPIRXAVIE SPITXEMPIE 0000 0000b E7h 0000 0111b E8h T2EXIE SWDT ADCPCIE MACOVIE I2CIE SPIRXOVIE SPITEIE reserved 0000 0000b SPITXEMPTO SPISLAVESEL E9h SPISEL SPIOV SPIRXAV SPITXEMP 00011001b EAh 0000 0000b EBh LOADPREV PREVMODE OVMODE OVRDVAL ADDSRC_1 ADDSRC_0 MULCMD_1 MULCMD_0 0000 0000b ECh 0000 0000b EDh 0000 0000b EEh 0000 0000b EFh 0000 0000b F0h 0000 0000b F1h MACCLR2_2 MACCLR2_1 MACCLR2_0 MACOV32IE MACOV16 MACOV32 0000 0000b F2h 0000 0000b F3h 0000 0000b F4h 0000 0000b F5h 0000 0000b F6h 0000 0000b F7h 0000 0000b F8h UF7 UF6 UF5 UF4 UF3 UF2 UF1 UF0 0000 0000b F9h 0000 0000b FAh 0000 0000b FBh SHIFTMODE ALSHSTYLE SHIFTAMPL_5 SHIFTAMPL_4 SHIFTAMPL_3 SHIFTAMPL_2 SHIFTAMPL_1 SHIFTAMPL_0 0000 0000b FCh 0000 0000b FDh 0000 0000b FEh 0000 0000b FFh 0000 0000b
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VMX51C1020
Peripheral Activation Control
Digital Peripheral Power Enable In order to save power upon reset, many of the digital peripherals of the VMX51C1020 are not activated. The peripherals affected by this feature are: o Timer 2 / Port1 o Watchdog Timer o MULT/ACCU unit o I²C interface o SPI interface o UART0 o UART1 o Differential Transceiver Before using any of the above-listed peripherals, they must first be enabled by setting the corresponding bit of the DIGPWREN SFR register to 1. The same rule applies when accessing a given peripheral’s SFR register(s). The targeted peripheral must have been powered on (enabled) first, otherwise the SFR register content will be ignored The following table shows the structure of the DIGPWREN register.
TABLE 13: (DIGPWREN) DIGITAL PERIPHERALS POWER ENABLE REGISTER - SFR 93H
Analog Peripheral Power Enable The analog peripherals, specifically, the op-amp digital potentiometer, current source and analog to digital converter, have a shared dedicated register used for enabling and disabling these peripherals. By default, these peripherals are powered down when the device is reset.
TABLE 14: (ANALOGPWREN) ANALOG PERIPHERALS POWER ENABLE REGISTER SFR 92H
7 OPAMPEN 3 TAEN Bit 7
6 DIGPOTEN 2 ADCEN
5 ISRCSEL 1 PGAEN
4 ISRCEN 0 BGAPEN
Mnemonic OPAMPEN
6
DIGPOTEN
5 4 3 2 1 0
ISRCSEL ISRCEN TAEN ADCEN PGAEN BGAPEN
Function 1 = User Op-Amp Enable 0 = User Op-Amp Disable 1 = Digital Potentiometer and Switch Enable 0 = Digital Potentiometer and Switch Disable 0 = ISRC with 200mV feedback 1 = ISRC with 200mV feedback 1 = ISRC Output Enable 0 = ISRC Output Disable 1 = TA Output Enable 0 = TA Output Disable 1 = ADC Enable 0 = ADC Disable 1 = PGA Enable 0 = PGA Disable 1 = Bandgap Enable 0 = Bandgap Disable
Note:
7 T2CLKEN 3 SPIEN Bit 7
6 WDOGEN 2 UART1DIFFEN
5 MACEN 1 UART1EN
4 I2CEN 0 UART0EN
The SFR registers associated with all analog peripherals are activated when one or more analog peripherals are enabled.
Mnemonic T2CLKEN
6 5 4 3 2 1 0
WDOGEN MACEN I2CEN SPIEN UART1DIFFEN UART1EN UART0EN
Function Timer 2 / PWM Enable 0 = Timer 2 CLK stopped 1 = Timer 2 CLK Running Watchdog Enable 0 = Watchdog Disable 1 = Watchdog Enable 1 = MULT/ACCU Unit Enable 0 = MULT/ACCU Unit Disable 1= I2C Interface Enable 0 = I2C Interface Disable
This bit is merged with CLK STOP bit
1 = SPI interface is Enable 0 = SPI interface is Disable UART1 Differential mode 0 = Disable 1 = Enable 0 = UART1 Disable 1 = UART1 Enable 0 = UART0 Disable 1 = UART0 Enable
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VMX51C1020
General Purpose I/O
The VMX51C1020 provides 28 general-purpose I/O pins. The I/Os are shared with digital peripherals and can be configured individually. At Reset, all the VMX51C1020 I/O ports are configured as Inputs The I/O Ports are bi-directional and the CPU can write or read data through any of these ports.
FIGURE 10: T YPICAL I/O VOUT VS. SOURCE CURRENT
5.00
4.90
I/O output voltage (Volts)
4.80
4.70
4.60
4.50
I/O Port Structure
The VMX51C1020 I/O port structure is shown in the following figure.
FIGURE 9 – I/O PORT STRUCTURE
0.40
0.0
2.0
4.0
6.0
8.0
10.0
I/O current source (mA)
FIGURE 11: T YPICAL I/O VOUT VS. SINK CURRENT
0.50
OE
VCC
VCC
I/O output voltage (Volts)
0.30
0.20
Driver
I/O Control logic
0.10
I/O
TTL
0.00 0.0 2.0 4.0 6.0 8.0 10.0
I/O current sink (mA)
Each I/O pin includes pull-up circuitry (represented by the internal pull-up resistor) and a pair of internal protection diodes connected to VCC and ground, providing ESD protection. The I/O operational configuration is defined in the I/O control logic block.
The maximum recommended driving current of a single I/O on a given port is 10mA. The recommended limit when more than one I/O on a given port is driving current is 5mA on each I/O. The total current drive of all I/O ports should be limited to 40mA The following figure shows typical I/O rise time when driving a 20pF capacitive load. In this case, rise time is about 14ns.
FIGURE 12: I/O RISE T IME WITH A 20PF LOAD
I/O Port Drive Capability
Each I/O port pin, when configured as an output is able to source or sink up to 4mA. The following graphs show typical I/O output voltage vs. source and I/O output voltage versus sink current.
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VMX51C1020
Input Voltage vs. Ext. device sink
The I/Os of the VMIX, when configured as Inputs, include an internal pull-up resistor made of a transistor that ensures the level present at the input is stable when the I/O pin is unconnected. Due to the presence of the pull-up resistor on the digital inputs, the external device driving the I/O must be able to sink enough current to bring the I/O pin low. The following figure shows the VMX51C1020 Input port voltage vs. external device sink current.
FIGURE 13: INPUT PORT VOLTAGE
VS . EXT DEVICE SINK CURRENT
The following registers are used to configure each of the ports as either general-purpose input, output or alternate peripheral function.. For example, when bit 5 of Port 2 is configured as an output, it will output the SCK signal if the SPI interface is enabled and working. The only exception to this rule is the I2C Clock and data bus signals. In these two cases, the VMX51C1020 configures the pins automatically as inputs or outputs. The P0PINCFG register controls the I/O access to UART1, the Timer 2 input and output, as well as defines the direction of the P0 when used as general purpose I/O.
TABLE 15: (P0PINCFG) PORT 0 PORT CONFIGURATION REGISTER - SFR 9BH
7
P07IO
6
P06IO
5
P05IO
4
P04IO
3
5.0
2
P0.2/TX1OE
1
P0.1/T2EXINE
0
P0.0/T2INE
P0.3/RX1INE
4.0
I/O Input Voltage (Volts)
Bit 7:4 3
Mnemonic P0xIO P0.3/RX1INE
3.0
2.0
2
P0.2/TX1OE
1.0
1
0.0 0 20 40 60 80 100 120 140 160 180
P0.1/T2EXINE
Ext. device sink current (uA)
0
P0.0/T2INE
I/O Port Configuration Registers
The VMX51C1020’s I/O port operation is controlled by two sets of four registers which are: o The Port Pin Configuration registers o The Port Access registers The port pin configuration registers combined with specific peripheral configuration will define if a given pin acts as a general purpose I/O or if it provides alternate peripheral functionality. Before using a peripheral that is shared with I/Os, the pin corresponding to the peripheral output must be configured as an output and the pins that are shared with the peripheral inputs must be configured as inputs.
Function Unavailable on VMX51C1020 0: General purpose input or UART1 RX 1: General purpose output When using UART1 you must set this bit to 0. 0: General purpose input 1: General purpose output or UART1 TX When using UART1 you must set this bit to 1. 0: General purpose input or Timer 2 EX 1: General purpose output When using Timer 2EX input you must set this bit to 0. 0: General purpose input or Timer 2 IN 1: General purpose output When using Timer 2 input you must set this bit to 0.
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VMX51C1020
The P1PINCFG register controls the access from the PWM to the I/O pins as well as defines the direction of the P1 when the PWM’s are not used.
TABLE 16: (P1PINCFG) PORT 1 PORT CONFIGURATION REGISTER - SFR 9C H
The P2PINCFG register controls the I/O access to SPI interface and defines the direction of the P2 when used as general purpose I/O
TABLE 17: (P2PINCFG) PORT 2 PORT CONFIGURATION REGISTER - SFR 9D H
7
P2.7/SDIEN 3
6
P2.6/SDOEN
5
P2.5/SCKEN 1 P2.1/CS2EN
4
P2.4/SSEN 0 P2.0CS3EN
7 P1.7 3
P1.3/PWM3OE
6 P1.6 2
P1.2/PWM2OE
5 P1.5 1
P1.1/PWM1OE
4 P1.4 0
P1.0/PWM0OE
2
P2.2/CS1EN
P2.3/CS0EN
Bit 7 6 5 4 3
Mnemonic P1.7 P1.6 P1.5 P1.4 P1.3/PWM3OE
Function 0: General purpose input 1: General purpose output 0: General purpose input 1: General purpose output 0: General purpose input 1: General purpose output 0: General purpose input 1: General purpose output 0: General purpose input 1: General purpose output or PWM bit 3 output When using PWM you must set this bit to 1. 0: General purpose input 1: General purpose output or PWM bit 2 output
Bit 7
Mnemonic P2.7/SDIEN
Function 0: General purpose input or SDI 1: General purpose output When using SPI you must set this bit to 0. 0: General purpose input 1: General purpose output or SDO When using SPI you must set this bit to 1. 0: General purpose input or SCK 1: General purpose output When using SPI you must set this bit to 0. 0: General purpose input or Slave Select 1: General purpose output When using SPI SS you must set this bit to 0. 0: General purpose input 1: General purpose output or Chip Select bit 0 output When using SPI CS0 you must set this bit to 1. 0: General purpose input 1: General purpose output or Chip Select bit 1 output When using SPI CS1 you must set this bit to 1. 0: General purpose input 1: General purpose output or Chip Select bit 2 output When using SPI CS2 you must set this bit to 1. 0: General purpose input 1: General purpose output or Chip Select bit 3 output When using SPI CS3 you must set this bit to 1.
6
P2.6/SDOEN
5
P2.5/SCKEN
2
P1.2/PWM2OE
4 When using PWM you must set this bit to 1 0: General purpose input 1: General purpose output or PWM bit 1 output 3 When using PWM you must set this bit to 1 0: General purpose input 1: General purpose output or PWM bit 0 output 2 When using PWM you must set this bit to 1
P2.4/SSEN
1
P1.1/PWM1OE
P2.3/CS0EN
0
P1.0/PWM0OE
P2.2/CS1EN
1
P2.1/CS2EN
0
P2.0/CS3EN
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VMX51C1020
Using General Purpose I/O Ports
The P3PINCFG register controls I/O access to UART0, the I2C interface, capture compare input0 and 1, Timer 0 and Timer 1 inputs as well as defines the direction of P3 when used as general purpose I/O
TABLE 18: (P3PINCFG) PORT 3 PORT CONFIGURATION REGISTER - SFR 9EH
The VMX51C1020’s 28 I/Os are grouped into four ports. For each port an SFR register location is defined. Those registers are bit addressable providing the ability to control the I/O lines individually. When the port pin configuration register value defines the pin as an output, the value written into the port register will be reflected at the pin level. Reading the I/O pin configured as input is done by reading the contents of its associated port register.
TABLE 19: PORT 0 - SFR 80H
7
P3.7/MSCLEN
6
P3.6/MSDAEN
5
P3.5/T1INE N
4
P3.4/CCU1E N
3
P3.3/CCU0EN
2
P3.2/T0INEN
1
P3.1/RX0EN
0
P3.0/TX0EN
Bit 7
Mnemonic
P3.7/MSCLEN
Function 0: General purpose input 1: General purpose output or Master I2C SCL output When using the I2C you must set this bit to 1. 0: General purpose input 1: General purpose output or Master I2C SDA When using the I2C you must set this bit to 1. 0: General purpose input or Timer1 Input 1: General purpose output When using Timer 1 you must set this bit to 0. 0: General purpose input or CCU1 Input 1: General purpose output
7 7 7 7
6 6 6 6
5 5 5 5
4
6
P3.6/MSDAEN
3 P0 [7:0] 4 3 P1 [7:0] 4 3 P2 [7:0] 4 3 P3 [7:0]
2 2 2 2
1 1 1 1
0 0 0 0
PORT 1 - SFR 90H
PORT 2 - SFR A0H
5
P3.5/T1INEN
PORT 3 - SFR B0H
Bit 7-0
Mnemonic P0, 1, 2, 3
4
P3.4/CCU1EN
3
When using the Compare and Capture unit you must set this bit to 0. 0: General purpose input or CCU0 Input 1: General purpose output
P3.3/CCU0EN
Function When the Port is configured as an output, setting a port pin to 1 will make the corresponding pin to output logic high. When set to 0, the corresponding pin will set a logic low.
I/O usage example The following example demonstrates the configuration of the VMX51C1020 I/Os. //--------------------------------------------------------------------------//This example continuously reads the P0 and writes its contents into //P1 and it toggle P2 and P3. //--------------------------------------------------------------------------#pragma TINY #pragma UNSIGNEDCHAR #include at 0x0000 void main (void) { DIGPWREN = 0x80; P1PINCFG = 0x00; P1PINCFG = 0xFF; P2PINCFG = 0xFF; P3PINCFG = 0xFF; while(1) { P1 = P0; P2 = ~P2; P3 = ~P3; } }//end of main() function
2
P3.2/T0INEN
When using the Compare and Capture unit you must set this bit to 0. 0: General purpose input or Timer 0 Input 1: General purpose output When using Timer 0 you must set this bit to 0. 0: General purpose input or UART0 Rx 1: General purpose output When using UART0 you must set this bit to 0. 0: General purpose input 1: General purpose output or UART0 Tx When using UART0 you must set this bit to 1.
1
P3.1/RX0EN
// Enable Timer 2 to activate P1 //Output // Configure all P0 as Input //Configure P1 as Output //Configure P2 as Output //Configure P3 as Output
//Write P0 into P1 //Toggle P2 & P3
0
P3.0/TX0EN
Using Port1.0-3 as General Purpose Output
Port1.0-P1.3 can be used as standard digital outputs. However, in order to do this, the Timer 2 clock must be enabled by setting the
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VMX51C1020
T2CLKEN bit of the DIGPWREN register. In addition, the Timer 2 CCEN register must also have the reset value.
Interrupt on Port1 Change Feature
The VMX51C1020 includes an Interrupt on Port1 change feature. This feature can be used to monitor the activity on each I/O Port1 pin (individually) and trigger an interrupt when the state of the pin on which this feature has been activated changes. This is equivalent to having eight individual external interrupt inputs. The Interrupt on Port1 change shares the interrupt vector of the ADC peripheral at address 006Bh. See the Interrupt section for more details on how to use this feature.
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VMX51C1020
MULT/ACCU - Multiply Accumulator Unit
The VMX51C1020 includes a hardware based multiply-accumulator unit which provides the user the ability to perform fast and complex arithmetic operations. MULT/ACCU Features: o Hardware Calculation Engine o Calculation result is ready as soon as the input registers are loaded o Signed mathematical calculations o Unsigned MATH operations are possible if the MUL engine operands are limited to 15-bits in size o Auto/Manual reload of MAC_RES o Enhanced VMX51C1020 MULT/ACCU Unit o Easy implementation of complex MATH operations o 16-bit and 32-bit Overflow Flag o 32-bit Overflow can raise an interrupt o MULT/ACCU operand registers can be cleared individually or all together o Overflow flags can be configured to stay active until manually cleared o Can store and use results from previous operations The MULT/ACCU can be configured to perform the following operations:
FIGURE 13: VMX51C1020 MULT/ACCU OPERATION
(MACA, MACB) + MACC = MAC_RESULT (MACA x MACB) + MACC = MAC_RESULT (MACA x MACB) + 0 = MAC_RESULT (MACA x MACB) + MAC_PREV = MAC_RESULT
MULT16 + ADD32
MULT/ACCU Control Registers
With the exception of the Barrel Shifter, the MULT/ACCU unit operation is controlled by two SFR registers: o o The MACCTRL1 The MACCTRL2
The following two tables describe the details of these control registers.
TABLE 20: (MACCTRL1) MULT/ACCU U NIT C ONTROL REGISTER - SFR EBH
7 LOADPREV
6 PREVMODE
5 OVMODE
4 OVRDVAL
3 2 ADDSRC [1:0] Bit 7 Mnemonic LOADPREV
1 0 MULCMD [1:0] Function MACPREV manual Load control 1 = Manual load of the MACPREV register content if PREVMODE = 1 Loading method of MACPREV register 0 = Automatic load when MACA0 is written. 1 = Manual Load when 1 is written into LOADPREV 0 = Once set by math operation, the OV16 and OV32 flag will remain set until the overflow condition is removed. 1= Once set by math operation, the OV16 and OV32 flag will stay set until it is cleared manually. 0 = The value on MACRES is the calculation result. 1 = the value on MACRES is the 32LSB of the MACRES when the OV32 overflow occurred 32-bit Addition source B Input 00 = 0 (No Add) 01 = C (std 32-bit reg) 10 = RES –1 11 = C (std 32-bit reg) A Input 00=Multiplication 01=Multiplication 10=Multiplication 11= Concatenation of {A, B} for 32-bit addition Multiplication Command 00 = MACA x MACB 01 = MACA x MACA 10 = MACA x MACPREV (16 LSB) 11 = MACA x MACB
6
PREVMODE
5
OVMODE
ADD32 + ADD32
4
OVRDVAL
(MACA x MACA) + MACC = MAC_RESULT (MACA x MACA) + 0 = MAC_RESULT (MACA x MACA) + MAC_PREV = MAC_RESULT (MACA x MAC_PREV(16lsb) + MACC (MACA x MAC_PREV(16lsb) + 0 (MACA x MAC_PREV(16lsb) + MAC_PREV = MAC_RESULT = MAC_RESULT = MAC_RESULT
3:2
ADDSRC[1:0]
Where MACA (multiplier), MACB (multiplicand), MACACC (accumulator) and MACRESULT (result) are 16, 16, 32 and 32 bits, respectively.
1:0
MULCMD[1:0]
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VMX51C1020
TABLE 21: (MACCTRL2) MULT/ACCU U NIT C ONTROL REGISTER 2 -SFR F1H TABLE 22: (MACA0) MULT/ACCU UNIT A OPERAND, LOW BYTE - SFR F2H
7
6 MACCLR2 [2:0] 2 Mnemonic MACCLR[2:0]
5
4 MACOV32IE 0 MACOV32
7
6
5
4
3 MACA0 [7:0]
2
1
0
3 Bit 7:5
1 MACOV16
Bit 7:0
Mnemonic MACA0
Function Lower segment of the MACA operand
4 3 2 1
MACOV32IE MACOV16
0
MACOV32
Function MULT/ACCU Register Clear 000 = No Clear 001 = Clear MACA 010 = Clear MACB 011 = Clear MACC 100 = Clear MACPREV 101 = Clear All MAC regs + Overflow Flags 110 = Clear Overflow Flags only MULT/ACCU 32-bit Overflow IRQ Enable 16-bit Overflow Flag 0 = No 16 overflow 1 = 16-bit MULT/ACCU Overflow occurred 32-bit Overflow Flag 1 = 32-bit MULT/ACCU Overflow This automatically loads the MAC32OV register. The MACOV32 can generate a MULT/ACCU interrupt when enabled.
TABLE 23: (MACA1) MULT/ACCU UNIT A OPERAND, HIGH BYTE - SFR F3 H
7
6
5
4 3 MACA1 [15:8]
2
1
0
Bit 15:8
Mnemonic MACA1
Function Upper segment of the MACA operand
TABLE 24: (MACB0) MULT/ACCU UNIT B OPERAND, LOW BYTE - SFR F9H
7
6
5
4 3 MACB0 [7:0]
2
1
0
Bit 7:0
Mnemonic MACB0
Function Lower segment of the MACB operand 5 4 3 MACB1 [7:0] 2 1 0
TABLE 25: (MACB1) MULT/ACCU UNIT B OPERAND, HIGH BYTE - SFR FA H
7
6
Bit 7:0
Mnemonic MACB1
Function Upper segment of the MACB operand
MACC Input Register
The MACC register is a 32-bit register used to perform 32-bit addition. It’s possible to substitute the MACPREV Register for the MACC register or 0 in the 32-bit addition.
TABLE 26: (MACC0) MULT/ACCU U NIT C OPERAND, LOW BYTE - SFR ECH
MULT/ACCU Unit Data Registers
The MULT/ACCU Data registers include operand and result registers that serve to store the numbers being manipulated in mathematical operations. Some of these registers are uniquely for addition (such as MACC) while others can be used for all operations. The MULT/ACCU operation registers are represented below.
7
6
5
4 3 MACC0 [7:0]
2
1
0
Bit 7:0
Mnemonic MACC0
Function Lower segment of the 32-bit addition register
MACA and MACB Multiplication (Addition) Input Registers
The MACA and MACB register serve as 16-bit input operands when performing multiplication. When the MULT/ACCU is configured to perform 32-bit addition, the MACA and the MACB registers are concatenated to represent a 32-bit word. In that case the MACA register contains the upper 16-bit of the 32-bit operand and the MACB contains the lower 16-bit
TABLE 27: (MACC1) MULT/ACCU U NIT C OPERAND, BYTE 1 - SFR EDH
7
6
5
4 3 MACC1 [15:8]
2
1
0
Bit 15:8
Mnemonic MACC1
Function Lower middle segment of the 32-bit addition register 4 3 MACC2 [23:16] 2 1 0
TABLE 28: (MACC2) MULT/ACCU U NIT C OPERAND, BYTE 2 - SFR EEH
7
6
5
Bit 23:16
Mnemonic MACC2
Function Upper middle segment of the 32-bit addition register
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TABLE 29: (MACC3) MULT/ACCU U NIT C OPERAND, HIGH BYTE - SFR EFH
7
6
5
4 3 MACC3 [31:24]
2
1
0
Bit 31:24
Mnemonic MACC3
Function Upper segment of the 32-bit addition register
As mentioned previously, there are two ways to load the MACPREV register controlled by the PREVMODE bit value: PREVMODE = 0: Auto MACPREV load, by writing into the MACA0 register. Selected when PREVMODE = 0. PREVMODE = 1: Manual load of MACPREV LOADPREV bit is set to 1 when the
MACRES Result Register
The MACRES register, which is 32-bits wide, contains the result of the MULT/ACCU operation. In fact, the MACRES register is the output of the Barrel Shifter.
TABLE 30: (MACRES0) MULT/ACCU UNIT RESULT, LOW BYTE - SFR F4H
7
6
5
4 3 MACRES0 [7:0]
2
1
0
Bit 7:0
Mnemonic MACRES0
Function Lower segment of the 32-bit MULT/ACCU result register 4 3 MACRES1 [15:8] 2 1 0
A good example using the auto loading of the MACPREV feature is the implementation of a FIR Filter. In that specific case, it is possible to save a total of 8 MOV operations per tap calculation.
TABLE 34: (MACPREV0) MULT/ACCU UNIT PREVIOUS OPERATION RESULT, LOW BYTE - SFR FCH
TABLE 31: (MACRES1) MULT/ACCU UNIT RESULT, BYTE 1 - SFR F5H
7
6
5
7 Bit 15:8 Mnemonic MACRES1 Function Lower middle segment of the 32-bit MULT/ACCU result register 4 3 MACRES2 [23:16] 2 1 0
6
5
4 3 MACPREV0 [7:0]
2
1
0
Bit 7:0
Mnemonic MACPREV0
TABLE 32: (MACRES2) MULT/ACCU UNIT RESULT, BYTE 2 - SFR F6H
7
6
5
Function Lower segment of 32-bit MULT/ACCU previous result register
TABLE 35: (MACPREV1) MULT/ACCU UNIT PREVIOUS OPERATION RESULT, BYTE 1 - SFR FDH
Bit 23:16
Mnemonic MACRES2
Function Upper middle segment of the 32-bit MULT/ACCU result register
7
6
5
4 3 MACPREV1 [7:0]
2
1
0
TABLE 33: (MACRES3) MULT/ACCU UNIT RESULT, HIGH BYTE - SFR F7 H
Bit 15:8 0
Mnemonic MACPREV1
7
6
5
4 3 MACRES3 [31:24]
2
1
Function Lower middle segment of 32-bit MULT/ACCU previous result register
Bit 31:24
Mnemonic MACRES3
Function Upper segment of the 32-bit MULT/ACCU result register
TABLE 36: (MACPREV2) MULT/ACCU UNIT PREVIOUS OPERATION RESULT, BYTE 2 - SFR FEH
7
6
5
4 3 MACPREV2 [15:8]
2
1
0
MACPREV Register
The MACPREV register provides the ability to automatically or manually save the contents of the MACRES register and re-inject it into the calculation. This feature is especially useful in applications where the result of a given operation serves as one of the operands of the next one.
Bit 23:16
Mnemonic MACPREV2
Function Upper middle segment of 32-bit MULT/ACCU previous result register
TABLE 37: (MACPREV3) MULT/ACCU UNIT PREVIOUS OPERATION RESULT, HIGH BYTE - SFR FFH
7
6
5
4 3 MACPREV3 [7:0]
2
1
0
Bit 31:24
Mnemonic MACPREV3
Function Upper segment of 32-bit MULT/ACCU previous result register
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VMX51C1020
FIGURE 14: VMX51C1020 MULT/ACCU FUNCTIONAL DIAGRAM
addsrc SFR registers Concatenation (A,B) ov32
B
shiftmode
SFR registers
MACA1 (MSB)
MACA
ov16a
ADD MSB
A
MUL (Signed) ov16b SHIFT MACRES MACRES (SFR regs)
MACRES3 (MSB) MACRES2
MACA0 (LSB) MACB1 (MSB)
MACB
B
ADD LSB
A
mulcmd MACC prevmode
ovrdval
MACRES1
Maca0 load loadprev
MACB0 (LSB) MACC3 (MSB)
(16 LSB)
0
MACRES0 (LSB) MAC32OV3 (MSB)
addsrc
MACPREV
MACC2 MACC1
ov32 1 ovmode rst ov32F rst 1
MAC32OV (stored) load
MAC32OV2 MAC32OV1
MACC0 (LSB)
ov32F / IRQ ov32 1 ovmode rst
OVCLR
MAC32OV0 (LSB)
Ov16a+b
MAC Control SFR ov16F
Ov16a+b
MACCTRL1 MACCTRL2 MACSHIFTCTRL
The above block diagram shows the interaction between the registers and the other components that comprise the MULT/ACCU unit on the VMX51C1020.
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VMX51C1020
MULT/ACCU Barrel Shifter
The MULT/ACCU includes a 32-bit Barrel Shifter at the output of the 32-bit addition unit. The Barrel Shifter can perform right/left shift operations in one cycle, which is useful for scaling the output result of the MULT/ACCU. The shift range is adjustable from 0 to 16 in both directions. The “shifted” addition unit output can be routed to the: o MACRES o MACPREV o MACOV32 The barrel shifter can perform both arithmetic and logical shifts: The shift left operation can be configured as an arithmetic or logical shift. In the later, the sign bit is discarded.
TABLE 38: (MACSHIFTCTRL) MULT/ACCU UNIT BARREL SHIFTER CONTROL REGISTER - SFR FBH
// MULT/ACCU example use MACA0 = 0xFF; MACA1 = 0x7F; MACB0 = 0xFF; MACB1 = 0xFF; MACC0 = 0xFF; MACC1 = 0xFF; MACC2 = 0xFF; MACC3 = 0x7F; //--- as soon as the MAC input registers are loaded the result is available in the MACRESx registers. }//end of main //--------------------------------------------------------------------------------// MAC 32 bit overflow Interrupt Function void int_5_mac (void) interrupt 12 { IEN0 &= 0x7F;
// Disable all interrupts
//Put MAC 32 bit Overflow Interrupt code here.*/ //Note that when a 32bit overflow occurs, the 32 least significant bit of the current //result are stored into the MAC32OVx registers and can be read at the location of MACRESx by setting to 1 the OVRDVAL bit of the MACCTRL register IRCON &= 0xEF; // Clear flag (IEX5) IEN0 |= 0x80; // Enable all interrupts } //--------------------------------------------------------------------------------
7 SHIFTMODE Bit 7 6
6 ALSHSTYLE
5
4 3 2 1 SHIFTAMPL [5:0]
0
Mnemonic SHIFTMODE ALSHSTYLE
5:0
SHIFTAMPL[5:0]
Function 0 = Logical SHIFT 1 = Arithmetic SHIFT Arithmetic Shift Left Style 0= Arithmetic Left Shift: Logical Left 1= Arithmetic Left Shift: Keep sign bit Shift Amplitude 0 to 16 (5 bits to provide 16 bits shift range) Neg. Number = Shift Right (2 complements) Pos. Number = Shift Left
MULT/ACCU Application Example: FIR Filter Function
The following ASM code shows the implementation of a FIR filter computation function for one iteration, the data shifting operation and the definition of the FIR filter coefficient table. The FIR computation is simple to implement, however, it is quite demanding in terms of processing power. For each new data point, the multiplication with associated coefficients + addition operation must be performed N times (N=number of filter tapps). Due to being hardware based and including features such as automatic reload of the result of the previous operation, the VMX51C1020 MULT/ACCU unit is very efficient for performing operations such as FIR filter computation. In the code example below, the COMPUTEFIR loop forms the heart of the FIR computation and it is clear that use of the MULT/ACCU unit implies very few instructions being required for mathematical operations. The net result is a dramatic performance improvement when compared with manual calculations done solely via the standard 8051 instruction set.
MULT/ACCU Unit Setup and OV32 Interrupt Example
In order to use the MULT/ACCU unit, the user must first set up and configure the module. The following provides setup code examples. The first part of the code is the interrupt setup and module configuration, whereas the second part is the interrupt function itself. Sample C code for MULT/ACCU Unit interrupt setup and module configuration:
//--------------------------------------------------------------------------// Sample C code to setup the MULT/ACCU unit //--------------------------------------------------------------------------//--- Program initialisation omitted… (…) void main(void){ // MULT/ACCU setup IEN0 |= 0x80; IEN1 |= 0x10; DIGPWREN |= 0x20; MACCTRL1 = 0x0C; MACCTRL2 = 0x10;
// Enable all interrupts // Enable MULT/ACCU interrupt // Enable MULT/ACCU unit // {A,B}+C // Enable INT overflow_32
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VMX51C1020
VMX51C1020 FIR Filter Example The example below shows how to use the MULT/ACCU unit of the VMX51C1020 to perform FIR filter computing. In order to minimize the example size, only the FIR computing function and the coefficient table are presented.
;----------------------------------------------------// ;** FIR Filter Computing Function // ;---------------------------------------------------// FIRCOMPUTE: MOV R0,#NPOINTSBASEADRS ;INPUT ADC RAW DATA ;AT Xn LOCATIONS... ;Saving acquired data from calling function into RAM for computation MOV MOV MOV INC MOV VARH,DATAH VARL,DATAL @R0,VARH R0 @R0,VARFL
MOV MOV LCALL MOV RET
DATAH,MACRES3 DATAL,MACRES2 SENDLTC1452 P3,#00
;---------------------------------------------------;* FIR Filter Coefficients Table * ;---------------------------------------------------;FSAMPLE 480HZ, N=16, LOW PASS 0.1HZ -78DB @ 60HZ COEFTABLE: DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW 023DH 049DH 086AH 0D2DH 1263H 1752H 1B30H 1D51H 1D51H 1B30H 1752H 1263H 0D2DH 086AH 049DH 023DH 0FFFFH ;END OF TABLE
;(MSB) ;(LSB)
;** Prepare to compute Yn... ;***Define Base ADRS of input values MOV R0,#NPOINTSBASEADRS ;***Define Base Address of coefficients MOV R1,#COEFBASEADRS MOV R7,#NPOINTS ;DEFINE COUNTER ;***Configure the MULT/ACCU unit as Follow: MOV MACCTRL,#00001000B No manual Previous result Automatic Previous result save when MULT/ACCUA0 is loaded Overflow flag remains ON until overflow condition exist The value of MACRES is the calculation result MACPREV is the Addition Source Mul Operation = MACAxMACB
;BIT7 LOADPREV = 0 ;BIT6 PREVMODE = 0 ; ;BIT5 OVMODE = 0 ; ;BIT4 OVRDVAL = 0 ; ;BIT3:2 ADDSRC = 10 ;BIT1:0 MULCMD = 00
;**Clear the MULT/ACCU registers content MOV MACCTRL2,#0A0H ;** COMPUTE Yn... COMPUTEFIR: MOVMACB1,@R1 INC MOV INC ;Put a given Coefficient into ;MULT/ACCUB
R1 MACB0,@R1 R1
MOV MACA1,@R0 ; Put a given Xn Input into INC R0 MOV MACA0,@R0 ;This last instruction load the MACPREV register for next Operation INC R0 DJNZ R7,COMPUTEFIR ;Do the Computation for N taps ;*** Second part ;-------------------------------------------------------------------------------------------------------// ;** SHIFT PREVIOUS INPUT VALUES TO LET PLACE FOR NEXT ONE... ;-------------------------------------------------------------------------------------------------------// SHIFTPAST: MOV R7,#(NPOINTS -1)*2 ;Define # of datashift ;To perform (N-1)*2 ;***COMPUTE FIRST FETCH ADDRESS MOV R0,#(NPOINTSBASEADRS - 1 + 2*(NPOINTS-1)) ;***COMPUTE FIRST DESTINATION ADDRESS MOV R1,#(NPOINTSBASEADRS + 1 + 2*(NPOINTS-1)) SHIFTLOOP: MOV A,@R0 ;Shift Given LSB input... MOV @R1,A ;To next location DEC R0 ;Prepare pointer for moving LSB DEC R1 DJNZ R7,SHIFTLOOP ;** PERFORM TRANSFORMATION OF Yn HERE AND PUT INTO BINH, BINL ;** IN THIS CASE THE COEFFICIENTS HAVE BEEN MULTIPLIED BY 65536 ;** SO THE RESULT IS ON 32-BITS ;** DIVISING YN BY 65536 MEAN ONLY TAKING THE UPPER 16-BITS
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VMX51C1020
VMX51C1020 Timers
The VMX51C1020 includes 3 general-purpose timer/counters o Timer0 o Timer1 o Timer2 Timer0 and Timer1 are general purpose timers that can operate as a timer with a clock rate based on the system clock, or as an event counter that monitosr events occurring on an external timer input pin (T0IN for Timer 0 and T1IN for Timer 1). Timers 0 and Timer 1 are similar to the standard 8051 timers. Apart from also being capabile of operating as a timer based on a system clock or as an event counter, Timer2 is also the heart of the PWM counter outputs and the Compare and Capture Units. Each of the VMX51C1020’s timers has a dedicated interrupt vector which can be triggered when the Timers overflow.
TABLE 39: (TL0) TIMER 0 LOW BYTE - SFR 8AH
7
6
5
4 3 TL0 [7:0] 4 3 TH0 [7:0] 4 3 TL1 [7:0] 4 3 TH1 [7:0]
2
1
0
TABLE 40: (TH0) TIMER 0 HIGH BYTE - SFR 8CH
7
6
5
2
1
0
TABLE 41: (TL1) TIMER 1 LOW BYTE - SFR 8BH
7
6
5
2
1
0
TABLE 42: (TH1) TIMER 1 HIGH BYTE - SFR 8DH
7
6
5
2
1
0
With the exception of their associated interrupts, the configuration and control of Timer0 and Timer1 is performed via the TMOD and TCON SFR registers. The following table shows the TCON special function register of the VMX51C1020. This register contains the Timer 0/1 overflow flags, Timer 0/1 run control bits, interrupt 0/1 edge flags, and the interrupt 0/1 interrupt type control bits.
TABLE 43: (TCON) TIMER 0, TIMER 1 TIMER/COUNTER CONTROL - SFR 88H
7
TF1
6
TR1
5
TF0
4
TR0
3
IE1
2
IT1
1
IE0
0
IT0
Bit 7
Mnemonic TF1
Timer 0 and Timer 1
The VMX51C1020’s Timer0 and Timer1 are very similar in their structure and operation. The main difference being that Timer1 serves as a baud rate generator for UART0 and it shares some of its resources when Timer0 is used in mode 3. Timer0 and Timer1 each consist of a 16-bit register for which the content is accessible as two independent SFR registers: TLx and THx.
6 TR1
5
TF0
4
TR0
3
IE1
2
IT1
1
IE0
0
IT0
Function Timer 1 overflow flag. Set by hardware when Timer 1 overflows. It is automatically cleared when the Timer 1 interrupt is serviced. This flag can also be cleared by software. Timer 1 Run control bit. TR1 = 0, Stop Timer 1 TR1 = 1, Start Timer 1 Timer 0 overflow flag. Set by hardware when Timer 0 overflows. It is automatically cleared when the Timer 0 interrupt is serviced. This flag can also be cleared by software. Timer 0 Run control bit. TR0 = 0, Stop Timer 0 TR0 = 1, Start Timer 0 Interrupt 1 edge flag. This flag is set by hardware when falling edge on external INT1 is observed. It is cleared when interrupt is processed. INT1 interrupt event type control bit. IT1 = 0, interrupt will be caused by a Low Level on INT1 IT1 = 1, Interrupt will be caused by a High to Low transition on INT1. INT0 edge flag configuration Set by hardware when falling edge on external pin INT0 is observed. It is cleared when interrupt is processed. INT0 interrupt event type control bit. IT0 = 0, interrupt will be caused by a Low Level on INT0 IT0 = 1, Interrupt will be caused by a High to Low transition on INT0.
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VMX51C1020
The TMOD register is mainly used to set the operating mode of the timers and it allows the user to enable the external gate control as well as select timer or counter operation.
TABLE 44: (TMOD) TIMER MODE CONTROL - SFR 89H
Low transitions on the TxIN pin of the VMX51C1020 increments the timer value. Note that when Timer0 and Timer1 operate in Timer mode, they use the System Clock as their source. Therefore configuring the CLKDIVCTRL register will affect the Timer’s operation.
7
GATE1
6
CT1
5
M11
4
M01
3
GATE0
2
CT0
1
M10
0
M00
Timer0 & Timer1 Gate Control
The Gate control makes it possible for an external device to control Timer0 and Timer1 operation through the interrupt (INTx) pins. When the GATEx and TRx bits of the TMOD register are set to 1: o o INTx = Logic LOW, The Timer x Stops INTx = Logic High, The Timer x Runs
Bit 7
Mnemonic GATE1
Function GATE1 = 0, The level present on the INT1 pin has no effect on Timer1 operation. GATE1 = 1, The level of INT1 pin serves as a Gate control on to Timer/Counter operation provided the TR1 bit is set. Applying a Low Level on the INT1 pin makes the Timer stop. Selects TIMER1 Operation. CT1 = 0, Sets the Timer 1 as a Timer which value is incremented by SYSCLK events. CT1 = 1, The Timer 1 operates as a counter which counts the High to Low transition on that occurs on the T1IN input. Selects mode for Timer/Counter 1, as shown in the Table below. GATE0 = 0, The level present on the INT0 pin has no effect on Timer1 operation. GATE0 = 1, The level of INT0 pin serves as a Gate control on to Timer/Counter operation provided the TR0 bit is set. Applying a Low Level on the INT0 pin makes the Timer stop.
CT1
When the Gate bit equals 0, then the logic level present at the INTx pin have no effect on the Timer Operation.
FIGURE 15: T IMER 0, T IMER 1 CTX & GATE CONTROL
5 4 3
M11 M01 GATE0
SYSCLK
÷12
0
CTx=0 CLK
1 TxIN
CTx=1
2
CT0
Selects Timer 0 Operation. CT1 = 0, Sets the Timer 0 as a Timer which value is incremented by SYSCLK events. The Timer 0 operates as a counter which counts the High to Low transition on that occurs on the T1IN input. Selects mode for Timer/Counter 0, as shown in the Table below. CT1 = 1,
TRx GATEx
INTx
1 0
M10 M00
Timer0/Timer1/Counter Operation
The CT0 and CT1 bits of the TMOD register control the Clock source for Timer0 and Timer1, respectively. When the CT bit is set to 0 (Timer mode) the Timer is sourced from the system clock divided by 12. Setting the CTx bit to 1 sets the Timer to operate in event counter mode. In this mode, High to
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VMX51C1020
Timer0, Timer1 Operation Modes
The operating mode of Timer0 and Timer1 is determined by the M1x and M0x bits in the TMOD register. The following summarizes the four modes of operation for Timers0 and 1.
TABLE 45: TIMER/COUNTER MODE DESCRIPTION S UMMARY
Timer 0, Timer 1: Mode 0 - Overflow Rate (Hz) CTx = 0 Timer overflow rate (Hz) = fSYSCLK_________ 12 x [8192-(THx, TLx)]
CTx = 1 M1 0 M0 0 Mode Mode 0 Function 13-bit Timer / Counter , with 5 lower bits in TL0 or TL1 register and bits in TH0 or TH1 register (for timer 0 and timer 1, respectively). The 3 high order bits of TL0 and TL1 are held at 0. 16-bit Timer / Counter 8-bit auto reload Timer / Counter. The reload value is kept in TH0 or TH1, while TL0 or TL1 is incremented every machine cycle. When TLx overflows, a value from THx is copied to TLx. If Timer 1 M1 and M0 bits are set to 1, Timer 1 stops. If Timer 0 M1 and M0 bits are set to 1, Timer 0 acts as two independent 8-bit Timers / Counters. Timer overflow rate (Hz) = fTxIN_________ [8192-(THx,TLx)]
Mode 1 (16-bit) Mode 1 operation is the same for Timer0 and Timer1. In Mode 1, the timer is configured as a 16-bit counter. Other than rollover at FFFFh, Mode 1 operation is the same as Mode 0.
FIGURE 16 : T IMER 0 MODE 0 & MODE 1
SYSCLK ÷12 TH0 CLK 1 P3.2-T0IN Mode = 1 CT0=1 0 4 7
0 1
1 0
Mode 1 Mode 2
1
1
Mode 3
0
CT0=0
Mode = 0
TR0 GATE0 0 TL0 7
Mode 0, 13-bit Timer/Counter Mode 0 operation is the same for Timer0 and Timer1. In Mode 0, the timer is configured as a 13-bit counter that uses bits 0-4 of the TLx register and all 8-bits of the THx register. The Timer Run bit (TRx) of the TCON SFR starts the timer. The value of the CTx bit defines if the Timer will operate as a Timer (CTx = 0), deriving its source from the System Clock, or count the High to Low Transitions (CTx = 1) that occurs on the External Timer input pin (TxIN). When the 13-bit count increments from 1FFFh (all ones) to all zeros, the TF0 (or TF1) bit will be set in the TCON SFR. The state of the upper 3-bits of the TLx register is indeterminate in Mode 0 and must be masked when the software evaluates the register’s contents.
INT0
TF0
INT
FIGURE 17: T IMER 1 MODE 0 & MODE 1
SYSCLK ÷12 TH1 CLK 1 P3.5-T1IN Mode = 1 TL1 CT1=1 0 4 7
0
CT1=0
Mode = 0
TR1 GATE1
0
7
INT1 TF1 INT
To UART0
The Timer0 and Timer1 overflow rate in mode 1 can be calculated using the following equations:
Timer 0, Timer 1: Mode 1 - Overflow Rate (Hz) CTx = 0 Timer overflow rate (Hz) = CTx = 1 Timer overflow rate (Hz) = fTxIN_________ [65536-(THx, TLx)] fSYSCLK_________ 12 x [65536-(THx, TLx)]
Mode 2 (8-bit) The operation of Mode2 is the same for Timer0 and Timer1. In Mode 2, the timer is configured
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VMX51C1020
as an 8-bit counter, with automatic reload of the start value. The LSB of the Timer register, TLx, is the counter itself and the MSB portion of the Timer, THx, stores the timer reload value. Mode 2’s counter control is the same as for Mode 0 and Mode 1. However, in Mode 2, when TLx rolls over from FFh, the value stored in THx is reloaded into TLx.
FIGURE 18 : T IMER 0 MODE 2
Using Timer1 in mode 2 is recommended as the best approach when using Timer1 as the UART0 baud rate generator. Mode 3 (2 x 8-bit) In Mode 3, Timer0 operates as two 8-bit counters and Timer1 stops counting and holds its value.
FIGURE 20: T IMER0, T IMER 1 STRUCTURE IN MODE 3
CLK 0 TH0 7
SYSCLK
÷12 TL0 0 7
0
CT0 = 0
1 P3.2 - T0IN
CT0 = 1
TR1
TF1
To UART0
INT
SYSCLK
0 TH0 7
÷12 0 1 CT0 = 0 CLK CT0 = 1 0 TL0 7
TR0
P3.2-T0IN
GATE0 INT0 TF0 INT
TR0 TF0 GATE0 INT0 INT
FIGURE 19: T IMER 1 MODE 2
SYSCLK ÷12 TL1 0 7
The Timer0 overflow rate in Mode 3 can be calculated by using following equations:
0 CT1 = 0
Timer 0, Timer 1: Mode 3 - Overflow Rate (Hz) TH0, CTx = 0 or 1 Timer overflow rate (Hz) = fSYSCLK_____ 12 x 256
1 P3.5 - T1IN
CT1 = 1
0 TH1
7
TL0, CTx = 0
TR1 GATE1 INT1 To UART0 TF1 INT
Timer overflow rate (Hz) =
fSYSCLK_____ 12 x 256
TL0, CTx = 1
The Timer0 and Timer1 overflow rate in Mode 2 can be calculated using the following equations:
Timer 0, Timer 1: Mode 2 - Overflow Rate (Hz) CTx = 0 Timer overflow rate (Hz) = fSYSCLK_________ 12 x [256-(THx)]
Timer overflow rate (Hz) =
__ fTxIN_____ 256
In Mode 3, the values present in the TH1 and TL1 registers, as well as the value of the GATE1 and CT1 control bits, have no impact on the Timer operation.
CTx = 1 Timer overflow rate (Hz) = __ f TxIN________ [256--(THx)]
Timer0 & Timer1 Interrupts
Timer0 and Timer1 have a dedicated interrupt vectors located at: o o 000Bh for the Timer 0 001Bh for the Timer 1
Using Timer1 as Baud Rate generator
The natural priority of Timer0 is higher than that of Timer1.
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VMX51C1020
The following table provides a summary of the Interrupt control and Flag bits associated with the Timer0 and Timer1 interrupts.
Bit Name EA Location IEN0.7 Description
Setting Up Timer1 Example
The following code provides an example of how to configure Timer1 (first part of the code is the interrupt setup and module configuration whereas the second part is the interrupt function). Example1: Delay function
//------------------------------------------------------------------------// Sample C code using the Timer 1: Delay function //------------------------------------------------------------------------VOID DELAY 1MS( UNSIGNED CHAR DLAIS) { IDATA UNSIGNED CHAR X=0; TMOD = 0X10; TL1 = 0X33; TH1 = 0XFB; ;//TIMER1 RELOAD VALUE FOR TCON = 0X40;
WHILE (DLAIS > 0)
T0IE
IEN0.1
T1IE
IEN0.3
TF0
TCON.5
TF1
TCON.7
General interrupt control bit 0, Interrupt Disabled 1, Enabled Interrupt active Timer 0 Overflow Interrupt 1 = Enable 0 = Disable Timer 1 Overflow Interrupt 1 = Enable 0 = Disable TF0 Flag is set when Timer 0 Overflow occurs. Automatically cleared when Timer 0 interrupt is serviced. This flag can also be cleared by software TF1 Flag is set when Timer 1 Overflow occurs. Automatically cleared when Timer 1 interrupt is serviced. This flag can also be cleared by software
{
DO{ X=TCON; X= X&0X80; }WHILE(X==0);
TCON = TCON&0X7F; TL1 = 0X33; TH1 = 0XFB; ;//TIMER1 RELOAD VALUE FOR
DLAIS = DLAIS-1; } }//END OF DELAY 1MS
Setting Up Timer0 Example
In order to use Timer0, the first step is to setup the interrupt and then configure the module and this is described in the following code example. Sample C code to set up Timer 0:
//--------------------------------------------------------------------------// Sample C code to setup Timer 0 //--------------------------------------------------------------------------// (…) PROGRAM INITIALIZATION OMITTED
AT 0X0100 VOID MAIN( VOID){
Example 2: Timer1 interrupt example
//------------------------------------------------------------------------// Sample C code using the Timer 1: Interrupt //------------------------------------------------------------------------// (…) PROGRAM INITIALIZATION OMITTED at 0xo100 void main(void){ // TIMER 1 setup IEN0 |= 0x80; IEN0 |= 0x08; TMOD = 0x20; TCON = 0x40; TL1 = 0xFC; do { }while(1); }//end of main() function //---------------------------------------// Timer 1 Interrupt function //---------------------------------------void int_timer_1 (void) interrupt 3 { IEN0 &= 0x7F; /* Put Interrupt code here*/ // Disable all interrupts //Wait Timer 1 interrupt // Enable all interrupts // Enable interrupt Timer1 // Timer 1 mode 2 // Start Timer 1 // Timer1 offset
// INTERRUPT + TIMER 0 SETUP IEN0 |= 0X80; IEN0 |= 0X02; TMOD = 0X02; TCON = 0X10;
DO{}WHILE(1);
// ENABLE ALL INTERRUPTS // ENABLE INTERRUPT TIMER 0 // TIMER 0 MODE 2 // START TIMER 0
//WAIT FOR TIMER 0 INTERRUPT
}//END OF MAIN() //--------------------------------------------------------------------------// INTERRUPT FUNCTION
VOID INT_ TIMER_0 ( VOID) INTERRUPT 1
{ IEN0 &= 0X7F; // DISABLE ALL INTERRUPTS /*------------------------*/ /*Put Interrupt code here*/ /*------------------------*/ IEN0 |= 0x80; // Enable all interrupts } //---------------------------------------------------------------------------
IEN0 |= 0x80; }
// Enable all interrupts
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VMX51C1020
Timer2
The VMX51C1020 Timer2 and associated peripherals include the following capabilities: o o o o 16-Bit Timer 16-Bit Auto-Reload Timer Compare and Capture units 8 / 16 PWM outputs
The T2CON register controls: o T2 clock source Prescaler o T2 count size (8/16-bits) o T2 reload mode o T2 Input selection
TABLE 50: (T2CON) TIMER 2 CONTROL REGISTER -SFR C8 H
7 T2PS 3 T2RM0
6 T2PSM 2 T2CM
5 T2SIZE 1 T2IN1
4 T2RM1 0 T2IN0
TABLE 46: (TL2) TIMER 2, LOW BYTE - SFR CCH
7
6
5
4 3 TL2 [7:0] 4 3 TH2 [7:0]
2
1
0
Bit 7
Mnemonic T2PS
TABLE 47: (TH2) TIMER 2, HIGH BYTE - SFR CDH
7
6
5
2
1
0 6 5 T2PSM T2SIZE
Figure 21 shows the Timer2 Compare/Capture unit block diagram. The following paragraphs will describe describe how these blocks work.
Timer2 Registers
Timer2 constists of a 16-bit register, whose upper and lower bytes are accessible via two independent SFR registers (TL2, TH2).
TABLE 48: (TL2) TIMER 2 LOW BYTE - SFR CCH
4 3
T2RM1 T2RM0
2
T2CM
7
6
5
4 3 TL2 [7:0]
2
1
0
1 0
T2IN1 T2IN0
TABLE 49: (TH2) TIMER 2 HIGH BYTE - SFR CDH
7
6
5
4 3 TH2 [7:0]
2
1
0
Function Prescaler select bit: 0 = Timer 2 is clocked with 1/12 of the oscillatory frequency 1 = Timer 2 is clocked with 1/24 of the oscillatory frequency 0 = Prescaler 1 = clock/2 Timer 2 Size 0 = 16-bit 1 = 8-bit Timer 2 reload mode selection 0X = Reload disabled 10 = Mode 0 11 = Mode 1 Timer 2 compare mode selection 0 = Mode 0 1 = Mode 1 Timer 2 input selection 00 = Timer 2 stops 01 = Input frequency f/2, f/12 or f/24 10 = Timer 2 is incremented by external signal at pin T2IN 11 = Internal clock is gated to the T2IN input.
Timer2 Control Register Most of Timer2’s control is accomplished via the T2CON register located at SFR address C8h.
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VMX51C1020
FIGURE 21: T IMER 2 AND COMPARE/CAPTURE UNIT
CCH3
10
T2IN
COCAH3
Enable Capture Comp Capture COCAH3
COCAH3
Capture
Sync
11
Data Latch
Compare
16-bit Comparator COCAH2
Enable Capture Comp Capture COCAH2
CCL3 CCH2
COCAH2 Data Latch
Capture
÷2
Compare
Capture
SYSCLK
1 ÷2 0 1 ÷12 0
01
T2INxx
COCAH1
Enable Capture
16-bit Comparator Data Latch
Capture Capture
CCL2 CCH1
Comp Capture COCAH1
00
T2SIZE COCAH0
Enable Capture
16-bit Comparator Data Latch COCAH0
Compare Reload Capture
Compare
T2PSM T2PS
COCAH1
Capture
Timer 2
Comp Capture COCAH0
T2EX
Sync
TL2 TH2
Reload
16-bit Comparator Data Latch
CCL1 CRCH
Compare
COCAH0
CRCL
INPUT/OUTPUT Control
T2EXIF T2EXIE
INTCOMP3 INTCOMP2 INTCOMP1 INTCOMP0 CCU0 CCU1 CCU2 P1.0-PWM0 P1.1-PWM1 P1.2-PWM2 P1.3-PWM3
T2IF
Interrupt Request
Timer2 Clock Sources
As previously stated, Timer2 can operate in Timer mode, in which case it derives its source from the System Clock (SYSCLK) or it can be configured as an event counter where the High to Low transition on the T2IN input makes the Timer 2 to increment. The T2IN0 and T2IN1 bits of the T2CON register serve to define the selected Timer2 input and the operating mode of Timer2 (see following table).
T IMER 2 CLOCK SOURCE
Timer2 Operating Modes
When the T2IN1 bit is set to 0 and the T2IN0 bit is set to 1, Timer2 derives its source from the internal pre-scaled clock or not, depending on the T2PSM bit value. Event Counter Mode When operating in the Event Counter Mode, the timer is incremented as soon as the external signal T2IN transitions from a 1 to a 0. A sample of the T2IN input is taken at every machine cycle. Timer 2 is incremented in the cycle following the one in which the transition was detected. Gated Timer Mode In the Gated Timer Mode, the internal clock, which serves as the Timer2 clock source, is gated by the external signal T2IN. In other words, when T2IN is high, the internal clock is allowed to pass through the AND gate. A low value of T2IN will diable the clock pulse. This provides the ability for an external device to control Timer2’s operation or to use Timer2 to monitor the duration of an event.
T2IN1 0 0 1 1
T2IN0 0 1 0 1
Selected Timer 2 input Timer 2 Stop Standard Timer mode using internal clock with or without prescaler External T2IN pin clock Timer2 Internal Clock is gated by the T2IN input When T2IN = 0, the Timer2 stop
When in Timer mode, Timer2 derives its source from the System Clock and the CLKDIVCTRL register will affect Timer 2’s operation. Timer 2 Stop When both T2IN1 and T2IN0 bit are set to 0, Timer2 is in STOP mode.
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VMX51C1020
Timer2 Clock Prescaler
When Timer2 is configured so that it derives its clock source from the System Clock, the Clock prescaling value can be controlled by software using the T2PSM and the T2PS bit of the T2CON register. The different system clock prescaling values are shown in the following table:
T2PSM 1 0 0 T2PS X 0 1 Timer 2 input clock SYSCLK / 2 SYSCLK / 12 SYSCLK / 24
Timer2 Mode 1 In Mode 1, a 16-bit reload from the CRCx register on the falling edge of T2EX occurs. This transition will set T2EXIF if T2EXIE is set. This action will cause an interrupt (providing that the Timer2 interrupt is enabled) and the T2IF flag value will not be affected. The value of the T2SIZE does not affect the Reload in Mode 1. Also, the reload operation is performed independently of the state of the T2EXIE bit.
FIGURE 22: T IMER 2 RELOAD MODE
T2EX Reload Mode 1
Timer2 Count Size
Timer2 can be configured to operate in 8-bit or 16-bit formats. The T2SIZE bit of the T2CON register selects the Timer2 count size. o o If T2SIZE = 0, Timer2 size is 16-bits If T2SIZE = 1, Timer2 size is 8-bits
Input Clock
Reload Mode 0 TL2
T2EXIE CRCL
Data Bus
Data Latch
Data Bus
Reload
Data Latch
Data Bus
Data Bus
Timer2 Reload Modes
The Timer2 reload mode is selected by the T2RM1 and T2RM0 bits of the T2CON register. The following figure shows the reload operation. Timer2 must be configured as a 16-bit Timer/Counter for the reload modes to be operational by clearing the T2SIZE bit. Timer 2 Mode 0 When the timer overflows, the T2IF overflow flag is set. Concurrently, this overflow causes Timer2 to be reloaded with the 16-bit value contained in the CRCx register, (which has been preset by software). This reload operation will occur during the same clock cycle in which T2IF was set.
TH2
CRCH EXF2 T2IF
Timer 2 interrupt request
Timer2 Overflows and Interrupts
Timer2’s interrupt is enabled when the Timer2 counter, the T2IF flag is set, and a Timer 2 interrupt occurs. A Timer2 interrupt may also be raised from T2EX if the T2EXIE bit of the IEN1 register is set. Finding the exact source of a Timer2 interrupt can be verified by checking the value of the T2IF and the T2EXIF bits of the IRCON register. Timer2’s interrupt vector is located at address 002Bh
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VMX51C1020
Timer2 Setup Example
In order to use Timer2, one must first set up and configure the module (see following code example).
//--------------------------------------------------------------------------// Sample C code to setup Timer 2 //--------------------------------------------------------------------------// (…) PROGRAM INITIALIZATION OMITTED at 0x100 void main(void){ // TIMER 2 & Interrupt setup DIGPWREN = 0x80; T2CON = 0x01; TL2 = 0xE0; TH2 = 0xFF; IEN0 |= 0x80; IEN0 |= 0x20; do{ }while(1); }//end of main() //--------------------------------------------------------------------------// Timer 2 Interrupt Function //--------------------------------------------------------------------------void int_timer_2 (void) interrupt 5 { IEN0 &= 0x7F; // Disable all interrupts /*------------------------*/ /*Interrupt code here*/ /*------------------------*/ IEN0 |= 0x80; } // Enable all interrupts // Enable Timer2, // Set timer 2 to OSC/12
Mnemonic COCAH0 0 0 1 1 COCAH1 0 0 1 1
Bit Mnemonic COCAL0 0 1 0 1 COCAL1 0 1 0 1 COCAL2 0 1 0 1 COCAL3 0 1 0 1
// Enable all interrupts // Enable interrupt Timer 2 //wait for Timer 2 interrupt
COCAH2 0 0 1 1 COCAH3 0 0 1 1
Function Compare and Capture mode for CRC register Compare/capture disabled Capture on a falling edge at pin CCU0 (1 cycle) Compare enabled (PWM0) Capture on write operation into register CRC1 Compare/capture mode for CC register 1 Compare/capture disabled Capture on a rising edge at pin CCU1 (2 cycles) Compare enabled (PWM1) Capture on write operation into register CCL1 Compare/capture mode for CC register 2 Compare/Capture disabled Capture on a rising edge at pin CCU2 (2 cycles) Compare enabled (PWM2) Capture on write operation into register CCL2 Compare/Capture mode for CC register 3 Compare/capture disabled N/A - CCU3 not pinned out Compare enabled (PWM) Capture on write operation into register CCL3
Timer2 Special Modes
For general timing/counting operations, the VMX51C1020’s Timer2 includes 4 Compare and Capture units that can be used to monitor specific events and serve to drive PWM outputs. Each Compare and Capture unit provides three specific operating modes that are controlled by the CCEN register. These 3 modes are:
o o o Compare Modes Enable. Capture on write into CRCL/CCLx registers. Capture on transitions at CCU input pins level.
6 COCAL3 2 COCAL1 5 COCAH2 1 COCAH0 4 COCAL2 0 COCAL0
This allows individual configuration and operation of each Compare and Capture Unit.
Compare/Capture & Reload Registers
Each Compare and Capture Unit has a specific 16-bit register accessible via two SFR addresses. Note that the CRCHx/CRCLx registers associated with Compare/Capture Unit 0 are the only ones that can be used to perform a reload of Timer2 operation. The following tables describe the different registers that may be captured or compared to the value of Timer2.
TABLE 52: (CRCL) COMPARE/RELOAD/CAPTURE REGISTER, LOW BYTE - SFR CAH
TABLE 51: (CCEN) COMPARE/C APTURE E NABLE REGISTER -SFR C9H
7 COCAH3 3 COCAH1
7
6
5
The CCEN register bits are grouped in pairs of COCAHx/COCALx bits. Each pair corresponds to one Compare and Capture Unit. The Compare and Compare unit operating mode vs. the configuration bit is described in the following table.
4 3 CRCL [7:0]
2
1
0
TABLE 53: (CRCH) COMPARE/RELOAD /C APTURE REGISTER, HIGH BYTE - SFR CB H
7
6
5
4 3 CRCH [7:0]
2
1
0
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VMX51C1020
TABLE 54: (CCL1) COMPARE/C APTURE REGISTER 1, LOW BYTE - SFR C2H
7
6
5
4 3 CCL1 [7:0]
2
1
0
Capture Mode 0 In Capture Mode 0, a transition on a given CCU pin triggers the latching of Timer2 data into the associated Compare/Capture register. Capture Mode 1
TABLE 55: (CCH1) COMPARE/C APTURE REGISTER 1, HIGH BYTE - SFR C3 H
7
6
5
4 3 CCH1 [7:0]
2
1
0
TABLE 56: (CCL2) COMPARE/C APTURE REGISTER 2, LOW BYTE - SFR C4H
7
6
5
4 3 CCL2 [7:0]
2
1
0
In Capture Mode 1, a capture of the Timer2 value will occur upon writing to the Low Byte of the chosen capture register. Note: On the VMX51C1020, the CCU3 input is NOT pinned out.
FIGURE 23: T IMER 2 CAPTURE MODE 0 FOR CRCL AND CRCH BLOCK DIAGRAM
CCUx Pin Write to CRCL, CCLx
Capture Mode 0 Capture Mode 1
TABLE 57: (CCH2) COMPARE/C APTURE REGISTER 2, HIGH BYTE - SFR C5 H
7
6
5
4 3 CCH2 [7:0]
2
1
0
TABLE 58: (CCL3) COMPARE/C APTURE REGISTER 3, LOW BYTE - SFR C6H
7
6
5
4 3 CCL3 [7:0]
2
1
0
TABLE 59: (CCH3) COMPARE/C APTURE REGISTER 3, HIGH BYTE - SFR C7 H
7
6
5
4 3 CCH3 [7:0]
2
1
0
TL2
CRCL / CCLx
Compare/Capture Data Line Width
The VMX51C1020 is capable of comparing and capturing data using data lines up to 16 bits wide. When comparing 2 registers or capturing 1 register, it is required to set the T2SIZE bit of the T2CON register to 1. This adjusts the line width to 8-bits. When comparing two pairs of registers, for example, CCH1 and CCL1 to TH2 and TL2, the T2SIZE bit must be set to 0. This adjusts the line width to 16 bits.
Input Clock
Data Bus
Data Latch
Data Bus
Reload
Data Latch
Data Bus
Data Bus
T2IF
Timer 2 interrupt request
TH2
CRCH / CCHx
The Capture modes can be especially useful for external event duration calculation with the ability to latch the timer value at a given time (computation can then be performed at a later time). When operating in Capture Modes, the Compare and Capture units don’t affect the VMX51C1020 Interrupts.
Timer2 Capture Modes
The Timer2 Capture Modes allow acquiring and storing the 16-bit contents of Timer2 into a Capture/Compare register following a MOV SFR operation or the occurrence of an external event on one of the CCU pins (described in the following table).
Capture input CCU0 CCU1 CCU2 Timer 2 Capture triggering event High to Low Transition on CCU0 Low to High Transition on CCU1 Low to High Transition on CCU2
Timer2 Compare Modes
In Compare Mode, a Timer2 count value is compared to a value that is stored in the CCHxx/CCLx or CRCHx/CRCLx registers. If the values compared match (i.e. when the pulse changes state), a Compare/Capture interrupt is generated, if enabled. Varying the value of the CCHx/CCLx or CRCHx/CRCLx allows a variation of the rectangular pulse generated at the output. This variation can be used to perform pulse width modulation. See PWM in the following section. In order to activate the Compare Mode on one of the four Compare Capture Units, the associated COCAHx and COCALx bits must be set to 1 and 0, respectively
Timer2 capture is done without affecting Timer2 operation. Each individual Compare and Capture Unit can be configured for Capture Mode by configuring the appropriate bit pair of the CCEN register. The two Capture modes are Mode 0 and Mode 1.
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VMX51C1020
When the Compare Mode is enabled, the corresponding output pin value is under the control of the internal timer circuitry. On the VMX51C1020, two Compare Modes are possible. In both modes, the new value arrives at port pin 1 in the same clock cycle as the internal compare signal is activated. The T2CM of the T2CON register defines the Compare Mode and is described in the following paragraphs. Compare Mode 0 A functional diagram of Compare Mode 0 is shown below. A comparison is made between the 16-bit value of the Compare/Capture registers and the TH2, TL2 registers. When the Timer2 value exceeds the value stored in the CRCH, CRCL / CCHx, CCLx registers, a high compare signal is generated and a Compare/Capture interrupt is activated if enabled. If T2SIZE = 1, the comparison is made between the TL2 and CRCL/CCLx register. This compare signal is then propagated to the pin corresponding P1.x Pin(s) and to the associated COMPINTx interrupt (if enabled). The corresponding P1.x pin is reset when a Timer2 overflow occurs.
FIGURE 24: T IMER 2 COMPARE MODE 0 BLOCK DIAGRAM
(x=0 to3) will not appear on the physical port pin until the next compare match occurs. As is the case in Compare Mode 0, the Compare signal in Mode 1 can also generate an interrupt (if enabled). The figure below shows the operating structure of a given Capture Compare unit operating in Compare Mode 1.
FIGURE 25: T IMER 2 COMPARE MODE 1 BLOCK DIAGRAM
CRCH, CCHX
CRCL, CCLX
Comparator
Compare Signal
COMPxINT Interrupt
Shadow Register
TH2
TL2
Data Latch
Port Register Circuit
Timer 2
Overflow Timer 2 Interrupt
P1.0PWM0
Output Register
P1.1PWM1
P1.2PWM2
P1.3PWM3
Timer 2 Compare Mode Interrupt
Configuration of the Compare and Capture Units for the “Compare Mode” through the CCEN register has an impact on the Interrupt structure of the VMX51C1020. In that specific mode each Compare Capture Unit takes control of one interrupt line. When using the PWM output device, some care must be excercised to avoid other peripheral interrupts from being blocked by this mechanism.
CRCH, CCHX
CRCL, CCLX
Comparator
Compare Signal
COMPxINT Interrupt
Set Register
TH2 TL2
Timer 2
Overflow Reset Timer 2 Register Interrupt
P1.0PWM0 P1.1PWM1 P1.2PWM0 P1.3PWM0
Compare Mode 1 When a given Compare Capture unit is operating in Mode 1, any write operations to the corresponding output register of the port P1.x
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VMX51C1020
FIGURE 26: COMPARE AND CAPTURE UNIT INTERRUPT CONTROL
COMPINT0 Interrupt 1
Interrupt Vector 0053h
SPI Rx & RxOV INT
Mode). As long as the value present in the Compare and Capture register is greater than the Timer2 value, the Compare unit will output a logic low. When the value of Timer2 equals the value of the Compare and Capture register, the Compare unit will change from a logic Low to a logic High. The clock source for the PWM is derived from Timer2; which is incremented at every signal pulse of the appropriate source. The source is selected by the T2IN1 and T2IN0 bits of the T2CON register The T2SIZE bit of the T2CON register allows configuring the PWM output for 8 or 16-bit operation. The Timer2 Size affects all the PWM outputs. When the Timer2 Size is 8-bits, the comparison is performed between Timer2 and the LSB of the Compare and Capture Unit register. The resulting PWM resolution is 8-bit. When the Timer2 Size is configured for 16-bit operation, the comparison is performed between Timer2 and the contents of the whole Compare and Capture Unit register. The resulting PWM resolution is 16-bits but the PWM frequency is consequently low. When the System clock is used as the Timer2 clock source, the PWM output frequency equals the Timer2 overflow rate. Note that the CLKDIVCTRL register contents affects Timer2 operation and thus, PWM output frequency.
Fosc 14.74MHz T2CON T2PSM 1 1 0 0 0 0 T2CON T2PS X x 0-12 0-12 1-24 1-24 T2CON T2SIZE 0 1 1-8 0-16 1-8 0-16 Freq PWM 112.5Hz 28.8KHz 4.8KHz 18.8Hz 2.4KHz 9.38Hz
0
CCEN(1,0) = 1,0
COMPINT1 Interrupt
1
Interrupt Vector 005Bh
I2C INT
0
CCEN(3,2) = 1,0
COMPINT2 Interrupt
1
Interrupt Vector 0063h
MAC Overflow INT
0
CCEN(5,4) = 1,0
COMPINT3 Interrupt
1
Interrupt Vector 006Bh
ADC & Port Change INT
0
CCEN(7,6) = 1,0
Using Timer 2 for PWM Outputs
Configuring the Compare and Capture Units in Compare Mode 0 allows PWM output generation on the Port1 I/O pins. This mode can be used for PWM applications such as: o o o o D/A conversion Motor control Light control Etc.
When one specific Compare and Capture unit is configured for this mode, its associated I/O pin is reserved for this operation only and any write operation to the associated I/O pin of the P1 register will have no effect on it. The following table shows the association between the Compare and Capture Units, associated registers and I/O pin
TABLE 60: COMPARE AND C APTURE UNIT P WM ASSOCIATION
Compare Capture Unit 0 1 2 3
Registers
CRCH / CRCL CCH1 / CCL1 CCH2 / CCL2 CCH3 / CCL3
I/O pin
P1.0 P1.1 P1.2 P1.3
PWM signal generation is derived from the comparison result between the values stored into the capture compare registers and the Timer2 value. When a digital value is written into one of the Compare and Capture registers, a comparison is performed between this register and the Timer2 value (providing that Timer2 is in Compare
The duty cycle of the PWM output is proportional to the ratio of the Compare and Capture Unit register’s content versus the Maximum Timer2 number of cycles before overflow: 256 or 65536, depending on the T2SIZE bit value
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VMX51C1020
PWM Duty Cycle Calculation: 8-bit
PWM duty cycle CCU0 (%) = 100% x (256-CRCL)_ 256
Using the PWM as a D/A Converter
One of the popular uses of the PWM is to perform D/A conversion by low pass filtering its’ modulated square wave output. The greater the duty cycle of the square wave, the greater the DC value is at the output of the low pass filter and vice versa. Variations in the duty cycle of the PWM when filtered can therefore generate arbitrary waveforms.
PWM duty cycle CCU1-3 (%) = 100% x
(256-CCLx)_ 256
PWM Duty Cycle Calculation: 16-bit
PWM duty cycle CCU0 (%) = 100% x 65536–(CRCH, CRCL) (CRCH, CRCL)
PWM duty cycle CCU1-3 (%) = 100% x 65536–(CRCH, CRCL) (CRCH, CRCL)
PWM Configuration Example
The following example shows how to configure the Timer2 based PWM in 8-bit mode.
(…) DIGPWREN = 0x80; T2CON = 0x61; //ENABLE TIMER 2 MODULE //BIT 7 - Select 0=1/12, 1=1/24 of Fosc //BIT 6 - T2 clk source: 0 = Presc, 1=clk/2 //BIT 5 - T2 size: 0=16-bit, 1=8-bit //BIT 4,3 - T2 Reload mode: //BIT 2 - T2 Compare mode //BIT 1,0 - T2 input select: 01= input derived from osc.
//W HEN THE P WM IS CONFIGURED IN 16-BIT FORMAT, THE P WM OUTPUT FREQUENCY IS GIVEN BY //THE FOLLOWING EXPRESSION: // PWM Freq = [(FOSC/2)] / 65536 // W ITH A 14.7456MHZ CRYSTAL PWM FREQUENCY = 112.5HZ //When the PWM is configured in 8-bit its output freq = [(Fosc/2)] / 256 //USING A 14.7456MHZ CRYSTAL PWM FREQUENCY = 28.8KHZ CCEN = 0x0AA; //Enable Compare on 4 PWM outputs
// In 16-bit PWM resolution both LSB and MSB of compare unit are used //In 8-bit PWM Resolution, only the LSB of compare units are used // and MSB is kept to 00h CRCL = 0x0E6; x100% CRCH = 0x000; CCL1 = 0x0C0; x100% CCH1 = 0x000; CCL2 = 0x080; CCH2 = 0x000; CCL3 = 0x033; CCH3 = 0x000; P1PINCFG = 0x0F; //PWM0 duty = [(256-CRCL)/256] //E6h => 10.1% //PWM1 duty = [(256-CCL1)/256] //C0h => 25% //PWM2 duty = [(256-CCL2)/256] x100% //80h => 50% //PWM3 duty = [(256-CCL3)/256] x100% //33h => 80% //Configure P1 LSQ as output to enable PWM
(…)
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VMX51C1020
Serial UART Interfaces
The VMX51C1020 includes two serial UART interface ports (UART0 and UART1). Each serial port has a 10-bit timer devoted to baud rate generation. Both serial ports can operate in full duplex mode. The VMX51C1020 also includes a double buffer, enabling the UART to accept an incoming word before the software has read the previous value.
UART0 Control Register
UART0 configuration is performed mostly via the S0CON SFR register located at address 98h.
TABLE 62: (S0CON) SERIAL PORT 0, CONTROL REGISTER - SFR 98H
7 S0M0 3 T0B8 Bit 7 6 5 4 Mnemonic S0M0 S0M1 MPCE R0EN
6 S0M1 2 R0B8
5 MPCE0 1 T0I
4 R0EN 0 R0I
UART0 Serial Interface
The operation of UART0 of the VMX51C1020 is similar to the standard 8051 UART. UART0 can derive its clock source from a 10-bit dedicated baud rate generator or from the Timer1 overflow.
3
T0B8
2
R0B8
UART0’s Transmit and Receive buffers are accessed through a unique SFR register named S0BUF.
1 T0I
The UART0 S0BUF has a double buffering feature on reception which allows accepting an incoming word before the software has read the previous value from the S0BUF.
TABLE 61: (S0BUF) SERIAL PORT 0, DATA B UFFER - SFR 99H
0
R0I
Function Sets Serial Port Operating Mode See Table 1 = Enables the multiprocessor communication feature. 1 = Enables serial reception. Cleared by software to disable reception. th The 9 transmitted data bit in Modes 2 and 3. Set or cleared by the CPU, depending on the function it performs (parity check, multiprocessor communication etc.) th In Modes 2 and 3, it is the 9 data bit received. In Mode 1, if sm20 is 0, RB80 is the stop bit. In Mode 0, this bit is not used. Must be cleared by software. Transmit interrupt flag set by hardware after completion of a serial reception. Must be cleared by software. Receive interrupt flag set by hardware after completion of a serial reception. Must be cleared by software.
7
6
5
4 3 S0BUF [7:0]
2
1
0
UART0 Operating Modes
UART0 can operate in four distinct modes, which are defined by the SM0 and SM1 bits of the S0CON register (see following table).
TABLE 63: SERIAL PORT 0 MODES
S M0 0 0 1 1
**Note
SM1 0 1 0 1
MODE 0 1 2 3
DESCRIPTION Shift Register 8-bit UART 9-bit UART 9-bit UART
BAUD RATE Fosc/12 Variable Fclk/32 or /64 Variable
that the speed in mode 2 depends on SMOD bit in the Special Function Register PCON when SMOD = 1 fclk/32
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VMX51C1020
UART0 - Mode 0 In this Mode, pin RX0 is used as an input and an output, while TX0 is used only to output the shift clock. For an operation in this mode, 8 bits are transmitted with the LSB as the first bit. Additionally, the baud rate is fixed at 1/12 of the crystal oscillator frequency. In order to initialize reception in this mode, the user must set bits R0I and R0EN in the S0CON register to 0 and 1, respectively. Note that in other Modes, when R0EN=1, the interface begins to receive data. UART0 - Mode 1 In this Mode, the RX0 pin serves as an input and the TX0 pin as a serial output and no external shift clock is used. In Mode 0, 10-bits are transmitted: o Start bit (logic low); o 8-bits of data (LSB first); o A stop bit (logic high). The start bit synchronizes data reception, with the 8-bits of received data then being available in the S0BUF register. Reception is completed once the stop bit sets the R0B8 flag in the S0CON register. UART0 - Mode 2 In this Mode the RX0 pin is used as an input and an output while TX0 is used to output the shift clock. In Mode 2, 11 bits are transmitted/received. hese 11-bits consist of: o o o o Start bit (logic low) 8 bits of data (LSB first), One programmable 9th bit, Stop bit (logic high).
UART0 - Mode 3 Mode 3 is essentially identical to Mode 2, with the difference being that the internal baud rate generator or Timer1 can be used to set the baud rate.
UART0 - Baud Rate Generator Source
As mentioned previously, the UART0 baud rate clock can be sourced from either Timer 1 or the dedicated 10-bit baud rate generator. Selection between these sources is enabled via the BAUDSRC bit of the U0BAUD register (see following table).
TABLE 64: (U0BAUD) UART0 BAUD RATE SOURCE SELECT - SFR D8H
7 BAUDSRC 7
6 -
5 -
4 -
3 -
2 -
1 -
0 -
BAUDSRC
6:0
-
Baud rate generator clock source 0 = Timer 1 1 = Use UART0 dedicated Baud rate generator -
The 9th bit is used for parity. In the data transmission case, bit TB80 of the S0CON is th th output as the 9 bit. For reception, the 9 bit will be stored captured in the RB80 bit of the S0CON register.
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VMX51C1020
Using the UART0 dedicated baud generator, frees up Timer 1 for other uses.
rate
Timer1 can also be used as the baud rate generator for the UART0. Set BAUDSRC to 0 and assign Timer1’s output to UART0. When the baud rate clock source is derived from Timer1, the baud rate and timer reload values can be calculated using the following formulas (examples follow).
TABLE 69: EQUATION TO CALCULATE BAUD R ATE FOR SERIAL 0
The S0RELH and S0REL registers are used to store the 10-bit reload value of the UART0 baud rate generator.
TABLE 65: (S0RELL) SERIAL PORT 0, RELOAD REGISTER, LOW BYTE - SFR 96H
7
6
5
4 3 S0RELL [7:0]
2
1
0
TABLE 66: (S0RELH) SERIAL PORT 0, RELOAD REGISTER, HIGH BYTE - SFR 97 H
7
6
5
4 3 S0RELH [15:8]
2
1
0
Serial 0: mode 1 and 3 Mode 1: ForU0BAUD.7=0 (standard mode) Baud Rate = 2 x fclk _ 32 x 12 x (256-TH1)
SMOD
The following equations should be used to calculate the reload value for the SOREL register (examples follow).
Mode 3: For BAUDSRC=1 SOREL = 1024 – 2 x fclk_______ 64 x Baud Rate
SMOD
TH1 = 256 -
2 x fclk____ 32x12x Baud Rate
SMOD
TABLE 70: UART 0 BAUD R ATE SAMPLE VALUES BAUDSRC =0, SMOD = 1
Baud Rate =
2 x fclk____ 64 x (1024 – S0REL)
SMOD
Desired Baud Rate
TH1 @ fclk= 11.059 MHz
TH1 @ fclk= 14.75 MHz
TABLE 67: SERIAL 0 BAUD R ATE SAMPLE VALUES BAUDSRC = 1, SMOD = 1
Desired Baud Rate
S0REL @ fclk= 11.059 MHz
S0REL @ fclk= 14.75 MHz
500.0 kbps 460.8 kbps 230.4 kbps 115.2 kbps 57.6 kbps 19.2 kbps 9.6 kbps 2.4 kbps 1.2 kbps 300 bps
3FDh 3FAh 3EEh 3DCh 370h 2E0h -
3FFh 3FEh 3FCh 3F8h 3E8h 3D0h 340h 280h -
115.2 kbps 57.6 kbps 19.2 kbps 9.6 kbps 2.4 kbps 1.2 kbps 300 bps
FFh FDh FAh E8h D0h 40h
FCh F8h E0h C0h -
TABLE 71:UART 0 BAUD R ATE SAMPLE VALUES BAUDSRC =0, SMOD = 0
Desired Baud Rate
TH1 @ fclk= 11.059 MHz
TH1 @ fclk= 14.75 MHz
TABLE 68: SERIAL 0 BAUD R ATE SAMPLE VALUES BAUDSRC =1, SMOD = 0
Desired Baud Rate
S0REL @ fclk= 11.059 MHz
S0REL @ fclk= 14.75 MHz
115.2 kbps 57.6 kbps 19.2 kbps 9.6 kbps 2.4 kbps 1.2 kbps 300 bps
FDh F4h E8h A0h
FEh FCh F0h E0h 80h
115.2 kbps 57.6 kbps 19.2 kbps 9.6 kbps 2.4 kbps 1.2 kbps 300 bps
3FDh 3F7h 3EEh 3B8h 370h 1C0h
3FEh 3FCh 3F4h 3E8h 3A0h 340h 100
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VMX51C1020
Example of UART0 Setup and Use
In order to use UART0, the following operations must be performed: o Enable the UART0 Interface o Set I/O Pad direction TX= output, RX=Input o Enable Reception (if required) o Configure the Uart0 controller S0CON The following are configuration and transmission code examples for UART0.
//----------------------------------------------------------------------------------------// // UART0 CONFIG with S0REL // // Configure the UART0 to operate in RS232 mode at 19200bps // with a crystal of 14.7456MHz // //----------------------------------------------------------------------------------------// void uart0ws0relcfg() { P3PINCFG |= 0x01; // pads for uart 0 DIGPWREN |= 0x01; // enable uart0/timer1 S0RELL = 0xF4; //com speed = 19200bps S0RELH = 0x03; S0CON = 0x50; // Uart0 in mode1, 8 bit, var. baud rate U0BAUD = 0x80; //Set S0REL is source for UART0 //Baud rate clock }//end of uart0ws0relcfg() function //----------------------------------------------------------------------------------------// // UART0 CONFIG with Timer 1 // // Configure the UART0 to operate in RS232 mode at 19200bps // with a crystal of 14.7456MHz // //----------------------------------------------------------------------------------------// void uart0wTimer1cfg() { P3PINCFG |= 0x01; // pads for uart0 DIGPWREN |= 0x01; // enable uart0/timer1 TMOD &= 0x0F; TMOD =0x20; //Set Timer 1, Gate 0, Mode 2 TH1 = 0xFE; //Com Speed = 19200bps TCON &= 0x0F; TCON =0x40; //Start Timer 1 U0BAUD = 0x00; //Set Timer 1 Baud rate //generator for UART0 PCON = 0x00; S0CON = 0x50; }//end of uart1Config() function //----------------------------------------------------------------------------------------// // Txmit0() // // One Byte transmission on UART0 //----------------------------------------------------------------------------------------// // - Constants definition sbit UART_TX_EMPTY = USERFLAGS^1; void txmit0( unsigned char charact){ S0BUF = charact; USERFLAGS = S0CON; //Wait TX EMPTY flag to be raised while (!UART_TX_EMPTY) {USERFLAGS = S0CON;} S0CON = //clear both R0I & T0I bits S0CON & 0xFD; }//end of txmit0() function //Set SMOD = 0 // Config Uart0 in mode 1, //8 bit, variable baud rate
See the Interrupt section for example of setup of UART0 interrupts
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VMX51C1020
UART1 Serial Interface
The UART1 serial interface is based on a subset of UART0. It provides two operating modes and its clock source is derived exclusively from a dedicated 10-bit baud rate generator. The UART1 Transmit and Receive buffers are accessed via SFR register S1BUF.
TABLE 72: (S1BUF) SERIAL PORT 1, DATA B UFFER - SFR C1H
UART1: Operating Modes
The VMX51C1020 UART1 has two operating Modes, A and B, which provide 9 or 8-bit operation, respectively (see following table).
TABLE 74: UART1 MODES
SM
MODE
DESCRIPTION
BAUD RATE
0 1
A B
9-bit UART 8-bit UART
Variable Variable
7
6
5
4 3 S1BUF [7:0]
2
1
0
UART1 - Mode A In this Mode, 11 bits are transmitted or received. These 11 bits are composed of: o A start bit (logic low), o 8 bits of data (LSB first), o A programmable 9th bit, o Stop bit (logic high). As in Mode 2 and 3 of UART0, the 9th bit is used for parity. For data transmission, the TB81 bit of the S1CON register holds the 9th bit. In the case of reception, the 9th bit will be captured into the R1B8 bit of the S1CON register. UART1 - Mode B In this of: o o o Mode, 10 bits are transmitted and consist A start bit (logic low) 8 bits of data (LSB first); A stop bit (logic high).
As is the case with UART0, UART1 includes a double buffering feature in order to avoid overwriting of the receive register.
UART1 Control Register
UART1 is controlled by the S1CON register. The following table provides a description of the UART1 Control Register.
TABLE 73: (S1CON) SERIAL PORT 1, CONTROL REGISTER - SFR C0H
7 S1M 3 T1B8 Bit 7 6 5 4
6 Reserved 2 R1B8
5 MPCE1 1 T1I
4 R1EN 0 R1I
Mnemonic S1M Reserved MPCE1 R1EN
3
T1B8
2
R1B8
1
T1I
0
R1I
Function Operation mode Select 1 = Enables multiprocessor communication feature. If set, enables serial reception. Cleared by software to disable reception. th The 9 transmitted data bit in mode A. Set or cleared by the CPU, depending on the function it performs (parity check, multiprocessor communication, etc.) th In Mode A, it is the 9 data bit received. In Mode B, if SM21 is 0, RB81 is the stop bit. Must be cleared by software. Transmit interrupt flag, set by hardware after completion of a serial transfer. Must be cleared by software Receive interrupt flag, set by hardware after completion of a serial reception. Must be cleared by software
Received data (8-bit) is read via the S1BUF register. Reception is completed once the stop bit sets the R1B8 flag in the S1CON register.
UART1 - Baud Rate Generator
As previously mentioned, UART1’s clock source is derived from a dedicated 10-bit baud rate generator module.
The S1REL registers are used to adjust the baud rate of UART1.
TABLE 75: (S1RELL) UART1, RELOAD REGISTER, LOW BYTE - SFR BEH
7
6
5
4 3 S1RELL [7:0]
2
1
0
TABLE 76: (S1RELH) UART 1, RELOAD REGISTER, HIGH BYTE - SFR BFH
7
6
5
4 3 S1RELH [7:0]
2
1
0
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VMX51C1020
The following formulas are used to calculate the baud Rate, S1RELL and S1RELH values.
Serial 1 Baud Rate= f clk__________ 32 x (1024-S1REL) Note: S1REL.9-0 = S1RELH.1-0 + S1RELL.7-0 S1REL = 1024 fclk__________ 32 x Baud Rate
Example of UART1 Setup and Use
The following are C code examples of UART1 configuration, serial byte transmission and interrupt usage.
//----------------------------------------------------------------------------------------// // UART1 CONFIG // // Configure the UART1 to operate in RS232 mode at 115200bps // with a crystal of 14.7456MHz //----------------------------------------------------------------------------------------// void uart1Config(void) { P0PINCFG |= 0x04; // pads for uart 1 DIGPWREN |= 0x02; // enable uart1 S1RELL = 0xFC; // Set com speed = 115200bps S1RELH = 0x03; S1CON = 0x90; // Mode B, receive enable }//end of uart1Config() function
TABLE 77: SERIAL 1 BAUD R ATE SAMPLE VALUES
Desired Baud Rate
S1REL @ fclk= 11.0592 MHz
S1REL @ fclk= 14.746 MHz
500.0 kbps 460.8 kbps 230.4 kbps 115.2 kbps 57.6 kbps 19.2 kbps 9.6 kbps 2.4 kbps 1.2 kbps
3FDh 3FAh 3EEh 3DCh 370h 2E0h
3FFh 3FEh 3FCh 3F8h 3E8h 3D0h 34Fh 280h
//----------------------------------------------------------------------------------------// // TXMIT1 -- Transmit one byte on the UART1 //----------------------------------------------------------------------------------------// void txmit1( unsigned char charact){ S1BUF = charact; USERFLAGS = S1CON; while (!UART_TX_EMPTY) {USERFLAGS = S1CON;} //Wait TX EMPTY flag S1CON = S1CON & 0xFD; //clear both R1I & T1I bits }//end of txmit1() function
Setting Up and Using UART1
In order to use UART1, the following operations must be performed: o
o
//----------------------------------------------------------------------------------------// // Interrupt configuration //---------------------------------------------------------------------------------------// IEN0 |= 0x80; IEN2 |= 0x01; // Enable all interrupts // Enable interrupt UART 1
o o
Enable the UART1 Interface Set I/O Pad direction TX= output, RX=Input Enable Reception (if required) Configure the UART1 controller S1CON
//----------------------------------------------------------------------------------------// // Interrupt function //----------------------------------------------------------------------------------------// void int_serial_1 (void) interrupt 16 { IEN0 &= 0x7F; /*------------------------*/ /*Interrupt code here*/ /*------------------------*/ if (S1CON&0x01==0x01) { S1CON &= 0xFE; } else { S1CON &= 0xFD; } IEN0 |= 0x80;} } } /-----------------------------------------------------------------------
// Disable all interrupts
// Clear RI (it comes // before T1I)
// Clear T1I // Enable all interrupts
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VMX51C1020
UART1 Driven Differential Transceiver
The VMX51C1020 includes a differential transceiver compatible with the J1708/RS485/RS-422 standards. These are driven by UART1. The Transceiver’s signals are differential which provide high electrical noise immunity. The differential interface is capable of transferring/recieving data over hundreds of feet of twisted pair wire. A number of devices can be connected in parallel to the differential bus in order to implement a multi-drop network. The number of devices that can be networked depends on the bus length and configuration. The admissible common mode voltage range of the differential interface is –2.0 V to +7.0 V. When implementing this type of transmission network over long distances in noisy environments, appropriate protection is recommended in order to prevent the common mode voltage from causing any damage to the VMX51C1020.
FIGURE 27: DIFFERENTIAL INTERFACE (J1708 CONFIG)
+5V
From the software point of view, the differential transceiver is viewed as differential UART. The differential transceiver I/Os are connected to UART1 of the VMX51C1020, therefore communication parameters such as the data length, speed, etc are managed by the UART1 peripheral interface/registers.
Using the UART1 Differential Transceiver
In order to use the Differential Transceiver interface, one must perform the following operations: o Enable UART1 and the differential interface by setting bits 1 and 2 of the DIGPWREN register. Configure UART1’s operating mode via the S1CON register. Set the baud rate via the S1RELH and S1RELL registers. Enable UART1’s interrupt, if required
o
o
o
Versa Mix
TX1D+
TX1D-
+5V
Use UART1’s S1BUF register to transmit and receive data through the differential transceiver. If the P0.2 pin is configured as an output, the signal corresponding to the TX1 signal of UART1 will appear on this pin (note that the P0.3-RX1 pin can be used as regular digital output). When the transceiver is connected in HalfDuplex mode (RX1D+ connected to TX1D+ and RX1D- connected to TX1D-) and UART1’s interrupts are enabled, careful management of the UART1 interrupts will be required as every byte transmitted will generate a local Rx interrupt.
RX1D+
RX1D-
FIGURE 28: DIFFERENTIAL INTERFACE (RS485 CONFIG)
+5V
Versa Mix
TX1D+
TX1D-
RX1D+
RX1D-
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VMX51C1020
Differential Interface Use Example
The following code provides and an example of configuration and use of the VMX51C1020 Differential Interface.
#pragma SMALL #pragma UNSIGNEDCHAR #include // --- function prototypes void txmit1( unsigned char charact); void uart1differential(void); // - global variables // - Constants definition sbit UART_TX_EMPTY = USERFLAGS^1; code char irq0msg[]="Ramtron inc”; //---------------------------------------------------------------------------------------------// // MAIN FUNCTION //---------------------------------------------------------------------------------------------// at 0x0100 void main (void) { // Enable and configure the UART1 uart1differential(); //---------------------------------------------------------------------------------------------// // EXT INT0 interrupt // // // when the External interrupt 0 is triggered A Message string is sent over the // the serial UART1 //---------------------------------------------------------------------------------------------// void int_ext_0 (void) interrupt 0 { int x=0; idata unsigned char IEN0 &= 0x7F; //disable ext0 interrupt cptr = cptr-1; while( irq0msg[cptr] != '\n') //Send a text string over the differential interface { txmit1( irq0msg[cptr]); cptr = cptr +1; } IEN0 = 0x81; //Enable all interrupts + int_0 //----------------------------------------------------------------------------------------------------// //------------------------------- Individual Functions ----------------------------------------// //----------------------------------------------------------------------------------------------------// //Config UART1 diff interface //----------------------------------------------------------------------------------------------------// // UART1 DIFFERENTIAL CONFIG // // Configure the UART1 differential interface to operate in // RS232 mode at 115200bps with a crystal of 14.7456MHz // //----------------------------------------------------------------------------------------------------// void uart1differential(void) { DIGPWREN |= 0x06; // enable uart1 & differential transceiver P0PINCFG |= 0x04; // pads for uart1 P0PINCFG = 0x00; S1RELL = 0xFC; // Set com speed = 115200bps S1RELH = 0x03; S1CON = 0x90; // Mode B, receive enable }//end of uart1differential() function //-----------------------------------------------------------------------------------------------// // TXMIT1 // // Transmit one byte on the UART1 Differential interface // //-----------------------------------------------------------------------------------------------// void txmit1( unsigned char charact){ S1BUF = charact; USERFLAGS = S1CON; //Wait TX EMPTY flag to be raised while (!UART_TX_EMPTY) {USERFLAGS = S1CON;} //clear both R1I & T1I bits // enable all interrupts S1CON = S1CON & 0xFD; }//end of txmit1() function //clear both R1I & T1I bits
cptr=0x01;
// Warning: The Clock Control circuit does affect the dedicated baud rate // generator S0REL, S1REL and Timer1 operation
//*** Configure the interrupts IEN0 |= 0x81; IEN2 |= 0x01; Txmit1(“A’); do { }while(1); }// End of main()...
//Enable interrupts + Ext. 0 interrupt //Enable UART1 Interrupt //Transmit one character on UART1
//Wait for UART1 Rx interrupt
//---------------------------------------------------------------------------------------------// // UART1 Differential interface interrupt // // In this example, the source of UART1 interrupt would be caused // by bytes reception on the differential interface //----------------------------------------------------------------------------------------------// void int_uart1 (void) interrupt 16 { unsigned char charact; IEN0 &= 0x7F; // -- Put you code here… S1CON = S1CON & 0xFC; IEN0 |= 0x80; }// end of uart1 INTERRUPT
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VMX51C1020
SPI Interface
The VMX51C1020’s SPI peripheral is a highly configurable and powerful interface enabling high speed serial data exchange with external devices such as A/Ds, D/Aa, EEPROMs, etc. The SPI interface can operate as either a master or a slave device. In master mode, it can control up to 4 slave devices connected to the SPI bus. The following lists a number VMX51C1020’s SPI features. o o o o o of the
FIGURE 29: SPI INTERFACE BLOCK DIAGRAM
VERSA MIX SPI INTERFACE
Serial Data IN SDI Serial Data OUT SDO Serial Clock IN/OUT SCK Chip Select Output CS0 Chip Select Output CS1 Chip Select Output CS2 To Slave Device #3 Chip Select Output Slave Select Input To Slave Device #4 From Master Device To Slave Device #2 To Slave Device #1
SPI SFRs
Processor
CS3
SPI IRQs
SS
Allows synchronous serial data transfers Transaction size is configurable from 132-bits and more. Full duplex support SPI Modes 0, 1, 2, 3 and 4 supported
(Full clock polarity and phase control)
SPI Transmit/Receive Buffer Structure
When receiving data, the first byte received stored in the SPIRX0 Buffer. As bits continue arrive, the data already present in the buffer shifted towards the least significant byte end the receive registers (see following figure). is to is of
o o o o
o o
Up to four slave devices can be connected to the SPI bus when it is configured in master mode Slave mode operation Data transmission speed is configurable Double 32-bit buffers in transmission and reception 3 dedicated interrupt flags o TX-Empty o RX Data Available o RX Overrun Automatic/Manual control of the chip selects lines. SPI operation is not affected by the clock control unit
For example (see following figure), assume the SPI is about to receive 4 consecutive bytes of data: W, X, Y and Z, where the first byte received is byte W, The first received byte (W) will be placed in the SPIRX0 register. Upon reception of the next byte (X), the contents of SPIRX0 will be shifted into SFR register SPIRX1 and byte X will be placed in the SPIRX0 registers. Following this same procedure, we bytes W, X, Y and Z will end up in RX data buffer registers SPIRX0, SPIRX1, SPIRX2 and SPIRX3, respectively. The case where the SDO and SDI pins are shorted together is represented in the following diagram.
The following provides a block diagram view of the SPI Interface.
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VMX51C1020
FIGURE 30 : SPI INTERFACE RECEIVE T RANSMIT SCHEMATIC
BEFORE A RECEPTION
TABLE 80: (SPIRX1TX2) SPI DATA BUFFER, BYTE 2 - SFR E3H
7
First Byte to be Transmitted
6
5
4 3 2 SPIRX1TX2 [23:16]
1
0
LSBit
MSBit
01234567
Bit 22:16
SPITX2 X SPITX1 Y SPITX0 Z msb
lsb TX Data Buffer msb RX Data Buffer
SPITX3 W
Mnemonic SPITX2 SPIRX1
Function SPI Transmit Data Bits 23:16 SPI Receive Data Bits 15:8
lsb SPIRX3 SPIRX2 SPIRX1 SPIRX0 First Byte Received is Placed in the least significant byte register
TABLE 81: (SPIRX0TX3) SPI DATA BUFFER, HIGH BYTE - SFR E4H
7
6
5
4 3 2 SPIRX0TX3 [31:24]
1
0
Bit 31:24
Mnemonic SPITX3 SPIRX0
Function SPI Transmit Data Bits 31:24 SPI Receive Data Bits 7:0
AFTER A RECEPTION
SPI Control Registers
SPITX0 msb
lsb TX Data Buffer msb RX Data Buffer
SPITX3
SPITX2
SPITX1
The SPI Control registers are used to define:
o o o
lsb Z SPIRX3 Y SPIRX2 X SPIRX1 W SPIRX0
Bytes are Shifted 1 byte position at a time each time a new byte is received MSBit LSBit
o
SPI operating speed (Master mode) Active Chip Select output (Master mode) SPI clock Phase (Master/Slave modes). SPI clock Polarity (Master/Slave modes).
7 6 SPICK [2:0] 2 SPICKPH 5 4 SPICS_1 0 SPIMA_SL
TABLE 82: (SPICTRL) SPI CONTROL REGISTER - SFR E5H
76543210 Close-Up View of how the bits within the byte is placed after it has been received
When using the SPI Interface, it is important to keep in mind that a transmission is started when the SPIRX3TX0 register is written to. From an SFR point of view, the transmission and reception buffers of the SPI interface occupy the following addresses.
TABLE 78: (SPIRX3TX0) SPI DATA BUFFER, LOW BYTE - SFR E1H
3 SPICS_0 Bit 7:5
1 SPICKPOL
Mnemonic SPICK[2:0]
7
6
5
4 3 2 SPIRX3TX0 [7:0]
1
0 4:3 SPICS[1:0]
Bit 7-0
Mnemonic SPITX0 SPIRX3 6 5
Function SPI Transmit Data Bits 7:0 SPI Receive Data Bits 31:24 4 3 2 SPIRX2TX1 [15:8] 1 0
TABLE 79: (SPIRX2TX1) SPI DATA BUFFER, BYTE 1 - SFR E2H
2 1
SPICKPH SPICKPOL
7
0 Bit 15:8 Mnemonic SPITX1 SPIRX2 Function SPI 1 Transmit Data Bits 15:8 SPI Receive 1 Data Bits 23:16
SPIMA_SL
Function SPI Clock control 000 = OSC Ck Div 2 001 = OSC Ck Div 4 010 = OSC Ck Div 8 011 = OSC Ck Div 16 100 = OSC Ck Div 32 101 = OSC Ck Div 64 110 = OSC Ck Div 128 111 = OSC Ck Div 256 Active CS line in Master Mode 00 = CS0- Active 01 = CS1- Active 10 = CS2- Active 11 = CS3- Active SPI Clock Phase SPI Clock Polarity 0 – CK Polarity is Low 1 – CK Polarity is High Master / -Slave 1 = Master 0 = Slave
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VMX51C1020
SPI Operating Speed
Three bit in the SPICTRL register serve to adjust the communication speed of the SPI interface.
SPICK[2:0] Div Ratio Clk Div 2 Clk Div 4 Clk Div 8 Clk Div 16 Clk Div 32 Clk Div 64 Clk Div 128 Clk Div 256 Fosc = 14.74MHz 7.37 MHz 3.68 MHz 1.84 MHz 922 kHz 461 kHz 230 kHz 115 kHz 57.6 kHz Fosc = 11.059MHz 5.53 MHz 2.76 MHz 1.38 MHz 691 kHz 346 kHz 173 kHz 86 kHz 43.2 kHz
SPI MODE 0: SPICKPOL =0,SPICKPH =0 CSX SCK SDO SDI
*Arrows indicate the edge where the data acquisition occurs
MSB
LSB
SPI Mode 1 o Data is placed on the SDO pin at the falling edge of the clock. Data is sampled on the SDI pin at the rising edge of the clock.
SPI Master Chip Select Control
When the SPI is configured in Master mode, the value of the SPICS[1:0] bits will define which Chip select pins will be active during the transaction. The following sections will describe how the SPI Clock Polarity and Phase affects the read and write operations of the SPI interface.
o
FIGURE 32: SPI MODE 1
SPI MODE 1: SPICKPOL =0,SPICKPH =1 CSX SCK SDO SDI
MSB LSB
SPI Operating Modes
The SPI interface can operate in four distinct modes defined by the SPICKPH and SPICKPOL bits of the SPICTRL register. SPICKPH defines the SPI clock phase and SPICKPOL defines the Clock polarity for data exchange.
*Arrows indicate the edge where the data acquisition occurs
SPICKPOL SPICKPH bit value bit value 0 0 0 1 1 0 1 1 SPI Mode 0 o o
SPI Operating Mode SPI Mode 0 SPI Mode 1 SPI Mode 2 SPI Mode 3
Data is placed on the SDO pin at the rising edge of the clock. Data is sampled on the SDI pin at the falling edge of the clock.
FIGURE 31 : SPI MODE 0
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VMX51C1020
SPI Mode 2 o o Data is placed on the SDO pin at the falling edge of the clock. Data is sampled on the SDI pin at the rising edge of the clock.
SPI Transaction Size
Many SPI based microcontrollers only allow a fixed SPI transaction size of 8-bits. However, most devices requiring SPI control require transactions of more than 8-bits, giving way to alternate inefficient means of dealing with SPI transactions. The VMX51C1020 SPI interface includes a transaction size control register, SPISIZE that enables different sized transaction to be performed. The SPI interface also automatically controls the Chip select line. The following table describes the SPISIZE register.
TABLE 83: (SPISIZE) SPI SIZE CONTROL REGISTER - SFR E7H
FIGURE 33: SPI MODE 2
SPI MODE 2: SPICKPOL =1,SPICKPH =0 CS X SCK SDO SDI
*Arrows indicate the edge where the data acquisition occurs
MSB
LSB
SPI Mode 3 o o Data is placed on the SDO pin at the rising edge of the clock. Data is sampled on the SDI pin at the falling edge of the clock.
7
6
5
4 3 SPISIZE[7:0]
2
1
0
Bit 7:0
Mnemonic SPISIZE[7:0]
Function Value of the SPI packet size
FIGURE 34: SPI MODE 3
SPI MODE 3: SPICKPOL =1,SPICKPH =1 CSX SCK SDO SDI
*Arrows indicate the edge where the data acquisition occurs
The following formula is used to calculate the transaction size. For SPISIZE from 0 to 31: SPI Transaction Size = [SPISIZE + 1]
MSB
LSB
For SPISIZE from 32 to 255*: SPI Transaction Size = [SPISIZE*8 - 216]
An SPI transaction size greater than 32 bits is possible when using the VMX51C1020 SPI interface, however, large data packets of this size require careful management of the associated interrupts in order to avoid buffer overwrites.
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VMX51C1020
SPI Interrupts
The SPI interrupts. o o o interface has three associated
TABLE 85: (SPIIRQSTAT) SPI INTERRUPT STATUS REGISTER - SFR E9H
7 3 SPISEL Bit 7:6 5 4
6 2 SPIOV Mnemonic SPITXEMPTO SPISLAVESEL
5
SPITXEMPTO
4
SPISLAVESEL
1 SPIRXAV Function
0 SPITXEMP
SPI RX Overrun SPI RX Data Available SPI TX Empty
The SPIRXOVIE, SPIRXAVIE and SPITXEMPIE bits of the SPICONFIG register allow individual enabling of the above interrupt sources at the SPI interface level. At the processor level, two interrupt vectors are dedicated to the SPI interface: o o SPI RX data available and Overrun interrupt SPI TX empty interrupt
3
SPISEL
2 1 0
SPIOV SPIRXAV SPITXEMP
Flag that indicates that we have not reloaded the transmit buffer fast enough (only used for packets greater than 32 bits.). Slave Select “NOT” (SSN) This bit is the result of the logical AND operation between CS0, CS1, CS2 and CS3. (Indicates if one chip is selected.) SPI Receiver overrun SPI Receiver available SPI Transmit buffer is ready to receive mode data. It does not flag that the transmission is completed.
In order to have the processor jump to the associated interrupt routine, you must also enable one or both of these interrupts in the IEN1 register as well as set the EA bit of the IEN0 register (see interrupt section).
TABLE 84: (SPICONFIG) SPI C ONFIG REGISTER - SFR E6H
SPI Manual Chip Select Control
In some applications, manual control of the active select line can be useful. Setting the SPICSLO bit of the SPICONFIG register forces the active chip select line to stay low when the SPI transaction is completed in Master mode. When the SPICSLO bit is cleared, the Chip select line returns to its inactive state.
7
SPICSLO
6
-
5
FSONCS3
4
SPILOAD
3 Bit 7
2 SPIRXOVIE Mnemonic SPICSLO
1 SPIRXAVIE
0 SPITXEMPIE
Function Manual CS up (Master mode) 0 = The CSx goes low when transmission begins and returns to high when it ends. 1 = The CSx stays low after transmission ends. The user must clear this bit for the CSx line to return high. This bit sends the frame select pulse on CS3. This bit sends load pulse on CS3. SPI Receiver overrun interrupt enable. SPI Receiver available interrupt enable. SPI Transmitter empty interrupt enable.
SPI Manual Load Control
The SPI can generate a LOAD pulse on the CS3 pin when the SPILOAD bit is set. This is useful for some D/A converters and avoids having to use a separate I/O pin for this purpose.
6 5 4 3 2 1 0
FSONCS3 SPILOAD SPIRXOVIE SPIRXAVIE SPITXEMPIE
The SPIIRQSTAT register contains interrupts flags associated with the interface.
the SPI
Monitoring these bits allows polling the control of the SPI interface.
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VMX51C1020
SPI Frame Select Control
It’s also possible to generate a positive pulse on the CS3 pin of the SPI interface by setting the FSONCS3 bit of the SPICONFIG register. This feature can be used to generate a Frame Select signal required by some DSP compatible devices without requiring the use of a separate I/O pin. Note that when both the SPILOAD and FSONCS3 are selected, the internal logic give priority to the Frame Select pulse.
do{ dacvall = dacvall + 1; if( dacvall==0xff) { dacvalh = dacvalh +1; dacvall = 0x00; } send16-bitdac( dacvalh, dacvall); }while( (dacvall != 0xff) && (dacvalh != 0xff) ); do{ dacvall = dacvall - 1; if( dacvall==0x00) { dacvalh = dacvalh - 1; dacvall = 0xff; } send16-bitdac( dacvalh, dacvall); }while( (dacvall != 0x00) && (dacvalh != 0x00) ); };
SPI Interface to 16-bit D/A Example
The following is a code example for doing 16-bit transfers over the the SPI interface.
//---------------------------------------------// // VMIX_SPI_to_dac_interface. c // //---------------------------------------------// // // This demonstration program show the how to interface a 16-bit D/A // to the VMX51C1020 SPI interface. // #pragma SMALL #include // --- function prototypes //Function Prototype: Send Data to the 16 bit D/A void send16bitdac( unsigned char valhigh, unsigned char vallow); // Bit definition sbit SPI_TX_EMPTY = USERFLAGS^0; //------------------------------------------------------------------------------// // MAIN FUNCTION // //-----------------------------------------------------------------------------// at 0x0100 main (void) { unsigned char dacvall=0; unsigned char dacvalh=0; DIGPWREN |= 0x08; //*** Initialise the SPI interface **** P2PINCFG |= 0x68;
//LSB of current DAC value //MSB of current DAC value //ENABLE SPI INTERFACE
}// End of main()... //-----------------------------------------------------------------------// // Send16-bitdac - Send data to 16 bit D/A Converter // //-----------------------------------------------------------------------// void send16-bitdac( unsigned char valhigh, unsigned char vallow){ // // USERFLAGS = 0x00; while(!SPI_TX_EMPTY){USERFLAGS = SPIIRQSTAT;} SPIRX2TX1 = vallow; SPIRX3TX0 = valhigh; //Put LSB of value in SPI transmit buffer //-> trigger transmission //Put MSB of value in SPI transmit buffer //-> trigger transmission
do{
//Wait SPI TX empty flag to be activated USERFLAGS = P2; USERFLAGS &= 0x08; }while( USERFLAGS == 0);
}//end of send16-bitdac
// config I/O port to allow the SPI //interface to access the pins // In this application we only need to configure the 5 upper bit of P2PINCFG // P2PINCFG bit 7 - SDIEN = 0 -> INPUT (NOT USED) // P2PINCFG bit 6 - SDOEN = 1 -> OUTPUT TO DAC SDI PIN // P2PINCFG bit 5 - SCKEN = 1 -> OUTPUT TO DAC SCK PIN // P2PINCFG bit 4 - SSEN = 0 -> INPUT (NOT USED) // P2PINCFG bit 3 - CS0EN = 1 -> OUTPUT TO DAC CS PIN // P2PINCFG bit 2 - CS1EN = 0 -> INPUT (NOT USED) // P2PINCFG bit 1 - CS2EN = 0 -> INPUT (NOT USED) // P2PINCFG bit 0 - CS3EN = 0 -> INPUT (NOT USED)
SPICTRL = 0x25;
// SPI ctrl: OSC/16, CS0, phase=0, pol=0, master // SPICK BIT 7:5 = 001 -> SPI CLK SPEED = OSC/2 // SPICS BIT 4:3 = 00 -> CS0 LINE IS ACTIVE // SPICKPH BIT 2 = 1 SPI CLK PHASE // SPICKPOL BIT 1 = 0 SPI CLOCK POLARITY // SPIMA_SL BIT 0 = 1 -> SET SPI IN MASTER MODE
SPICONFIG = 0x00;
// SPI CONFIG: auto CSLO, no FS, NO Load, clear IRQ flags // SPICSLO BIT 7 = 0 AUTOMATIC CHIP SELECT CONTROL // UNSUSED BIT 6 = 0 // FSONCS3 BIT 5 = 0 Do not send FrameSelect Signal on CS3 // SPILOAD BIT 4 = 0 do not Sen the Low pulse on CS3 // UNUSED BIT 3 = 0 // SPIRXOVIE BIT 2 = 0 Dont enable SPI RX Overrun IRQ // SPIRXAVIE BIT 1 = 0 Dont enable SPI RX AVAILLABLE IRQ // SPITXEMPIE BIT 0 = 0 Dont Enable SPI TX EMPTY IRQ
SPISIZE = 0x0F;
// SPI SIZE: 16-bits
// GENERATE A TRIANGLE WAVE ON THE DAC OUTPUT
while(1){
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VMX51C1020
SPI Interrupt Example
The following provides an example of basic SPI configuration and Interrupt handling.
//-------------------------------------------------------------------------------// // Sample C code for SPI RX & TX interrupt set-up //-------------------------------------------------------------------------------// // #pragma SMALL #include at 0x0100 main (void) {
The SPI also includes double buffering for data reception. Once a data reception is completed, the RX interrupt is activated and the data is transferred into the SPI RX buffer. At this point, the SPI interface can receive more data. However, the processor must have retrieved the first data stream before the second data stream reception is complete, otherwise a data overrun will occur and the SPI RX overrun interrupt will be activated, if enabled.
DIGPWREN = 0x08; P2PINCFG = 0x4F; SPICONFIG = 0x03; SPISIZE = 0x07;
// Enable SPI // Set pads direction // Enable Rx_avail + TX_empty
// SPI SIZE: 8 bits
IEN0 |= 0x80; IEN1 |= 0x06; SPIRX3TX0 = valhigh;
// Enable all interrupts // Enable SPI Txempty + RXavail interrupt //Put MSB of value in SPI transmit buffer //-> trigger transmission
Do{ }while(1) }//end of main()
//---------------------------------------------------------------------------// // SPI TX Empty Interrupt function //---------------------------------------------------------------------------// void int_2_spi_tx (void) interrupt 9 { IEN0 &= 0x7F; /*-------------------------*/ /* Interrupt code here*/ /*-------------------------*/ IRCON &= 0xFD; IEN0 |= 0x80; } // Clear flag SPITXIF // Enable all interrupts
// Disable all interrupts
//---------------------------------------------------------------------------// // SPI RX availlable function //---------------------------------------------------------------------------// void int_2_spi_rx (void) interrupt 10 { IEN0 &= 0x7F; /*-------------------------*/ /* Interrupt code here*/ /*-------------------------*/ IRCON &= 0xFB; IEN0 |= 0x80; } // Clear flag SPIRXIF // Enable all interrupts
// Disable all interrupts
//---------------------------------------------------------------------------//
Due to the double buffering of the SPI interface, an SPI TX empty interrupt will be activated as soon as the data to be transmitted is written into the SPI interface transmit buffer. If data is subsequently written into the SPI transmit buffer before the original data has been transmitted, the TX empty interrupt will only be activated when the original data has been fully transmitted.
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VMX51C1020
I²C Interface
The VMX51C1020 includes an I²C compatible communication interface that can be configured in Master mode or in Slave mode.
The I2CIRQSTAT register provides the status of the I2C interface operation and monitors the I2C bus status.
TABLE 88: (I2CIRQSTAT) I2C INTERRUPT STATUS - SFR DDH
7 I2CGOTSTOP
6 I2CNOACK 2 I2CRXOV
5 I2CSDA 1 I2CRXAV
4 I2CDATACK 0 I2CTXEMP
I2C Control Registers
The I2CRXTX SFR register is used to retrieve and transmit data on the I2C interface.
T ABLE86: (I2CRXTX) I2C DATA BUFFER - SFR DEH
3 I2CIDLE
Bit 7 6 5 4 3 I2CRXTX [7:0] 2 1 0
Mnemonic
7
I2CSGOTSTOP
Bit 7:0
Mnemonic I2CRXTX[7:0]
Function I2C Data Receiver / Transmitter buffer
6 5 4 3 2 1 0
I2CNOACK I2CSDA I2CDATACK I2CIDLE I2CRXOV I2CRXAV I2CTXEMP
The I2CCONFIG register serves to configure the operation of the VMX51C1020 I2C interface. The following table describes the I2CCONFIG register bits.
TABLE 87: (I2CCONFIG) I2C CONFIGURATION - SFR DA H
Function This means that the slave has received a stop (this bit is read only). Reset only when the master begins a new transmission. Flag that indicates that no acknowledge has been received. Is reset at the start of the next transaction Value of SDA line. Data acknowledge phase. Indicates that I2C is idle I2C Receiver overrun I2C Receiver available I2C Transmitter empty
7 I2CMASKID 3 I2CMANACK
6 I2CRXOVIE 2 I2CACKMODE
5 I2CRXDAVIE 1 I2CMSTOP
4 I2CTXEMPIE 0 I2CMASTER
Bit 7
Mnemonic
Function This is used to mask the chip ID when you have only two devices. Therefore in a transaction, rather that receiving the chip ID first, you will receive the first packet of data. I2C Receiver overrun interrupt enable I2C Receiver available interrupt enable I2C Transmitter empty interrupt enable 1= Manual acknowledge line goes to 0 0= Manual acknowledge line goes to 1 Used only with Master Rx, Master Tx, and Slave Rx. 1= Manual Acknowledge on 0= Manual Acknowledge off I2C Master receiver stops at next acknowledge phase. (read during data phase) I2C Master mode enable 1= I2C interface is Master 0= I2C interface is Slave
The I2CCHIPID register holds the VMX51C1020 I2C interface ID as well as the status bit that indicates if the last byte monitored on the I2C interface was destined for the VMX51C1020 or not.
I2CMASKID
6 5 4 3
I2CRXOVIE I2CRXDAVIE I2CTXEMPIE I2CMANACK
2
I2CACKMODE
1
I2CMSTOP
0
I2CMASTER
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VMX51C1020
The reset value of this register is 0x42, corresponding to an I2C Chip ID of 0x21. The chip ID value of the VMX51C1020 can be dynamically changed by writing the desired ID into the I2CCHIPID register (see following table).
TABLE 89: (I2CCHIPID) I2C C HIP ID - SFR DCH
formula is used to calculate the I2C clock frequency in Master mode.
I2C Clk =
________fosc__________ [8 x (I2CCLKCTRL)]
7
6
5
4 3 I2CID [6:0]
2
1
0 I2CWID
Bit 7:1
Mnemonic I2CID[6:0]
0
I2WID
Function The value of this chip’s ID Read Only and is used only in slave mode. 0:The .ID received corresponds to the I2CID 1: The ID received do not correspond to the I2CID
The following table provides examples of I2C clock (on SCL pin) speeds for various setting of the I2CCLKCTRL register when using a 14.75MHz oscillator to drive the VMX51C1020.
I2CCLKCTRL Value 01h 03h 07h 13h 27h C7h I2C Clock (SCL Value) 920kHz 461KHz 230KHz 92KHz 46KHz 9.2KHz
The I2WID bit is “read only” and used only in Slave mode and is an indicator of whether the transaction is targeted to the VMX1020 device. If the device ID sent by the Master device corresponds to the I2CID value stored in the I2CCHIPID, the I2WID bit will be cleared to 0 by the I2C module. If the transaction was destined for another I2C slave device, the I2WID bit will be set to 1. The I2WID value is valid at the moment the device ID transmission from the master device on the I2C bus has completee. In the case where the I2C RX available interrupt is activated, once the device ID is received, an I2C RX available interrupt will be triggered. The interrupt service routine should then monitor the I2WID bit in order to establish if the transaction is destined for this VMX1020 device. If the I2WID bit is set to 1, the I2C interrupt service routine can be terminated and there won’t be another I2C Rx available interrupt until 2 the next I C transaction. If the I2WID bit is cleared, the RX Available interrupt, if enabled, will be triggered for each data byte received.
When the I2C interface is configured for slave modethe I2CCLKCTRL is not used
TABLE 90: (I2CCLKCTRL) I2C CLOCK CONTROL - SFR DBH
7
6
5
4 3 2 I2CCLKCTRL [7:0]
1
0
Bit 7:0
Mnemonic I2CCLKCTRL
Function I2C Clock speed control
I2C Clock Speed
The VMX51C1020’s I C communication speed is fully configurable. Control of the I2C communication speed enabled via the I2CCLKCTRL register. The following
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2
VMX51C1020
I2C Interface Interrupts
The I C interface has a dedicated interrupt vector located at address 0x5B. Three flags (see below) share the I2C interrupt vector and can be used to monitor the I2C interface status making it possible to activate the I2C interrupt. I2CTXEMP: I2CRXAV: I2CRXOV:
Is set to 1 when the transmit buffer is empty Is set to 1 when data byte reception completes . Is set to 1 if a new byte reception completes before the previous data in the reception buffer is read, resulting in a data collision.
2
Reading the value of the I2CRXTX register resets the I2CRXAV bit. Once started, the I2C byte read process will continue until the Master generates a STOP condition. When the I2C interface is configured as a Master, setting the I2CMSTOP bit of the I2CCONFIG register to a 1 will result in the I2C interface generating a STOP condition after the reception of the next byte. In Master Mode, it’s possible to manually control the operation of the acknowledged timing when receiving data. To do this, you must first set the I2CMANACK bit of the I2CCONFIG register to 1. Then, once you have received a byte, you can manually control the acknowledge level by clearing or setting the I2CMANACK bit. Note: The VMX51C1020 I2C Interface is not compatible with the I2C multi-master mode.
These flags can all trigger the I2C interrupt if their corresponding bit in the I2CCONFIG register is set to one. In the case where more than one of these flags can activate an I2C interrupt, the interrupt service routine is left to figure out which condition generated the interrupt. Note that the I2CRXAV, I2CTXEMP and I2CRXOV flags can still be polled if their corresponding interrupt enable flag is cleared. Therefore they can still be used to monitor status.
Slave I2C Operation
The VMX51C1020 I2C interface can be configured as a Slave by clearing the I2CMASTER bit of the I2CCONFIG register. In Slave mode, the VMX51C1020 has no control over the rate or timing of the data exchange that occurs on the I2C bus. Therefore, in Slave mode, it is preferable to manage the transactions using the I2C interrupts. The I2CMASKID bit, when set, will configure the Slave device to mask the received ID byte and receive the data directly. This is useful when 2 only two devices are present on the I C bus. Note: When the VMX51C1020 starts transmitting data in Slave mode, it will continually transmit the value present in the I2C transmit register as long as the Master provides the clock signal or until the Master device generates a STOP condition
Master I C Operation
In Master mode, the VMX51C1020 I2C interface controls the I2C bus transfers. In order to configure the I2C interface as a Master, the I2CMASTER bit of the I2CCONFIG register must be set to one. Once the I2C interface is configured, sending data to a Slave device connected to the bus is done by writing the data into the I2CRXTX register. Before sending data to a Slave device, a byte containing the target device’s chip ID and Read/Write bit must be sent to it. A master mode data read is triggered by reading the I2CRXAV (bit 1) of the I2CIRQSTAT register. The data is present on the I2CRXTX register when the I2CRXAV bit is set.
2
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VMX51C1020
Errata: The VMX1020 I C Interface has a critical timing issue when the device is configured as a Slave and transmits multiple data bytes. Single byte transmission in slave mode is not effected. The condition arises if the Master device releases the SDA line at the same time it brings the SCL line low for the Acknowledge phase. In order for the VMX1020 I2C Slave transmission to work properly for multiple bytes, the Master device MUST release the SDA line AFTER the SCL negative edge. For this reason it is not possible to have a VMX1020 device configured as an I2C Master and VMX1020 devices configured as I2C Slaves on the same I2C bus. Unless data transmitted from VMX1020 I2C Slaves to the I2C Master is done one byte at a time.
2
I2C EEPROM Interface Example Program
The following provides an example program using the VMX51C1020 I2C interface for performing read and write operations to an externally connected EEPROM device.
#pragma SMALL #include // --- Function prototypes unsigned char eeread(idata unsigned char, idata unsigned char); void eewrite(idata unsigned char, idata unsigned char, unsigned char); // - Global variables idata unsigned char sbit sbit sbit sbit
irqcptr=0x00;
I2C_TX_EMPTY = USERFLAGS^0; I2C_RX_AVAIL = USERFLAGS^1; I2C_IS_IDLE = USERFLAGS^3; I2C_NO_ACK = USERFLAGS^6;
//-------------------------------------------------------------------------------// // MAIN FUNCTION // //------------------------------------------------------------------------------// void main (void){ unsigned char x=0; DIGPWREN = 0x13; //Enable the I2C peripheral
//*** configure I2C Speed. I2CCLKCTRL = 0x013; //…To about 100KHZ... //*** Configure the interrupts IEN0 |= 0x81; //Enable Ext INT0 interrupt + main //*** infinite loop waiting for ext IRQ while(1){ }; }// End of main()... //-------------------------------------------------------------------------------// // EXT INT0 interrupt // // When the External interrupt 0 is triggered read and write // operations are performed on the EEPROM //-------------------------------------------------------------------------------// void int_ext_0 (void) interrupt 0 { // Local variables declaration idata unsigned char eedata; idata unsigned char adrsh =0; idata unsigned char adrsl =0; idata int adrs =0; // IEN0 &= 0x7F; //disable ext0 interrupt //(Masked for debugger compatibility)
//Write irqcptr into the EEPROM at adrs 0x0100 eewrite( 0x01,0x00,irqcptr); irqcptr = irqcptr + 1; //Increment the Interrupt counter
//Perform an EEPROM read at address 0x100 eedata = eeread(0x01, 0x00); delay1ms(100); IEN0 = 0x81; //Debo delay for the switch on INT0 // enable all interrupts + int_0 (Removed //for debugger compatibility)
//
}// end of EXT INT 0 //---------------------------------------------------------------------------------// // INDIVIDUALS FUNCTIONS // //--------------------------------------------------------------------------------// //-----------------------------------------------------------------// // EEREAD - EEPROM Random Read // //----------------------------------------------------------------// unsigned char eeread(idata unsigned char adrsh, idata unsigned char adrsl) { idata unsigned char x=0; idata unsigned char readvalue=0;
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VMX51C1020
I2CCONFIG = 0x03; //I2C MASTER MODE NO INTERRUPT I2CRXTX = 0xA8; //SEND 24LC64 ADRS + write COMMAND USERFLAGS = 0x00; while(!I2C_TX_EMPTY){USERFLAGS = I2CIRQSTAT;} I2CRXTX = adrsh; //SEND 24LC64 ADRSH USERFLAGS = 0x00; while(!I2C_TX_EMPTY){USERFLAGS = I2CIRQSTAT;} I2CRXTX = adrsl; //SEND 24LC64 ADRSL USERFLAGS = 0x00; while(!I2C_TX_EMPTY){USERFLAGS = I2CIRQSTAT;} USERFLAGS = 0x00; //wait for I2C interface to be idle while(!I2C_IS_IDLE){USERFLAGS = I2CIRQSTAT;} I2CCONFIG &= 0xFD; I2CCONFIG |= 0x02; I2CRXTX = 0xA9; // Chip ID read
//set Master Rx Stop, only 1 byte to receive
USERFLAGS = 0x00; while(!I2C_RX_AVAIL){USERFLAGS = I2CIRQSTAT;} readvalue = I2CRXTX; USERFLAGS = 0x00; while(!I2C_IS_IDLE){USERFLAGS = I2CIRQSTAT;} //Wait for I2C IDLE return readvalue; }//End of EEREAD //----------------------------------------------------------------// // EEWRITE - EEPROM Random WRITE // //----------------------------------------------------------------// void eewrite(idata unsigned char adrsh, idata unsigned char adrsl, unsigned char eedata) { idata unsigned char x; I2CCONFIG = 0x01; //I2C MASTER MODE NO INTERRUPT I2CRXTX = 0xA8; //SEND EEPROM ADRS + READ //COMMAND USERFLAGS = 0x00; while(!I2C_TX_EMPTY){USERFLAGS = I2CIRQSTAT;} I2CRXTX = adrsh; //SEND ADRSH USERFLAGS = 0x00; while(!I2C_TX_EMPTY){USERFLAGS = I2CIRQSTAT;} I2CRXTX = adrsl; //SEND ADRSL USERFLAGS = 0x00; while(!I2C_TX_EMPTY){USERFLAGS = I2CIRQSTAT;} I2CRXTX = eedata; //SEND 24LC64 DATA and wait //for I2C bus IDLE USERFLAGS = 0x00; while(!I2C_IS_IDLE){USERFLAGS = I2CIRQSTAT;} ///--Wait Write operation to end I2CCONFIG = 0x01; //I2C Master Mode no Interrupt
do{ I2CRXTX = 0xA8; //Send 24LC64 Adrs +read Command USERFLAGS = 0x00; while(!I2C_TX_EMPTY){USERFLAGS = I2CIRQSTAT;} USERFLAGS = I2CIRQSTAT; }while(I2C_NO_ACK); delay1ms(5); //5ms delay for EEPROM write }// End of EEPROM Write
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VMX51C1020
Analog Signal Path
The VMX51C1020 implements a complete single chip acquisition system by integrating the following analog peripherals: o 12-bit A/D converter having 4 external inputs as well as 3 internal connections to the Operational amplifier and Current source input and output for a total of 7 inputs. The ADC conversion rate is programmable up to 10KHz Internal Bandgap reference and PGA 1 Programmable current source 2 Digital potentiometers 1 Digital switch
Internal Reference and PGA
The VMX51C1020 provides a temperature calibrated internal bandgap reference coupled with a programmable gain amplifier. The programmable gain amplifier’s role is to amplify the bandgap output to 2.7 volts and provide the drive required for the ADC reference input and current source. Both the bandgap and the PGA are calibrated during production and their associated calibration registers are automatically loaded with the appropriate calibration vectors when the device is reset. The bandgap and PGA calibration vectors are stored into the BGAPCAL and PGACAL SFR registers when a reset occurs. It is possible for the user program to overwrite the contents of those registers.
TABLE 91: (BGAPCAL) BAND-GAP C ALIBRATION VECTOR REGISTER - SFR B3H
ISRCOUT/TA
o o o o
The following figure provides a block diagram of the VMX51C1020’s analog peripherals and their connection.
FIGURE 35: ANALOG S IGNAL PATH OF THE VMX51C1020
BANDGAP
PGA
AIN0 AIN1 AIN2 AIN3 VBGAP Reserved unused unused
7
6
5
4 3 BGAPCAL [7:0]
2
1
0
200mV XTVREF 800mV AIN0 AIN1 AIN2 AIN3 OPOUT RESERVED ISRCIN ISRCOUT
Bit 7:0 7 Bit 7:0
Mnemonic BGAPCAL 6 5
Function Band-gap data calibration 4 3 PGACAL [7:0] 2 1 0
TABLE 92: (PGACAL) PGA CALIBRATION VECTOR REGISTER - SFR B4H
ISRCIN
Total of 7 A/D inputs
OPOUT A/D
Mnemonic PGACAL
Function 8 MSBs of PGA Calibration Vector (LSBit is on ISRCCAL1)
SW1
POT1
POT2
Using the VMX51C1020 Internal Reference
The configuration and setup up of the VMX51C1020’s internal reference is done by setting bits 0 and 1 of the ANALOGPWREN register to 1. This powers on the bandgap and the PGA, respectively.
The on-chip calibrated bandgap or the external reference provides the basis for all derived onchip voltages. These signals serve as reference for the ADC and the current source.
Analog Peripheral Power Control
Selection of the internal/ external reference, the multiplexer’s current source drive, ADC control, and the respective power downs for these peripherals are controlled via the ANALOGPWREN SFR registers.
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VMX51C1020
Use of the internal reference requires the addition of two external tank capacitors on the XTVREF pin. These capacitors consist of one 4.7uF to 10uF Tantalum capacitor in parallel with one 0.1uF Ceramic capacitor. The following shows the connection of the tank capacitors to the XTVREF pin
FIGURE 36: T ANK CAPACITORS CONNECTION TO THE XTVREF PIN
The external reference voltage source can be set from 0.5 to 3.5 volts and must provide sufficient drive to operate the ADC load.
FIGURE 38: EXTERNAL REFERENCE CONNECTION TO THE XTVREF PIN
XTVREF 4.7uF to 10uF
0.1uF
V
2.7V
XTVREF 4.7uF to 10uF
0.1uF
Warning: When an external reference source is applied to the XTVREF pin, it is mandatory not to power-on the PGA. The internal bandgap reference should also be kept de-activated.
The VMX51C1020 internal reference can also be used as an external reference provided that the load on the XTVREF pin is kept to a minimum. The following table shows the typical effect of loading on the XTVREF voltage.
FIGURE 37: T ANK CAPACITORS CONNECTION TO THE XTVREF PIN
2.75
Reference Impact on the Programmable Current Source
The Programmable Current Source uses the same reference as the ADC for its operation, therefore, using an external reference will have a direct impact on the current source output. The 200/800mV current source reference voltage, calibrated at 2.7V will change in a linear fashion according to the voltage present on the XTVREF pin. For example, in the case where the reference voltage applied to the XTVREF pin is 3V, the current source reference voltage will be scaled up by a factor of [VXTVREF/2.7V] to 222mV and 889mV respectively.
XTVREF reference voltage (Volts)
2.70
2.65 0.0 1.0 2.0 3.0 4.0 5.0
Load current on XTVREF (mA)
It is recommended that the external load on the XTVREF pin be less than 1mA. Note: A stabilization delay of more than 1ms should be provided between the activation of the bandgap, the PGA and the first A/D conversion or measurement made on the programmable current source.
A/D Converter
The VMX51C1020 includes a feature rich, highly configurable on-chip 12-bit A/D converter. The A/D conversion data is output as unsigned 12-bit binary, with 1 LSB = Full Scale/4096. The following figure describes the ideal transfer function for the ADC.
Using an External Reference
An external reference can be used to drive the VMX51C1020 ADC and the programmable current source instead of the internal reference.
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VMX51C1020
FIGURE 39: IDEAL A/D CONVERTER T RANSFER FUNCTION
OUTPUT CODE 1111_1111_1111 1111_1111_1110 1111_1111_1101 1111_1111_1100 1 LSB = XTVREF / 4096
TABLE 93: (ADCD0LO) ADC CHANNEL 0 DATA REGISTER, LOW BYTE - SFR A6H
Bit 7:0 Bit 3:0
Mnemonic ADCD0LO Mnemonic ADCD0HI 6 5
Function ADC channel 0 low Function ADC channel 0 high 4 3 2 ADCD1LO [7:0] 1 0
TABLE 94: (ADCD0HI) ADC C HANNEL 0 DATA REGISTER, HIGH BYTE - SFR A7H
0000_0000_0011 0000_0000_0010 0000_0000_0001 0000_0000_0000 0V XTVREF
TABLE 95: (ADCD1LO) ADC CHANNEL 1 DATA REGISTER, LOW BYTE - SFR A9H
7
The A/D converter includes a system that provides the ability to trigger automatic periodic conversions of up to 10kHz without processor intervention. Once the conversion is complete, the A/D system can activate an interrupt that can wakeup the processor (assuming it has been put into idle mode) or automatically throttle the processor clock to full speed. The VMX51C1020 A/D converter can also be configured to perform the conversion on one specific channel or on four consecutive channels (in round-robin fashion). These features make the A/D adaptable for many applications. The following paragraphs describe the VMX51C1020’s A/D converter register features.
Bit 7:0 7 Bit 3:0 7
Mnemonic ADCD1LO 6 5 -
Function ADC channel 1 low 4 3 2 1 ADCD1HI [3:0] 0
TABLE 96: (ADCD1HI) ADC C HANNEL 1 DATA REGISTER, HIGH BYTE - SFR AAH
Mnemonic ADCD1HI 6 5
Function ADC channel 1 high 4 3 ADCD2LO [7:0] 2 1 0
TABLE 97: (ADCD2LO) ADC CHANNEL 2 DATA REGISTER, LOW BYTE - SFR ABH
Bit 7:0 7 Bit 7:4 3:0 6 -
Mnemonic ADCD2LO 5 Mnemonic ADCD2HI 4 -
Function ADC channel 2 low 3 2 1 ADCD2HI [3:0] 0
TABLE 98: (ADCD2HI) ADC C HANNEL 2 DATA REGISTER, HIGH BYTE - SFR ACH
Function ADC channel 2 high
TABLE 99: (ADCD3LO) ADC CHANNEL 3 DATA REGISTER, LOW BYTE - SFR ADH
7
6
5
ADC Data Registers
The ADC data registers hold the ADC conversion results. The ADCDxLO register(s) hold the 8 Least Significant Bits (LSBs) of the conversion results while the ADCDxHI register(s) hold the 4 Most Significant Bits (MSB) of the conversion results.
Bit 7:0 7 Bit 7:4 3:0 6 Mnemonic ADCD3LO 5 Mnemonic ADCD3HI
4 3 ADCD3LO [7:0]
2
1
0
Function ADC channel 3 low 4 3 2 1 ADCD3HI [3:0] 0
TABLE 100: (ADCD3HI) ADC C HANNEL 3 DATA REGISTER, HIGH BYTE - SFR AEH
Function ADC channel 3 high
ADC Input Selection
A/D conversions can be performed on a single channel, sequentially on the four lower channels, or sequentially on the four upper channels of the ADC input multiplexer. An input buffer is present on each of the four external ADC inputs (ADIN0 to AIN3) These buffers must be enabled before a conversion can take place on the ADC AIN0_________________________________________________________________________________________________ page 59 of 80 www.ramtron.com
VMX51C1020
AIN3 inputs. These buffers are enabling by setting the corresponding bits of the lower nibble (AIEN [3:0]) of the INMUXCTRL register to 1.
TABLE 101: (INMUXCTRL) ANALOG INPUT M ULTIPLEXER CONTROL REGISTER SFR B5H
implement continuous conversions at a rate defined by the Conversion Rate register. When the CONT bit is set to 0, the A/D operates in “One Shot” mode, initiating a conversion when the ONESHOT bit of the ADCCONTRL register is set. ADC One Channel/ Four Channel Conversion The VMX51C1020’s ADC includes a feature that renders it possible to perform a conversion on one specific channel or on four consecutive channels. This feature minimizes the load on the processor when reading more than one ADC input is required. The ONECHAN bit of the ADCCTRL register controls this feature. When the ONECHAN is set to 1, the conversion will take place on the channel selected by the INMUXCTRL register. Once the conversion is completed, the result will be put into the ADCD0LO and ADCD0HI registers When the ONECHAN bit is set to 0, the conversion, once triggered, will be done sequentially on four channels and the conversion results will be placed into the ADCDxLO and ADCDxHI registers. Bit 6 of the INMUXCTRL register controls whether the conversion will take place on the four upper channels of the input multiplexer or the 4 lower channels.
7 Bit 7 6:4
6 5 4 ADCINSEL [2:0] Mnemonic ADCINSEL[2:0]
3
2 1 AINEN [3:0]
0
Function ADC Input Select 000 - AIN0 001 - AIN1 010 - AIN2 011 - AIN3 100 - OPOUT 101 - VSR 110 - ISRCIN 111 - ISRCOUT Analog Input Enable
3:0
AINEN[3:0]
The upper four bits of the INMUXCTRL register are used to define the channel on which the conversion will take place when the ADC is set to perform the conversion on one specific channel.
ADC Control Register
The ADCCTRL register is the main register used for control and operation of the ADC.
TABLE 102: (ADCCTRL) ADC CONTROL REGISTER - SFR A2 H
7 ADCIRQCLR 3 ADCIE Bit 7 6 5 4 3 2
6 XVREFCAP 2 ONECHAN
5 1 1 CONT
4 ADCIRQ 0 ONESHOT
Mnemonic ADCIRQCLR XVREFCAP Reserved = 1 ADCIRQ ADCIE ONECHAN
1 0
CONT ONESHOT
Function ADC interrupt clear Writing 1 Clears interrupt Always keep this bit at 1 Keep this bit = 1 Read ADC Interrupt Flag Write 1 generate ADC IRQ ADC interrupt enable 1 = Conversion is performed on one channel Specified ADCINSEL 0 = Conversion is performed on 4 ADC channels 1 = Enable ADC continuous conversion 1 = Force a single conversion on 1 or 4 channels
ADC Continuous/One Shot Conversion The CONT bit sets the ADC conversion mode. When the CONT bit is set to 1, the ADC will
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VMX51C1020
ADC Clock Source Configuration
A/D converter derives its clock source from the main VMX51C1020 clock. The frequency of the ADC clock should be set between 250kHz to 1.25MHz Configuration of the ADC clock source frequency is done by adjusting the value of the ADCCLKDIV register. The following equation is used to calculate the ADC reference clock value. ADC Clock Reference Equation:
ADC Clk ref = f OSC 4x (ADCCDIV +1)
ADC Conversion Rate Configuration
The VMX51C1020’s ADC conversion rate, when configured in continuous mode is defined by the 24-bit A/D Conversion Rate register that serves as the time base for triggering the ADC conversion process. The following equation is used to calculate the value of the conversion rate.
Conversion Rate Equation: Conversion rate registers value (24-bit) = fOSC Conv_Rate
The ADC conversion requires 111 ADC clock cycles to perform the conversion on one channel. The following table provides recommended ADCCLKDIV register values versus conversion rate. The numbers given are conservative figures and derived from a 14.74MHz clock
ADCCLKDIV 0x02 0x03 0x05 0x07 0x08 0x09 0x0B 0x0D, 0x0E, 0x0F Maximum Conv. Rate* 10500 Hz 8000 Hz 5000 Hz 4000 Hz 3500 Hz 3200 Hz 2500 Hz 2200 Hz
The conversion rate register is accessible using three SFR registers as follows:
TABLE 104: (ADCCONVRLOW) ADC CONVERSION R ATE REGISTER LOW BYTE SFR A3H
Bit 7:0
Mnemonic ADCCONVRLOW
Function Conversion rate low byte
TABLE 105: (ADCCONVRMED) ADC CONVERSION RATE REGISTER MED BYTE SFR A4H
Bit 7:0
Mnemonic ADCCONVRMED
Function Conversion rate medium byte
TABLE 106: (ADCCONVRHIGH) ADC CONVERSION RATE REGISTER HIGH BYTE SFR A5H
Bit 7:0
Mnemonic ADCCONVRHIGH
Function Conversion rate high byte
The following table provides examples of typical values versus conversion rate.
Conversion Rate 1Hz 10Hz 100Hz 1kHz 2.5kHz 5kHz 8kHz 10kHz ADC conv. rate register value. Fosc= 14.74MHz E10000h 168000h 024000h 003999h 00170Ah 000B85h 000733h 0005C2h
* The maximum conversion rate is for the single channel condition. If the conversion is performed on 4 channels, divide the maximum conversion rate by 4. For example to perform the conversion at 2.5KHz on four channels, the ADCCLKDIV register should be set to 0x02 (4x 2500Hz =10KHz)
TABLE 103: (ADCCLKDIV) ADC CLOCK DIVISION CONTROL REGISTER - SFR 95 H
7
6
5
4 3 2 ADCCLKDIV [7:0]
1
0
Bit 7:0
Mnemonic ADCCLKDIV[7:0]
Function ADC clock divider
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VMX51C1020
ADC Status Register
The ADC shares interrupt vector 0x6B with the Interrupt on Port 1 Change and the Compare and Capture Unit 3. To enable the ADC interrupt, the ADCIE bit of the ADCCTRL register must be set. Before or at the same time this bit is set, the ADCIRQCLR and the ADCIRQ bits must be cleared. The ADCPCIE bit of the IEN1 register must also be set, as well as the EA bit of the IEN0 register. Once the ADC interrupt occurs, ADC Interrupt must be cleared by writing a ‘1’ into the ADCINTCLR bit of the ADCCTRL register. The ADCIF flag in the IRCON register must also be cleared.
//*** Configure the interrupts IEN0 |= 0x80; //enable main interrupt IEN1 |= 0x020; //Enable ADC Interrupt while(1); //Infinite loop waiting ADC interrupts }// End of main()... //-----------------------------------------------------------------------// // ADC INTERRUPT ROUTINE //-----------------------------------------------------------------------// void int_adc (void) interrupt 13 { idata int value = 0; IEN0 &= 0x7F; ADCCTRL |=0x80; // Read ADC channel 0 value = ADCD0HI; value = valeur*256; value = valeur + ADCD0LO; (…) // Read ADC channel 3 value = ADCD3HI; value = valeur*256; value = valeur + ADCD3LO; (…) IRCON &= 0xDF; ADCCTRL |=0xFA; IEN0 |= 0x80; }// End of ADC IRQ (…) //disable ext0 interrupts //Clear ADC interrupt
//Clear adc irq flag //prepare adc for next acquisition // enable all interrupts
A/D Converter Example
The following provides example code for the A/D converter. The first section of the code covers interrupt setup/module configuration whereas the second section is the interrupt function itself. Sample C code to setup the A/D converter:
//-----------------------------------------------------------------------// // MAIN FUNCTION //-----------------------------------------------------------------------// (…) at 0x0100 void main (void) { //*** Initialize the Analog Peripherals *** ANALOGPWREN = 0x07; //Enable the following analog //peripherals: ISRC, ADC, PGA, // BGAP. TA = OFF (mandatory)
Warning: When using the ADC, make sure the output multiplexer controlled by the TAEN bit of the ANALOGPWREN register (92h) is powered down at all times, otherwise, the signal present on the ISRCOUT can be routed back to the selected ADC input, causing conversion errors.
//Configure the ADC and Start it ADCCLKDIV=0x0F; ADCCONVRLOW =0x00; ADCCONVRMED=0x40; ADCCONVRHIGH =0x02; INMUXCTRL=0x0F; ADCCTRL=0xEA;
//SET ADC CLOCK SOURCE //CONFIGURE CONVERSION RATE //= 100Hz @ 14.74 MHz
//Enable All ADC External inputs //buffers and select ADCI0 //Configure the ADC as follow: //bit 7: =1 ADCIRQ Clear //Bit 6: =1 XVREFCAP (always) //Bit 5: =1 (always) //Bit 4: =0 = ADCIRQ (don’t care) //Bit 3: =1 = ADC IRQ enable //Bit 2: =0 conversion on 4 //channels //Bit 1: =1 Continuous conversion //Bit 0: =0 No single shot mode
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VMX51C1020
Programmable Current Source
The VMX51C1020 includes a programmable current source used to drive external devices such as resistive sensors connected between the ISRCOUT and ISRCIN pins To ensure current output stability, the current source provides a feedback input, ISRCIN. The feedback is voltage controlled and can be dynamically set to either 200mV or 800mV. Placing a resistor between the ISRC pin and the ground defines the output current of the current source. The VMX51C1020 current Source can drive currents up to 500µA when the reference is set to 800mV.
FIGURE 40: PROGRAMMABLE CURRENT SOURCE TO EXCITE SENSOR
TABLE 108: (ISRCCAL2) C URRENT SOURCE CALIBRATION VECTOR FOR 800MV FEEDBACK VALUE - SFR BD H
7 Bit 7 6:0
6
5
4 3 2 ISRCCAL2 [6:0]
1
0
Mnemonic ISRCCAL2[6:0]
Function Calibration Value for ISRC feedback of 800mV
Current Source Setup Example
The following provides setup examples for the current source. Enabling the Current Source using the 200mV reference:
MOV ANALOGPWREN,#00110011B ;Enable Analog peripherals ;Bit 7: OPAMPEN = 0 Op-Amp OFF ;Bit 6: DIGPOTEN= 0 Dig Pot OFF ;Bit 5: ISRCSEL = 1 ISRC 800mV ;Bit 4: ISRCEN = 1 ISRC ON ;Bit 3: TAEN = 0 TA output OFF ;Bit 2: ADCEN = 0 ADC OFF ;Bit 1: PGAEN = 1 PGA ON ;Bit 0: BGAPEN = 1 BandGap ON
To A/D
ISRCOUT
Sensor
ISRCIN
Enabling the Current Source using the 200mV reference:
;MOV ANALOGPWREN,#00010011B ;Enable Analog peripherals ;Bit 7: OPAMPEN = 0 Op-Amp OFF ;Bit 6: DIGPOTEN= 0 Dig Pot OFF ;Bit 5: ISRCSEL = 0 ISRC 200mV ;Bit 4: ISRCEN = 1 ISRC ON ;Bit 3: TAEN = 0 TA output OFF ;Bit 2: ADCEN = 0 ADC OFF ;Bit 1: PGAEN = 1 PGA ON ;Bit 0: BGAPEN = 1 BandGap ON
Rref
200 mV 800 mV
As shown above, a resistive device (sensor) must be connected between the ISRCOUT and the ISRCIN. In order to perform A/D conversion of the voltage present at the terminal of the current source, there is an internal link between each of the ISRCOUT and ISRCIN pins as well as the Input multiplexer of the A/D converter.
TABLE 107: (ISRCCAL1) C URRENT SOURCE CALIBRATION VECTOR FOR 200MV FEEDBACK VALUE - SFR BC H
7 PGACAL0 Bit 7 6:0
6
5
4 3 2 ISRCCAL1 [6:0]
1
0
Mnemonic PGACAL0 ISRCCAL1[6:0]
Function Bit 0 of PGACAL Calibration Value for ISRC feedback of 200mV
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VMX51C1020
Digital Potentiometers
The VMX51C1020 has two digital potentiometers that are controlled by DIGPOTx registers (DIGPOT1, DIGPOT2) that can be used in applications such as: o o o o Gain control Offset adjustment A/D input attenuation Digitally controlled filter
Rpotentiometer * = [ 256 - DIGPOTx[7:0] ] x 30k 256
*Potentiometer value
Digital Potentiometer Setup Example
Only two instructions are required to enable and configure the digital Potentiometers of the VMX51C1020:
MOV MOV MOV ANALOGPWREN,#01000000B DIGPOT1,#0C0h ;SET POT1 to 25% of Max Pot value DIGPOT2,#040h ;SET POT2 to 75% of Max Pot value
FIGURE 41: DIGITAL POTENTIOMETER FUNCTIONAL DIAGRAM
POTx A POTx B
Operational Amplifier
The VMX51C1020 is equipped with an operational amplifier. This op-amp can be used for a wide array of analog applications such as: o o o o o Gain control Offset Control Reference buffering Integrator Other standard op amp applications
DIGPOTx register
TABLE 109: (DIGPOT1) DIG. POTENTIOMETER 1 CONTROL REGISTER - SFR BAH
7
6
5
4 3 DIGPOT1 [7:0]
2
1
0
Bit 7-0 7
Mnemonic DIGPOT1 6 5
Function Potentiometer 1 Value 4 3 DIGPOT2 [7:0] 2 1 0
TABLE 110: (DIGPOT2) DIG. POTENTIOMETER 2 CONTROL REGISTER - SFR BBH
The op-amp on the VMX51C1020 has an openloop gain of 100dB; a unity gain bandwidth of 5MHz and it is able to drive a 1kO and 40pf load. The slew rate of the Op-Amp is 7V/µs and the output voltage can swing between 25mV and 4.975 Volts (10kO load). To activate the Operational Amplifier, the OPAMPEN bit (bit 7) of the ANALOGPWREN register (SFR 92h) must be set to 1. Warning:
Bit 7-0
Mnemonic DIGPOT2
Function Potentiometer 2 Value
The digital potentiometers are floating devices, meaning that there are no restrictions on the voltage present on their terminals as long as they are kept within the nominal operating range of the VMX51C1020. The current flow through the potentiometers should be limited to 5mA max. The digital potentiometer maximum nominal resistance is 30k +/- 2Kohms from device to device. On a given device the two digital potentiometer values usually match within 1%. Before using the digital potentiometers, they must first be enabled by setting bit 6 of the ANALOGPWREN register (92h) to 1. The potentiometer value is governed by the following equation.
If the VMX51C1020 Op-Amp inputs are left floating, it should be kept in power down to prevent risk of oscillation.
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VMX51C1020
Digitally Controlled Switches
The VMX51C1020 include a digital switch composed of 4 sub-switches connected in parallel. These sub-switches can be individually controlled by writing to the SFR register at B7h.
FIGURE 42: SWITCH FUNCTIONAL DIAGRAM
SW1A SW1B
Analog Output Multiplexer
The VMX51C1020’s analog output multiplexer is used for production test purposes and provides access to internal test points of the analog signal path.. It can however, be used in applications, but due to its high intrinsic impedance, care must be taken with respect to loading. The analog output multiplexer shares its output with the current source output and therefore must be disabled when the current source or the ADC is used. Inversely, when the analog output multiplexer is used, the current source must be powered down. The following table summarizes the analog output multiplexer select line settings.
TABLE 112: (OUTMUXCTRL) A NALOG OUTPUT M ULTIPLEXER CONTROL REGISTER - SFR B6H
x
xx
x
sw1d sw1c sw1b sw1a
SWITCHCTRL register
The switch “ON” resistance is between 50 and 100 Ohms depending on the number of subswitches being used. If, for example, one subswitch is closed, the switch resistance will be about 100 Ohms, and if all 4 switches are closed, the switch resistance will go down to about 50 Ohms.
TABLE 111: (SWITCHCTRL) USER SWITCHES CONTROL REGISTERS - SFR B7H
7 Bit 7:3 2:0
6 -
5 -
4 -
3 -
2 1 0 TAOUTSEL [2:0] Function Unused Signal output on TA 000 – AIN0 001 – AIN1 010 – AIN2 011 – AIN3 100 – VBGAP 101 – reserved 110 – unused 111 – unused
Mnemonic Unused TAOUTSEL[2:0]
7 6 5 4 Not Used but implemented Bit 7:4 Mnemonic User Flags
3
2 1 SWTCH1 [3:0]
0
3:0
SWITCH1[3:0]
Function Not used but implemented bits Can be used as general purpose storage Switch 1 control (composed of 4 individual switches each bit controlled)
The upper 4 bits of the SWITCHCTRL register can be used as general purpose flags.
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VMX51C1020
VMX51C1020 Interrupts
The VMX51C1020 is a highly integrated device incorporating a vast number of peripherals for which a comprehensive set of 29 interrupt sources sharing 12 interrupt vectors is available. Most of the VMX51C1020 peripherals can generate an interrupt, providing feedback to the MCU core that an event has occurred or a task has been completed. The following features are key VMX51C1020 interrupt features. o o o o Each digital peripheral on the VMX51C1020 has an interrupt channel. The SPI, UARTs and I²C all have event specific flag bits. When the processor is in IDLE mode, an interrupt may be used to wake it up. The processor can run at full speed during interrupt routines.
Interrupt Enable Registers
The following tables describe the interrupt enable registers their associated bit functions:
TABLE 114: (IEN0) INTERRUPT E NABLE REGISTER 0 - SFR A8H
7 EA 3 T1IE Bit 7 Mnemonic EA
6 WDT 2 INT1IE
5 T2IE 1 T0IE
4 S0IE 0 INT0IE
6
WDT
5
T2IE
4
S0IE
The following table summarizes the interrupt sources, natural priority and the associated interrupt vector addresses of the VMX51C1020.
TABLE 113: INTERRUPT SOURCES AND NATURAL PRIORITY
3
T1IE
2
INT1IE
Interrupt Reserved INT0 UART1 TIMER 0 SPI Tx INT1 SPI RX & SPI RX OVERRUN / COMPINT0 TIMER 1 I2C (Tx, Rx, Rx Overrun) / COMPINT1 UART0 MULT/ACCU 32bit Overflow / COMPINT2 TIMER 2: T2 Overflow, T2EX ADC and interrupt on Port 1 change (8 int.) / COMPINT3
Interrupt Vector 0E43h 0003h 0083h 000Bh 004Bh 0013h 0053h 001Bh 005Bh 0023h 0063h 002Bh 006Bh
1
T0IE
0
INT0IE
Function General Interrupt control 0 = Disable all Enabled interrupts 1 = Authorize all Enabled interrupts Watchdog timer refresh flag. This bit is used to initiate a refresh of the watchdog timer. In order to prevent an unintentional reset, the watchdog timer the user must set this bit directly before SWDT. Timer 2 Overflow / external Reload interrupt 0 = Disable 1 = Enable Uart0 interrupt. 0 = Disable 1 = Enable Timer 1 overflow interrupt 0 = Disable 1 = Enable External Interrupt 1 0 = Disable 1 = Enable Timer 0 overflow interrupt 0 = Disable 1 = Enable External Interrupt 0 0 = Disable 1 = Enable
It is also possible to program the interrupts to wake-up the processor from an IDLE condition or force its clock to throttle up to full speed when an interrupt condition occurs.
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VMX51C1020
TABLE 115: (IEN1) INTERRUPT E NABLE 1 REGISTER -SFR E8H
7 T2EXIE 3 I2CIE Bit 7
6 SWDT 2 SPIRXOVIE
5 ADCPCIE 1 SPITEIE
4 MACOVIE 0 reserved
Timer2 Compare Mode Impact on Interrupts
The SPI RX (and RXOV), I2C, MULT/ACCU and ADC Interrupts are shared with the four Timer2 Compare and Capture Unit interrupts. When the Compare and Capture Units of Timer2 are configured in Compare Mode via CCEN register, the Compare and Capture unit takes control of one interrupt vector as shown below.
FIGURE 43: COMPARE CAPTURE INTERRUPT STRUCUTRE
COMPINT0 Interrupt 1
Mnemonic T2EXIE
6
SWDT
5
ADCPCIE
4
MACOVIE
3
I2CIE
2
SPIRXOVIE
1
SPITEIE
Function T2EX interrupt Enable 0 = Disable 1 = Enable Watchdog timer start/refresh flag. Set to activate/refresh the watchdog timer. When directly set after setting WDT, a watchdog timer refresh is performed. Bit SWDT is reset. ADC and Port change interrupt 0 = Disable 1 = Enable MULT/ACCU Overflow 32 bits interrupt 0 = Disable 1 = Enable I2C Interrupt 0 = Disable 1 = Enable SPI Rx avail + Overrun 0 = Disable 1 = Enable SPI Tx Empty interrupt 0 = Disable 1 = Enable
Interrupt Vector 0053h
SPI Rx & RxOV INT
0
CCEN(1,0) = 1,0
COMPINT1 Interrupt
1
Interrupt Vector 005Bh
I2C INT
0
CCEN(3,2) = 1,0
COMPINT2 Interrupt
1
Interrupt Vector 0063h
MAC Overflow INT
0
CCEN(5,4) = 1,0
COMPINT3 Interrupt
1
0
reserved
ADC & Port Change INT 0
Interrupt Vector 006Bh
TABLE 116: (IEN2) INTERRUPT E NABLE 2 REGISTER - SFR 9AH
7 Bit 7-1 0
6 -
5 -
4 Function
3 -
2 -
1 -
0 S1IE
CCEN(7,6) = 1,0
Mnemonic S1IE
UART 1 Interrupt 0 = Disable UART 1 Interrupt 1 = Enable UART 1 Interrupt
The impact of this is that the corresponding peripheral interrupt, if enabled, will be blocked. The output signal from the comparison module will be routed to the Interrupt system and the control lines will be dedicated to the Compare and Capture unit. This interrupt control “take over” is specific to each individual Compare and Capture unit. For example if Compare and Capture Unit number 2 is configured to generate a PWM signal on P1.2, the MULT/ACCU overflow interrupt, if enabled, will be dedicated to the Compare and Capture Unit number 2 and the SPI, I2C and ADC interrupts won’t be affected.
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VMX51C1020
Interrupt Status Flags
The IRCON register is used to identify the source of an interrupt. Before exitingthe interrupt service routine, the IRCON register bit that corresponds with the serviced interrupt should be cleared.
TABLE 117: (IRCON) INTERRUPT REQUEST CONTROL REGISTER - SFR 91H
TABLE 118: (IP0) INTERRUPT PRIORITY REGISTER 0 - SFR B8H
7 UF8 Bit 7 6
6 WDTSTAT Mnemonic UF8 W DTSTAT
5
4
3
2 IP0 [5:0]
1
0
7 T2EXIF 3 I2CIF Bit 7
6 T2IF 2 SPIRXIF
5 ADCIF 1 SPITXIF
4 MACIF 0 Reserved
5 4 3 2 1 0
IP0.5 IP0.4 IP0.3 IP0.2 IP0.1 IP0.0
Mnemonic T2EXIF
6 5
T2IF ADCIF / COMPINT3 MACIF / COMPINT2 I2CIF / COMPINT1 SPIRXIF / COMPINT0 SPITXIF Reserved
4 3 2 1 0
Function Timer 2 external reload flag This bit informs the user whether an interrupt has been generated from T2EX, if the T2EXIE is enabled. Timer 2 interrupt flag A/D converter interrupt request flag/ port 0 change. / COMPINT3 MULT/ACCU unit interrupt request flag / COMPINT2 2 I C interrupt request flag / COMPINT1 RX available flag SPI + RX Overrun / / COMPINT0 TX empty flag SPI Reserved
Function User Flag bit Watchdog timer status flag. Set to 1 by hardware when the watchdog timer overflows. Must be cleared manually Port1 Timer 2 ADC Change UART0 MULT/ACCU Timer 1 I2C External SPI RX INT1 available Timer 0 SPI TX Interrupt Empty External External UART1 INT0 INT 0
Table 119: (IP1) Interrupt Priority Register 1 - SFR B9h 7 6 5 4 3 2 1 IP1 [5:0] Bit 7 6 Mnemonic Function -
0
5 4 3 2 1
IP1.5 IP1.4 IP1.3 IP1.2 IP1.1 IP1.0
Timer 2 UART0 Timer 1 External INT1 Timer 0 Interrupt External INT0
Port1 Change UART1
ADC MULT/ACCU I2C SPI RX available SPI TX Empty External INT 0
Interrupt Priority Register
All of the VMX51C1020’s interrupt sources are combined into groups with four levels of priority. These groups can be programmed individually to one of the four priority levels: from Level0 to Level3 with Level3 being the highest priority. The IP0 and IP1 registers serve to define the specific priority of each of the interrupt groups. By default, when the IP0 and IP1 registers are at reset state 00h, the natural priority order of the interrupts shown previously are in force.
0
Configuring the IP0 and IP1 registers makes it possible to change the priority order of the peripheral interrupts in order give higher priority to a given interrupt that belongs to a given group.
TABLE 120: INTERRUPT GROUPS
Bit
IP1.5, IP0.5 IP1.4, IP0.4 IP1.3, IP0.3 IP1.2, IP0.2 IP1.1, IP0.1 IP1.0, IP0.0
Interrupt Group
Timer 2 UART0 Timer 1 External INT1 Timer 0 Interrupt External INT0 Port1 Change UART1 ADC MULT/ACCU I2C SPI RX available SPI TX Empty External INT 0
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VMX51C1020
The respective values of the IP1.x and IP0.x bits define the priority level of the interrupt group vs. the other interrupt groups as follows.
TABLE 121: INTERRUPT PRIORITY LEVEL
IP1.x 0 0 1 1
IP0.x 0 1 0 1
Priority Level Level 0 (Low) Level 1 Level 2 Level 3 (High)
The WDTSTAT bit of the IP0 register is the Watchdog status flag and is set to 1 by the hardware whenever a Watchdog Timer overflow occurs. This bit must be cleared manually. Finally, bit 7 of the IP0 register can be used as a general purpose user flag.
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VMX51C1020
Setting up INT0 and INT1 Interrupts
The IT0 and IT1 bits of the TCON register define whether external interrupts 0 and 1 will be edge or level triggered. When an interrupt condition occurs on INT0 or INT1, the associated interrupt flag IE0 or IE1 will be set. The interrupt flag is automatically cleared when the interrupt is serviced.
TABLE 122: (TCON) TIMER 0, TIMER 1 TIMER/COUNTER CONTROL - SFR 88H
INT0 example The following provides example code for interrupt setup and module configuration.
//--------------------------------------------------------------------------// Sample C code to setup INT0 //--------------------------------------------------------------------------#pragma TINY #include at 0x0100 void main (void) { // INT0 Config TCON |= 0x01; //Interrupt on INT0 will be caused by a High->Low //edge on the pin // Enable INT0 interrupts IEN0 |= 0x80; // Enable all interrupts IEN0 |= 0x01; // Enable interrupt INT0 // Wait for INT0… do { }while(1); }//end of main function //--------------------------------------------------------------------------// Interrupt Function void int_ext_0 (void) interrupt 0 { IEN0 &= 0x7F; /* Put the Interrupt code here*/ IEN0 |= 0x80; // Enable all interrupts } //---------------------------------------------------------------------------
7
TF1
6
TR1
5
TF0
4
TR0
3
IE1
2
IT1
1
IE0
0
IT0
//Wait for INT0 interrupts
Bit 7
Mnemonic TF1
6 5
TR1 TF0
4 3
TR0 IE1
2
IT1
1
IE0
0
IT0
Function Timer 1 overflow flag set by hardware when Timer 1 overflows. This flag can be cleared by software and is automatically cleared when interrupt is processed. Timer 1 Run control bit. If cleared Timer 1 stops. Timer 0 overflows flag set by hardware when Timer 0 overflows. This flag can be cleared by software and is automatically cleared when interrupt is processed. Timer 0 Run control bit. If cleared timer 0 stops. Interrupt 1 edge flag. Set by hardware when falling edge on external INT1 is observed. Cleared when interrupt is processed. Interrupt 1 type control bit. Selects falling edge or low level on input pin to cause interrupt. Interrupt 0 edge flag. Set by hardware when falling edge on external pin INT0 is observed. Cleared when interrupt is processed. Interrupt 0 type control bit. Selects falling edge or low level on input pin to cause interrupt.
// Disable all interrupts
INT1 example The following code example shows the INT1 interrupt setup and module configuration:
//------------------------------------------------------------------------// Sample C code to setup INT1 //------------------------------------------------------------------------#pragma TINY #include at 0x0100 void main (void) { // INT1 Config TCON |= 0x04; //Interrupt on INT1 will be caused by a High->Low //edge on the pin // Enable INT1 interrupts IEN0 |= 0x80; IEN0 |= 0x04; // Wait for INT1… do { }while(1); // Enable all interrupts // Enable interrupt INT1
//Wait for INT1 interrupts
// Interrupt function void int_ext_1 (void) interrupt 2 { IEN0 &= 0x7F; /* Put the Interrupt code here*/ IEN0 |= 0x80; } // Enable all interrupts
// Disable all interrupts
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VMX51C1020
UART0 and UART1 Interrupt Example
The following program examples demonstrate how to initialization the UART0 and UART1 interrupts.
//------------------------------------------------------------------------------// Sample C code for UART0 and UART1 interrupt example //------------------------------------------------------------------------------#pragma TINY #include // --- function prototypes void txmit0( unsigned char charact); void txmit1( unsigned char charact); void uart1Config(void); void uart0ws0relcfg(void); // - Constants definition sbit UART_TX_EMPTY = USERFLAGS^1; //--------------------------------------------------------------------------// MAIN FUNCTION //--------------------------------------------------------------------------at 0x0100 void main (void) { // Enable and configure the UART0 & UART1 uart0ws0relcfg(); //Configure UART0 uart1Config(); //Configure UART1
Interrupt on P1 Change
The VMX51C1020 includes an Interrupt on Port change feature, which is available on the Port1 pins of the VMX51C1020. This feature is like having eight extra external interrupt inputs sharing the ADC interrupt vector at address 006Bh and can be very useful for applications such as switches, keypads, etc. To activate this interrupt, the bits corresponding to the pins being monitored must be set in the PORTIRQEN register. The ADCPCIE bit in the IEN1 register must be set as well as the EA bit of the IEN0 register.
TABLE 123: (PORTIRQEN) PORT C HANGE IRQ CONFIGURATION - SFR 9FH
7 P17IEN 3 P13IEN Bit 7 Mnemonic P17IEN
6 P16IEN 2 P12IEN
5 P15IEN 1 P11IEN
4 P4IEN 0 P10IEN
//*** Configure the interrupts IEN0 |= 0x91; IEN2 |= 0x01; do { }while(1); // End of main()...
//Enable UART0 Int + enable all int //Enable UART1 Interrupt
//Wait for UARTs interrupts
//--------------------------------------------------------------------------// INTERRUPT ROUTINES //--------------------------------------------------------------------------//--------------------------------------------------------------------------// UART0 interrupt // // Retrieve character received in S0BUF and transmit it // back on UART0 // //------------------------------------------------------------------------void int_uart0 (void) interrupt 4 { IEN0 &= 0x7F; //--- The only UART0 interrupt source is Rx... txmit0(S0BUF); //disable All interrupts
6
P16IEN
5
P15IEN
4
P14IEN
3
// Return the character //received on UART0 //clear R0I & T0I bits // enable all interrupts
P13IEN
S0CON = S0CON & 0xFC; IEN0 |= 0x80; }// end of UART0 interrupt
2
P12IEN
//--------------------------------------------------------------------------// UART1 interrupt // // Retrieve character received in S1BUF and transmit it // back on UART1 // //--------------------------------------------------------------------------void int_uart1 (void) interrupt 16 { IEN0 &= 0x7F; //--- The only UART1 interrupt source is Rx... txmit1(S1BUF); S1CON = S1CON & 0xFC; IEN0 |= 0x80; }// end of UART1 interrupt Note: See UART0 / UART1 section for configuration examples and TXMITx functions //disable All interrupts
1
P11IEN
0
P10IEN
Function Port 1.7 IRQ on change enable 0 = Disable 1 = Enable Port 1.6 IRQ on change enable 0 = Disable 1 = Enable Port 1.5 IRQ on change enable 0 = Disable 1 = Enable Port 1.4 IRQ on change enable 0 = Disable 1 = Enable Port 1.3 IRQ on change enable 0 = Disable 1 = Enable Port 1.2 IRQ on change enable 0 = Disable 1 = Enable Port 1.1 IRQ on change enable 0 = Disable 1 = Enable Port 1.0 IRQ on change enable 0 = Disable 1 = Enable
// Return the character // received on UART1 // clear both R1I & T1I bits // enable all interrupts
The PORTIRQSTAT register monitors the occurrence of the Interrupt on port change. This register serves to define which P1 pin has changed when an interrupt occurs.
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VMX51C1020
TABLE 124: (PORTIRQSTAT) PORT C HANGE IRQ STATUS - SFR A1H
7 P17ISTAT 3 P13ISTAT Bit 7
6 P16ISTAT 2 P12ISTAT
5 P15ISTAT 1 P11ISTAT
4 P14ISTAT 0 P10ISTAT
The following provides an assembler example for configuration of the Interrupt on Port1 pin change and how it is shared with the ADC interrupt.
include VMIXreg.INC ;*** INTERRUPT VECTORS JUMP TABLE * ORG 0000H ;BOOT ORIGIN VECTOR LJMP START ORG 006BH ;INT ADC and P1 change interrupt LJMP INT_ADC_P1 ;*** MAIN PROGRAM ORG 0100h START: MOV MOV DIGPWREN,#01H P2PINCFG,#0FFH ;ENABLE TIMER 2
Mnemonic P17ISTAT
6
P16ISTAT
5
P15ISTAT
4
P14ISTAT
3
P13ISTAT
2
P12ISTAT
1
P11ISTAT
0
P10ISTAT
Function Port 1.7 changed 0 = No 1 = Yes Port 1.6 changed 0 = No 1 = Yes Port 1.5 changed 0 = No 1 = Yes Port 1.4 changed 0 = No 1 = Yes Port 1.3 changed 0 = No 1 = Yes Port 1.2 changed 0 = No 1 = Yes Port 1.1 changed 0 = No 1 = Yes Port 1.0 changed 0 = No 1 = Yes
;*** Initialise Port change interrupt on P1.0 - P1.7 MOV PORTIRQSTAT,#00H MOV PORTIRQEN,#11111111B ;*** Initialise the ADC, BGAP, PGA Operation MOV ANALOGPWREN,#07h ;Select CH0 as ADC input + Enable input buffer + Adc clk MOV INMUXCTRL,#0Fh MOV ADCCLKDIV,#0Fh MOV ADCCONVRLOW,#000h ;*** configure ADC Conversion Rate MOV ADCCONVRMED,#080h MOV ADCCONVRHIGH,#016h MOV ADCCTRL,#11111010b ;***Activate All interrupts + (serial port for debugger support) MOV IEN0,#090H ;*** Enable ADC interrupt MOV IEN1,#020H ;***Wait IRQ… WAITIRQ: LJMP
WAITIRQ
FIGURE 44: APPLICATION EXAMPLE OF PORT CHANGE INTERRUPT
Numeric Keypad
1 4 7 *
2 5 8 0
3 6 9 #
P1.4 P1.5 P1.6
ORG 0200h ;************************************************************************ ;* IRQ ROUTINE: IRQADC + P1Change ;************************************************************************ INT_ADC_P1: ;MOV IEN0,#00h ;DISABLE ALL INTERRUPT ;***Check if IRQ was caused by Port Change ;***If PORTIRQSTAT = 00h -> IRQ comes from ADC MOV A,PORTIRQSTAT JZ CASE_ADC ;*** If interrupt was caused by Port 1, change CASE_P0CHG: MOV PORTIRQSTAT,#00H ;*** Perform other instructions related to Port1 change IRQ ;(...) ;*** Jump to Interrupt end AJMP ENDADCP1INT
VMX51C1020
P1.7
P1.3 P1.2 P1.1
;*** If interrupt was caused by ADC CASE_ADC: ANL ADCCTRL,#11110011b ;***Reset ADC interrupt flags & Reset ADC for next acquisition ORL ADCCTRL,#080h ORL ADCCTRL,#11111010b ;*** Perform other instructions related to Port1 change IRQ ;(...) ;** End of ADC and Port 1 Change interrupt ENDADCP0INT: ANL IRCON,#11011111b ;***Enable All interrupts before exiting ; MOV IEN0,#080H RETI END
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VMX51C1020
The Clock Control Circuit
The VMX51C1020’s clock control circuit allows dynamic adjustment of the clock from which the processor and the peripherals derive their clock source. This allows reduction of overall power consumption by modulating the operating frequency according to processing requirements or peripheral use. A typical application for this can be portable acquisition systems in which significant power savings can be achieved by lowering the operating frequency between A/D conversions and automatically throttling it back to full speed when an A/D interrupt is generated. Note that A/D converter operation is not affected by the Clock Control Unit. The clock control circuit allows adjusting the System clock from [Fosc/1] (full speed) down to [Fosc/512]. The clock division control is done via the CLKDIVCTRL register located at address 94h of the SFR register area.
TABLE 125: (CLKDIVCTRL) CLOCK DIVISION CONTROL REGISTER -SFR 94 H
FIGURE 45: CLOCK TIMING W HEN AN INTERRUPT OCCURS
INTERNAL CLOCK
INTERRUPT
INTERRUPT SET
INTERRUPT CLEARED
Once the interrupt is cleared, the VMX51C1020 returns to the selected operating speed as defined by the MCKDIV [3:0] bits of the CLKDIVCTRL register. When the IRQNORMSPD bit is set, the VMX51C1020 will continue to operate at the selected speed as defined by the MCKDIV [3:0] bits of the CLKDIVCTRL register. Note: With the exception of the A/D converter and analog only peripherals such as the current source, potentiometers and opamp, all the peripheral operating speeds are affected by the Clock Control circuit
7 SOFTRST 3
6 -
5 2 1 MCKDIV [3:0]
4 IRQNORMSPD 0
Software Reset
Software reset can be generated by setting the SOFTRST bit of the CLKDIVCTRL register to 1.
Bit 7 6:5 4
Mnemonic SOFTRST IRQNORMSPD
3:0
MCKDIV [3:0]
Function Writing 1 into this bit location provokes a reset. Read as a 0 0 = Full Speed in IRQ 1 = Selected speed during IRQs Master Clock Divisor 0000 – Sys CLK 0001 = SYS /2 0010 = SYS /4 0011 = SYS /8 0100 = SYS /16 0101 = SYS /32 0110 = SYS /64 0111 = SYS /128 1000 = SYS /256 1001 = SYS /512 (…) 1111 = SYS /512
The value written into the lower nibble of the CLKDIVCTRL register, MCKDIV[3:0], defines the clock division ratio. When the IRQNORMSPD bit is cleared, the VMX51C1020 will run at the maximum operating speed when an interrupt occurs (see following figure).
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VMX51C1020
Power-on/Brown-Out Reset
The VMX51C1020 includes a Power-OnReset/Brown-Out detector circuit that ensures the VMX51C1020 enters and stays in the reset state as long as the supply voltage is below the reset threshold voltage (order of 3.7 – 4.0 Volts). In most applications, the VMX51C1020 requires no external components to perform a Power-on Reset when the device is powered on. The VMX51C1020 includes a RESET input for applications in which external Reset control is required. The reset pin includes an internal pullup resistor. When a Power-on reset occurs, all SFR locations return to their default values and peripherals are disabled. Errata Note:
The VMX51C1020 may fail to exit the reset state if the supply voltage drops below the reset threshold, but not below 3V. For applications where this condition can occur, use an external supply monitoring circuit to reset the device.
STOP Mode In this mode, in contrast to IDLE mode, all internal clocking shuts down. In order to enter STOP mode, the user must set the STOP bit of the PCON register. The CPU will exit this state only when a non-clocked external interrupt or reset occurs (internal interrupts are not possible because they require clocking activity). The following interrupts can restart the processor from STOP mode: Reset, INT0, INT1, SPI Rx/Rx Overrun, and the I2C interface.
FIGURE 46: POWER MANAGEMENT ON THE VMX51C1020
IDLE
STOP INTERRUPT REQUEST
CLKCPU GATE
CLK FOR CPU
CLKPER GATE
CLK FOR PERIPHERALS
CLK
The following table describes the power control register of the VMX51C1020.
TABLE 126: (PCON) POWER CONTROL (CPU) - SFR 87 H
7 SMOD
6 -
5 -
4 -
3 GF1
2 GF0
1 STOP
0 IDLE
Processor Power Control
The processor power management unit has two modes of operation: IDLE and STOP mode. IDLE Mode When the VMX51C1020 is in IDLE mode, the processor clock is halted. However, the internal clock and peripherals continue to run. The power consumption drops because the CPU is not active. As soon as an interrupt or reset occurs, the CPU exits the IDLE mode. In order to enter IDLE mode, the user must set the IDLE bit of the PCON register. Any enabled interrupts will force the processor to exit IDLE mode
Bit 7
Mnemonic SMOD
Function The speed in Mode 2 of Serial Port 0 is controlled by this bit. When SMOD= 1, fclk /32. This bit is also significant in Mode 1 and 3, as it adds a factor of 2 to the baud rate.
-
6 5 4
-
3 2 1
GF1 GF0 STOP
0
IDLE
Not used for power management Not used for power management Stop mode control bit. Setting this bit turns on the STOP Mode. STOP bit is always read as 0. IDLE mode control bit. Setting this bit turns on the IDLE mode. IDLE bit is always read as 0.
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VMX51C1020
Watchdog Timer
The VMX51C1020’s Watchdog Timer is used to monitor program operation and reset the processor in the case where the program code would not be able to refresh the Watchdog before its timeout period has lapsed. This can come about from an event that results in the Program Counter executing faulty or incorrect code and inhibiting the device from doing its intended job. The Watchdog Timer consists of a 15-bit counter composed of two registers (WDTL and WDTH) and a reload register (WDTREL). See following figure.
FIGURE 47: W ATCH DOG TIMER
SYSCLK ÷ 12
TABLE 128: (IP0) INTERRUPT PRIORITY REGISTER 0 - SFR B8H
7 UF8 Bit 7 6
6 WDTSTAT Mnemonic UF8 WDTSTAT
5
4
3
2 IP0 [5:0]
1
0
5 4 3 2 1 0
IP0.5 IP0.4 IP0.3 IP0.2 IP0.1 IP0.0
Function User Flag bit Watchdog timer status flag. Set to 1 by hardware when the watchdog timer overflows. Must be cleared manually Port1 Timer 2 ADC Change UART0 MULT/ACCU Timer 1 I2C External SPI RX INT1 availlable Timer 0 SPI TX Interrupt Empty External External UART1 INT0 INT 0
÷2
The WDTSTAT bit of the IP0 register is the Watchdog status flag. This bit is set to 1 by the hardware whenever a Watchdog Timer overflow occurs. This bit must be cleared manually.
0 WDTL 7 8 WDTH 14 WDTR
Setting-up the Watchdog Timer
Control of the Watchdog Timer’s is enabled by the following bits:
Bit WDOGEN WDTR WDTS Location DIGPWREN.6 IEN0.6 IEN1.6 Role Watchdog timer Enable Watchdog timer refresh flag Watchdog Timer Start bit
÷16
0 Control Logic
WDTREL
7
WDTR
(Refresh)
WDTS
(Start)
The WDTL and WDTH registers are not accessible from the SFR register. However the WDTREL register makes it possible to load the upper 6 bits of the WDTH register. The PRES bit of the WDTREL register selects the Clock prescaler that is fed into the Watchdog Timer. When PRES = 0, the clock prescaler = 24 When PRES = 1, the clock prescaler = 384
TABLE 127: (WDTREL) W ATCHDOG TIMER RELOAD REGISTER - SFR D9H
In order for the Watchdog to begin counting, the user must set the WDOGEN bit (bit 6) of DIGPWREN register, as follows:
MOV DIGPWREN,#x1xxxxxxB ;x=0 or 1 depending ;of other peripherals ;to enable
7 PRES Bit 7
6
5
4 3 2 WDTREL [6:0]
1
0
Mnemonic PRES
6-0
WDTREL
Function Pre-scaler select bit. When set, the Watchdog is clocked through an additional divide-by-16 pre-scaler. 7-bit reload value for the high-byte of the Watchdog timer. This value is loaded into the WDT when a refresh is triggered by a consecutive setting of bits WDT and SWDT.
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VMX51C1020
The value written into the WDTREL register defines the Delay Time of the Watchdog Timer asfollows: WDT delay when the WDTREL bit 7 is cleared
WDT Delay = 24*[ 32768–(WDTREL(6:0) x 256)] Fosc
*** The Simple way *** MOV MOV IEN0,#x1xxxxxxB IEN1,#x1xxxxxxB ;DIRECT WRITE THAT SET BIT ;WDTR (x = 0 or 1) ;DIRECT WRITE THAT SET BIT ;WDTS (x = 0 or 1)
In the case where the program makes use of the interrupts, it is recommended to deactivate interrupts before the Watch Dog refresh is performed and reactivate them afterwards. b) Watch Dog Timer refresh example 2:
*** If Interrupts are used: *** CLR MOV ORL XCH MOV ORL MOV MOV SETB IEN0.7 A,IEN0 A,#01000000B A,R1 A,IEN1 A,#01000000B IEN0,R1 IEN1,A IEN0.7 ;Deactivate the interrupt ;Retrieve IEN0 content ;set the bit 6 (WDTR) ;Store IENO New Value ;Retrieve IEN1 content ;Set bit 6, (WDTS) ; Set WDTR BIT ;Set WDTS BIT ;Reactivate the Interrupts
WDT delay when the WDTREL bit 7 is set
WDT Delay = 384*[ 32768–(WDTREL(6:0) x 256)] Fosc
The following table provides WDT reload values and their corresponding delay times Fosc 14.74MHz 14.74MHz 14.74MHz WDTREL 00h 4Fh CCh WDT Delay 53.3ms 20.4ms 347ms
Watchdog Timer Reset
To determine whether the Reset condition was caused by the Watchdog Timer, the state of the WDTSTAT bit of the IP0 register should be monitored. On a standard power on reset condition, this bit is cleared.
Note: The value present in the CLKDIVCTRL Register affects the Watchdog Timer Delay time. The above equations and examples assume that the CLKDIVCTRL register content is 00h
Starting the Watchdog Timer
To start the Watchdog timer using the hardware automatic start procedure, the WDTS (IEN1) and WDTR (IEN0) bits must be set. The Watchdog will begin to run with default settings, i.e. all registers will be set to zero.
;*** Do a Watchdog Timer Refresh / Start sequence SETB SETB ;WDTS bit IEN0.6 IEN1.6 ;Set the WDTR bit first ;Then without delay set the
When the WDT registers enter the state 7FFFh, the asynchronous signal, WDTS will become active. This signal will set bit 6 in the IP0 register and trigger a reset. To prevent the Watchdog Timer from resetting the VMX51C1020, you must reset it periodically by clearing the WDTR and, immediately afterwards, clear the WDTS bit. As a security feature to prevent inadvertent clearing of the Watchdog timer, no delay (instruction) is allowed between the clearing of the WDTR and the WDTS bits. a) Watchdog Timer refresh example 1:
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VMX51C1020
WDT Initialization and Use Example Program
ORG 0000H LJMP START ;RESET & WD IRQ VECTOR ;************************************* ;* MAIN PROGRAM BEGINNING * ;************************************* ORG 0100h ;*** Initialize WDT and other peripherals*** MOV DIGPWREN,#40H ;ENABLE WDT OPERATION ;*** INITIALIZE WATCHDOG TIMER RELOAD VALUE MOV WDTREL,#04FH ;The WDTREL register is used to ;define the Delay Time WDT. ;Bit 7 of WDTREL define clock ;prescalng value ;Bit 6:0 of WDTREL defines the ;upper 7 bits reload value of the ;watchdog Timer 15-bit timer ;*** PERFORM A WDT REFRESH/START SEQUENCE SETB IEN0.6 ;Set the WDTR bit first SETB IEN1.6 ;Then without delay (instruction) ;set the WDTS bit right after. ;No Delays are permitted between ;setting of the WDTR bit and ;setting of the WDTS bit. ;This is a security feature to ;prevent inadvertent reset/start of ;the WDT ;IF other interrupt are enabled, ;It is recommended to disable ;interrupts before refreshing the ;WDT and reactivate them after ;*** Wait WDT Interrupt WAITWDT: NOP
VMX51C1020 Programming
When the PM pin is set to 1, the I²C interface becomes the programming interface for the VMX51C1020’s Flash memory. An In-circuit programming interface is easy to implement at the board level. See VMIX APPNote001. Erasing and programming the VMX51C1020’s Flash memory requires an external programming voltage of 12V. This programming voltage is supplied/controlled by the programming hardware/tools. The VMX51C1020 can be programmed using the Ramtron In-Circuit Programmer.
FIGURE 48: VMX51C1020 PROGRAMMING
;*** If the two following code lines below are put "in-comment", the ;***WDT will trigger a reset, and the program will restart. ;*** PERFORM A WATCHDOG TIMER REFRESH/START SEQUENCE ;SETB IEN0.6 ;Set the WDTR bit first ;SETB IEN1.6 ;Then without delay (instruction) LJMP WAITWDT ;set the WDTS bit right after. ;No Delays are permitted between ;setting of the WDTR bit and ;setting of WDTS bit. ;This is a security feature to ;prevent inadvertent reset/start of ;the WDT ;It is recommended to disable ;interrupts before refreshing the ;WDT and reactivate them after
RS-232
5V (optional) SCL SDA
Target PC Board
VERSA-ICP
VPP 12V PM RES - (RESET) GND
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VMX51C1020
VMX51C1020 Debugger
The VMX51C1020 includes hardware Debugging features that speed-up embedded software development time.
FIGURE 49: VMX51C1020 DEBUGGER HARDWARE INTERFACE
VERSA Ware VMX Software
Debugger Features
The VMX51C1020 Debugger supports breakpoints and single-stepping of the user program. It supports retrieval and editing of the contents of the SFR Registers and RAM memory contents when a breakpoint is reached or when the device operates in single-step mode. Unlike ROM monitor programs that execute user program instruction at a much lower speed, the VMX51C1020 Debugger does not affect program operating speed when in “Run Mode” before encountering a breakpoint.
RS-232 RS-232
RS232 Transceiver
To UART0
VERSA-ICP
Target PC Board
Debugger Hardware Interface
The VMX51C1020’s Development System provides the ideal platform for running the Debugger. Interfacing to the VMX51C1020’s Debugger is done via the UART0 serial interface. It is possible to run the VMX51C1020 Debugger on the end user PCB provided that access to the VMX51C1020’s UART0 is available. However, a connection to a stand alone In-Circuit Programmer (ICP) will be required to perform Flash programming, control of the Reset line, and to activate the Debugger on the target VMX51C1020 device.
Debugger Software Interface
The VERSA WARE VMX51C1020 / VERSA1 Windows™ software provides an easy to use user interface for In-Circuit Debugging For more details on the VMX51C1020 Debugger, see the “VERSA WARE VMX51C1020 - V1 Software User Guide.pdf” All documents are accessible on the Ramtron Inc. website at www.ramtron.com
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VMX51C1020
VMX51C1020 64 pin Quad Flat Package
E E1
10
A2
A 10 e
D
D1
A1
VMX51C1020 QFP-64
64
1
0.30 RAD. TYP. 64 A STANDOFF A1 0.20 RAD. TYP. L 0.17 MAX SEATING PLANE
0.25
b
BODY +3.20mm Footprint PACKAGE THICKNESS Dims. A A1 A2 D D1 E E1 L e b +.10/-.05 ±.25 ±.10 ±.25 ±.10 +.15/-.10 BASIC ±.05
TOLS. LEADS
2.00 64L 2.35 0.25MAX 2.00 17.20 14.00 17.20 14.00 .88 .80 .35 0º-7º
NOTES: 1) ALL DIMENSIONS ARE IN MILLIMETERS 2) DIMENSIONS SHOWN ARE NOMINAL WITH TOLERANCES AS INDICATED. 3) FOOT LENGTH "L" IS MEASURED AT GAGE PLANE, 0.25 ABOVE SEATING PLANE
MAX.
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VMX51C1020
Ordering Information
Device Number Structure
VMX51C1020 Ordering Options
Device Number
VMX51C1020-14-QC VMX51C1020-14-QCG
*See Errata information below
Package Option
QFP-64 QFP-64
Operating Voltage
4.75V to 5.5V 4.75V to 5.5V
Temperature
0°C to +70°C 0°C to +70°C
Frequency
14.75MHz 14.75MHz
VMX51C1020 Errata
The VMX51C1020 operating frequency and temperature range have been revised with more conservative values. The maximum operating frequency specifications of the VMX51C1020 has been revised to 14.75MHz and its operating temperature range to 0ºC to 70ºC. These new specifications affect all the VMX51C1020 devices with the markings of VMX51C1020-QAI16. In order to reflect the specification updates of the VMX51C1020, the new VMX51C1020 devices that have the same silicon version, features and performances as the VMX51C1020-QAI16 will now be marked VMX51C1020-QAC14.
Disclaimer
Right to make changes - Ramtron reserves the right to make changes to its products - including circuitry, software and services without notice at any time. Customers should obtain the most current and relevant information before placing orders. Use in applications - Ramtron assumes no responsibility or liability for the use of any of its products, and conveys no license or title under any patent, copyright or mask work right to these products and makes no representations or warranties that these products are free from patent, copyright or mask work right infringement unless otherwise specified. Customers are responsible for product design and applications using Ramtron parts. Ramtron assumes no liability for applications assistance or customer product design. Life support – Ramtron products are not designed for use in life support systems or devices. Ramtron customers using or selling Ramtron products for use in such applications do so at their own risk and agree to fully indemnify Ramtron for any damages resulting from such applications.
Note: PC is a registered trademark of IBM Corp. Windows is a registered trademark of Microsoft Corp. I2C is a registered trademark of Philips Corporation. SPI is a registered trademark of Motorola Inc. All other trademarks are the property of their respective owners.
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