VP-1410A

VOICE FEATURES n n n n n n High quality voice & sound generation 10 messages with direct trigger pins Playback-only with external EPROM or ROM Stand-alone operation 128K x 8 direct memory addressing, expandable Single 5V DC supply voltage n n n n n n VP-1410A Digital Voice Processor Low power consumption Internal RC oscillator or external clock Continuous Variable Slope Delta (CVSD) modulation Sampling rate from 24Kbps to 128 Kbps Message digitization with the VP-880 system 48-pin DIP (VP-1410A) or 48-pin QFP (VP-1410AF) GENERAL DESCRIPTIONS The VP-1410A Digital Voice Processor is an advanced CMOS LSI chip designed for multiple-message playback applications. It can access up to 10 different messages of variable length stored in external EPROM or ROM chips. Message activation is simplified since each message has its own trigger pin . If memory bank switching technique is used, the number of messages supported can be easily expanded to 20, 40 or more. The VP-1410A is totally self-contained. It can access the external memory all by itself without the help from any microprocessor. Although the chip provides only 16 address lines, an external counter can be easily added to extend the memory addressing to virtuely no limitation. Therefore very long message length can be achieved easily. Overall, the VP-1410A offers high voice quality and flexible memory addressing that no other chips can. APPLICATIONS n Multiple message playback n Sound effects generator n Digital message repeaters for consumer, industrial, security and telecommunication products VP-1410A (DIP48) Pin Assignment VP-1410AF (QFP48) Pin Assignment Eletech Enterprise Co., Ltd. 531-3F Chung-Cheng Road Hsin Tien, Taipei Hsien, Taiwan Tel:+886 2-2218-0068 Fax:+886 2-2218-0254 http://www.eletech.com Eletech Electronics, Inc. 16019 Kaplan Avenue Industry, CA 91744, U.S.A. Tel: (626) 333-6394 Fax: (626) 333-6494 Supply Voltage, VDD - VSS ..................................... 0 to 5.5V Input Volotage, VIN ........................................... VSS to VDD Operating Temperature, TOP ...................... -10oC to 60oC Storage Temperature, TST .......................... -20oC to 80oC ABSOLUTE MAXIMUM RATINGS* * Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. ELECTRICAL CHARACTERISTICS Symbol VDD IDD IDRIVE ISINK VIH VIL IDRIVE ISINK TRESET Ttr FC Parameter Supply Voltage Standby Current Clock Drive Current Clock Sink Current Input Voltage Output Current Reset Pulse Width I/O Input Pulse Width (VDD = 5V, FOSC = 2048KHz, FCLOCK = 32 KHz unless otherwise specified) Min. 4.5 12 12 High Low Drive Sink 3.5 0 3 3 500 35 12 4 4 5 1.5 Typ. 5 1.4 Max. 5.5 Units V mA mA mA V V mA mA ns us MHz Internal Memory Search Clock TIMING DIAGRAM RESET Ttr I/O READ BUSY (internal) SYSTEM CLK (internal) I/O SCAN (internal) 12MHz 12MHz VOICE VP-1410A..........................................................................................2 PIN DESCRIPTIONS A0 - A16 Output, address bus, expandable by adding a counter. Note that VP-1410AF does not have A16. ANG & ANG Output, differential analog audio signal. ANGD Input, analog signal to be connected to the external comparator output. C1 Input, internal RC oscillator. If external clock is to be used, it must be connected to this pin and its frequency 64x the sampling rate. CLK DRV Output, buffered clock signal, a square wave of the same frequency as the sampling rate. D0 - D7 Input, data bus. ENV Input, to be connected to an external integrator output. INT Output, connected to an external integrator to produce envelope waveform. GND Ground. I/O1 ~ I/O10 Input/output, trigger pin, active low. I/O1 is for message #1, I/O2 is for message #2 and etc. When the chip is idle but not under reset, this pin is the trigger input and pulsing it will put the chip in the "Play" mode and start the message. Once in the "Play" mode, the pin becomes a "low" output until the message is over. R1 Output, internal oscillator pin. Leave un-connected when using external clock. READ Output, active low. It indicates the chip is in the "Play" mode. This signal is usually used to enable memory output. RESET Input, active high. Reset the chip back to the "Idle" mode. This pin is level sensitive. TEST For factory use only, keep it un-connected. VCC Input, supply voltage. Block Diagram D0 ........... D7 A0 : A16 CLK DRV VDD GND RESET READ ADDRESS GENERATOR INPUT BUFFER & SHIFT REGISTER VDD GND TEST OSC. & TIMING CTRL 12MHz CLOCK 6-AA FLAG RECEIVER I/O CONTROL & LATCH I/O SCANNER CVSD DEMODULATOR ANG ANG ANGD I/O1 .......... I/O10 ENV INT VOICE VP-1410A..........................................................................................3 APPLICATION NOTES 1. VP-1410AF Missing A16 Due to packaging constraint, the VP-1410AF does not provide address line A16. Therefore, A16 must be generated externally by adding a binary counter, as explained below. 2. Memory Address Expansion The VP-1410A's internal 17-bit address counter covers memory space up to 128K x 8, or 1M bits. It can be easily expanded by just adding an external binary counter, clocked by the falling edge of address line A16. The first counter output becomes A17, the second output becomes A18 and etc. This is possible since once started, the VP1410A will continue to play until it reaches the EOM (End Of Message) flag. When the internal address counter reaches the maximum count before the chip sees the EOM flag, the counter simply overflows and restarts from zero again. Therefore the VP-1410A can access an unlimited amount of memory by adding an external address counter. 3. EOM (End Of Message) Flag The EOM flag consists of six consecutive bytes of "AA", or "10101010" in binary format. After a trigger signal is received, the VP-1410A uses the internal 12MHz system clock to scan through memory space and finds the correct message by counting the number of EOM flags. For example, to find the 5th message, it must scan through each and every memory location until it finds 4 EOM flags. The first byte following the 4th EOM flag is the first byte of the 5th message. 4. Creating Master EPROM File on the VP-880 System Follow these steps to create the master EPROM file: 1. Digitize, edit and save each message in a separate file. 2. Use VP-880's function "H" to combine all the messages together. The VP-880 program will automatically search and eliminate any EOM flag within each messge, which is naturally formed during digitization. It will then put a EOM flag at the end of each message and combine them into one or several master files. CIRCUIT DESIGN EXAMPLES 1. 10-Message Playback, 8M EPROM VOICE VP-1410A..........................................................................................4