VRS51C1100-40-L

VRS51C1100 Datasheet Rev 1.1 Versa 8051 MCU with 128KB of IAP/ISP Flash Overview The VRS51C1100 is based on the standard 8051 microcontroller architecture and is a pin compatible drop-in replacement for the 8051. The VRS51C1100 is aimed at a diversity of applications that require a large amount of program/data memory with non-volatile data storage and/or code/field based firmware upgrade capability coupled with comprehensive peripheral support. It features 64KB of In-System/In-Application Programmable Flash memory, 64KB Data Flash memory, 1KB of RAM, 4 PWM outputs, a UART, three 16-bit timers/counters, a watchdog timer and power down features. The VRS51C1000 is available with firmware that enables In-System Programming (firmware based bootloader) of the Flash memory via the UART interface (ISPVx version). General Flash memory programming is supported by device programmers available from Ramtron or other 3rd party commercial programmer suppliers. The VRS51C1100 is available in PLCC-44, QFP-44 and DIP-40 packages and functions over the industrial temperature range. FIGURE 1: VRS51C1100 FUNCTIONAL DIAGRAM Feature Set • • • • • • • • • • • • • • • • • • • 80C51/80C52 pin compatible 64KB Program + 64KB Data Flash memory In-System / In-Application Flash Programming (ISP/IAP) Program voltage: 5V 1024 Bytes on chip data RAM Four 8-bit I/Os + one 4-bit I/O 4 PWM outputs on P1.3 to P1.7 One Full Duplex UART serial port Three 16-bit Timers/Counters W atchdog Timer Bit operation instruction 8-bit Unsigned Multiply and Division instructions BCD arithmetic Direct and Indirect Addressing Two Levels of Interrupt Priority and Nested Interrupts Power saving modes Code protection function Low EMI (inhibit ALE) Operating Temperature Range -40ºC to +85ºC FIGURE 2: VRS51C1100 QFP-44 AND PLCC-44 PIN OUT DIAGRAMS P0 .4/AD4 P0 .5/AD5 P0 .6/AD6 P0 .7/AD7 # EA # PSEN P2 .7/A15 P2 .6/A14 P2 .5/A13 23 22 33 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 VDD 34 P4 .1 AL E P2.4/A12 P2.3/A11 P2.2/A10 64KB Data FLASH 64KB Program FLASH 1024 Bytes of RAM 8051 PROCESSOR ADDRESS/ DATA BUS P4.2 T2/P1.0 T2EX/P1.1 PWM0/P1.2 PWM1/P1.3 PWM2/P1.4 44 1 VRS51C1100 QFP-44 P2.1/A9 P2.0/A8 P4.0 VSS XTAL1 XTAL2 12 11 #RD/P3.7 #WR/P3.6 PORT 0 8 PWM3/P1.5 P1.6 P1.7 RE S RX D/P 3.0 P4.3 T XD/P3.1 # INT 0/P3.2 #INT 1/P3.3 PORT 1 8 PWM2/P1.4 PWM1/P1.3 PWM0/P1.2 T2EX /P1 .1 T2 /P 1.0 P4.2 UART PORT 2 8 VDD P0.0/AD0 P0.1/AD1 P0.2/AD2 2 INTERRUPT INPUTS TIMER 0 TIMER 1 TIMER 2 RESET POWER CONTROL WATCHDOG TIMER PORT 3 8 6 40 39 1 PWM3/P1.5 7 P0.3/AD3 T 0/P3.4 T 1/P3.5 PORT 4 4 P1.6 P1.7 RES RXD/P3.0 P4.3 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 #EA P4.1 ALE #PSEN P2.7/A15 P2.6/A14 P2.5/A13 PWM 4 TXD/P3.1 #INT0/P3.2 #INT1/P3.3 T0/P3.4 T1/P3.5 17 18 VRS51C1000 PLCC-44 29 28 XTA L1 VSS P 4.0 #WR/P3.6 Ramtron International Corporation 1850 Ramtron Drive Colorado Springs Colorado, USA, 80921 ? ? ? http://www.ramtron.com MCU customer service: 1-800-943-4625, 1-514-871-2447, ext. 208 1-800-545-FRAM, 1-719-481-7000 # RD/P 3.7 XTA L2 P2 .0 /A 8 P2 .1 /A 9 P2.2/A10 P2.3/A11 P2.4/A12 page 1 of 50 VRS51C1100 Pin Descriptions for QFP-44/PLCC-44 T ABLE 1: PIN DESCRIPTIONS FOR QFP-44/PLCC-44 QFP - 44 PLCC - 44 Name I/O Function 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 PWM3 P1.5 P1.6 P1.7 RES RXD P3.0 P4.3 TXD P3.1 #INT0 P3.2 #INT1 P3.3 T0 P3.4 T1 P3.5 # WR P3.6 #RD P3.7 XTAL2 XTAL1 VSS P4.0 P2.0 A8 P2.1 A9 P2.2 A10 P2.3 A11 P2.4 A12 P2.5 A13 O I/O I/O I/O I I I/O I/O O I/O I I/O I I/O I I/O I I/O O I/O O I/O O I I/O I/O O I/O O I/O O I/O O I/O O I/O O PWM Channel 3 Bit 5 of Port 1 Bit 6 of Port 1 Bit 7 of Port 1 Reset Receive Data Bit 0 of Port 3 Bit 3 of Port 4 Transmit Data & Bit 1 of Port 3 External Interrupt 0 Bit 2 of Port 3 External Interrupt 1 Bit 3 of Port 3 Timer 0 Bit 4 of Port 3 Timer 1 & 3 Bit 5 of Port Ext. Memory Write Bit 6 of Port 3 Ext. Memory Read Bit 7 of Port 3 Oscillator/Crystal Output Oscillator/Crystal In Ground Bit 0 of Port 4 Bit 0 of Port 2 Bit 8 of External Memory Address Bit 1 of Port 2 Bit 9 of External Memory Address Bit 2 of Port 2 Bit 10 of External Memory Address Bit 3 of Port 2 & Bit 11 of External Memory Address Bit 4 of Port 2 Bit 12 of External Memory Address Bit 5 of Port 2 Bit 13 of External Memory Address QFP - 44 PLCC - 44 Name I/O Function 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 1 2 3 4 P2.6 A14 P2.7 A15 #PSEN ALE P4.1 #EA P0.7 AD7 P0.6 AD6 P0.5 AD5 P0.4 AD4 P0.3 AD3 P0.2 AD2 P0. 1 AD1 P0.0 AD0 VDD P4.2 T2 P1.0 T2EX P1.1 PWM0 P1.2 I/O O I/O O O O I/O I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I/O I I/O O I/O O I/O O I/O Bit 6 of Port 2 Bit 14 of External Memory Address Bit 7 of Port 2 Bit 15 of External Memory Address Program Store Enable Address Latch Enable Bit 1 of Port 4 External Access Bit 7 Of Port 0 Data/Address Bit 7 of External Memory Bit 6 of Port 0 Data/Address Bit 6 of External Memory Bit 5 of Port 0 Data/Address Bit 5 of External Memory Bit 4 of Port 0 Data/Address Bit 4 of External Memory Bit 3 Of Port 0 Data/Address Bit 3 of External Memory Bit 2 of Port 0 Data/Address Bit 2 of External Memory Bit 1 of Port 0 & Data Address Bit 1 of External Memory Bit 0 Of Port 0 & Data Address Bit 0 of External Memory VCC Bit 2 of Port 4 Timer 2 Clock Out Bit 0 of Port 1 Timer 2 Control Bit 1 of Port 1 PWM Channel 0 Bit 2 of Port 1 PWM Channel 1 Bit 3 of Port 1 PWM Channel 2 Bit 4 of Port 1 43 5 PWM1 P1.3 PWM2 P1.4 44 6 P 0.4/AD 4 P 0.5/AD 5 P 0.6/AD 6 P 0.7/AD 7 # EA # PSE N P 2.7/A1 5 P 2.6/A1 4 P 2.5/A1 3 PWM2 /P 1.4 P WM1 /P 1.3 PWM0 /P 1.2 T2 EX/P1.1 V DD P0.0 /A D0 P0.1 /A D1 P0 .2 /A D2 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 VDD P4.2 T2/P1.0 T2EX/P1.1 PWM0/P1.2 PWM1/P1.3 PWM2/P1.4 33 32 31 30 29 28 27 26 25 24 34 35 36 37 38 39 40 41 42 43 44 1 2 3 4 5 6 7 8 9 10 23 22 21 20 19 P2.4/A12 P2.3/A11 P2.2/A10 P2.1/A9 P2.0/A8 P4.0 VSS XTAL1 XTAL2 #RD/P3.7 #WR/P3.6 6 5 4 3 2 PWM3/P1.5 P1.6 P1.7 RES RXD/P3.0 P4.3 TXD/P3.1 #INT0/P3.2 #INT1/P3.3 T0/P3.4 T1/P3.5 7 8 9 10 11 12 13 14 15 16 1 44 43 42 41 40 39 38 37 36 P0.3/AD 3 T 2/P1.0 P4.2 P 4.1 A LE P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 #EA P4.1 ALE #PSEN P2.7/A15 P2.6/A14 P2.5/A13 VRS51C1100 QFP-44 18 17 16 15 14 13 12 11 VRS51C1100 PLCC-44 35 34 33 32 31 30 29 17 18 19 20 21 22 23 24 25 26 27 28 PWM3 /P 1.5 P 1.6 P 1.7 RE S RXD/P3 .0 P 4.3 TXD /P 3.1 # INT0 /P 3.2 # INT1 /P 3.3 T0 /P 3.4 T1 /P 3.5 P 2.0/A8 P 2.1/A9 P2 .2 /A 10 P2.3/A1 1 XT AL1 #WR/P3 .6 # RD/P3.7 XT AL2 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 #EA #PSEN P2.7/A15 _______________________________________________________________________________________________ www.ramtron.com page 2 of 50 P2.6/A14 P2.5/A13 P4.1 ALE P2.4/A1 2 V SS P4.0 VRS51C1100 VRS51C1100 DIP40 Pin Descriptions T ABLE 2: VRS51C1100 PIN DESCRIPTIONS FOR DIP40 PACKAGE DIP40 Name I/O Function 21 22 23 24 25 26 27 28 29 30 31 32 DIP40 Name I/O Function 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 T2 P1.0 T2EX P1.1 PWM0 P1.2 PWM1 P1.3 PWM2 P1.4 PWM3 P1.5 P1.6 P1.7 RESET RXD P3.0 TXD P3.1 #INT0 P3.2 #INT1 P3.3 T0 P3.4 T1 P3.5 # WR P3.6 #RD P3.7 XTAL2 XTAL1 VSS I I/O I I/O O I/O O I/O O I/O O I/O I/O I/O I I I/O O I/O I I/O I I/O I I/O I I/O O I/O O I/O O I - Timer 2 Clock Out Bit 0 of Port 1 Timer 2 Control Bit 1 of Port 1 PWM Channel 0 Bit 2 of Port 1 PWM Channel 1 Bit 3 of Port 1 PWM Channel 2 Bit 4 of Port 1 PWM Channel 3 Bit 5 of Port 1 Bit 6 of Port 1 Bit 7 of Port 1 Reset Receive Data Bit 0 of Port 3 Transmit Data & Bit 1 of Port 3 External Interrupt 0 Bit 2 of Port 3 External Interrupt 1 Bit 3 of Port 3 Timer 0 Bit 4 of Port 3 Timer 1 & 3 Bit 5 of Port Ext. Memory Write Bit 6 of Port 3 Ext. Memory Read Bit 7 of Port 3 Oscillator/Crystal Output Oscillator/Crystal In Ground P2.0 A8 P2.1 A9 P2.2 A10 P2.3 A11 P2.4 A12 P2.5 A13 P2.6 A14 P2.7 A15 #PSEN ALE #EA / VPP P0.7 AD7 P0.6 I/O O I/O O I/O O I/O O I/O O I/O O I/O O I/O O O O I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O - 33 AD6 P0.5 34 AD5 P0.4 35 AD4 P0.3 36 AD3 P0.2 37 38 39 AD2 P0. 1 AD1 P0.0 AD0 VDD T2 / P1.0 T2EX / P1.1 PWM0 / P1.2 PWM1 / P1.3 PWM2 / P1.4 PWM3 / P1.5 P1.6 P1.7 RESET RXD / P3.0 TXD / P3.1 #INT0 / P3.2 #INT1 / P3.3 T0 / P3.4 T1 / P3.5 #WR / P3.6 #RD / P3.7 XTAL2 XTAL1 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 VDD P0.0 / AD0 P0.1 / AD1 P0.2 / AD2 P0.3 / AD3 P0.4 / AD4 P0.5 / AD5 P0.6 / AD6 P0.7 / AD7 #EA / VPP ALE PSEN P2.7 / A15 P2.6 / A14 P2.5 / A13 P2.4 / A12 P2.3 / A11 P2.2 / A10 P2.1 / A9 P2.0 / A8 40 Bit 0 of Port 2 Bit 8 of External Memory Address Bit 1 of Port 2 Bit 9 of External Memory Address Bit 2 of Port 2 Bit 10 of External Memory Address Bit 3 of Port 2 & Bit 11 of External Memory Address Bit 4 of Port 2 Bit 12 of External Memory Address Bit 5 of Port 2 Bit 13 of External Memory Address Bit 6 of Port 2 Bit 14 of External Memory Address Bit 7 of Port 2 Bit 15 of External Memory Address Program Store Enable Address Latch Enable External Access Flash programming voltage input Bit 7 Of Port 0 Data/Address Bit 7 of External Memory Bit 6 of Port 0 Data/Address Bit 6 of External Memory Bit 5 of Port 0 Data/Address Bit 5 of External Memory Bit 4 of Port 0 Data/Address Bit 4 of External Memory Bit 3 Of Port 0 Data/Address Bit 3 of External Memory Bit 2 of Port 0 Data/Address Bit 2 of External Memory Bit 1 of Port 0 & Data Address Bit 1 of External Memory Bit 0 Of Port 0 & Data Address Bit 0 of External Memory Supply input VRS51C1100 DIP-40 32 31 30 29 28 27 26 25 24 23 22 21 _______________________________________________________________________________________________ www.ramtron.com page 3 of 50 VRS51C1100 Instruction Set The following table describes the VRS51C1100 instruction set. The instructions are function and binary code compatible with industry standard 8051s. T ABLE 3: LEGEND FOR INSTRUCTION SET T ABLE Symbol A Rn Direct @Ri rel bit #data #data 16 addr 16 addr 11 Function Accumulator Register R0-R7 Internal register address Internal register pointed to by R0 or R1 (except MOVX) Two's complement offset byte Direct bit address 8-bit constant 16-bit constant 16-bit destination address 11-bit destination address Mnemonic Description Size (bytes) 1 2 1 2 1 2 2 2 2 2 2 2 1 2 1 2 1 2 2 2 2 3 2 3 1 2 2 3 1 1 1 1 1 1 2 2 1 2 1 1 2 3 1 1 2 3 2 2 2 3 3 3 1 2 2 3 3 3 3 2 3 1 Instr. Cycles Boolean Instruction CLR C Clear Carry bit CLR bit Clear bit SETB C Set Carry bit to 1 SETB bit Set bit to 1 CPL C Complement Carry bit CPL bit Complement bit ANL C,bit Logical AND between Carry and bit ANL C,#bit Logical AND between Carry and not bit ORL C,bit Logical ORL between Carry and bit ORL C,#bit Logical ORL between Carry and not bit MOV C,bit Copy bit value into Carry MOV bit,C Copy Carry value into Bit Data Transfer Instructions MOV A, Rn Move register to A MOV A, direct Move direct byte to A MOV A, @Ri Move data memory to A MOV A, #data Move immediate to A MOV Rn, A Move A to register MOV Rn, direct Move direct byte to register MOV Rn, #data Move immediate to register MOV direct, A Move A to direct byte MOV direct, Rn Move register to direct byte MOV direct, direct Move direct byte to direct byte MOV direct, @Ri Move data memory to direct byte MOV direct, #data Move immediate to direct byte MOV @Ri, A Move A to data memory MOV @Ri, direct Move direct byte to data memory MOV @Ri, #data Move immediate to data memory MOV DPTR, #data Move immediate to data pointer MOVC A, @A+DPTR 1 1 1 1 1 1 2 2 2 2 1 2 1 1 1 1 1 2 1 1 2 2 2 2 1 2 1 2 2 2 2 2 2 2 2 2 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 T ABLE 4: VRS51C1100 INSTRUCTION SET Mnemonic Description Size (bytes) 1 2 1 2 1 2 1 2 1 2 1 2 1 1 2 1 1 1 2 1 1 1 1 1 1 2 1 2 2 3 1 2 1 2 2 3 1 2 1 2 2 3 1 1 1 1 1 1 1 Instr. Cycles Arithmetic instructions ADD A, Rn Add register to A ADD A, direct Add direct byte to A ADD A, @Ri Add data memory to A ADD A, #data Add immediate to A ADDC A, Rn Add register to A with carry ADDC A, direct Add direct byte to A with carry ADDC A, @Ri Add data memory to A with carry ADDC A, #data Add immediate to A with carry SUBB A, Rn Subtract register from A with borrow SUBB A, direct Subtract direct byte from A with borrow SUBB A, @Ri Subtract data mem from A with borrow SUBB A, #data Subtract immediate from A with borrow INC A Increment A INC Rn Increment register INC direct Increment direct byte INC @Ri Increment data memory DEC A Decrement A DEC Rn Decrement register DEC direct Decrement direct byte DEC @Ri Decrement data memory INC DPTR Increment data pointer MUL AB Multiply A by B DIV AB Divide A by B DA A Decimal adjust A Logical Instructions ANL A, Rn AND register to A ANL A, direct AND direct byte to A ANL A, @Ri AND data memory to A ANL A, #data AND immediate to A ANL direct, A AND A to direct byte ANL direct, #data AND immediate data to direct byte ORL A, Rn OR register to A ORL A, direct OR direct byte to A ORL A, @Ri OR data memory to A ORL A, #data OR immediate to A ORL direct, A OR A to direct byte ORL direct, #data OR immediate data to direct byte XRL A, Rn Exclusive-OR register to A XRL A, direct Exclusive-OR direct byte to A XRL A, @Ri Exclusive-OR data memory to A XRL A, #data Exclusive-OR immediate to A XRL direct, A Exclusive-OR A to direct byte XRL direct, #data Exclusive-OR immediate to direct byte CLR A Clear A CPL A Compliment A SWAP A Swap nibbles of A RL A Rotate A left RLC A Rotate A left through carry RR A Rotate A right RRC A Rotate A right through carry 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 4 4 1 1 1 1 1 1 2 1 1 1 1 1 2 1 1 1 1 1 2 1 1 1 1 1 1 1 Move code byte relative DPTR to A MOVC A, @A+PC Move code byte relative PC to A MOVX A, @Ri Move external data (A8) to A MOVX A, @DPTR Move external data (A16) to A MOVX @Ri, A Move A to external data (A8) MOVX @DPTR, A Move A to external data (A16) PUSH direct Push direct byte onto stack POP direct Pop direct byte from stack XCH A, Rn Exchange A and register XCH A, direct Exchange A and direct byte XCH A, @Ri Exchange A and data memory XCHD A, @Ri Exchange A and data memory nibble Branching Instructions ACALL addr 11 Absolute call to subroutine LCALL addr 16 Long call to subroutine RET Return from subroutine RETI Return from interrupt AJMP addr 11 Absolute jump unconditional LJMP addr 16 Long jump unconditional SJMP rel Short jump (relative address) JC rel Jump on carry = 1 JNC rel Jump on carry = 0 JB bit, rel Jump on direct bit = 1 JNB bit, rel Jump on direct bit = 0 JBC bit, rel Jump on direct bit = 1 and clear JMP @A+DPTR Jump indirect relative DPTR JZ rel Jump on accumulator = 0 JNZ rel Jump on accumulator 1= 0 CJNE A, direct, rel Compare A, direct JNE relative CJNE A, #d, rel Compare A, immediate JNE relative CJNE Rn, #d, rel Compare reg, immediate JNE relative CJNE @Ri, #d, rel Compare ind, immediate JNE relative DJNZ Rn, rel Decrement register, JNZ relative DJNZ direct, rel Decrement direct byte, JNZ relative Miscellaneous Instruction NOP No operation Rn: Any of the register R0 to R7 @Ri: Indirect addressing using Register R0 or R1 #data: immediate Data provided with Instruction #data16: Immediate data included with instruction bit: address at the bit level rel: relative address to Program counter from +127 to –128 Addr11: 11-bit address range Addr16: 16-bit address range #d: Immediate Data supplied with instruction _______________________________________________________________________________________________ www.ramtron.com page 4 of 50 VRS51C1100 Special Function Registers (SFR) Addresses 80h to FFh of the SFR address space can be accessed in direct addressing mode only. The following table lists the VRS51C1100 special function registers. T ABLE 5: SPECIAL FUNCTION REGISTERS (SFR) SFR Register P0 SP DPL DPH MPAGE DBANK PCON TCON TMOD TL0 TL1 TH0 TH1 P1 WDTKEY SCON SBUF PWME WDTCTRL P2 PWMC PWMD0 PWMD1 PWMD2 PWMD3 IE P3 IP SYSCON T2CON RCAP2L RCAP2H TL2 TH2 PSW P4 ACC B IAPFADHI IAPFADLO IAPFDATA IAPFCTRL SFR Adrs 80h 81h 82h 83h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 90h 97h 98h 99h 9Bh 9Fh A0h A3h A4h A5h A6h A7h A8h B0h B8h BFh C8h CAh CBh CCh CDh D0h D8h E0h F0h F4h F5h F6h F7h Bit 7 BSE SMOD TF1 GATE1 SM0 WDTE PWMD0.4 PWMD1.4 PWMD2.4 PWMD3.4 EA WDR TF2 CY FA15 FA7 FD7 IAPSTART Bit 6 TR1 C/T1 SM1 PWMD0.3 PWMD1.3 PWMD2.3 PWMD3.3 EXF2 AC FA14 FA6 FD6 Bit 5 TF0 M1.1 SM2 PWM3E CLEAR PWMD0.2 PWMD1.2 PWMD2.2 PWMD3.2 ET2 PT2 RCLK F0 FA13 FA5 FD5 FZONE Bit 4 TR0 M0.1 REN PWM2E PWMD0.1 PWMD1.1 PWMD2.1 PWMD3.1 ES PS TCLK RS1 FA12 FA4 FD4 Bit 3 BS3 GF1 IE1 GATE0 TB8 PWM1E PWMD0.0 PWMD1.0 PWMD2.0 PWMD3.0 ET1 PT1 DATAFE EXEN2 RS0 P4.3 FA11 FA3 FD3 Bit 2 BS2 GF0 IT1 C/T0 RB8 PWM0E PS2 NP0.2 NP1.2 NP2.2 NP3.2 EX1 PX1 IAPE TR2 OV P4.2 FA10 FA2 FD2 Bit 1 BS1 PDOWN IE0 M1.0 TI PS1 PDCK1 NP0.1 NP1.1 NP2.1 NP3.1 ET0 PT0 XRAME C/T2 P4.1 FA9 FA1 FD1 IAPFCT1 Bit 0 BS0 IDLE IT0 M0.0 RI PS0 PDCK0 NP0.0 NP1.0 NP2.0 NP3.0 EX0 PX0 ALEI CP/RL2 P P4.0 FA8 FA0 FD0 IAPFCT0 Reset Value 1111 1111b 0000 0111b 0000 0000b 0000 0000b 0000 0000b 0000 0001b 0000 0000b 0000 0010b 0000 0000b 0000 0000b 0000 0000b 0000 0000b 0000 0000b 1111 1111b 0000 0000b 0000 0000b 0111 1111b 0000 0000b 0000 0000b 1111 1111b 0000 0000b 0000 0000b 0000 0000b 0000 0000b 0000 0000b 0000 0000b 1111 1011b 0000 0000b 0000 1010b 0000 0000b 0000 0000b 0000 0000b 0000 0000b 0000 0000b 0000 0001b ****1111b 0000 0000b 0000 0000b 0000 0000b 0000 0000b 0000 0000b ______________________________________________________________________________________________ www.ramtron.com page 5 of 50 VRS51C1100 VRS51C1100 Program + Data Flash Memory The VRS51C1100 includes 64KB of on-chip Flash memory that can be used as program memory or as non-volatile data storage memory using the InApplication Programming feature (IAP). The VRS51C1100 also includes 64KB of data storage Flash memory that is also IAP programmable. Programming the ISP Boot Program The ISP boot program is programmed into the device using a parallel programmer, such as the VERSAMCUPPR, or a commercial parallel programmer that supports the VRS51C1100. The Flash memory reserved for the ISP program is defined by the parallel programmer software (ISP Page Config) when the device is programmed. When programming the ISP boot program into the VRS51C1100, the “lock bit” option should be activated to protect the ISP Flash memory zone from being inadvertently erased, which can happen when Flash Erase operations are performed under the control of the ISP boot program, or to prevent the VRS51C1100 Flash memory from being read back using a parallel programmer. If an Erase operation is performed using a parallel programmer, the entire Flash memory, including the ISP Boot program memory zone, will be erased. ISP Boot Program Memory Zone The upper portion of the VRS51C1100 Flash program memory can be reserved to store an ISP (In-System Programmable) boot loader program. This boot program can be used to program the Flash memory via the serial interface (or via any other method). by making use of the In-Application Programming (IAP) feature. This allows the processor to load the program or data from an external device or system, and to program it into the Flash memory (see the VRS51C1100 IAP feature section). The size of the memory block reserved for the ISP boot loader program (when activated) is adjustable from 512 to 4KB bytes in increments of 512 bytes, using the ISP Page config parameter. FIGURE3: VRS51C1100-ISP PROGRAM SIZE VS ISP CONFIG. VALUE FFFFh ISPCFG=1 ISP Boot Program Start Conditions Setting the ISP page configuration to a value other than 0 will cause the processor to jump to the base address of the ISP boot code when a hardware reset is performed (provided that the value FFh is present at program address 0000h). ISPCFG=2 ISPCFG=3 FE00h ISPCFG=4 ISPCFG=5 FC00h ISPCFG=6 ISPCFG=7 FA00h ISPCFG=8 ISP Program Size = ISP Page Config value x 512Bytes F800h F600h F400h F200h F000h 0000h ______________________________________________________________________________________________ www.ramtron.com page 6 of 50 VRS51C1100 An alternate way to force the VRS51C1100 to jump to the ISP boot program is to maintain pins P2.6 and P2.7 or pin P4.3 at a low logic level during a hardware reset, as shown in the diagram below: FIGURE 4: VRS51C1100 ALTERNATE ISP BOOT PROGRAM ACCESS VRS51C1100 ISPVx Firmware Boot Program An ISP boot loader program is available for the VRS51C1100. (ISPVx Firmware, x = revision, see Ramtron website for latest revision) that resides in locations F200h to FFFFh in the upper 3.5KB of the VRS51C1100 Program Flash memory. The ISPVx Firmware enables In-System-Programming of the VRS51C1100 on the final application PCB using the UART interface. The VRS51C1100 can be ordered with or without the ISPVx bootloader firmware (see the ordering information section of this datasheet for part number information). See the following figure for a hardware configuration example. Other configurations are also possible. 10ms 10ms P2.7 P2.6 RES FIGURE 5: VRS51C1100 INTERFACE FOR IN-SYSTEM PROGRAMMING VRS51C1100 RS232 Transceiver (with ISPV2 Firmware) TXD OR... To PC RS232 interf. RXD 51k 10ms 10ms PNP 150k Creset RES P4.3 Rreset RES Visit the Ramtron web site to download the “Versa Ware ISP” Window™’s application, which enables communication with the ISPVx firmware. The ISPVx bootloader firmware can also be programmed into the VRS51C1000 by the user. Source code is included with the Versa Ware ISP application software. For more information on the ISPVx firmware, please consult the “VRS51C1100 ISPVx Firmware User Guide.pdf,” available on the Ramtron web site. Note: The current ISPVx firmware and Versa Ware software does not allow VRS51C1100 Data Flash programming. Future versions of both will provide support for VRS51C1100 Data Flash programming. The ISP boot program can also be accessed via the LJMP instruction. When the ISP page configuration is set to 0 while the device is being programmed with a parallel programmer, the ISP boot feature will be disabled. ______________________________________________________________________________________________ www.ramtron.com page 7 of 50 VRS51C1100 VRS51C1100 IAP feature The VRS51C1100 IAP feature allows the processor to self-program its program and data Flash memory from within the user program. Five SFR registers serve to control the IAP operation. The description of these registers is provided below. IAP Flash Address and Data Registers The IAPFADHI and IAPADLO registers are used to specify at which address the IAP function will be performed. T ABLE 7:IAP FLASH ADDRESS HIGH (IAPFADHI) - SFR F4H 7 6 5 4 3 2 IAPFADHI[15:8] 1 0 System Control Register The system control register controls the activation of the data Flash and the expanded RAM and serves to monitor the watchdog timer status. T ABLE 6: SYSTEM CONTROL REGISTER (SYSCON) – SFR BFH T ABLE 8:IAP FLASH ADDRESS LOW (IAPFADLO) - SFR F5H 7 6 5 4 3 2 IAPFADLO[15:8] 1 0 The IAPFDATA SFR register contains the data byte required to perform the IAP function. T ABLE 9:IAP FLASH DATA REGISTER (IAPFDATA) - SFR F6H 7 WDR 6 5 Unused 4 3 DFLASHE 2 IAPE 1 XRAME 0 ALEI 7 6 5 4 3 2 IAPFDATA[7:0] 1 0 Bit 7 Mnemonic WDR 6 5 4 3 Unused Unused Unused DFLASHE 2 IAPE 1 0 XRAME ALEI Description This is the watchdog timer reset bit. It will be set to 1 when the reset signal generated by WDT overflows. Data Flash memory Enable 0: Data Flash is Disabled 1: Data Flash is Enabled IAP function enable bit 0: IAP is Disabled 1: ISP is Enabled 768 byte on-chip enable bit ALE output inhibit bit, which is used to reduce EMI. 0: ALE active 1: ALE activity is inhibited The WDR bit of the SYSCON register indicates whether the system has been reset due to the overflow of the watchdog timer. For this reason, users should check the WDR bit whenever an unexpected reset occurs. Setting the DFLASHE bit of the SYSCON register to 1 activates the 64KB on-chip data Flash memory, which is disabled by default. The IAPE bit is used to activate the IAP function. When set to 1, the XRAME bit enables the expanded 768 bytes of RAM. Bit 0 of this register is the ALE output inhibit bit. Setting this bit to 1 will inhibit the Fosc/6Hz clock signal output to the ALE pin. ______________________________________________________________________________________________ www.ramtron.com page 8 of 50 VRS51C1100 IAP Flash Control Register The VRS51C1100’s IAP function operation is controlled by the IAP Flash control register, IAPFCTRL. T ABLE 10:IAP FLASH CONTROL REGISTER (IAPFCTRL) - SFR F7H Note that for security reasons, the IAPSTART bit of the IAPFCTRL register is configured as read-only by default. To set the IAPSTART to 1, the following operation sequence must be performed first: MOV MOV MOV IAPFDATA,#55h IAPFDATA,#AAh IAPFDATA,#55h 7 6 5 4 3 2 IAPFCTRL[15:8] 1 0 Bit 7 6 5 4 3 2 1 0 Mnemonic IAPSTART Unused FZONE Unused Unused Unused IAPFCT[1:0] Description IAP Selected operation Start sequence Flash zone select for IAP Flash operations: 0: Flash Program Zone 1: Flash Data Zone Flash Memory IAP Function (see below) Once the start bit is set to 1, the IAP subsystem will read the contents of the IAP Flash address and data registers and hold the VRS51C1100 program counter at its current value until the IAP operation is complete. When the IAP operation is complete, the IAPSTART bit will be cleared and the program will continue executing. IAP Byte Program in the VRS51C1100 Program Flash The IAP byte program function is used to program a byte into a specified program memory location under the control of the IAP feature. See the following program example: IAP_PROG: MOV MOV MOV IAPFDATA,#55H IAPFDATA,#0AAH IAPFDATA,#55H ;Sequence to Enable Writing ; the IAPSTART bit VRS51C1100 IAP operations can be performed in either the 64KB Flash program memory zone or the 64KB data Flash memory zone. The FZONE bit selects the area in which the IAP operations will be performed and acts as the 17th bit of the 128KB Flash address. FZONE = 0: IAP functions target program Flash FZONE = 1: IAP functions target data Flash Setting the IAPSTART bit to 1 starts the execution of the IAP command specified by the IAPFCT[1:0] bits of the IAP Flash control register. If the IAPSTART bits equal 0, no IAP operations will be performed. The IAP subsystem handles four different functions. The IAP function performed is controlled by the IAPFCT bits, as shown below: T ABLE 11:IAP FUNCTIONS MOV SYSCON,#04H ;ENABLE IAP FUNCTION MOV IAPFADHI, FADRSH ;Set MSB of address to program MOV IAPFADLO,FADRSL ;Set LSB of address to program MOV IAPFDATA,FDATA ;Set Data to Program MOV IAPFCTRL,#80H ;Set the IAP Start bit + Byte Program ;**The program Counter will stop until the IAP function is completed IAP Byte Program in the VRS51C1100 Data Flash The IAP byte program function can also be used to program a byte into a specified data Flash memory location under the control of the IAP feature. See the following program example: IAP_PROG: MOV MOV MOV MOV IAPFDATA,#55H IAPFDATA,#0AAH IAPFDATA,#55H ;Sequence to Enable Writing ; the IAPSTART bit IAPFCT[1:0] Bits value 00 01 10 11 IAP Function Flash Byte Program Flash Erase Protect Flash Page Erase Flash Erase When activated, the Flash Erase function will erase the entire VRS51C1100 Flash memory except for the ISP boot program, if the ISP config bits (lock) have been activated. Be careful when performing Flash Erase under final application program control. SYSCON,#0CH ;ENABLE IAP FUNCTION + Enable ;Data Flash MOV IAPFADHI, FADRSH ;Set MSB of address to program MOV IAPFADLO,FADRSL ;Set LSB of address to program MOV IAPFDATA,FDATA ;Set Data to Program MOV IAPFCTRL,#A0H ;Set the IAP Start bit + FZONE bit ;**The program Counter will stop until the IAP function is completed ______________________________________________________________________________________________ www.ramtron.com page 9 of 50 VRS51C1100 IAP Page Erase Function By using the IAP feature, it is possible to perform a page erase of the VRS51C1100 program or data Flash memory (note that the memory area occupied by the ISP boot program cannot be page erased). Each page is 512 bytes in size. To perform a Flash page erase, the page address is specified by the XY (hex) value written into the IAPFADHI register. (The value 00h must be written into the IAPFADLO registers.) If the “Y” portion of the IAPFADHI register represents an even number, the page that will be erased corresponds to the range XY00h to X(Y+1)FFh. If the “Y” portion of the IAPFADHI register represents an odd number, the page that will be erased corresponds to the range X(Y-1)00h to XYFFh. The following program example demonstrates how to erase the page corresponding to the address B000hCFFFh in the program memory zone: ;** Erase Flash Program page located at address B000h to CFFFh. PageErase: MOV IAPFDATA,#55H ;Sequence to Enable Writing MOV IAPFDATA,#0AAH ; the IAPSTART bit MOV IAPFDATA,#55H MOV MOV MOV MOV SYSCON,#04H IAPFADHI, #0B0h IAPFADLO,#00h IAPFCTRL,#82H ;Enable IAP ;Set MSB of Page address to erase ;Set LSB of address = 00 ;Set the IAP Start Bit ISP/AIP operation Durations The following table shows the duration of the ISP/IAP operations for an oscillator clock of 40MHz. Operation Byte Program Page Erase Chip Erase Chip Protect Max Duration (Fosc = 40MHz) 30us 10ms 3sec 400us All ISP/IAP operations require a supply voltage of 5V to be executed properly. Program Status Word Register The PSW register is a bit addressable register that contains the status flags (CY, AC, OV, P), user flag (F0) and register bank select bits (RS1, RS0) of the 8051 processor. T ABLE 12: PROGRAM STATUS WORD REGISTER (PSW) - SFR DOH 7 CY Bit 7 6 5 4 3 2 1 0 6 AC 5 F0 4 RS1 3 RS0 2 OV 1 - 0 P The following example shows how to erase the same page in the data Flash memory zone: ;** Erase Flash Data page located at address B000h to CFFFh. PageErase: MOV IAPFDATA,#55H ;Sequence to Enable Writing MOV IAPFDATA,#0AAH ; the IAPSTART bit MOV IAPFDATA,#55H MOV MOV MOV MOV SYSCON,#0CH IAPFADHI, #0B0h IAPFADLO,#00h IAPFCTRL,#A2H ;Enable IAP + Data Flash ;Set MSB of Page address to erase ;Set LSB of address = 00 ;Set The IAP Start bit + FZONE bit Mnemonic CY AC F0 RS1 RS0 OV P Description Carry Bit Auxiliary Carry Bit from bit 3 to 4. User definer flag R0-R7 Registers bank select bit 0 R0-R7 Registers bank select bit 1 Overflow flag Parity flag RS1 0 0 1 1 RS0 0 1 0 1 Active Bank 0 1 2 3 Address 00h-07h 08h-0Fh 10h-17h 18-1Fh IAP Chip Erase Function The IAP chip erase function will erase the entire Flash memory contents with the exception of the ISP boot program area. Running this function will also automatically unprotect the Flash memory. IAP Chip Protect Function When the chip protect function is enabled, values read back from Flash memory will be 00h. ______________________________________________________________________________________________ www.ramtron.com page 10 of 50 VRS51C1100 Data Pointer The VRS51C1100 has one 16-bit data pointer. The DPTR is accessed via two SFR addresses: DPL located at address 82h and DPH located at address 83h. The DFLASHE and XRAME bits of the SYSCON register define which area the MOVX instruction will target: DFLASHE XRAME MOVX 2FFh Stack Pointer The stack pointer (SP) is a register located at address 81h of the SFR register area whose value corresponds to the address of the last item that was put on the processor stack. Each time new data is put on the SP, the value of the stack pointer is incremented. By default, the stack pointer value is 07h, but it is possible to program the processor stack pointer to point anywhere in the 00h to FFh range of RAM memory. When a function call is performed or an interrupt is serviced, the 16-bit return address (2 bytes) is stored on the stack. Data can be placed manually on the stack by using the PUSH and POP functions. 0 0 1 1 0 1 0 1 Ext. Memory Int. RAM Int. Data Flash Int. RAM Ext. Memory Ext. Memory Int. Data Flash Int. Data Flash Lower 128 bytes (00h to 7Fh, Bank 0 & Bank 1) The lower 128 bytes of data memory (from 00h to 7Fh) is summarized as follows: o Address range 00h to 7Fh can be accessed in direct and indirect addressing modes o Address range 00h to 1Fh includes R0-R7 register areas o Address range 20h to 2Fh is bit addressable o Address range 30h to 7Fh is not bit addressable and can be used for generalpurpose storage Upper 128 bytes (80h to FFh, Bank 2 & Bank 3) The upper 128 bytes of the data memory ranging from 80h to FFh can be accessed using indirect addressing or by using the bank mapping in direct addressing mode. Expanded RAM Access Using the MOVX @DPTR Instruction (0000-02FF, Bank4-Bank15) The 768 bytes of expanded RAM data memory occupies addresses 0000h to 02FFh. This can be accessed using external direct addressing (i.e. the MOVX instruction) or bank mapping direct addressing. When indirect addressing executes the MOVX @DPTR instruction, if the address is larger than 02FFh and the data Flash is disabled (DFLASHE=0), the VRS51C1100 will access off-chip memory in the external memory space using the external memory control signals. Data Memory The VRS51C1100 has 1KB of on-chip RAM: 256 bytes are configured like the internal memory structure of a standard 8052, while the remaining 768 bytes can be accessed using external memory addressing (MOVX). The VRS51C1100 also includes a large block of 64KB of data Flash that is mapped on the processor’s external memory bus for read access. FIGURE 6: VRS51C1100 DATA MEMORY STRUCTURE FFFFh IF DFLASHE = 1 Data Flash Mapped as External Memory Use MOVX to Read 02FFh Expanded 768 bytes (Accessed by direct external addressing mode, using the MOVX instruction) (XRAME=1) Lower 128 bytes RAM 02FFh IF XRAME = 1 and DFLASHE = 1 Data Flash Mapped as External Memory Use MOVX to Read FFh 80h 7Fh 00h Upper 128 bytes RAM (Indirect addressing only) SFR (Direct addressing only) 0000h 0000h By default, after reset the expanded RAM area and the data Flash areas are disabled. They are enabled by setting the XRAME and the DFLASHE bits (respectively) of the SYSCON register located at address BFh in the SFR. The MPAGE Register (Extra Read Data Pointer) The VRS51C1100 features a second data pointer called MPAGE, which is dedicated to data Flash and external RAM read access using the MOVX @Ri (I=0,1) instruction. The MPAGE register provides the high byte of the address, while the contents of the Ri register provides the low byte of the address. The operation of the MPAGE register resembles that of the ______________________________________________________________________________________________ www.ramtron.com page 11 of 50 VRS51C1100 MOVX @DPTR instruction, but is limited as a read function. The MPAGE register default setting is 00h. T ABLE 13: MPAGE REGISTER (MPAGE) - SFR 85H W indowed access to the entire 1KB of on-chip RAM in the range of 40h-7Fh is described in the following table. T ABLE 15: BANK MAPPING DIRECT ADDRESSING MODE 7 6 5 4 3 MPAGE[7:0] 2 1 0 BS3 0 BS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 BS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 BSO 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 040h~07fh mapping address 000h-03Fh 040h-07Fh 080h-0BFh 0C0h-0FFh 0000h-003Fh 0040h-007Fh 0080h-00BFh 00C0h-00FFh 0100h-013Fh 0140h-017Fh 0180h-01BFh 01C0h-01FFh 0200h-023Fh 0240h-027Fh 0280h-02BFh 02C0h-02FFh Note Lower 128 bytes RAM Lower 128 bytes RAM Upper 128 bytes RAM Upper 128 bytes RAM On-chip expanded 768 bytes RAM On-chip expanded 768 bytesRAM On-chip expanded 768 bytes RAM On-chip expanded 768 bytes RAM On-chip expanded 768 bytes RAM On-chip expanded 768 bytes RAM On-chip expanded 768 bytes RAM On-chip expanded 768 bytes RAM On-chip expanded 768 bytes RAM On-chip expanded 768 bytes RAM On-chip expanded 768 bytes RAM On-chip expanded 768 bytes RAM Data Bank Control Register The DBANK register enables the data bank select function to map the entire contents of the RAM memory in the range of 40h to 7Fh for applications that require direct addressing of the expanded RAM contents. The data bank select function is activated by setting the data bank select enable bit (BSE) to 1. Setting this bit to zero disables the function. The lower nibble of this register controls the mapping of the entire 1KB bytes on-chip RAM space into the 040h-07Fh range. T ABLE 14: DATA BANK CONTROL REGISTER (DBANK) – SFR 86H 0 0 0 0 0 0 0 1 1 1 7 BSE Bit 7 6 5 Unused 4 3 BS3 2 BS2 1 BS1 0 BS0 1 1 Mnemonic BSE 6 5 4 3 2 1 0 Unused Unused Unused BS3 BS2 BS1 BS0 Description Data Bank Select Enable Bit BSE=1, Data Bank Select enabled BSE=0, Data Bank Select disabled Allows the mapping of the 1KB RAM into the 040h - 07Fh RAM space 1 1 1 Example: User writes #55h to address 203h: MOV MOV MOV DBANK, #8CH A, #55H 43H, A ;Set bank mapping 40h-07Fh to 0200h-023Fh ;Store #55H to A ;Write #55H to 0203h ;address ______________________________________________________________________________________________ www.ramtron.com page 12 of 50 VRS51C1100 Power Control Register The VRS51C1100 provides two power saving modes: Idle and Power Down, which are controlled by the PDOWN and IDLE bits of the PCON register at address 87h. T ABLE 16: POWER CONTROL REGISTER (PCON) - SFR 87H 7 6 5 4 Unused 3 2 1 RAMS1 0 RAMS0 Bit 7 Mnemonic SMOD Description 1: Double the baud rate of the serial port frequency that was generated by Timer 1. 0: Normal serial port baud rate generated by Timer 1. 6 5 4 3 2 1 0 GF1 GF0 P DOWN IDLE General Purpose Flag General Purpose Flag Power Down mode control bit Idle mode control bit In Idle mode, the processor is stopped but the oscillator continues to run. The content of the RAM, I/O state and SFR registers are maintained and the Timer and external interrupts are left operational. The processor will be woken up when an external event, triggering an interrupt, occurs. In Power Down mode, the oscillator and the peripherals are disabled. The contents of the RAM and the SFR registers, however, are maintained. The only way to exit from the Power Down mode is via a hardware reset (note that the watchdog timer is stopped in Power Down). When the VRS51C1100 is in Power Down, its current consumption drops to about 50uA. The SMOD bit of the PCON register controls the oscillator divisor applied to Timer 1 when used as a baud rate generator for the UART. Setting this bit to 1 doubles the UART’s baud rate generator frequency. ______________________________________________________________________________________________ www.ramtron.com page 13 of 50 VRS51C1100 Input/Output Ports The VRS51C1100 has 36 bi-directional lines grouped into four 8-bit I/O ports and one 4-bit I/O port. These I/Os can be individually configured as inputs or outputs. With the exception of the P0 I/Os, which are of the open drain type, each I/O consists of a transistor connected to ground and a weak, transistor-based pullup resistor. Writing a 0 in a given I/O port bit register will activate the transistor connected to Vss and bring the I/O to a low level. Writing a 1 into a given I/O port bit register deactivates the transistor between the pin and ground. In this case, an internal weak pull-up resistor will bring the pin to a high level (except for Port 0, which is open-drain). To use a given I/O as an input, a 1 must be written into its associated port register bit. By default, upon reset all the I/Os are configured as inputs. The VRS51C1100 I/O ports are not designed to source current. corresponding bit register must be high. This would correspond to #Q=0 in Figure 7. The transistor would be off (open-circuited) and current would flow from the VCC to the pin, generating a logical high at the output. Note that if an external device with a logical low value is connected to the pin, the current will flow out of the pin. The presence of the pull-up resistance, even when the I/O’s are configured as inputs, means that a small current is likely to flow from the VRS51C1100 I/O’s pull-up resistors to the driving circuit when the inputs are driven low. For this reason, the VRS51C1100 I/O ports P1, P2, P3 and P4 are called “quasi bidirectional”. Structure of Port 0 The internal structure of P0 is shown in the next figure. The auxiliary function of this port requires a particular logic. As opposed to the other ports, P0 is truly bidirectional. In other words, when used as an input, it is considered to be in a floating logical state (high impedance state). This arises from the absence of the internal pull-up resistance. The pull-up resistance is actually replaced by a transistor that is only used when the port is configured to access external memory/data bus (EA=0). When used as an I/O port, P0 acts as an open drain port and the use of an external pull-up resistor is likely to be required for most applications. FIGURE 8: PORT P0’ S PARTICULAR STRUCTURE Structure of the P1, P2, P3 and P4 Ports The following figure demonstrates the general structure of the P1, P2, P3 and P4 port I/Os. For these ports, the output stage is composed of a transistor (X1) and a transistor set configured as a weak pull-up. Note that the figure below does not show the intermediary logic that connects the register’s output and the output stage because this logic varies with the auxiliary function of each port. FIGURE 7: GENERAL STRUCTURE OF THE O UTPUT STAGE OF P1, P2, P3 AND P4 Read Register Address A0/A7 Read Register Control Vcc Vcc Pull-up Network Internal Bus Q IC Pin D Flip-Flop X1 Internal Bus Q IC Pin D Flip-Flop Write to Register Q Write to Register Q X1 Read Pin Read Pin Each line may be used independently as a logical input or output. When used as an input, the When P0 is used as an external memory bus input (for a MOVX instruction, for example), the outputs of the register are automatically forced to 1. ______________________________________________________________________________________________ www.ramtron.com page 14 of 50 VRS51C1100 The bit addressable P0 register, located at address 80h, controls the P0 individual pin directions when used as I/Os (see the following table). T ABLE 17: PORT 0 REGISTER (P0) - SFR 80H Port P0 and P2 as Address and Data Bus The output stage may receive data from two sources: o The outputs of register P0 or the bus address itself multiplexed with the data bus for P0 The outputs of the P2 register or the high byte (A8 through A15) of the bus address for the P2 port 7 P0.7 Bit 7 6 5 4 3 2 1 0 6 P0.6 5 P0.5 4 P0.4 3 P0.3 2 P0.2 1 P0.1 0 P0.0 o Mnemonic P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0 Description For each bit of the P0 register correspond to an I/O line: 0: Output transistor pull the line to 0V 1: The output transistor is blocked so the pull-up brings the I/O to 5V. FIGURE 9: P2 PORT STRUCTURE Read Register Vcc Address Pull-up Network Internal Bus Q IC Pin D Flip-Flop Port 2 Port P2 is similar to ports 1 and 3, the difference being that P2 is used to drive the A8-A15 lines of the address bus when the EA line of VRS51C1100 is held low at reset time or when a MOVX instruction is executed. Like the P0, P1 and P3 registers, the P2 register is bit addressable. T ABLE 18: PORT 2 REGISTER (P2) - SFR A0H Write to Register Q Control X1 Read Pin 7 P2.7 Bit 7 6 5 4 3 2 1 0 6 P2.6 5 P2.5 4 P2.4 3 P2.3 2 P2.2 1 P2.1 0 P2.0 When the ports are used as an address or data bus, special function registers P0 and P2 are disconnected from the output stage, the 8 bits of the P0 register are forced to 1 and the contents of the P2 register remains constant. Port 1 The P1 register controls the direction of the Port 1 I/O pins. Writing a 1 into the P1.x bit (see the following table) of the P1 register configures the bit as an output, presenting a logic 1 to the corresponding I/O pin or enables use of the I/O pin as an input. Writing a 0 activates the output “pull-down” transistor, which will force the corresponding I/O line to a logic low. T ABLE 19: PORT 1 REGISTER (P2) - SFR 90H Mnemonic P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0 Description For each bit of the P2 register correspond to an I/O line: 0: Output transistor pull the line to 0V 1: The output transistor is blocked so the pull-up brings the I/O to 5V. 7 P1.7 Bit 7 6 5 4 3 2 1 0 6 P1.6 5 P1.5 4 P1.4 3 P1.3 2 P1.2 1 P1.1 0 P1.0 Mnemonic P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0 Description For each bit of the P1 register correspond to an I/O line: 0: Output transistor pull the line to 0V 1: The output transistor is blocked so the pull-up bring the I/O to 5V. ______________________________________________________________________________________________ www.ramtron.com page 15 of 50 VRS51C1100 Auxiliary Port 1 Functions The Port 1 I/O pins are shared with the PWM outputs, Timer 2 EXT and T2 inputs, as shown below: Pin P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 Mnemonic T2 T2EX Function Timer 2 counter input Timer 2 Auxiliary input PWM0 output PWM1 output PWM2 output PWM3 output PWM4 output IC Pin X1 Internal Bus Q D Flip-Flop Write to Register Q Auxiliary P3 Port Functions The Port 3 I/O pins are shared with the UART interface, INT0 and INT1 interrupts, Timer 0 and Timer 1 inputs and the #WR and #RD lines when external memory accesses are performed. PWM0 PWM1 PWM2 PWM3 PWM4 FIGURE 10: P3 PORT STRUCTURE Read Register Auxiliary Function: Output Vcc Port 3 The Port 3 structure is similar that of Port 1. T ABLE 20: PORT 3 REGISTER (P3) - SFR B0H Read Pin 7 P3.7 Bit 7 6 5 4 3 2 1 0 6 P3.6 5 P3.5 4 P3.4 3 P3.3 2 P3.2 1 P3.1 0 P3.0 Auxiliary Function: Input Mnemonic P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 P3.1 P3.0 Description For each bit of the P3 register correspond to an I/O line: 0: Output transistor pull the line to 0V 1: The output transistor is blocked so the pull-up brings the I/O to 5V. To configure P3 pins as input or use alternate P3 function the corresponding bit must be set to 1. The following table describes the auxiliary functions of the Port 3 I/O pins. T ABLE 21: P3 AUXILIARY F UNCTION T ABLE Pin P3.0 Mnemonic RXD P3.1 TXD P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 INT0 INT1 T0 T1 WR RD Function Serial Port: Receive data in asynchronous mode. Input and output data in synchronous mode. Serial Port: Transmit data in asynchronous mode. Output clock value in synchronous mode. External Interrupt 0 Timer 0 Control Input External Interrupt 1 Timer 1 Control Input Timer 0 Counter Input Timer 1 Counter Input Write signal for external memory Read signal for external memory ______________________________________________________________________________________________ www.ramtron.com page 16 of 50 VRS51C1100 Port 4 Port 4 has four related I/O pins and its port address is located at 0D8H. T ABLE 22: PORT 4 (P4) - SFR D8H T ABLE 23: LIST OF INSTRUCTIONS THAT READ AND MODIFY THE PORT USING REGISTER VALUES 7 6 5 Unused Mnemonic Unused Unused Unused Unused P4.3 P4.2 P4.1 P4.0 4 3 P4.3 2 P4.2 1 P4.1 0 P4.0 Bit 7 6 5 4 3 2 1 0 Description Used to output the setting to pins P4.3, P4.2, P4.1, P4.0 respectively. Instruction ANL ORL XRL JBC CPL INC DEC DJNZ MOV P.,C CLR P.x SETB P.x Function Logical AND ex: ANL P0, A Logical OR ex: ORL P2, #01110000B Exclusive OR ex: XRL P1, A Jump if the bit of the port is set to 0 Complement one bit of the port Increment the port register by 1 Decrement the port register by 1 Decrement by 1 and jump if the result is not equal to 0 Copy the held bit C to the port Set the port bit to 0 Set the port bit to 1 Port Operation Timing Software Port Control Writing to a Port (Output) Some instructions allow the user to read the logic state of the output pin, while others allow the user to read the contents of the associated port register. These instructions are called read-modify-write instructions. A list of these instructions are found in the following table. Upon execution of these instructions, the content of the port register (at least 1 bit) is modified. The other read instructions take the present state of the inputs into account. For example, instruction ANL P3,#01h obtains the value in the P3 register; performs the desired logic operation with the constant 01h; and recopies the result into the P3 register. When users want to take the present state of the inputs into account, they must first read these states and perform an AND operation between the read value and the constant. MOV A, P3; State of the inputs in the accumulator ANL A, #01; AND operation between P3 and 01h When the port is used as an output, the register contains information on the state of the output pins. Measuring the state of an output directly on the pin is inaccurate because the electrical level depends mostly on the type of charge that is applied to it. The functions shown next take the value of the register rather than that of the pin. When an operation results in a modification of the content in a port register, the new value is placed at the output of the D flip-flop during the last machine cycle that the instruction needed to execute. Reading a Port (Input) To be sampled, the signal duration present on the I/O inputs must be longer than Fosc/12. ______________________________________________________________________________________________ www.ramtron.com page 17 of 50 VRS51C1100 I/O Ports Driving Capability The maximum allowable continuous current that the device can sink on an I/O port is described in the following table: Maximum sink current on one given I/O Maximum total sink current for P0 Maximum total sink current for P1, 2, 3 Maximum total sink current on all I/O 10mA 26mA 15mA 71mA Timers 1 and 0 are configured by the TMOD and TCON registers. T ABLE 24: T IMER MODE CONTROL REGISTER (TMOD) – SFR 89H 7 GATE1 6 C/T1 5 T1M1 4 T1M0 3 GATE0 2 C/T0 1 T0M1 0 T0M0 Bit 7 Mnemonic GATE1 It is not recommended to exceed the sink currents outlined in the above table. Doing so will likely make the low-level output voltage exceed device specifications and affect device reliability. The VRS51C1100 I/O ports are not designed to source current. 6 C/T1 5 4 3 T1M1 T1M0 GATE0 Description 1: Enables external gate control (pin INT1 for Counter 1). When INT1 is high, and TRx bit is set (see TCON register), a counter is incremented every falling edge on the T1IN input pin. Selects timer or counter operation (Timer 1). 1 = A counter operation is performed 0 = The corresponding register will function as a timer. Selects the operating mode of Timer/Counter 1 If set, enables external gate control (pin INT0 for Counter 0). When INT0 is high, and TRx bit is set (see TCON register), a counter is incremented every falling edge on the T0IN input pin. Selects timer or counter operation (Timer 0). 1 = A counter operation is performed 0 = The corresponding register will function as a timer. Selects the operating mode of Timer/Counter 0. VRS51C1100 Timers The VRS51C1100 includes three 16-bit timers: Timer 0, Timer 1 and Timer 2. The Timers can operate in two modes: o Event counting mode o Timer mode When operating in event counting mode, the counter is incremented each time an external event, such as a transition in the logical state of the timer input (T0, T1, T2 input), is detected. When operating in timer mode, the counter is incremented by the microcontroller’s system clock (Fosc/12) or by a divided version of it. 2 C/T0 1 0 T0M1 T0M0 The table below summarizes the four modes of operation of timers 0 and 1. The timer operating mode is selected by bits T1M1/T1M0 and T0M1/T0M0 of the TMOD register. T ABLE 25: T IMER/COUNTER MODE DESCRIPTION SUMMARY M1 0 0 1 M0 0 1 0 Mode Mode 0 Mode 1 Mode 2 Function 13-bit Counter 16-bit Counter 8-bit auto-reload Counter/Timer. The reload value is kept in TH0 or TH1, while TL0 or TL1 is incremented every machine cycle. When TLx overflows, the value of THx is copied to TLx. If Timer 1 M1 and M0 bits are set to 1, Timer 1 stops. Timer 0 and Timer 1 Timers 0 and 1 have four modes of operation. These modes allow the user to change the size of the counting register or to authorize an automatic reload when provided with a specific value. Timer 1 can also be used as a baud rate generator to generate communication frequencies for the serial interface. 1 1 Mode 3 ______________________________________________________________________________________________ www.ramtron.com page 18 of 50 VRS51C1100 Timer 0, Timer 1 Counter / Timer Functions Timing Function When Timer 1 or Timer 0 is configured to operate as a timer, its value is automatically incremented at every machine cycle. Once the timer value rolls over, a flag is raised and the counter acquires a value of zero. The overflow flags (TF0 and TF1) are located in the TCON register. The TR0 and TR1 bits of the TCON register gate the corresponding timer operation. In order for the timer to run, the corresponding TRx bit must be set to 1. The IT0 and IT1 bits of the TCON register control the event that will trigger an external interrupt as follows: IT0 = 0: The INT0, if enabled, occurs if a low level is present on P3.2 IT0 = 1: The INT0, if enabled, occurs if a high to low transition is detected on P3.2 IT1 = 0: The INT1, if enabled, occurs if a low level is present on P3.3 IT1 = 1: The INT1, if enabled, occurs if a high to low transition is detected on P3.3 The IE0 and IE1 bits of the TCON register are external flags that indicate whether a transition has been detected on the INT0 and INT1 interrupt pins, respectively. If the external interrupt is configured as edge sensitive, the corresponding IE0 and IE1 flags are automatically cleared when the corresponding interrupt is serviced. If the external interrupt is configured as level sensitive, the corresponding flag must be cleared by the software. T ABLE 26: T IMER 0 AND 1 CONTROL REGISTER (TCON) –SFR 88H 7 TF1 6 TR1 5 TF0 4 TR0 3 IE1 2 IT1 1 IE0 0 IT0 Bit 7 Mnemonic TF1 Description Timer 1 Overflow Flag. Set by hardware on Timer/Counter overflow. Cleared by hardware on Timer/Counter overflow. Cleared by hardware when processor vectors to interrupt routine. Timer 1 Run Control Bit. Set/cleared by software to turn Timer/Counter on or off. Timer 0 Overflow Flag. Set by hardware on Timer/Counter overflow. Cleared by hardware when processor vectors to interrupt routine. Timer 0 Run Control Bit. Set/cleared by software to turn Timer/Counter on or off. Interrupt Edge Flag. Set by hardware when external interrupt edge is detected. Cleared when interrupt processed. Interrupt 1 Type Control Bit. Set/cleared by software to specify falling edge/low level triggered external interrupts. Interrupt 0 Edge Flag. Set by hardware when external interrupt edge is detected. Cleared when interrupt processed. Interrupt 0 Type control bit. Set/cleared by software to specify falling edge/low level triggered external interrupts. 6 TR1 5 TF0 4 3 2 1 0 TR0 IE1 IT1 IE0 IT0 Counting Function When operating as a counter, the timer’s register is incremented at every falling edge of the T0 and T1 signals located at the input of the timer. When the sampling circuit sees a high immediately followed by a low in the next machine cycle, the counter is incremented. Two machine cycles are required to detect and record an event. In order to be properly sampled, the duration of the event presented to the timer input should be greater than 1/24 of the oscillator frequency. Timer 0 / Timer 1 Operating Modes The user may change the operating mode by setting the M1 and M0 bits of the TMOD SFR. ______________________________________________________________________________________________ www.ramtron.com page 19 of 50 VRS51C1100 Mode 0 A schematic representation of this mode of operation is presented in the figure below. In Mode 0, the timer operates as a 13-bit counter made up of 5 LSBs of the TLx register and the 8 upper bits of the THx register. When an overflow causes the value of the register to rollover to 0, the TFx interrupt signal goes to 1. The count value is validated as soon as TRx goes to 1 and the GATE bit is 0, or when INTx is 1. FIGURE 11: T IMER/COUNTER 1 MODE 0: 13-BIT COUNTER FIGURE 12: T IMER/COUNTER 1 MODE 2: 8-BIT AUTOMATIC RELOAD Fosc ÷12 C/T1 / C/T0 = 1 0 C/T1 / C/T0 = 1 TL1 / TL0 7 0 1 T1 / T0 Pin Control Reload 0 TH1 / TH0 7 TR1 / TR0 GATE1 / GATE0 TF1 / TF0 INT1 / INT0 pin INT Fosc ÷12 TL1 / TL0 CLK 1 C/T1 / CT0 =1 Control 0 4 7 0 C/T1 / C/T0 =0 Mode 0 T1/T0 pin Mode 1 TR1/TR0 GATE1 / GATE0 INT1 / INT0 pin 0 TH1 / TH0 7 TF1 / TF0 INT Mode 3 In Mode 3, Timer 1 is blocked as if its control bit, TR1, was set to 0. In this mode, Timer 0’s registers, TL0 and TH0, are configured as two separate 8-bit counters. The TL0 counter uses Timer 0’s control bits (C/T, GATE, TR0, INT0, TF0), and the TH0 counter is held in timer mode (counting machine cycles) and gains control over TR1 and TF1 from Timer 1. At this point, TH0 controls the Timer 1 interrupt. FIGURE 13: T IMER/COUNTER 0 MODE 3 Mode 1 Mode 1 is almost identical to Mode 0, the difference being that in Mode 1, the counter/timer uses the full 16-bits of the timer. Fosc ÷12 TL0 TH0 CLK 0 7 Control TR1 TF1 INTERRUPT Mode 2 0 C/T =0 CLK 0 7 In this Mode, the register of the timer is configured as an 8-bit automatically re-loadable counter/timer. In Mode 2, the lower byte TLx is used as the counter. In the event of a counter overflow, the TFx flag is set to 1 and the value contained in THx, which is preset by software, is reloaded into the TLx counter. The value of THx remains unchanged. 1 T0PIN C/T =1 Control TF0 INTERRUPT TR0 GATE INT0 PIN ______________________________________________________________________________________________ www.ramtron.com page 20 of 50 VRS51C1100 Timer 2 Timer 2 of the VRS51C1100 is a 16-bit timer/counter and is similar to timers 0 and 1 in that it can operate as either an event counter or a timer. This is controlled by the C/T2 bit in the T2CON special function register. Timer 2 has three operating modes: Auto-Load, Capture, and Baud Rate Generator. These modes are selected via the T2CON. The following table describes the T2CON special function register bits. T ABLE 27: T IMER 2 CONTROL REGISTER (T2CON) –SFR C8H 0 CP/RL2 Capture/Reload Select. 1: Capture of Timer 2 value into RCAP2H, RCAP2L is performed if EXEN2=1 and a negative transitions occurs on the T2EX pin. The capture mode requires RCLK and TCLK to be 0. 0: Auto-reload reloads will occur either with Timer 2 overflows or negative transitions at T2EX when EXEN2=1. When either RCK =1 or TCLK =1, this bit is ignored and the timer is forced to auto-reload on Timer 2 overflow. 7 TF2 6 EXF2 5 RCLK 4 TCLK 3 EXEN2 2 TR2 1 C/T2 0 CP/RL2 The Timer 2 mode selection bits and their functions are described in the following table: T ABLE 28: T IMER 2 MODE SELECTION BITS Bit Mnemonic 7 TF2 6 EXF2 5 RCLK Description Timer 2 Overflow Flag: Set by an overflow of Timer 2 and must be cleared by software. TF2 will not be set when either RCLK =1 or TCLK =1. Timer 2 external flag change in state occurs when either a capture or reload is caused by a negative transition on T2EX and EXEN2=1. When Timer 2 is enabled, EXF=1 will cause the CPU to Vector to the Timer 2 interrupt routine. Note that EXF2 must be cleared by software. Serial Port Receive Clock Source. 1: Causes Serial Port to use Timer 2 overflow pulses for its receive clock in Modes 1 and 3. 0: Causes Timer 1 overflow to be used for the Serial Port receive clock. Serial Port Transmit Clock. 1: Causes Serial Port to use Timer 2 overflow pulses for its transmit clock in Modes 1 and 3. 0: Causes Timer 1 overflow to be used for the Serial Port transmit clock. Timer 2 External Mode Enable. 1: Allows a capture or reload to occur as a result of a negative transition on T2EX if Timer 2 is not being used to clock the Serial Port. 0: Causes Timer 2 to ignore events at T2EX. Start/Stop Control for Timer 2. 1: Start Timer 2 0: Stop Timer 2 Timer or Counter Select (Timer 2) 1: External event counter falling edge triggered. 0: Internal Timer (OSC/12) RCLK + TCLK 0 0 1 X CP/RL2 0 1 X X TR2 1 1 1 0 MODE 16-bit Auto-Reload Mode 16-bit Capture Mode Baud Rate Generator Mode Timer 2 stops The details of each mode are described in the following sections. Timer 2 Capture Mode In capture mode, the EXEN2 bit of the T2CON register controls whether an external transition on the T2EX pin will trigger the capture of the timer value. When EXEN2 = 0, the Timer 2 acts as a 16-bit timer/counter, which, upon overflowing, will set the TF2 bit (Timer 2 overflow bit). This overflow can be used to generate an interrupt. FIGURE 14: T IMER 2 IN CAPTURE MODE FOSC ÷12 4 TCLK 3 EXEN2 0 C/T2 1 T2 pin TIMER 0 COUNTER TL2 7 0 TH2 7 2 1 TR2 0 TR2 RCAP2L 7 0 RCAP2H 7 TF2 T2EX pin EXF2 C/T2 EXEN2 Timer 2 Interrupt When EXEN2 = 1, the above still applies, however, in addition, it is possible to allow a 1 to 0 transition at the T2EX input to cause the current value stored in the Timer 2 registers (TL2 and TH2) to be captured into ______________________________________________________________________________________________ www.ramtron.com page 21 of 50 VRS51C1100 the RCAP2L and RCAP2H registers. Furthermore, the transition at T2EX causes bit EXF2 in T2CON to be set, and EXF2, like TF2, can generate an interrupt. Note that both EXF2 and TF2 share the same interrupt vector. Timer 2 Baud Rate Generator Mode Timer 2 can be used for UART Baud Rate generation. This mode is activated when RCLK is set to 1 and/or TCLK is set to 1. This mode is described further in the serial port section. FIGURE 16: T IMER 2 IN AUTOMATIC BAUD GENERATOR MODE Timer 2 Auto-Reload Mode In this mode, there are also two options controlled by the EXEN2 bit in the T2CON register. FOSC ÷2 If EXEN2 = 0, when Timer 2 rolls over, it not only sets TF2, but also causes the Timer 2 registers to be reloaded with the 16-bit value in the RCAP2L and RCAP2H registers previously initialised. In this mode, Timer 2 can be used as a baud rate generator source for the serial port. If EXEN2=1, then Timer 2 still performs the above operation, but a 1 to 0 transition at the external T2EX input will also trigger an anticipated reload of Timer 2 with the value stored in RCAP2L, RCAP2H and set EXF2. FIGURE 15: T IMER 2 IN AUTO-RELOAD MODE 0 C/T2 1 T2 pin TIMER 0 COUNTER TL2 7 0 TH2 7 0 TR2 RCAP2L 1 0 0 7 0 RCAP2H 7 ÷16 TCLK 1 0 TX Clock RX Clock ÷16 Timer 1 Overflow ÷2 1 RCLK SMOD T2EX pin EXF2 Timer 2 Interrupt Request EXEN2 UART Serial Port The serial port on the VRS51C1100 can operate in full duplex (it can transmit and receive data simultaneously.) This occurs at the same speed if one timer is assigned as the clock source for both transmission and reception, and at different speeds if transmission and reception are each controlled by their own timer. TF2 FOSC ÷12 0 C/T2 1 T2 pin TIMER 0 COUNTER TL2 7 0 TH2 7 0 TR2 RCAP2L 7 0 RCAP2H 7 T2EX pin EXF2 EXEN2 Timer 2 Interrupt The VRS51C1100 serial port includes a double buffer for the receiver, which allows reception of a byte even if the previously received byte has not been retrieved from the receive register by the processor. However, if the first byte still has not been read by the time reception of the second byte is complete, the byte present in the receive buffer will be lost. The SBUF register provides access to the transmit and receive registers of the serial port. Reading from the SBUF register will access the receive register, while a write to the SBUF loads the transmit register. ______________________________________________________________________________________________ www.ramtron.com page 22 of 50 VRS51C1100 Serial Port Control Register The SCON (serial port control) register contains control and status information, and includes the 9th data bit for transmit/receive (TB8/RB8 if required), mode selection bits and serial port interrupt bits (TI and RI). T ABLE 29: SERIAL PORT CONTROL REGISTER (SCON) – SFR 98H T ABLE 30: SERIAL PORT MODES OF OPERATION S M0 SM1 Mode Description Baud Rate 0 0 1 1 0 1 0 1 0 1 2 3 Shift Register 8-bit UART 9-bit UART 9-bit UART Fosc/12 Variable Fosc/64 or Fosc/32 Variable UART Operating Modes 1 TI 7 SM0 6 SM1 5 SM2 4 REN 3 TB8 2 RB8 0 RI Bit 7 6 Mnemonic SM0 SM1 5 SM2 Description Bit to select mode of operation (see table below) Bit to select mode of operation (see table below) Multiprocessor communication is possible in Modes 2 and 3. In Modes 2 or 3 if SM2 is set to 1, RI will th not be activated if the received 9 data bit (RB8) is 0. In Mode 1, if SM2 = 1 then RI will not be activated if a valid stop bit was not received. Serial Reception Enable Bit This bit must be set by software and cleared by software. 1: Serial reception enabled 0: Serial reception disabled th 9 data bit transmitted in Modes 2 and 3 This bit must be set by software and cleared by software. th 9 data bit received in modes 2 and 3. In Mode 1, if SM2 = 0, RB8 is the stop bit that was received. In Mode 0, this bit is not used. This bit must be cleared by software. Transmission Interrupt flag. The VRS51C1100’s serial port can operate in four different modes. In all four modes, a transmission is initiated by an instruction that uses the SBUF register as a destination register. In Mode 0, reception is initiated by setting RI to 0 and REN to 1. An incoming start bit initiates reception in the other modes, provided that REN is set to 1. The following paragraphs describe these four modes. UART Operation in Mode 0 In this mode, the serial data exits and enters through the RXD pin. TXD is used to output the shift clock. The signal is composed of 8 data bits starting with the LSB. The baud rate in this mode is 1/12 the oscillator frequency. FIGURE 17: SERIAL PORT MODE 0 BLOCK DIAGRAM Internal Bus 1 Write to SBUF 4 REN 3 2 TB8 RB8 S D CLK Q SBUF Shift ZERO DETECTOR RXD P3.0 Shift Clock Shift TXD P3.1 1 TI Start TX Control Unit Fosc/12 TX Clock TI Send 0 RI Automatically set to 1 when: th • The 8 bit has been sent in Mode 0. • Automatically set to 1 when the stop bit has been sent in the other modes. This bit must be cleared by software. Reception Interrupt flag Automatically set to 1 when: th • The 8 bit has been received in Mode 0. • Automatically set to 1 when the stop bit has been sent in the other modes (see SM2 exception). This bit must be cleared by software. Serial Port Interrupt RX Clock RI REN RI RX Control Unit Start Shift 1 1 1 1 1 1 1 0 Receive RXD P3.0 Input Function Shift Register RXD P3.0 SBUF READ SBUF Internal Bus ______________________________________________________________________________________________ www.ramtron.com page 23 of 50 VRS51C1100 UART Transmission in Mode 0 Any instruction that uses SBUF as a destination register may initiate a transmission. The “write to SBUF” signal also loads a 1 into the 9th position of the transmit shift register and informs the TX control block to begin a transmission. The internal timing is such that one full machine cycle will elapse between a write to SBUF instruction and the activation of SEND. The SEND signal enables the output of the shift register to the alternate output function line of P3.0 and enables SHIFT CLOCK to the alternate output function line of P3.1. At every machine cycle in which SEND is active, the contents of the transmit shift register are shifted to the right by one position. Zeros come in from the left as data bits shift out to the right. The TX control block sends its final shift and deactivates SEND while setting T1 after one condition is fulfilled: When the MSB of the data byte is at the output position of the shift register; the 1 that was initially loaded into the 9th position is just to the left of the MSB; and all positions to the left of that contain zeros. Once these conditions are met, the deactivation of SEND and the setting of T1 occur at T1 of the 10th machine cycle after the “write to SBUF” pulse. UART Reception in Mode 0 When REN and R1 are set to 1 and 0, respectively, reception is initiated. The bits 11111110 are written to the receive shift register at the end of the next machine cycle by the RX control unit. In the following phase, the RX control unit will activate RECEIVE. The contents of the receive shift register are shifted one position to the left at the end of every machine cycle during which RECEIVE is active. The value that comes in from the right is the value that was sampled at the P3.0 pin. 1’s are shifted out to the left as data bits are shifted in from the right. The RX control block is flagged to do one last shift and load the SBUF when the 0 that was initially loaded into the rightmost position arrives at the leftmost position in the shift register. UART Operation in Mode 1 In a Mode 1 operation, 10 bits are transmitted (through TXD) or received (through RXD). The transactions are composed of: a Start bit (Low); 8 data bits (LSB first) and a Stop bit (high). The reception is completed once the Stop bit sets the RB8 flag in the SCON register. Either Timer 1 or Timer 2 controls the baud rate in this mode. The following diagram demonstrates the serial port structure when configured in Mode 1. FIGURE 18: SERIAL PORT MODE 1 AND 3 BLOCK DIAGRAM Internal Bus 1 Write to SBUF Timer 1 Overflow S D CLK Timer 2 Overflow Q SBUF TXD ÷2 01 SMOD ZERO DETECTOR 0 1 TCLK ÷16 Start Shift TX Control Unit Data TX Clock TI Send 0 RCLK 1 ÷16 Serial Port Interrupt RX Clock 1-0 Transition Detector Start RI RX Control Unit Load SBUF SHIFT RXD Bit Detector LOAD SBUF 9-Bit Shift Register Shift SBUF READ SBUF Internal Bus ______________________________________________________________________________________________ www.ramtron.com page 24 of 50 VRS51C1100 UART Transmission in Mode 1 Transmission in this mode is initiated by any instruction that makes use of SBUF as a destination register. The 9th bit position of the transmit shift register is loaded by the “write to SBUF” signal. This event also flags/informs the TX control unit that a transmission has been requested. It is after the next rollover in the divide-by-16 counter when transmission actually begins. It follows that the bit times are synchronized to the divide-by-16 counter and not to the “write to SBUF” signal. When a transmission begins, it places the Start bit at TXD. Data transmission is activated one bit time later. This activation enables the output bit of the transmit shift register to TXD. One bit time after that, the first shift pulse occurs. In this mode, zeros are clocked in from the left as data bits are shifted out to the right. When the most significant bit of the data byte is at the output position of the shift register, the 1 that was initially loaded into the 9th position is to the immediate left of the MSB and all positions to the left of that contain zeros. This condition flags the TX control unit to shift one more time. UART Reception in Mode 1 A one to zero transition at pin RXD will initiate reception. It is for this reason that RXD is sampled at a rate of 16 multiplied by the baud rate that has been established. When a transition is detected, 1FFh is written into the input shift register and the divide-by-16 counter is immediately reset. The divide-by-16 counter is reset in order to align its rollovers with the boundaries of the incoming bit times. In total, there are 16 states in the counter. During the 7th, 8th and 9th counter states of each bit time, the bit detector samples the value of RXD. The accepted value is the one seen in at least two of the three samples. The purpose of doing this is for noise rejection. If the value accepted during the first bit time is not zero, the receive circuits are reset and the unit goes back to searching for another one to zero transition. All false start bits are rejected by doing this. If the start bit is valid, it is shifted into the input shift register, and the reception of the rest of the frame will proceed. For a receive operation, the data bits come in from the right as 1’s shift out on the left. As soon as the start bit arrives at the leftmost position in the shift register, (9bit register), it tells the UART’s receive controller block to perform one last shift operation: to set RI and to load SBUF and RB8. The signal to load SBUF and RB8, and to set RI will be generated if, and only if, the following conditions are met at the time the final shift pulse is generated: o o Either SM2 = 0 or the received stop bit = 1 RI = 0 If both conditions are met, the stop bit goes into RB8, the 8 data bits go into SBUF and RI is activated. If one of these conditions is not met, the received frame is completely lost. At this time, whether the above conditions are met or not, the unit returns to searching for a one to zero transition in RXD. UART Operation in Mode 2 In Mode 2 a total of 11 bits are transmitted (through TXD) or received (through RXD). The transactions are composed of: a Start bit (low), 8 data bits (LSB first), a programmable 9th data bit and a Stop bit (high). For transmission, the 9th data bit comes from the TB8 bit of SCON. For example, the parity bit P in the PSW could be moved into TB8. In the case of receive, the 9th data bit is automatically written into RB8 of the SCON register. ______________________________________________________________________________________________ www.ramtron.com page 25 of 50 VRS51C1100 In Mode 2, the baud rate is programmable to either 1/32 or 1/64 the oscillator frequency. FIGURE 19: SERIAL PORT MODE 2 BLOCK DIAGRAM Internal Bus 1 Write to SBUF UART Operation in Mode 3 In Mode 3, 11 bits are transmitted (through TXD) or received (through RXD). The transactions are composed of: a Start bit (low), 8 data bits (LSB first), a programmable 9th data bit and a Stop bit (high). Mode 3 is identical to Mode 2 in all respects but one, the baud rate. Either Timer 1 or Timer 2 generates the baud rate in Mode 3. FIGURE 20: SERIAL PORT MODE 3 BLOCK DIAGRAM Fosc/2 S D CLK Q SBUF TXD ÷2 01 SMOD ÷16 Stop Start TX Clock ZERO DETECTOR Shift TX Control Unit TI Data Internal Bus 1 Send Write to SBUF ÷16 Serial Port Interrupt RX Clock Control RI RX Control Unit Load SBUF SHIFT Timer 1 Overflow S D CLK Timer 2 Overflow Q SBUF Sample 1-0 Transition Detector Start TXD ÷2 01 SMOD ZERO DETECTOR 0 1 TCLK ÷16 Start Shift TX Control Unit Data RXD Bit Detector LOAD SBUF 9-Bit Shift Register Shift 0 RCLK 1 TX Clock TI Send ÷16 Serial Port Interrupt RI RX Control Unit Load SBUF SHIFT SBUF READ SBUF SAMPLE 1-0 Transition Detector RX Clock Start Internal Bus RXD Bit Detector LOAD SBUF 9-Bit Shift Register Shift SBUF READ SBUF Internal Bus ______________________________________________________________________________________________ www.ramtron.com page 26 of 50 VRS51C1100 UART in Mode 2 and 3: Additional Information As mentioned previously, for an operation in modes 2 and 3, 11 bits are transmitted (through TXD) or received (through RXD). The signal is comprised of: a logical low Start bit, 8 data bits (LSB first), a programmable 9th data bit and a logical high Stop bit. On transmit, (TB8 in SCON) can be assigned the value of 0 or 1. On receive, the 9th data bit goes into RB8 in SCON. The baud rate is programmable to either 1/32 or 1/64 the oscillator frequency in Mode 2. Mode 3 may have a variable baud rate generated from either Timer 1 or Timer 2 depending on the states of TCLK and RCLK. UART Transmission in Mode 2 and Mode 3 The transmission is initiated by any instruction that makes use of SBUF as the destination register. The 9th bit position of the transmit shift register is loaded by the “write to SBUF” signal. This event also informs the UART transmission control unit that a transmission has been requested. After the next rollover in the divide-by16 counter, a transmission actually starts at the beginning of the machine cycle. It follows that the bit times are synchronized to the divide-by-16 counter and not to the “write to SBUF” signal, as in the previous mode. Transmissions begin when the SEND signal is activated, which places the Start bit on the TXD pin. Data is activated one bit time later. This activation enables the output bit of the transmit shift register to the TXD pin. The first shift pulse occurs one bit time after that. The first shift clocks a Stop bit (1) into the 9 bit position of the shift register on TXD. Thereafter, only zeros are clocked in. Thus, as data bits shift out to the right, zeros are clocked in from the left. When TB8 is at the output position of the shift register, the stop bit is just to the left of TB8, and all positions to the left of that contain zeros. This condition signals to the TX control unit to shift one more time and set TI, while th deactivating SEND. This occurs at the 11 divide-by16 rollover after “write to SBUF”. th UART Reception in Mode 2 and Mode 3 One to zero transitions on the RXD pin initiate reception. For this reason the RXD is sampled at a rate of 16 multiplied by the established baud rate..When a transition is detected, the 1FFh is written into the input shift register and the divide-by-16 counter is immediately reset. During the 7th, 8th and 9th counter states of each bit time, the bit detector samples the value of RXD. The accepted value is the one seen in at least two of the three samples. If the value accepted during the first bit time is not zero, the receive circuits are reset and the unit goes back to searching for another one to zero transition. If the Start bit is valid, it is shifted into the input shift register, and the reception of the rest of the frame will proceed. For a receive operation, the data bits come in from the right as 1’s shift out on the left. As soon as the Start bit arrives at the leftmost position in the shift register (9-bit register), it informs the RX control block to do one more shift, to set RI and to load SBUF and RB8. The signal to set RI and to load SBUF and RB8 will be generated if, and only if, the following conditions are satisfied when the final shift pulse is generated: Either SM2 = 0 or the received 9th bit equal 1 RI = 0 If both conditions are met, the 9th data bit received goes into RB8, and the first 8 data bits go into SBUF. If one of these conditions is not met, the received frame is completely lost. One bit time later, whether the above conditions are met or not, the unit goes back to searching for a one to zero transition at the RXD input. Please note that the value of the received Stop bit is unrelated to SBUF, RB8 or RI. ______________________________________________________________________________________________ www.ramtron.com page 27 of 50 VRS51C1100 The value to write into the TH1 register is defined by the following formula: UART Baud Rates In Mode 0, the baud rate is fixed and can be represented by the following formula: TH1 = 256 - 2SMODx Fosc 32 x 12x (Baud Rate) Mode 0 Baud Rate = Oscillator Frequency 12 Generating UART Baud Rates with Timer 2 Timer 2 is often preferred to generate the baud rate, as it can be easily configured to operate as a 16-bit timer with auto-reload. This enables far better resolution than using Timer 1 in 8-bit auto-reload mode. The baud rate using Timer 2 is defined as: In Mode 2, the baud rate depends on the value of the SMOD bit in the PCON SFR. From the formula below, we can see that if SMOD = 0 (which is the value on reset), the baud rate is 1/32 the oscillator frequency. Mode 2 Baud Rate = 2SMOD x (Oscillator Frequency) 64 Mode 1,3 Baud Rate = Timer 2 Overflow Rate 16 The Timer 1 and/or Timer 2 overflow rate determines the baud rates in Modes 1 and 3. Generating UART Baud Rate with Timer 1 When Timer 1 functions as a baud rate generator, the baud rate in modes 1 and 3 is determined by the Timer 1 overflow rate. The timer can be configured as either a timer or a counter in any of its three running modes. In typical applications, it is configured as a timer (C/T2 is set to 0). To make Timer 2 operate as a baud rate generator, the TCLK and RCLK bits of the T2CON register must be set to 1. The baud rate generator mode is similar to the autoreload mode in that an overflow in TH2 causes the Timer 2 registers to be reloaded with the 16-bit value in registers RCAP2H and RCAP2L, which are preset by the software. However, when Timer 2 is configured as a baud rate generator, its clock source is Osc/2. Mode 1,3 Baud Rate = 2SMODx Timer 1 Overflow Rate 32 Timer 1 must be configured as an 8-bit timer (TL1) in auto-reload mode with a TH1 value when an overflow occurs (Mode 2). In this application, the Timer 1 interrupt should be disabled. The two following formulas can be used to calculate the baud rate and the reload value written into the TH1 register. Mode 1,3 Baud Rate = 2SMODx Fosc 32 x 12(256 – TH1) ______________________________________________________________________________________________ www.ramtron.com page 28 of 50 VRS51C1100 The following formula can be used to calculate the baud rate in modes 1 and 3 using Timer 2: Modes 1, 3 Baud Rate = Oscillator Frequency 32x[65536 – (RCAP2H, RCAP2L)] The formula below is used to define the reload value written into the RCAP2h, RCAP2L registers to achieve a given baud rate. (RCAP2H, RCAP2L) = 65536 - Fosc 32x[Baud Rate] In the above formula, RCAP2H and RCAP2L are the contents of RCAP2H and RCAP2L taken as a 16-bit unsigned integer. Note that a rollover in TH2 does not set TF2 and will not generate an interrupt. As such, the Timer 2 interrupt does not have to be disabled when Timer 2 is configured in baud rate generator mode. Furthermore, when Timer 2 is configured as a UART baud rate generator and is running (TR2 is set to 1), the user should not try to perform read or write operations to the TH2/TL2, RCAP2H and RCAP2L registers. ______________________________________________________________________________________________ www.ramtron.com page 29 of 50 VRS51C1100 Timer 1 Reload Value in Modes 1 & 3 for UART Baud Rate The following table provides examples of the Timer 1, 8-bit reload value when used as a UART baud rate generator and the SMOD bit of the PCON register is set to 1: 22.184MHz FFh Feh FDh FAh F4h D0h A0h 16.000MHz DDh BBh 14.745MHz FEh FCh F8h E0h C0h 00h 12.000MHz FEh E6h CCh 30h 11.059MHz FFh FDh FAh E8h D0h 40h 8.000MHz DDh 75h 3.57MHz C2h 115200bps 57600bps 38400bps 31250bps 19200bps 9600bps 2400bps 1200bps 300bps Timer 2 Reload Value in Modes 1 & 3 for UART Baud Rate The following are examples of [RCAP2H, RCAP2L] reload values for Timer 2 when it is used as a baud rate generator for the VRS51C1100 UART: 22.184MHz FFFDh FFFAh FFF4h FFEEh FFEAh FFDCh FFB8h FEE0h FDC0h F700h 16.000MHz FFF3h FFF0h FFE6h FFCCh FF30h FE5Fh F97Dh 14.745MHz FFFEh FFFCh FFF8h FFF4h FFF1h FFE8h FFD0h FF40h FE80h FA00h 12.000MHz FFF4h FFD9h FF64h FEC7h FB1Eh 11.059MHz FFFDh FFFAh FFF7h FFF5h FFEEh FFDCh FF70h FEE0h FB80h 8.000MHz FFF8h FFF3h FFE6h FF98h FF30h FCBEh 3.57MHz FFD1h FFA3h FE8Bh 230400bps 115200bps 57600bps 38400bps 31250bps 19200bps 9600bps 2400bps 1200bps 300bps UART initialization in Mode 3 using Timer 1 ;*** INTIALIZE THE UART @ 9600BPS, Fosc=11.0592MHz INISER0T1I: MOV A,T2CON ANL A,#11001111B MOV T2CON,A MOV PCON,#80H MOV TL1,#0FAH MOV TH1,#0FAH ;RETRIEVE CURRENT VALUE OF T2CON ;RCLK & TCLK BIT = 0 -> TO USE TIMER1 ;BAUD RATE GENERATOR SOURCE FOR UART ;SET THE SMOD BIT TO 1 ;CONFIG TIMER1 AT 8BIT WITH AUTO-RELOAD ;CALCULATE THE TIMER 1 RELOAD VALUE ;TH1 = [(2^SMOD) * Fosc] / (32 * 12 * Fcomm) ;TH1 FOR 9600BPS @ 11.059MHz = FAh MOV SCON,#05Ah ;CONFIG SCON_0 MODE_1 MOV TMOD,#00100000B ;CONFIG TIMER 1 IN MODE 2, 8BIT ; + AUTO RELOAD MOV TCON,#01000000B ;START TIMER1 UART initialization in Mode 3, using Timer 2 ;*** INTIALIZE THE UART @57600BPS, Fosc=11.0592MHz INISER0T2I: MOV SCON,#05Ah ;CONFIG SCON_0 MODE_1, ;CALCULATE RELOAD VALUE WITH T2 ;RCAP2H,RCAP2L = 65536 - [ Fosc / (32*Fcomm)] ;RELOAD VALUE 57600bps, 11.059MHz =FFFAh ; ;SERIAL PORT0, TIMER2 RELOAD START MOV MOV RCAP2H,#0FFh RCAP2L,#0DCh MOV T2CON,#034h CLR CLR SCON.0 SCON.1 ;CLEAR UART RX, TX FLAGS CLR CLR MOV SCON.0 SCON.1 SBUF,#DATA ;CLEAR UART RX, TX FLAGS MOV SBUF,#DATA ;SEND ONE BYTE ON THE SERIAL PORT ;SEND ONE BYTE ON THE SERIAL PORT ______________________________________________________________________________________________ www.ramtron.com page 30 of 50 VRS51C1100 Interrupts The VRS51C1100 has 8 interrupt sources (9 if the WDT is included) and 7 interrupt vectors (including reset) used for handling. The interrupts are enabled via the IE register shown below: T ABLE 31: IE INTERRUPT ENABLE REGISTER –SFR A8H Interrupt Vectors The table below specifies each interrupt source, its flag and its vector address. T ABLE 32: INTERRUPT VECTOR ADDRESS Interrupt Source RESET (+ WDT) INT0 Timer 0 INT1 Timer 1 Serial Port Timer 2 Flag WDR IE0 TF0 IE1 TF1 RI+TI TF2+EXF2 7 EA 6 - 5 ET2 4 ES 3 ET1 2 EX1 1 ET0 0 EX0 Bit 7 Mnemonic EA Description Disables All Interrupts 0: no interrupt acknowledgment 1: Each interrupt source is individually enabled or disabled by setting or clearing its enable bit. Reserved Timer 2 Interrupt Enable Bit Serial Port Interrupt Enable Bit Timer 1 Interrupt Enable Bit External Interrupt 1 Enable Bit Timer 0 Interrupt Enable Bit External Interrupt 0 Enable Bit Vector Address 0000h* 0003h 000Bh 0013h 001Bh 0023h 002Bh *If location 0000h = FFh, the PC jump to the ISP program. 6 - 5 4 3 2 1 0 ET2 ES ET1 EX1 ET0 EX0 External Interrupts The VRS51C1100 has two external interrupt inputs (INT0 and INT1). These interrupt lines are shared with the P3.2 and P3.3 I/Os. Bits IT0 and IT1 of the TCON register determine whether the external interrupts are level or edge sensitive. If ITx = 1, the interrupt will be raised when a 1-> 0 transition occurs at the interrupt pin. The duration of the transition must be at least equal to 12 oscillator cycles. The following figure illustrates the various interrupt sources on the VRS51C1100. FIGURE 21: INTERRUPT SOURCES INT0 IT0 IE0 If ITx = 0, the interrupt will occur when a logic low condition is present on the interrupt pin. TF0 INT1 IT1 IE1 INTERRUPT SOURCES The state of the external interrupt, when enabled, can be monitored using the flags, IE0 and IE1 of the TCON register and will be set when the interrupt condition occurs. In the case where the interrupt was configured as edge sensitive, the associated flag is automatically cleared when the interrupt is serviced. If the interrupt is configured as level sensitive, the interrupt flag must be cleared by the software. TF1 T1 RI TF2 EXF2 ______________________________________________________________________________________________ www.ramtron.com page 31 of 50 VRS51C1100 Timer 0 and Timer 1 Interrupt Both Timer 0 and Timer 1 can be configured to generate an interrupt when a rollover of the timer/counter occurs (except Timer 0 in Mode 3). The TF0 and TF1 flags serve to monitor timer overflow occurring in Timer 0 and Timer 1. These interrupt flags are automatically cleared when the interrupt is serviced. Execution of an Interrupt When the processor receives an interrupt request, an automatic jump to the desired subroutine occurs. This jump is similar to executing a branch to a subroutine instruction: the processor automatically saves the address of the next instruction on the stack. An internal flag is set to indicate that an interrupt is taking place, and then the jump instruction is executed. An interrupt subroutine must always end with the RETI instruction. This instruction allows users to retrieve the return address placed on the stack. The RETI instruction also allows updating of the internal flag that will take into account an interrupt with the same priority. Timer 2 interrupt A Timer 2 interrupt can occur if TF2 and/or EXF2 flags are set to 1 and if the Timer 2 interrupt is enabled. The TF2 flag is set when a rollover of the Timer 2 Counter/Timer occurs. The EXF2 flag can be set by a 1 to 0 transition on the T2EX pin by the software. Note that neither flag is cleared by the hardware upon execution of the interrupt service routine. The service routine may have to determine whether it was TF2 or EXF2 that generated the interrupt. These flag bits will have to be cleared by the software. Every bit that generates interrupts can either be cleared or set by the software, yielding the same result as when the operation is done by the hardware. In other words, pending interrupts can be cancelled and interrupts can be generated by the software. Interrupt Enable and Interrupt Priority When the VRS51C1100 is initialized, all interrupt sources are inhibited by the bits of the IE register being reset to 0. It is necessary to start by enabling the interrupt sources that the application requires.This is achieved by setting bits in the IE register, as discussed previously. This register is part of the bit addressable internal RAM. For this reason, it is possible to modify each bit individually in one instruction without having to modify the other bits of the register. All interrupts can be inhibited by setting EA to 0. The order in which interrupts are serviced is shown in the following table: T ABLE 33: INTERRUPT PRIORITY Serial Port Interrupt The serial port can generate an interrupt upon byte reception or once the byte transmission is completed. These two conditions share the same interrupt vector and it is up to the user-developed interrupt service routine software to determine the cause of the interrupt by examining serial interrupt flags RI and TI. Note that neither of these flags is cleared by the hardware upon execution of the interrupt service routine. The software must clear these flags. Interrupt Source RESET + WDT (Highest Priority) IE0 TF0 IE1 TF1 RI+TI TF2+EXF2 (Lowest Priority) ______________________________________________________________________________________________ www.ramtron.com page 32 of 50 VRS51C1100 Modifying the Order of Priority The VRS51C1100 allows the user to modify the natural priority of the interrupts. The order can be modified by programming the bits in the IP (Interrupt Priority) register. When any bit in this register is set to 1, it gives the corresponding source priority over interrupts coming from sources that don’t have their corresponding IP bits set to 1. The IP register is represented in the table below. T ABLE 34: IP INTERRUPT PRIORITY REGISTER –SFR B8H T ABLE 35: WATCH DOG T IMER KEY REGISTER: WDTKEY – SFR 97H 7 6 5 4 3 WDTKEY7:0 Description Watch Dog Key 2 1 0 Bit 7:0 Mnemonic WDTKEY The WDTCTRL register is, by default, configured as a read-only register. To modify its contents, two consecutive write operations to the WDTKEY register must be performed: MOV MOV WDTKEY,#01Eh WDTKEY,#0E1h 7 EA 6 - 5 ET2 4 ES 3 ET1 2 EX1 1 ET0 0 EX0 Bit 7 6 Mnemonic - Description 5 4 3 2 1 0 PT2 PS PT1 PX1 PT0 PX0 Gives Timer 2 Interrupt Higher Priority Gives Serial Port Interrupt Higher Priority Gives Timer 1 Interrupt Higher Priority Gives INT1 Interrupt Higher Priority Gives Timer 0 Interrupt Higher Priority Gives INT0 Interrupt Higher Priority Once the configuration or WDT reset operation is complete, the WDTCTRL register can be restored to read-only by writing the following sequence into the WDTKEY register: MOV MOV WDTKEY,#0E1h WDTKEY,#01Eh Once the WDT operation is activated, the user software must clear it periodically. If the WDT is not cleared, its overflow will trigger a reset of the VRS51C1100. T ABLE 36: WATCH DOG T IMER CONTROL (WDTCTRL) – SFR 9FH The Watchdog Timer The VRS51C1100 watchdog timer (WDT) is a 16-bit free-running counter operating from an independent 250KHz internal RC oscillator. The overflow of the watchdog timer counter will reset the processor. The WDT is a useful safety measure for systems that are susceptible to noise, power glitches and other conditions that can cause the software to go into infinite dead loops or runaways; The WDT provides a recovery mechanism from abnormal software conditions. 7 WDTE Bit 7 6 Unused Mnemonic WDTE 5 WDT CLR 4 3 Unused 2 WDT PS2 1 WDT PS1 0 WDT PS0 Watchdog Timer Registers The configuration and use of the VRS51C1100 watchdog timer is handled by three registers: WDTKEY, WDTCTRL and SYSCON. The WDTKEY register ensures that the watchdog timer is not inadvertently reset in case of program malfunction. 6 5 [4:3] 2 1 0 Unused WDTCLR Unused WDTPS2 WDTPS1 WDTPS0 Description Watchdog Timer Enable Bit 0: Watchdog Timer is disabled 1: Watchdog Timer is enabled Watchdog Timer Counter Clear Bit Clock Source Divider Bit 2 Clock Source Divider Bit 1 Clock Source Divider Bit 0 The WDT timeout delay can be adjusted by configuring the clock divider input on the WDT’s time base source clock. To select the divider value, the [WDTPS2~WDTPS0] bits of the WDT control register should be set accordingly. The following table provides the approximate timeout periods associated with different values of the WDTPSx bits of the watchdog timer register. ______________________________________________________________________________________________ www.ramtron.com page 33 of 50 VRS51C1100 T ABLE 37: WDT T IMEOUT PERIOD AT WDT Initialization Example WDT Period WDTPS [2:0] 000 001 010 011 100 101 110 111 2.05ms 4.10ms 8.19ms 16.38ms 32.77ms 65.54ms 131.07ms 262.14ms The following program example demonstrates the watchdog timer initialization sequence and the routine to periodically clear it. ;*** VARIABLE DEFINITION *** CPTR PORTVAL EQU EQU 020H 00H ;*** PROGRAM START HERE **** ORG 0000h LJMP START ;*** MAIN PROGRAM START *** ORG 0100h ;*** CHECK IF RESET WAS CAUSED BY THE WATCHDOG TIMER START: MOV A,SYSCON ANL A,#80H JNZ WDTRESET ;WDT BIT SET -> WE GOT A WDT RESET INITWDT: MOV MOV WDTKEY,#01EH WDTKEY,#0E1H ;UNLOCK THE WDTCTRL REG ACCESS IN ;WRITING MODE To enable the WDT, the user must set bit 7 (WDTE) of the WDTCTRL register to 1. The 16-bit counter will start to count using the internal 250kHz oscillator as a clock source, divided according to the value of the WDTPS2~WDTPS0 bits. To clear the WDT, set the WDTCLR bit of the WDTCTRL to 1. This action will clear the contents of the 16-bit counter and force it to restart. If the watchdog timer overflows, it will reset the processor, the WDR bit (7) of SYSCON register will be set to 1 and the WDTE bit will be cleared to 0. The user should check the WDR bit if an unexpected reset has taken place. If the WDR bit is set, the processor reset was caused by the watchdog timer. MOV WDTCTRL,#10000010B ;CONFIG THE WATCHDOG TIMER ;BIT 7 - WDTEN=1 WATCHDOG TIMER ENABLE ;BIT 6 - UNUSED ;BIT 5 - WDTCLR=1 WATCHDOG CLEAR ;BIT 4:3 - UNUSED ;BIT 2:0 - WDTCLK=010 - WDT TIMEOUT = 8mS MOV MOV MOV WDTKEY,#0E1H WDTKEY,#01EH PORTVAL,#00H ;LOCK THE WDTCTRL ACCESS IN WRITING ;INIT PORT VALUE TO 00H WDTRESET: NOP MOV CPL MOV MOV A,PORTVAL A PORTVAL,A P1,A ;IF THE WDT CAUSE THE RESET INIT PORTVAL ;TOGGLE P1 VALUE ;*** SEQUENCE TO CLEAR THE WATCHDOG TIMER (SAME AS CONFIG) LOOP: ;MOV WDTKEY,#01EH ;UNLOCK THE WDTCTRL REG ACCESS IN ;WRITING MODE ;MOV WDTKEY,#0E1H ;MOV WDTCTRL,#10100010B ;CONFIG THE WDT TIMER ;BIT 7 - WDTEN=1 WDT ENABLE ;BIT 6 - UNUSED ;BIT 5 - WDTCLR=1 WDT CLEAR ;BIT 4:3 - UNUSED ;BIT 2:0 - WDTCLK=010 - WDT TIMEOUT = 8mS ;MOV ;MOV (…) LJMP LOOP WDTKEY,#0E1H ;LOCK THE WDTCTRL ACCESS IN WRITING WDTKEY,#01EH ______________________________________________________________________________________________ www.ramtron.com page 34 of 50 VRS51C1100 Pulse Width Modulation (PWM) The Pulse Width Modulation (PWM) module consists of four outputs. Each output uses an 8-bit PWM data register (PWMD) to set the number of continuous pulses within a PWM frame cycle. PWM Output Enable Register T ABLE 38: PWM O UTPUT ENABLE REGISTER (PWME) – SFR 9BH 7 -3 PWM1E Bit 7:6 5 4 3 2 1:0 Mnemonic PWM3E PWM2E PWM1E PWM0E - 6 5 PWM3E 1 - 4 PWM2E 0 2 PWM0E Description PWM Function Description: Each 8-bit PWM output incorporates an 8-bit register that consists of a 5-bit PWM (5 MSBs) and a 3-bit (LSBs) narrow pulse generator (NP). The 5-bit PWM determines the duty cycle of the output. The 3-bit NPx generates and inserts narrow pulses among the PWM frame made of 8 cycles. The number of pulses generated is equal to the number programmed into the 3-bit NP. The NP is used to generate an equivalent 8-bit resolution PWM-type DAC with a reasonably high repetition rate through a 5bit PWM clock speed. The PDCK[1:0] settings of the PWMC (A3h) register are used to derive the PWM clock from Fosc. When bit is set to one, the corresponding PWM pin is active as a PWM function. When the bit is cleared, the corresponding PWM pin is active as an I/O pin. These five bits are cleared upon reset. PWM Registers -PWM Control Register The table below describes the PWM control register. T ABLE 39: PWM CONTROL REGISTER (PWMC) – SFR A3H 7 6 5 4 Unused 3 2 1 PDCK1 0 PDCK0 PWM Clock = Fosc 2(PDCK [1:0] +1) Bit [7:2] 1 0 Mnemonic Unused PDCK1 PDCK0 Description Input Clock Frequency Divider Bit 1 Input Clock Frequency Divider Bit 0 The PWM output cycle frame repetition rate (frequency) is calculated using the following formula: The following table describes the relationship between the values of PDCK1/PDCK0 and the value of the divider. Numerical values of the corresponding frequencies are also provided. PDCK1 0 0 1 1 PDCKO 0 1 0 1 Divider 2 4 8 16 PWM clock, Fosc=20MHz 10MHz 5MHz 2.5MHz 1.25MHz PWM clock, Fosc=24MHz 12MHz 6MHz 3MHz 1.5MHz PWM Clock = Fosc 32 x 2(PDCK [1:0] +1) ______________________________________________________________________________________________ www.ramtron.com page 35 of 50 VRS51C1100 PWM Data Registers The following tables describe the PWM data registers. The PWMDx bits hold the content of the PWM data register and determine the duty cycle of the PWM output waveforms. The NPx[2:0] bits will insert narrow pulses into the 8-PWM-cycle frame. T ABLE 40: PWM DATA REGISTER 0 (PWMD0) – SFR A4H Bit 7 6 5 4 3 2 1 0 Mnemonic PWMD2.4 PWMD2.3 PWMD2.2 PWMD2.1 PWMD2.0 NP2.2 NP2.1 NP2.0 Description Contents of PWM Data Register 2 Bit 4 Contents of PWM Data Register 2 Bit 3 Contents of PWM Data Register 2 Bit 2 Contents of PWM Data Register 2 Bit 1 Contents of PWM Data Register 2 Bit 0 Inserts Narrow Pulses in a 8-PWM-Cycle Frame T ABLE 43: PWM DATA REGISTER 3 (PWMD3) – SFR A7H 7 PWMD0.4 3 PWMD0.0 Bit 7 6 5 4 3 2 1 0 Mnemonic PWMD0.4 PWMD0.3 PWMD0.2 PWMD0.1 PWMD0.0 NP0.2 NP0.1 NP0.0 6 PWMD0.3 2 NP0.2 5 PWMD0.2 1 NP0.1 4 PWMD0.1 0 NP0.0 7 PWMD3.4 3 PWMD3.0 Bit 7 6 5 4 3 2 1 Mnemonic PWMD3.4 PWMD3.3 PWMD3.2 PWMD3.1 PWMD3.0 NP3.2 NP3.1 6 PWMD3.3 2 NP3.2 5 PWMD3.2 1 NP3.1 4 PWMD3.1 0 NP3.0 Description Contents of PWM Data Register 0 Bit 4 Contents of PWM Data Register 0 Bit 3 Contents of PWM Data Register 0 Bit 2 Contents of PWM Data Register 0 Bit 1 Contents of PWM Data Register 0 Bit 0 Inserts Narrow Pulses in a 8-PWM-Cycle Frame Description Contents of PWM Data Register 3 Bit 4 Contents of PWM Data Register 3 Bit 3 Contents of PWM Data Register 3 Bit 2 Contents of PWM Data Register 3 Bit 1 Contents of PWM Data Register 3 Bit 0 Inserts Narrow Pulses in a 8-PWM-Cycle Frame T ABLE 41: PWM DATA REGISTER 1 (PWMD1) – SFR A5H 7 PWMD1.4 3 P WMD1.0 Bit 7 6 5 4 3 2 1 0 Mnemonic PWMD1.4 PWMD1.3 PWMD1.2 PWMD1.1 PWMD1.0 NP1.2 NP1.1 NP1.0 6 PWMD1.3 2 NP1.2 5 PWMD1.2 1 NP1.1 4 PWMD1.1 0 NP1.0 The table below shows the number of PWM cycles inserted into an 8-cycle frame when we vary the NP number. NP[2:0] 000 001 010 011 100 101 110 111 Number of PWM cycles inserted in an 8-cycle frame 0 1 2 3 4 5 6 7 Description Contents of PWM Data Register 1 Bit 4 Contents of PWM Data Register 1 Bit 3 Contents of PWM Data Register 1 Bit 2 Contents of PWM Data Register 1 Bit 1 Contents of PWM Data Register 1 Bit 0 Inserts Narrow Pulses in a 8-PWM-Cycle Frame T ABLE 42: PWM DATA REGISTER 2 (PWMD2) – SFR A6H 7 PWMD2.4 3 PWMD2.0 6 PWMD2.3 2 NP2.2 5 PWMD2.2 1 NP2.1 4 PWMD2.1 0 NP2.0 ______________________________________________________________________________________________ www.ramtron.com page 36 of 50 VRS51C1100 Example of PWM Timing Diagram MOV PWMD0 #83H MOV PWME, #08H FIGURE 22: PWM T IMING DIAGRAM ; PWMD04:0]=10h (=16T high, 16T low), NP02:0] = 3 ; Enable P1.3 as PWM output pin 1st Cycle frame 32T 2nd Cycle frame 32T 3rd Cycle frame 32T 4th Cycle frame 32T 5th Cycle frame 32T 6th Cycle frame 32T 7th Cycle frame 32T 8th Cycle frame 32T 16 16 16 16 16 1T (Narrow pulse inserted by NP0[2:0]=3) 1T 1T PWM clock= 1/T= Fosc / 2^(PDIV+1) The SPWM output cycle frame frequency = SPWM clock/32 = [Fosc/2^(PDIV+1)]/32 If Fosc = 20MHz, PDCK[1:0] of PWMC = #03H, then PWM clock = 20MHz/2^4 = 20MHz/16 = 1.25MHz. PWM output cycle frame frequency = (20MHz/2^4)/32 = 39.1 kHz. ______________________________________________________________________________________________ www.ramtron.com page 37 of 50 VRS51C1100 Crystal consideration The crystal connected to the VRS51C1100 oscillator input should be of a parallel type, operating in fundamental mode. The following table provides suggested capacitor and resistor feedback values for different operating frequencies. Valid for VRS51C1100 XTAL 3MHz C1 30 pF C2 30 pF R open XTAL C1 C2 R 16MHz 30 pF 30 pF open The user should review the technical literature supplied with specific crystal or ceramic resonators or contact the manufacturer to select the appropriate values for external components. XTAL1 XTAL 6MHz 30 pF 30 pF open 25MHz 15 pF 15 pF 62KO 9MHz 30 pF 30 pF open 33MHz 5 pF 5 pF 6.8KO 12MHz 30 pF 30 pF open 40MHz 2 pF 2 pF 4.7KO VRS51C1100 R XTAL2 C1 C2 Note: Oscillator circuits may differ with different crystals or ceramic resonators in higher oscillator frequencies. Crystals or ceramic resonator characteristics vary from one manufacturer to the other. ______________________________________________________________________________________________ www.ramtron.com page 38 of 50 VRS51C1100 Operating Conditions T ABLE 44: OPERATING CONDITIONS Symbol TA TS VCC5 Fosc 40 Description Operating temperature Storage temperature Supply voltage Oscillator Frequency Min. -40 -55 4.5 3.0 Typ. 25 25 5.0 - Max. +85 155 5.5 40 Unit ºC ºC V MHz Remarks Ambient temperature under bias For 5V application DC Characteristics T ABLE 45: DC CHARACTERISTICS Symbol VIL1 VIL2 VIH1 VI H2 VOL1 VOL2 VOH1 VOH2 IIL Parameter Input Low Voltage Input Low Voltage Input High Voltage Input High Voltage Output Low Voltage Output Low Voltage Output High Voltage Output High Voltage Logical 0 Input Current Logical Transition Current Input Leakage Current Reset Pull-down Resistance Pin Capacitance Valid P o r t 0,1,2,3,4,#EA RES, XTAL1 P o r t 0,1,2,3,4,#EA RES, XTAL1 Port 0, ALE, #PSEN P o r t 1,2,3,4 Port 0 Port 1,2,3,4,ALE,#PSEN P o r t 1,2,3,4 P o r t 1,2,3,4 P o r t 0, #EA RES Min. -0.5 0 2.0 70% VCC Max. 1.0 0.8 VCC+0.5 VCC+0.5 0.45 0.45 2.4 90%VCC 2.4 90% VCC -75 -650 +10 50 300 10 Unit V V V V V V V V V V uA uA uA Kohm pF mA mA mA mA mA mA uA Test Conditions VCC=5V VCC=5V VCC=5V VCC=5V IOL=3.2mA IOL=1.6mA IOH=-800uA IOH=-80uA IOH=-60uA IOH=-10uA Vin=0.45V Vin=2.OV 0.45V