VSRABC-PLI23

VERSA Datasheet Rev 1.3 VRS700 VERSA 700: 64kB FLASH, 4kB RAM 23MHz, 3V, 8-Bit MCU Datasheet Rev 1.3 1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4 Tel: (514) 871-2447 http://www.goalsemi.com 1 VERSA Datasheet Rev 1.3 VRS700 Overview The VRS700 is a 3V, 8-bit microcontroller with 64kB of Flash memory and 4K RAM that is based on the architecture of the standard 80C51 microcontroller family. It is pin compatible with these devices. Among the VRS700’s features are 8 PWM outputs, a Watch Dog Timer, bank mapping to permit direct addressing of the 4096 bytes of RAM and a serial port. The VRS700’s hardware features and powerful instruction set make it a versatile and cost-effective controller for a wide range of applications requiring a microcontroller running at 3V. The Flash memory can be programmed using programmers available from Goal Semiconductor or other 3rd party commercial programmers. The VRS700 is available in PLCC-44 and QFP-44 packages in the Industrial Temperature Range. Features • • • • • • • • • • • • • • • • • • • Operating voltage: 3.0V ~ 3.6V General 80C51/80C52 family compatible 64kB on-chip Flash memory 4096 bytes on-chip data RAM Bank mapping direct addressing mode to access RAM Four 8-bit I/O ports + one 4-bit I/O port 8-Channel PWM on P1.0~P1.7 Full duplex serial port (UART) Three 16-bit Timers/Counters W atch Dog Timer 8-bit Unsigned Multiply and Division Instructions BCD arithmetic Direct and Indirect Addressing Two levels of Interrupt Priority and Nested Interrupts Power saving modes Code protection functions Operates at a clock frequency from 3MHz to 23MHz Low EMI (inhibit ALE) Industrial Temperature Range (-40ºC to +85ºC) FIGURE 2: VRS700 PLCC-44 AND QFP-44 PIN OUT DIAGRAMS PWM4/P1.4 PWM3/P1.3 PWM2/P1.2 PWM1/T2EX/P1.1 PWM0/T2/P1.0 P4.2 VDD P0.0/AD0 P0.1/AD1 P0.2/AD2 FIGURE 1: VRS700 BLOCK DIAGRAM 8051 PROCESSOR 64kx8 FLASH 4096 Bytes of RAM ADDRESS/ DATA BUS PWM5/P1.5 6 7 40 39 1 P0.3/AD3 PORT 0 8 PWM6/P1.6 PWM7/P1.7 RES RXD/P3.0 P4.3 TXD/P3.1 #INT0/P3.2 #INT1/P3.3 PORT 1 8 VRS700 PLCC-44 P0.4/AD4 P0.5/AD5 P0.7/AD7 P0.6/AD6 #EA P4.1 ALE #PSEN P2.7/A15 UART PORT 2 8 T0/P3.4 T1/P3.5 17 18 28 29 P2.6/A14 P2.5/A13 #WR/P3.6 #RD/P3.7 XTAL2 XTAL1 VSS P4.0 P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P0.7/AD7 #EA P4.1 ALE P2.7/A15 #PSEN TIMER 0 TIMER 1 TIMER 2 RESET POWER CONTROL WATCHDOG TIMER P0.4/AD4 P0.5/AD5 P0.6/AD6 PWM 8 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 VDD P4.2 SPWM0/T2/P1.0 SPWM1/T2EX/P1.1 SPWM2/P1.2 SPWM3/P1.3 SPWM4/P1.4 44 34 33 P2.6/A14 P2.5/A13 23 22 PORT 4 4 P2.4/A12 2 INTERRUPT INPUTS PORT 3 8 P2.4/A12 P2.3/A11 P2.2/A10 VRS700 QFP-44 P2.1/A9 P2.0/A8 P4.0 VSS XTAL1 XTAL2 12 11 1 #RD/P3.7 #WR/P3.6 SPWM7/P1.7 RE S RXD/P3.0 SPWM5/P1.5 SPWM6/P1.6 P4.3 TXD/P3.1 #INT0/P3.2 1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4 Tel: (514) 871-2447 http://www.goalsemi.com #INT1/P3.3 T0/P3.4 T1/P3.5 2 VERSA Datasheet Rev 1.3 VRS700 Pin Descriptions for QFP-44/PLCC-44 TABLE 1: PIN DESCRIPTIONS FOR QFP-44/PLCC-44 QFP - 44 PLCC - 44 Name I/O F unction QFP - 44 PLCC - 44 Name I/O F unction 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 SPWM5 P1.5 SPWM6 P1.6 SPWM7 P1.7 RES RXD P3.0 P4.3 TXD P3.1 # INT0 P3.2 # INT1 P3.3 T0 P3.4 T1 P3.5 #WR P3.6 #RD P3.7 XTAL2 XTAL1 VSS P4.0 P2.0 A8 P2.1 A9 P2.2 A10 P2.3 A11 P2.4 A12 P2.5 A13 O I/O O I/O O I/O I I I/O I/O O I/O I I/O I I/O I I/O I I/O O I/O O I/O O I I/O I/O O I/O O I/O O I/O O I/O O I/O O SPWM Channel 5 Bit 5 of Port 1 SPWM Channel 6 Bit 6 of Port 1 SPWM Channel 7 Bit 7 of Port 1 Reset Receive Data Bit 0 of Port 3 Bit 3 of Port 4 Transmit Data & Bit 1 of Port 3 Low True Interrupt 0 Bit 2 of Port 3 Low True Interrupt 1 Bit 3 of Port 3 Timer 0 Bit 4 of Port 3 Timer 1 & 3 Bit 5 of Port 3 Ext. Memory Write Bit 6 of Port 3 Ext. Memory Read Bit 7 of Port 3 Oscillator/Crystal Output Oscillator/Crystal In Ground Bit 0 of Port 4 Bit 0 of Port 2 Bit 8 of External Memory Address Bit 1 of Port 2 Bit 9 of External Memory Address Bit 2 of Port 2 Bit 10 of External Memory Address Bit 3 of Port 2 & Bit 11 of External Memory Address Bit 4 of Port 2 Bit 12 of External Memory Address Bit 5 of Port 2 Bit 13 of External Memory Address 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 1 2 3 4 5 6 P2.6 A14 P2.7 A15 #PSEN ALE P4.1 #EA P0.7 AD7 P0.6 AD6 P0.5 AD5 P0.4 AD4 P0.3 AD3 P0.2 AD2 P0. 1 AD1 P0.0 AD0 VDD P4.2 T2 P1.0 SPWM0 T2EX P1.1 SPWM1 P1.2 SPWM2 P1.3 SPWM3 P1.4 SPWM4 I/O O I/O O O O I/O I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I/O O I I/O O I/O O I/O O I/O O Bit 6 of Port 2 Bit 14 of External Memory Address Bit 7 of Port 2 Bit 15 of External Memory Address Program Store Enable Address Latch Enable Bit 1 of Port 4 External Access Bit 7 Of Port 0 Data/Address Bit 7 of External Memory Bit 6 of Port 0 Data/Address Bit 6 of External Memory Bit 5 of Port 0 Data/Address Bit 5 of External Memory Bit 4 of Port 0 Data/Address Bit 4 of External Memory Bit 3 Of Port 0 Data/Address Bit 3 of External Memory Bit 2 of Port 0 Data/Address Bit 2 of External Memory Bit 1 of Port 0 & Data Address Bit 1 of External Memory Bit 0 Of Port 0 & Data Address Bit 0 of External Memory VCC Bit 2 of Port 4 Timer 2 Clock Out Bit 0 of Port 1 SPWM Channel 0 Timer 2 Control Bit 1 of Port 1 SPWM Channel 1 Bit 2 of Port 1 SPWM Channel 2 Bit 3 of Port 1 SPWM Channel 3 Bit 4 of Port 1 SPWM Channel 4 SPWM1/T2E X/P1.1 SPWM0/T2/P 1.0 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 #PSEN P2.7/A15 P2.6/A14 P2.5/A13 SPWM4/P1.4 SPWM3/P1.3 SPWM2/P1.2 P4.1 ALE #EA P0.0/AD0 P0.1/AD1 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 VDD P4.2 SPWM0/T2/P1.0 SPWM1/T2EX/P1.1 SPWM2/P1.2 SPWM3/P1.3 SPWM4/P1.4 33 32 31 30 29 28 27 26 25 24 23 34 22 35 36 37 38 39 40 41 42 43 44 1 2 3 4 5 6 7 8 21 20 19 18 17 16 15 14 13 12 9 10 11 P2.4/A12 P2.3/A11 P2.2/A10 P2.1/A9 P2.0/A8 P4.0 VSS XTAL1 XTAL2 #RD/P3.7 #WR/P3.6 6 5 4 3 2 SPWM5/P1.5 SPWM6/P1.6 SPWM7/P1.7 RES RXD/P3.0 P4.3 TXD/P3.1 #INT0/P3.2 #INT1/P3.3 T0/P3.4 T1/P3.5 7 8 9 10 11 12 13 14 15 16 17 1 4 4 43 42 41 40 39 38 37 36 P0.2/AD2 P4.2 VDD P0.3/AD3 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 #EA P4.1 ALE #PSEN P2.5/A13 P2.6/A14 P2.7/A15 VRS700L QFP-44 VRS700L PLCC-44 35 34 33 32 31 30 29 18 1 9 20 2 1 2 2 23 2 4 25 26 27 28 RES SPWM5/P1.5 SPWM6/P1.6 SPWM7/P1.7 #INT0/P3.2 #INT1/P3.3 RXD/P3.0 TXD/P3.1 T0/P3.4 T1/P3.5 P4.3 #RD/P3.7 XTAL2 XTAL1 VSS P2.1/A9 P2.2/A10 P2.3/A11 #WR/P3.6 1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4 Tel: (514) 871-2447 http://www.goalsemi.com P 2.4/A12 P4.0 P2.0/A8 3 VERSA Datasheet Rev 1.3 Instr. Cycles 1 1 1 1 1 1 1 1 1 1 1 2 1 1 2 2 2 2 1 2 1 2 2 2 2 2 2 2 2 2 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 VRS700 Instruction Set All VRS700 instructions are binary code compatible and perform the same functions as the industry standard 8051. The following two tables describe the instruction set of the VRS700. TABLE 2: LEGEND FOR I NSTRUCTION SET TABLE Symbol A Rn Direct @Ri rel bit #data #data 16 addr 16 addr 11 Function Accumulator Register R0-R7 Internal register address Internal register pointed to by R0 or R1 (except MOVX) Two' complement offset byte s Direct bit address 8-bit constant 16-bit constant 16-bit destination address 11-bit destination address Mnemonic CPL A SWAP A RL A RLC A RR A RRC A MOV A, Rn MOV A, direct MOV A, @Ri MOV A, #data MOV Rn, A MOV Rn, direct MOV Rn, #data MOV direct, A MOV direct, Rn MOV direct, direct Size (bytes) 1 2 1 2 1 2 1 2 1 2 1 2 1 1 2 1 1 1 2 1 1 1 1 1 1 2 1 2 2 3 1 2 1 2 2 3 1 2 1 2 2 3 1 MOV direct, @Ri Instr. Cycles MOV direct, #data MOV @Ri, A MOV @Ri, direct 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 4 4 1 1 1 1 1 1 2 1 1 1 1 1 2 1 1 1 1 1 2 1 MOV @Ri, #data MOV DPTR, #data M OVC A, @A+DPTR Description Compliment A Sw ap nibbles of A Rotate A left Rotate A left through carry Rotate A right Rotate A right through carry Move register to A Move direct byte to A Move data memory to A Move immediate to A Move A to register Move direct byte to register Move immediate to register Move A to direct byte Move register to direct byte Move direct byte to direct byte Move data memory to direct byte Move immediate to direct byte Move A to data memory Move direct byte to data memory Move immediate to data memory Move immediate to data pointer Move code byte relative DPTR to A Move code byte relative PC to A Move external data (A8) to A Move external data (A16) to A Move A to external data (A8) Move A to external data (A16) Push direct byte onto stack Pop direct byte from stack Exchange A and register Exchange A and direct byte Exchange A and data memory Exchange A and data memory nibble A bsolute call to subroutine Long call to subroutine Return from subroutine Return from interrupt A bsolute jump unconditional Long jump unconditional Short jump (relative address) Jump on carry = 1 Jump on carry = 0 Jump on direct bit = 1 Jump on direct bit = 0 Jump on direct bit = 1 and clear Jump indirect relative DPTR Jump on accumulator = 0 Jump on accumulator 1= 0 Compare A, direct JNE relative Compare A, immediate JNE relative Compare reg, immediate JNE relative Compare ind, immediate JNE relative Decrement register, JNZ relative Decrement direct byte, JNZ relative No operation Size (bytes) 1 1 1 1 1 1 1 2 1 2 1 2 2 2 2 3 2 3 1 2 2 3 1 1 1 1 1 1 2 2 1 2 1 1 2 3 1 1 2 3 2 2 2 3 3 3 1 2 2 3 3 3 3 2 3 1 Data Transfer Instructions TABLE 3: VERSA 700 I NSTRUCTION SET Mnemonic Description Arithmetic instructions A dd register to A ADD A, Rn ADD A, direct ADD A, @Ri ADD A, #data ADDC A, Rn ADDC A, direct ADDC A, @ Ri ADDC A, #data SUBB A, Rn SUBB A, direct SUBB A, @Ri SUBB A, #data INC A INC Rn INC direct INC @Ri DEC A DEC Rn DEC direct DEC @Ri INC DPTR MUL AB DIV AB DA A Logical Instructions ANL A, Rn ANL A, direct ANL A, @ Ri ANL A, #data ANL direct, A ANL direct, #data ORL A, Rn ORL A, direct ORL A, @Ri ORL A, #data ORL direct, A ORL direct, #data XRL A, Rn XRL A, direct XRL A, @Ri XRL A, #data XRL direct, A XRL direct, #data CLR A A dd direct byte to A A dd data memory to A A dd immediate to A A dd register to A with carry A dd direct byte to A with carry A dd data memory to A w ith carry A dd immediate to A w ith carry Subtract register from A w ith borrow Subtract direct byte from A w ith borrow Subtract data mem from A w ith borrow Subtract immediate from A w ith borrow Increment A Increment register Increment direct byte Increment data memory Decrement A Decrement register Decrement direct byte Decrement data memory Increment data pointer Multiply A by B Divide A by B Decimal adjust A A ND register to A A ND direct byte to A A ND data memory to A A ND immediate to A A ND A to direct byte A ND immediate data to direct byte O R register to A O R direct byte to A O R data memory to A O R immediate to A O R A to direct byte O R immediate data to direct byte Exclusive-OR register to A Exclusive-OR direct byte to A Exclusive-OR data memory to A Exclusive-OR immediate to A Exclusive-OR A to direct byte Exclusive-OR immediate to direct byte Clear A MOVC A, @A+PC MOVX A, @Ri MOVX A, @DPTR MOVX @Ri, A MOVX @DPTR, A PUSH direct POP direct XCH A, Rn XCH A, direct XCH A, @Ri XCHD A, @Ri Branching Instructions ACALL addr 11 LCALL addr 16 RET RETI AJMP addr 11 LJMP addr 16 SJMP rel JC rel JNC rel JB bit, rel JNB bit, rel JBC bit, rel JMP @A+DPTR JZ rel JNZ rel CJNE A, direct, rel CJNE A, #d, rel CJNE Rn, #d, rel CJNE @ Ri, #d, rel DJNZ Rn, rel DJNZ direct, rel NOP Miscellaneous Instruction 1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4 Tel: (514) 871-2447 http://www.goalsemi.com 4 VERSA Datasheet Rev 1.3 VRS700 Special Function Registers (SFR) Addresses 80h to FFh of the SFR address space can be accessed in direct addressing mode only. The following table lists the VRS700 Special Function Registers. TABLE 4: SPECIAL FUNCTION REGISTERS (SFR) SFR Register P0 SP DPL DPH (Reserved) RCON DBANK PCON TCON TMOD TL0 TL1 TH0 TH1 P1 WDTKEY SCON SBUF SPWME WDTC P2 IE P3 SPWMD0 SPWMD1 SPWMD2 SPWMD3 IP SPWMD4 SPWMD5 SPWMD6 SPWMD7 SCONF T2CON T2MOD RCAP2L RCAP2H TL2 TH2 PSW SPWMC0 SPWMC1 SPWMC2 SPWMC3 P4 SPWMC4 SPWMC5 SPWMC6 SPWMC7 ACC B SFR Adrs 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 90h 97h 98h 99h 9Bh 9Fh A0h A8h B0h B3h B4h B5h B6h B8h BBh BCh BDh BEh BFh C8h C9h CAh CBh CCh CDh D0h D3h D4h D5h D6h D8h DBh DCh DDh DEh E0h F0h Bit 7 BSE SMOD TF1 GATE1 WDTKEY7 SM0 SPWM7E WDTE EA WDR TF2 CY - Bit 6 TR1 C/T1 WDTKEY6 SM1 SPWM6E EXF2 AC - Bit 5 BS5 TF0 M1.1 WDTKEY5 SM2 SPWM5E CLEAR ET2 PT2 RCLK F0 - Bit 4 BS4 TR0 M0.1 WDTKEY4 REN SPWM4E ES PS TCLK RS1 - Bit 3 RAMS3 BS3 GF1 IE1 GATE0 WDTKEY3 TB8 SPWM3E ET1 PT1 EXEN2 RS0 P4.3 Bit 2 RAMS2 BS2 GF0 IT1 C/T0 WDTKEY2 RB8 SPWM2E PS2 EX1 PX1 TR2 OV PBS0 PBS1 PBS2 PBS3 P4.2 PBS4 PBS5 PBS6 PBS7 - Bit 1 RAMS1 BS1 PDOWN IE0 M1.0 WDTKEY1 TI SPWM1E PS1 ET0 PT0 OME C/T2 T2OE PFS01 PFS11 PFS21 PFS31 P4.1 PFS41 PFS51 PFS61 PFS71 - Bit 0 RAMS0 BS0 IDLE IT0 M0.0 WDTKEY0 RI SPWM0E PS0 EX0 PX0 ALEI CP/RL2 DCEN P PFS00 PFS10 PFS20 PFS30 P4.0 PFS40 PFS50 PFS60 PFS70 - Reset Value 00000000b 0***0001b 00000000b 00000000b 00000000b ********b 00000000b 00000000b 0*0**000b 00000000b 00000000b 00000000b 00000000b 00000000b 00000000b 00000000b 00000000b 00000000b 00000000b 0****00b 00000000b 00000000b - - - - - ******00b ******00b ******00b ******00b ****1111b ******00b ******00b ******00b ******00b 1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4 Tel: (514) 871-2447 http://www.goalsemi.com 5 VERSA Datasheet Rev 1.3 VRS700 Program Memory Structure Program Memory The VRS700 includes 64K of on-chip Flash memory that can be used as general program memory. The address range for the 64KB of Flash memory is 0000h to FFFFh. FIGURE 3: VRS700 DATA MEMORY 0EFF Program Status Word Register The register below contains the program state flags. These flags may be read or written to by the user. TABLE 5: PROGRAM STATUS W ORD REGISTER (PSW) - SFR DOH FF 80 7F 00 FF Upper 128 bytes (Can only be accessed in indirect addressing mode only) Lower 128 bytes (Can be accessed in indirect and direct addressing mode) SFR (Can only be accessed in direct addressing mode only) Expanded 3840 bytes (Mapped on "external" memory space. Can by accessed by using the MOVX instruction or by Bank mapping direct addressing mode) (OME=1) 80 0000 7 CY Bit 7 6 5 4 3 2 1 0 6 AC 5 F0 4 RS1 3 RS0 2 OV 1 - 0 P Mnemonic CY AC F0 RS1 RS0 OV P Description Carry Bit Auxiliary Carry Bit from bit 3 to 4. User definer flag R0-R7 Registers bank select bit 0 R0-R7 Registers bank select bit 1 Overflow flag Parity flag By default, the expanded RAM area is active. It is possible to disable it by clearing the OME bit of the SCONF register located at address BFh in the SFR. Lower 128 bytes (00h to 7Fh, Bank 0 & Bank 1) The lower 128 bytes (Figure 3) of data memory (from 00h to 7Fh) can be summarized in the following points: • • • • • Address range 00h to 7Fh can be accessed in direct and indirect addressing modes. Address range 00h to 1Fh includes R0-R7 registers area. Address range 20h to 2Fh is bit addressable. Address range 30h to 7Fh is not bit addressable and can be used as general purposes storage. Range 40h-7Fh can be configured as a window to access the whole 4K of RAM memory. RS1 0 0 1 1 RS0 0 1 0 1 Active Bank 0 1 2 3 Address 00h-07h 08h-0Fh 10h-17h 18-1Fh Data Pointer The VRS 700 has one 16-bit data pointer. The DPTR is accessed through two SFR addresses: DPL located at address 82h and DPH located at address 83h. Data Memory The VRS700 has 4K of on-chip SRAM: 256 bytes are configured like the internal memory structure of a standard 80C52, while the expanded 3840 bytes can be accessed using external memory addressing (MOVX) or in bank mapping direct addressing mode. Note: By default, the expanded RAM memory is disabled. To use it, users must first set the bit OME (2) of the System Control Register (SFR BFh). Upper 128 bytes (80h to FFh) The upper 128 bytes of the data memory ranging from 80h to FFh can be accessed using indirect addressing or by using the bank mapping in direct addressing mode (see Table 8). 1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4 Tel: (514) 871-2447 http://www.goalsemi.com 6 VERSA Datasheet Rev 1.3 VRS700 Expanded RAM Access Using the MOVX @DPTR Instruction (0000-0EFF, Bank4-Bank63) The 3840 bytes of the expanded RAM data memory occupy addresses 0000h to 0EFFh mapped on the “external” memory bus. These bytes can be accessed using the MOVX instruction. Note that in the case of indirect addressing using the MOVX @DPTR instruction, if the address exceeds 0EFFh, the VRS700 will generate the external memory control signal automatically. The value of the RAMS0, RAMS1, RAMS2, RAMS3 bits define the page of the expanded RAM that will be accessed by the MOVX @Rn instruction. The default setting of the RAMS0, RAMS1, RAMS2 and RAMS3 bits is 0000 (page 0). Each page has 256 bytes. TABLE 7: MAPPING OF EXPANDED RAM P AGE ACCESS RAMS3 RAMS2 RAMS1 RAMS0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Internal RAM Access using MOVX @Rn instruction and the IRAM Control Register The 3840 bytes of expanded RAM of the VRS700 can also be accessed using the MOVX @Rn instruction (where n = 0,1). Since this instruction can only address 256 bytes of data, it must be used in conjunction with the internal RAM RCON register that serves to select which part of the expanded RAM will be targeted by the instruction. TABLE 6: I NTERNAL R AM CONTROL REGISTER (RCON) - SFR 85H 7 6 5 Unused Mnemonic Unused Unused Unused Unused RAMS3 RAMS2 RAMS1 RAMS0 4 3 RAMS3 2 RAMS2 1 RAMS1 0 RAMS0 0000h-00FFh 0100h-01FFh 0200h-02FFh 0300h-03FFh 0400h-04FFh 0500h-05FFh 0600h-06FFh 0700h-07FFh 0800h-08FFh 0900h-09FFh 0A00h-0AFFh 0B00h-0BFFh 0C00h-0CFFh 0D00h-0DFFh 0E00h-0EFFh MOVX@Ri I=0, 1 mapping to expanded RAM address Bit 7 6 5 4 3 2 1 0 Description See Table 8 for details See Table 8 for details See Table 8 for details See Table 8 for details 1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4 Tel: (514) 871-2447 http://www.goalsemi.com 7 VERSA Datasheet Rev 1.3 VRS700 Data Bank Control Register The DBANK register allows the user to map the entire content of the RAM memory in the 64 bytes RAM memory window ranging from 40h to 7Fh. This allows for faster direct addressing of the entire RAM content. The Data Bank Control Register permits this feature to be activated and selects which 64-byte-block of RAM will be mapped into the 40h to 7Fh window. The Data Bank Select function is activated by setting the Data Bank Select enable bit (BSE) to 1. Setting this bit to zero disables this function. The 6 least significant bits of this register control the mapping of the entire 4K bytes on-chip RAM space into the 040h-07Fh range. See tables 8 and 9. TABLE 8: DATA BANK CONTROL REGISTER (DBANK) – SFR 86H TABLE 9:BANK MAPPING DIRECT ADDRESSING MODE BS5 BS4 BS3 BS2 BS1 BSO 040h~ 07fh mapping address Note 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 000h03Fh 040h07Fh 080h0BFh 0C0h0FFh 0000h003Fh 0040h007Fh 0080h00BFh 00C0h00FFh 0100h013Fh 0140h017Fh 0180h01BFh 01C0h01FFh 0200h023Fh 0240h027Fh 0280h02BFh 02C0h02FFh 0300h033Fh 0340h037Fh 0380h03BFh 03C0h03FFh 0400043Fh 0440h047Fh 0480h04BFh Lower 128 byte RAM Lower 128 byte RAM Upper 128 byte RAM Upper 128 byte RAM On-chip expanded 768 byte RAM “ “ “ “ “ “ “ “ “ “ “ “ “ “ “ “ “ “ 7 BSE Bit 7 6 5 4 3 2 1 0 6 unused Mnemonic BSE Unused BS5 BS4 BS3 BS2 BS1 BS0 5 BS5 4 BS4 3 BS3 2 BS2 1 BS1 0 BS0 0 0 0 0 0 0 0 0 0 Description Data Bank Select Enable Bit BSE=1, Data Bank Select enabled BSE=0, Data Bank Select disabled Allows the mapping of the 4K RAM into the 040h - 07Fh RAM space. See Table 8 for a complete description. Example: User writes #30h to 101h address: MOV MOV MOV DBANK, #88H A, #30H 41H, A ;Set bank mapping 0100h-013Fh ;Store #30H to A ;Write #30 to 0101h ;address 40h-07Fh to 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 … (Follow the same pattern) … 0D80h0 1 0 0DBFh 0DC0h0 1 1 0DFFh 0E00h1 0 0 0E3Fh 0E40h1 0 1 0E7Fh 0E801 1 0 0EBFh 0EC0h1 1 1 0EFFh “ “ “ “ “ “ 1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4 Tel: (514) 871-2447 http://www.goalsemi.com 8 VERSA Datasheet Rev 1.3 VRS700 Description of Peripherals System Control Register The System control Register serves the following functions: • • • Flag that shows Watch Dog Timer reset has occurred. Controls the activation of the expanded RAM Memory. Controls the ALE output. Power Control Register The VRS700 provides two power saving modes: Idle and Power Down. These two modes serve to reduce the power consumption of the device. In Idle mode, the processor is stopped but the oscillator is still running. The content of the RAM, I/O state and SFR registers are maintained. Timer operation is maintained, as well as the external interrupts. This mode is useful for applications in which stopping the processor to save power is required. The processor will be woken up when an external event, triggering an interrupt, occurs. In Power stopped. disabled. registers, Down mode, the oscillator of the VRS700 is This means that all the peripherals are The content of the RAM and the SFR however, is maintained. The Table 10 shows the structure of the System Control Register. The WDR bit is a flag that indicates whether the Watch Dog Timer has caused the system reset. When the WDT is enabled, users should check the WDR bit whenever an unpredicted reset occurs. The OME bit allows the user to enable or disable the on-chip expanded 3840 bytes of RAM. By default, after reset, the expanded RAM memory is disabled (OME=0). This bit must be set to 1 to activate the expanded RAM memory. The ALE bit controls the ALE output activity. By default, the ALE pin is active. In applications where the program is executed from the internal flash memory of the VRS700, the ALE pin is usually of no use, so it is advisable to inhibit the ALE output in order to reduce the EMI generated by the device. By default, the ALE pin is active and emits a signal of a frequency of Fosc/6. Setting the ALE bit of the System Control Register inhibits the ALE output. TABLE 10: SYSTEM CONTROL REGISTER (SCONF) – SFR BFH These power saving modes are controlled by the PDOWN and IDLE bits of the PCON register (Table 11) at address 87h. TABLE 11: POWER CONTROL REGISTER (PCON) - SFR 87H 7 6 5 4 Unused 3 2 1 RAMS1 0 RAMS0 Bit 7 Mnemonic SMOD Description 1: Double the baud rate of the serial port frequency that was generated by Timer 1. 0: Normal serial port baud rate generated by Timer 1. General Purpose Flag General Purpose Flag Power down mode control bit Idle mode control bit 7 WDR Bit 7 6 5 4 3 2 1 0 6 5 4 3 Unused 2 1 OME 0 ALEI 6 5 4 3 2 1 0 Unused Unused Unused GF1 GF0 PDOWN IDLE Mnemonic WDR Unused Unused Unused Unused Unused OME ALEI Description This is the Watch Dog Timer reset bit. It will be set to 1 when the reset signal generated by WDT overflows. 3840 bytes of on-chip enable bit ALE output inhibit bit, which is used to reduce EMI. 1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4 Tel: (514) 871-2447 http://www.goalsemi.com 9 VERSA Datasheet Rev 1.3 VRS700 Input/Output Ports The VRS700 has 36 bi-directional lines grouped into four 8-bit I/O ports and one 4-bit I/O port. These I/Os can be individually configured as input or output. Except for the P0 I/Os, which are of the open drain type, each I/O is made of a transistor connected to ground and a dynamic pull-up resistor made of a combination of transistors. Writing a 0 in a given I/O port bit register will activate the transistor connected to ground, this will bring the I/O to a LOW level. Writing a 1 into a given I/O port bit register deactivates the transistor between the pin and ground. In this case, the pull-up resistor will bring the Pin to a HIGH level. To use a given I/O as an input, one must write a 1 into its associated port register bit. By default, upon reset all the I/Os are configured as input. FIGURE 4: I NTERNAL STRUCTURE OF ONE OF THE EIGHT I /O PORT LINES Read Register Internal Bus Q D F lip-Flop Output Stage IC Pin Write to Register Q Read Pin Structure of the P1, P2, P3 and P4 Ports The following figure (Figure 5) gives a general idea of the structure of one of the lines of the P1, P2 and P3 ports. For each port, the output stage is composed of a transistor (X1) and 3 other pull-up transistors. It is important to note that the figure below does not show the intermediary logic that connects the output of the register and the output stage together because this logic varies with the auxiliary function of each port. FIGURE 5: GENERAL STRUCTURE OF THE OUTPUT STAGE OF P1, P2 AND P3 General Structure of an I/O Port The following elements establish the link between the core unit and the pins of the microcontroller: • • Special Function Register (same name as port) Output Stage Amplifier (the structure of this element varies with its auxiliary function) From Figure 4, one may see that the D flip-flop stores the value received from the internal bus after receiving a write signal from the core. Also, notice that the Q output of the flip-flop can be linked to the internal bus by executing a read instruction. This is how one would read the content of the register. It is also possible to link the value of the pin to the internal bus. This is done by the “read pin” instruction. In short, the user may read the value of the register or the pin. Read Register Vcc Pull-up Network Q D F lip-Flop Write to Register Q X1 Internal Bus IC Pin Read Pin Each line may be used independently as a logical input or output. When used as an input, as mentioned earlier, the corresponding bit register must be high. 1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4 Tel: (514) 871-2447 http://www.goalsemi.com 10 VERSA Datasheet Rev 1.3 VRS700 The transistor would be off and the pull-up will maintain the output at a high level. Also, note that if an external device with a logical low value is connected to the pin, the current will flow out of the pin. In order to have a real bi-directional output, the input should be in a high impedance state. It is for this reason that we call ports P1, P2, P3 and P4 “quasi bi-directional”. Port P0 and P2 as Address and Data Bus The output stage may receive data from two sources (Figure 7): • • The outputs of register P0 or the bus address itself multiplexed with the data bus for P0. The outputs of the P2 register or the high part (A8/A15) of the bus address for the P2 port. Structure of Port 0 The internal structure of P0 is shown in Figure 6. The auxiliary function of this port requires a particular logic. As opposed to the other ports, P0 is truly bi-directional. In other words, when used as an input, it is considered to be in a floating logical state (high impedance state). This arises from the absence of the internal pull-up resistance. The pull-up resistance is actually replaced by a transistor that is only used when the port is used to access external memory/data bus (EA=0). When used as an I/O port, P0 acts as an open drain port and the use of an external pull-up resistor is likely to be required for most applications. FIGURE 6: PORT P0’ S PARTICULAR STRUCTURE FIGURE 7: P2 PORT STRUCTURE Read Register A ddress V cc Pull-up Network Q D F lip-Flop Write t o Register Q Control X1 Internal Bus I C Pin Read P in When the ports are used as an address or data bus, the special function registers P0 and P2 are disconnected from the output stage. The 8 bits of the P0 register are forced to 1 and the content of the P2 register remains constant. Address A0/A7 Read Register Control Auxiliary Port 1 Functions Vcc Internal Bus Q D F lip-Flop The port 1 I/O pins are shared with the SPWM outputs, Timer 2 EXT and T2 input as shown below: IC Pin W rite t o Register Q X1 Pin P1.0 Read Pin P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 Mnemonic T2 SPWM0 T2EX SPWM1 SPWM2 SPWM3 SPWM4 SPWM5 SPWM6 SPWM7 When P0 is used as an external memory bus input (for a MOVX instruction, for example), the outputs of the register are automatically forced to 1. Function Timer 2 counter input SPWM0 output Timer2 Auxiliary input SPWM1 output SPWM2 output SPWM3 output SPWM4output SPWM5 output SPWM6 output SPWM7 output 1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4 Tel: (514) 871-2447 http://www.goalsemi.com 11 VERSA Datasheet Rev 1.3 VRS700 Auxiliary P3 Port Functions The Port 3 I/O pins are shared with the UART interface, INT0 and INT1 interrupts, Timer 0 and Timer 1 inputs and finally the #WR and #RD lines, when external memory access is performed. To maintain the correct functionality of the line in auxiliary function mode, it is necessary that the Q output of the register is held stable at 1. Conversely, if the pull-down transistor continues conducting, it will set the IC pin at a voltage of approximately 0 (Figure 8). FIGURE 8: P3 PORT STRUCTURE Port 4 Port 4 (Table 13) has four pins and its port address is located at 0D8H. The functionality of Port 4 is identical to that of Port 1, Port 2 Port 3. TABLE 13: PORT 4 (P4) - SFR D8H 7 6 5 Unused 4 3 P4.3 2 P4.2 1 P4.1 0 P4.0 Read Regist er Auxiliary Function: Output Vcc Bit 7 6 5 4 3 2 1 0 Mnemonic Unused Unused Unused Unused P4.3 P4.2 P4.1 P4.0 Description Used to output the setting to pins P4.3, P4.2, P4.1, P4.0 respectively. IC Pin X1 Internal Bus Q D F lip-Flop Write to Regist er Q Some instructions allow the user to read the logic state of the output pin, while others allow the user to read the content of the associated port register. These instructions are called read-modify-write instructions. A list of these instructions is found in the table below. Upon execution of these instructions, the content of the port register (at least 1 bit) is modified. The other read instructions take the present state of the input into account. For example, the instruction ANL P3,#01h obtains the value in the P3 register, performs the desired logic operation with the constant 01h and recopies the result into the P3 register. When users want to take the present state of the inputs into account, they must first read these states and perform an AND operation between the reading and the constant. ! " Software Particularities Concerning the Ports Read Pin Auxiliary Function: Input The following table describes the auxiliary function of the port 3 I/O pins. TABLE 12: P3 AUXILIARY FUNCTION TABLE Pin P3.0 Mnemonic RXD P3.1 TXD P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 INT0 INT1 T0 T1 WR RD Function Serial Port: Receive data in asynchronous mode. Input and output data in synchronous mode. Serial Port: Transmit data in asynchronous mode. Output clock value in synchronous mode. External Interrupt 0 Timer 0 Control Input External Interrupt 1 Timer 1 Control Input Timer 0 Counter Input Timer 1 Counter Input Write signal for external memory Read signal for external memory When the port is used as an output, the register contains information on the state of the output pins. Measuring the state of an output directly on the pin is inaccurate because the electrical level depends mostly on the type of charge that is applied to it. The functions shown below (Table 14) take the value of the register rather than that of the pin. 1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4 Tel: (514) 871-2447 http://www.goalsemi.com 12 VERSA Datasheet Rev 1.3 TABLE 14: LIST OF I NSTRUCTIONS THAT READ AND MODIFY THE PORT USING REGISTER VALUES VRS700 Instruction A NL ORL XRL JBC CPL INC DEC DJNZ MOV P.,C CLR P.x SETB P.x Function Logical AND ex: ANL P0, A Logical OR ex: ORL P2, #01110000B Exclusive OR ex: XRL P1, A Jump if the bit of the port is set to 0 Complement one bit of the port Increment the port register by 1 Decrement the port register by 1 Decrement by 1 and jump if the result is not equal to 0 Copy the held bit C to the port Set the port bit to 0 Set the port bit to 1 Port Operation Timing Writing to a Port (Output) When an operation induces a modification of the content in a port register, the new value is placed at the output of the D flip-flop during the T12 period of the last machine cycle that the instruction needed to execute. It is important to note, however, that the output stage only samples the output of the registers on the P1 phase of each period. It follows that the new value only appears at the output after the T12 period of the following machine cycle (see Figure 24). Reading a Port (Input) The reading of an I/O pin takes place: • • • During T9 cycle for P0, P1 During T10 cycle for P2, P3 When the ports are configured as I/Os (see Figure 24). In order to get sampled, the signal duration present on the I/O configured input must have a duration longer than Fosc/12. 1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4 Tel: (514) 871-2447 http://www.goalsemi.com 13 VERSA Datasheet Rev 1.3 VRS700 Timers The VRS700 includes three 16-bit timers: T0, T1 and T2. The timers can operate in two specific modes: • • Event counting mode Timer mode The table below (Table 16) summarizes the four modes of operation of timers 0 and 1. The timer operating mode is selected by the bits M1 and M0 of the TMOD register. TABLE 16: TIMER/COUNTER MODE DESCRIPTION SUMMARY When operating in counting mode, the counter is incremented each time an external event, such as a transition in the logical state of the timer input (T0, T1, T2 input), is detected. When operating in timer mode, the counter is incremented by the microcontroller’s direct clock pulse or by a divided version of it. M1 0 0 1 M0 0 1 0 Mode Mode 0 Mode 1 Mode 2 Function 13-bit Counter 16-bit Counter 8-bit auto-reload Counter/Timer. The reload value is kept in TH0 or TH1, while TL0 or TL1 is incremented every machine cycle. When TLx overflows, the value of THx is copied to TLx. If Timer 1 M1 and M0 bits are set to 1, Timer 1 stops. 1 1 Mode 3 T imer 0 and Timer 1 Timers 0 and 1 have four modes of operation. These modes allow the user to change the size of the counting register or to authorize an automatic reload when provided with a specific value. Timer 1 can even be used as a baud rate generator to generate communication frequencies for the serial interface. Timer 1 and Timer 0 are configured by the TMOD (Table 15) and TCON (Table 16) registers. TABLE 15: TIMER MODE CONTROL REGISTER (TMOD) – SFR 89H 7 GATE Bit 7 6 C/T Mnemonic GATE1 5 M1 4 M0 3 GATE 2 C/T 1 M1.0 0 M0.0 6 C/T1 5 4 3 M1.1 M0.1 GATE0 2 C/T0 1 0 M1.0 M0.0 Description 1: Enables external gate control (pin INT1 for Counter 1). When INT1 is high, and TRx bit is set (see TCON register), a counter is incremented every falling edge on the T1IN input pin. Selects timer or counter operation (Timer1). 1 = A counter operation is performed 0 = The corresponding register will function as a timer. Selects mode for Timer/Counter 1, as shown in Table 16. Selects mode for Timer/Counter 1, as shown in Table 16. If set, enables external gate control (pin INT0 for Counter 0). When INT0 is high, and TRx bit is set (see TCON register), a counter is incremented every falling edge on the T0IN input pin. Selects timer or counter operation (Timer 0). 1 = A counter operation is performed 0 = The corresponding register will function as a timer. Selects mode for Timer/Counter 0. Selects mode for Timer/Counter 0. 1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4 Tel: (514) 871-2447 http://www.goalsemi.com 14 VERSA Datasheet Rev 1.3 VRS700 Counter and Timer Functions T iming Function When operating as a timer, the counter is automatically incremented at every machine cycle. When a timer overflow condition occurs an associated overflow flag, TF0 or TF1 flag is set to 1. These flags are part of the TCON register. TABLE 17:TIMER 0 AND 1 CONTROL REGISTER (TCON) –SFR 88H Operating Modes The user may change the operating mode by varying the M1 and M0 bits of the TMOD SFR. Mode 0 In Mode 0, the timer operates as an 8-bit counter preceded by a divide-by-32 prescaler made of the 5 LSB of TL1. The register of the counter is configured to be 13 bits long. When an overflow causes the value of the register to roll over to 0, the TFx interrupt signal goes to 1. The count value is validated as soon as TRx goes to 1 and the GATE bit is 0, or when INTx is 1. The figure below shows this mode of operation. FIGURE 9: TIMER/COUNTER 1 MODE 0: 13-BI T COUNTER T F1 7 TR1 6 TF0 5 TR0 4 IE1 3 IT1 2 IE0 1 IT0 0 Bit 7 Mnemonic TF1 Description Timer 1 Overflow Flag. Set by hardware on Timer/Counter overflow. Cleared by hardware on Timer/Counter overflow. Cleared by hardware when processor vectors to interrupt routine. Timer 1 Run Control Bit. Set/cleared by software to turn Timer/Counter on or off. Timer 0 Overflow Flag. Set by hardware on Timer/Counter overflow. Cleared by hardware when processor vectors to interrupt routine. Timer 0 Run Control Bit. Set/cleared by software to turn Timer/Counter on or off. Interrupt Edge Flag. Set by hardware when external interrupt edge is detected. Cleared when interrupt processed. Interrupt 1 Type Control Bit. Set/cleared by software to specify falling edge/low level triggered external interrupts. Interrupt 0 Edge Flag. Set by hardware when external interrupt edge is detected. Cleared when interrupt processed. Interrupt 0 Type control bit. Set/cleared by software to specify falling edge/low level triggered external interrupts. 6 TR1 C LK ÷12 TL1 CLK 1 C/T =1 Co ntro l 5 T F0 0 C/T =0 0 4 7 Mode 0 T1PIN 4 3 2 1 0 T R0 IE1 IT1 IE0 IT0 Mode 1 TR1 GATE INT1 PIN 0 TH1 7 TF1 INT Mode 1 Mode 1 is almost identical to Mode 0. They differ in that, in Mode 1, the counter is 16 bits wide and has no prescaler. Mode 2 In this mode, the timer is configured as an 8-bit counter with auto-reload. The lower byte of the timer, TLx is used as the counter and the upper byte serves to store the timer reload value which will be automatically copied into the TLx portion of the timer when TFx flag is set in response to the overflow. The value of THx remains unchanged. Counting Function When operating as a counter, the timer’s register is incremented at every falling edge of the T0, T1 and T2 signals located at the input of the timer. In this case, the signal is sampled at the T10 phase of each machine cycle for Timer 0, Timer 1 and T9 for Timer 2. When a high to low transition is detected at the timer input pin, the counter is incremented. Two machine cycles are required to detect and record an event. This means that the event duration must be greater than (Fosc/24)-1. 1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4 Tel: (514) 871-2447 http://www.goalsemi.com 15 VERSA Datasheet Rev 1.3 FIGURE 10: TIMER/COUNTER 1 MODE 2: 8-BIT AUTOMATIC RELOAD VRS700 Timer 2 Timer 2 of the VRS700 is a 16-bit Timer/Counter. Similar to timers 0 and 1, Timer 2 can operate either as an event counter or as a timer. The user may switch functions by writing to the C/T2 bit located in the T2CON Special Function Register. Timer 2 has three operating modes: “Auto-Load”, “Capture” and “Baud Rate Generator”. The T2CON SFR configures the modes of operation of Timer 2. Table 18 describes each bit in the T2CON Special Function Register. TABLE 18: TIMER 2 CONTROL REGISTER (T2CON) – SFR C8H TF1 INT CLK ÷12 C/T =0 0 C/T=1 TL1 0 7 1 T1 Pin Control Re loa d 0 TH1 7 TR1 GATE INT0 PIN T F2 7 EXF2 6 RCLK 5 TCLK 4 EXEN2 3 TR2 2 C/T2 1 CP/RL2 0 Bit Mode 3 In Mode 3 (Figure 11), Timer 1 is blocked as if its control bit, TR1, was set to 0. In this mode, Timer 0’s registers TL0 and TH0 are configured as two separate 8-bit counters. Also, the TL0 counter uses Timer 0’s control bits C/T, GATE, TR0, INT0, TF0, and the TH0 counter is held in Timer Mode (counting machine cycles) and gains control over TR1 and TF1 from Timer 1. At this point, TH0 controls the Timer 1 interrupt. FIGURE 11: TIMER/COUNTER 0 MODE 3 CLK 0 TH0 7 7 Mnemonic T F2 6 EXF2 5 RCLK Description Timer 2 Overflow Flag. Set by an overflow of Timer 2 and must be cleared by software. TF2 will not be set when either RCLK =1 or TCLK =1. Timer 2 external flag change in state occurs when either a capture or reload is caused by a negative transition on T2EX and EXEN2=1. When Timer 2 is enabled, EXF=1 will cause the CPU to vector to the Timer 2 interrupt routine. Note that EXF2 must be cleared by software. Serial Port Receive Clock Source. 1: Causes serial port to use Timer 2 overflow pulses for its receive clock in modes 1 and 3. 0: Causes Timer 1 overflow to be used for the Serial Port receive clock. Serial Port Transmit Clock. 1: Causes serial port to use Timer 2 overflow pulses for its transmit clock in modes 1 and 3. 0: Causes Timer 1 overflow to be used for the serial port transmit clock. Timer 2 External Mode Enable. 1: Allows a capture or reload to occur as a result of a negative transition on T2EX if Timer 2 is not being used to clock the serial port. 0: Causes Timer 2 to ignore events at T2EX. Start/Stop Control for Timer 2. 1: Start Timer 2 0: Stop Timer 2 Timer or Counter Select (Timer 2) 1: External event counter falling edge triggered. 0: Internal Timer (OSC/12) Cont rol TR1 TF1 INTERRUPT 4 TL0 CLK T CLK CLK ÷12 0 C/T =0 0 7 1 T0PIN C/T =1 Cont rol TF0 INTERRUPT 3 EXEN2 TR0 GATE INT0 PIN 2 1 T R2 C/T2 1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4 Tel: (514) 871-2447 http://www.goalsemi.com 16 VERSA Datasheet Rev 1.3 VRS700 0 CP/RL2 Capture/Reload Select. 1: Capture of Timer 2 value into RCAP2H. RCAP2L is performed if EXEN2=1 and a negative transitions occurs on the T2EX pin. The capture mode requires RCLK and TCLK to be 0. 0: Auto-reload reloads will occur either with Timer 2 overflows or negative transitions at T2EX when EXEN2=1. When either RCK =1 or TCLK =1, this bit is ignored and the timer is forced to auto-reload on Timer 2 overflow. When EXEN2 = 1, the above still applies. In addition, it is possible to allow a 1 to 0 transition at the T2EX input to cause the current value stored in the Timer 2 registers (TL2 and TH2) to be captured into the RCAP2L and RCAP2H registers. Furthermore, the transition at T2EX causes bit EXF2 in T2CON to be set, and EXF2, like TF2, can generate an interrupt. Note that both EXF2 and TF2 share the same interrupt vector. Auto-Reload Mode In this mode (Figure 13), there are also two options. The user may choose either option by writing to bit EXEN2 in T2CON. If EXEN2=0, then when Timer 2 rolls over, it not only sets TF2, but also causes the Timer 2 registers to be reloaded with the 16-bit value in the RCAP2L and RCAP2H registers previously initialised. In this mode, Timer 2 can be used as a baud rate generator source for the serial port. If EXEN2=1, then Timer 2 still performs the above operation, but a 1 to 0 transition at the external T2EX input will also trigger an anticipated reload of the Timer 2 with the value stored in RCAP2L, RCAP2H and set EXF2. FIGURE 13: TIMER 2 IN AUTO-RELOAD MODE Table 19 enumerates the possible combinations of control bits that may be used for the mode selection of Timer 2. TABLE 19: TIMER 2 MODE SELECTION BITS RCLK + TCLK 0 0 1 X CP/RL2 0 1 X X TR2 1 1 1 0 MODE 16-bit AutoReload Mode 16-bit Capture Mode Baud Rate Generator Mode Off The details of each mode are described below. Capture Mode In Capture Mode the EXEN2 bit value defines whether the external transition on the T2EX pin will trigger the capture of the timer value. When EXEN2=0, Timer 2 acts as a 16-bit timer or counter, which, when an overflow occurs, will set bit TF2 (Timer 2 overflow bit). This overflow can be used to generate an interrupt. FIGURE 12: TIMER 2 IN CAPTURE MODE F OSC ÷12 0 C/T2 1 CO UNTER TIMER 0 TL2 7 0 TH2 7 T2 Pin 0 TR2 RCAP2L 7 0 RCAP2H 7 TF2 T2 E X Pin EXF2 EXEN2 FO SC ÷12 Timer 2 Int errupt 0 C/T 2 1 T2 Pin TIMER 0 TL2 7 0 T H2 7 COUNTER 0 TR2 RCAP2L 7 0 RCAP2H 7 TF2 T2 EX Pin EXF2 EXEN2 Timer 2 Interrupt 1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4 Tel: (514) 871-2447 http://www.goalsemi.com 17 VERSA Datasheet Rev 1.3 TABLE 20: TIMER 2 MODE CONTROL (T2MOD) – SFR C9H VRS700 7 - 6 - 5 - 4 - 3 - 2 - T 2OE 1 DCEN 0 Serial Port The serial port on the VRS700 can operate in full duplex; in other words, it can transmit and receive data simultaneously. This occurs at the same speed if one timer is assigned as the clock source for both transmission and reception, and at different speeds if transmission and reception are each controlled by their own timer. The serial port receive is buffered, which means that it can begin reception of a byte even if the one previously received byte has not been retrieved from the receive register by the processor. However, if the first byte still has not been read by the time reception of the second byte is complete, the byte present in the receive buffer will be lost. One SFR register, SBUF, gives access to the transmit and receive registers of the serial port. When the user reads from the SBUF register he will access the receive register. When the user writes to the SBUF, the transmit register will be loaded. 7 6 5 4 3 2 1 0 Bit T 2OE Mnemonic Description DCEN Timer 2 Output Enable. This bit enables/disables the Timer 2 clock-out function. Countdown Enable. This bit, when set to 1, causes Timer 2 to count down. Baud Rate Generator Mode This mode (Figure 14) is activated when RCLK is set to 1 and/or TCLK is set to 1. This mode will be described in the serial port section. FIGURE 14: TIMER 2 IN AUTOMATIC BAUD GENERATOR MODE FOS C ÷2 0 C/T2 1 COUNTER TIME R Serial Port Control Register 0 TL2 7 0 TH2 7 T2 Pin 0 TR2 RCAP2L 1 0 0 Timer 1 Overflow 1 SMOD RCLK TCLK 1 0 7 0 RCA P2H 7 ÷16 ÷16 TX Clock RX Clock The serial port control register and status register (SCON) (Table 21) contain the 9th data bit for transmit and receive (TB8 and RB8) and all the mode selection bits. SCON also contains the serial port interrupt bits (TI and RI). ÷2 T2 EX Pin EXF2 Timer 2 Interrupt Request EXEN2 1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4 Tel: (514) 871-2447 http://www.goalsemi.com 18 VERSA Datasheet Rev 1.3 TABLE 21: SERIAL PORT CONTROL REGIS TER (SCON) – SFR 98H VRS700 SM0 7 SM1 6 SM2 5 REN 4 TB8 3 RB8 2 TI 1 RI 0 Modes of Operation The VRS700’s serial port can operate in four different modes. In all modes, a transmission is initiated by an instruction that uses the SBUF SFR as a destination register. In Mode 0, reception is initiated by setting RI to 0 and REN to 1. An incoming start bit initiates reception in the other modes provided that REN is set to 1. The following sections describe the four modes. Mode 0 In this mode (shown in Figure 15), serial data exits and enters through the RXD pin. TXD is used to output the shift clock. The signal is composed of 8 data bits starting with the LSB. The baud rate in this mode is 1/12 the oscillator frequency. FIGURE 15: SERIAL PORT MODE 0 BLOCK DIAGRAM Bit 7 6 Mnemonic SM0 SM1 5 SM2 Description Bit to select mode of operation (see table below) Bit to select mode of operation (see table below) Multiprocessor communication is possible in modes 2 and 3. In modes 2 or 3, if SM2 is set to 1, RI will not be activated if the received 9th data bit (RB8) is 0. In Mode 1, if SM2=1, RI will not be activated if a valid stop bit was not received. Serial Reception Enable Bit. This bit must be set by software and cleared by software. 1: Serial reception enabled 0: Serial reception disabled 9th Data Bit Transmitted In Modes 2 and 3. This bit must be set by software and cleared by software. 9th Data Bit Received In Modes 2 and 3. In Mode 1, if SM2=0, RB8 is the stop bit that was received. In Mode 0, this bit is not used. This bit must be cleared by software. Transmission Interrupt flag. Automatically set to 1 when: • The 8th bit has been sent in Mode 0. • Automatically set to 1 when the stop bit has been sent in the other modes. This bit must be cleared by software. Reception interrupt flag automatically set to 1 when: • The 8th bit has been received in Mode 0. • Automatically set to 1 when the stop bit has been sent in the other modes (see SM2 exception). This bit must be cleared by software. 4 REN 3 2 T B8 RB8 Internal Bus 1 Write to SBUF S D CLK Q SBUF Shift ZERO DETECTOR RXD P3.0 Shift Clock Shift TXD P3.1 1 TI Start TX Control Unit F osc/12 TX Clock TI Send Serial Port Interrupt RX Clock RI REN Start Shift 1 1 RI RX Control Unit 1 1 1 1 1 0 Receive 0 RI RXD P3.0 Input Function Shift Register RXD P3.0 SBUF READ SBUF TABLE 22: SERIAL PORT MODES OF OPERATION Internal Bus SM0 0 0 1 1 SM1 0 1 0 1 Mode 0 1 2 3 Description Shift Register 8-bit UART 9-bit UART 9-bit UART Baud Rate Fosc/12 Variable Fosc/64 or Fosc/32 Variable T ransmission (Mode 0) Any instruction that uses SBUF as a destination register may initiate a transmission. The “write to SBUF” signal also loads a 1 into the 9th position of the transmit shift register and tells the TX control block to begin a transmission. The internal timing is such that one full machine cycle will elapse between a write to SBUF instruction and the activation of SEND. The Tel: (514) 871-2447 http://www.goalsemi.com 19 1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4 VERSA Datasheet Rev 1.3 VRS700 SEND signal enables the output of the shift register to the alternate output function line of P3.0 and enables SHIFT CLOCK to the alternate output function line of P3.1. SHIFT CLOCK is high during T11, T12 and T1, T2 and T3, T4 of every machine cycle and low during T5, T6, T7, T8, T9 and T10. At T12 of every machine cycle in which SEND is active, the contents of the transmit shift register are shifted to the right by one position. Zeros come in from the left as data bits shift out to the right. The TX control block sends its final shift and deactivates SEND while setting T1 after one condition is fulfilled: When the MSB of the data byte is at the output position of the shift register; the 1 that was initially loaded into the 9th position is just to the left of the MSB; and all positions to the left of that contain zeros. Once these conditions are met, the deactivation of SEND and the setting of T1 occur at T1 of the 10th machine cycle after the “write to SBUF” pulse. Reception (Mode 0) When REN and R1 are set to 1 and 0 respectively, reception is initiated. The bits 11111110 are written to the receive shift register at T12 of the next machine cycle by the RX control unit. In the following phase the RX control unit will activate RECEIVE. SHIFT CLOCK to the alternate output function line of P3.1 is enabled by RECEIVE. At every machine cycle, the SHIFT CLOCK makes transitions at T5 and T11. The contents of the receive shift register are shifted one position to the left at T12 of every machine in which RECEIVE is active. The value that comes in from the right is the value that was sampled at the P3.0 pin at T10 of the same machine cycle. 1’s are shifted out to the left as data bits are shifted in from the right. The RX control block is flagged to do one last shift and load SBUF when the 0 that was initially loaded into the rightmost position arrives at the leftmost position in the shift register. Mode 1 For an operation in Mode 1 (Figure 16), 10 bits are transmitted (through TXD) or received (through RXD). The transactions are composed of: a Start bit (Low); 8 data bits (LSB first) and one Stop bit (high). The reception is completed once the Stop bit sets the RB8 flag in the SCON register. Either Timer 1 or Timer 2 controls the baud rate in this mode. The following diagram shows the serial port structure when configured in Mode 1. FIGURE 16: SERIAL PORT MODE 1 AND 3 BLOCK DIAGRAM I nternal Bus 1 Write to SBUF Timer 1 Overflow S D CLK Timer 2 Overflo w Q SBUF TXD ÷2 01 SMOD 0 ZERO DETECTOR 1 Start TCLK ÷16 TX Clock ÷16 Shift TX Control Unit TI Data Send 0 RCLK 1 Serial Port Interrupt RX Clock RI RX Control Unit Load SB UF SHIFT 1-0 Transition Detector Start RXD Bit Detector LOAD SBUF 9-Bit Sh ift Register Shift SBUF READ SBUF Inte rn al Bus T ransmission (Mode 1) Transmission is initiated by any instruction that makes use of SBUF as a destination register. The 9th bit position of the transmit shift register is loaded by the “write to SBUF” signal. This event also flags the TX Control Unit that a transmission has been requested. It is after the next rollover in the divide-by-16 counter when transmission actually begins at T1 of the machine cycle. It follows that the bit times are synchronized to the divide-by-16 counter and not to the “write to SBUF” signal. 1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4 Tel: (514) 871-2447 http://www.goalsemi.com 20 VERSA Datasheet Rev 1.3 VRS700 When transmission begins, it places the start bit at TXD. Data transmission is activated one bit time later. This activation enables the output bit of the transmit shift register to TXD. One bit time after that, the first shift pulse occurs. In this mode, zeros are clocked in from the left as data bits are shifted out to the right. When the most significant bit of the data byte is at the output position of the shift register, the 1 that was initially loaded into the 9th position is to the immediate left of the MSB, and all positions to the left of that contain zeros. This condition flags the TX Control Unit to shift one more time. Reception (Mode 1) One to zero transitions at RXD initiate reception. It is for this reason that RXD is sampled at a rate of 16 multiplied by the baud rate that has been established. When a transition is detected, 1FFh is written into the input shift register and the divide-by-16 counter is immediately reset. The divide-by-16 counter is reset in order to align its rollovers with the boundaries of the incoming bit times. In total, there are 16 states in the counter. During the 7th, 8th a nd 9th c ounter states of each bit time, the bit detector samples the value of RXD. The accepted value is the value that was seen in at least two of the three samples. The purpose of doing this is for noise rejection. If the value accepted during the first bit time is not zero, the receive circuits are reset and the unit goes back to searching for another one to zero transition. All false start bits are rejected by doing this. If the start bit is valid, it is shifted into the input shift register, and the reception of the rest of the frame will proceed. For a receive operation, the data bits come in from the right as 1’s shift out on the left. As soon as the start bit arrives at the leftmost position in the shift register, (9bit register), it tells the RX control block to perform one last shift operation: to set RI and to load SBUF and RB8. The signal to load SBUF and RB8, and to set RI, will be generated if, and only if, the following conditions are met at the time the final shift pulse is generated: Either SM2 = 0 or the received stop bit = 1 RI = 0 If both conditions are met, the stop bit goes into RB8, the 8 data bits go into SBUF, and RI is activated. If one of these conditions is not met, the received frame is completely lost. At this time, whether the above conditions are met or not, the unit goes back to searching for a one to zero transition in RXD. Mode 2 In Mode 2 a total of 11 bits are transmitted (through TXD) or received (through RXD). The transactions are composed of: a Start bit (Low), 8 data bits (LSB first), a programmable 9th data bit, and one Stop bit (High). For transmission, the 9th data bit comes from the TB8 bit of SCON. For example, the parity bit P in the PSW could be moved into TB8. In the case of receive, the 9th data bit is automatically written into RB8 of the SCON register. In Mode 2, the baud rate is programmable to either 1/32 or 1/64 the oscillator frequency. FIGURE 17: SERIAL PORT MODE 2 BLOCK DIAGRAM I nternal Bus 1 W rite to SBUF Fosc/2 S D CLK Q SBUF TXD ÷2 01 SMOD ÷16 Stop Start TX Clock ÷16 ZERO DETECTOR Shift TX Control Unit TI Data Send Serial Port Interrupt RX Clock Control RI RX Control Unit Load SBUF SHIFT Sample 1-0 Transition Detector Start RXD Bit Detector LOAD SBUF 9-Bit Shift Register Shift SBUF READ SBUF Internal Bus 1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4 Tel: (514) 871-2447 http://www.goalsemi.com 21 VERSA Datasheet Rev 1.3 VRS700 Mode 3 In Mode 3 (Figure 18), 11 bits are transmitted (through TXD) or received (through RXD). The transactions are composed of: a Start bit (Low), 8 data bits (LSB first), a programmable 9th data bit, and one Stop bit (High). Mode 3 is identical to Mode 2 in all respects but one: the baud rate. Either Timer 1 or Timer 2 generates the baud rate in Mode 3. FIGURE 18: SERIAL PORT MODE 3 BLOCK DIAGRAM T ransmission (Mode 2 and 3) The transmission is initiated by any instruction that makes use of SBUF as the destination register. The 9th bit position of the transmit shift register is loaded by the “write to SBUF” signal. This event also informs the TX control unit that a transmission is requested. It is after the next rollover in the divide-by-16 counter when transmission actually begins at T1 of the machine cycle. It follows that the bit times are synchronized to the divide-by-16 counter and not to the “write to SBUF” signal, as in the previous mode. Transmissions begin when the SEND signal is activated, which places the Start bit at TXD. Data is activated one bit time later. This activation enables the output bit of the transmit shift register to TXD. The first shift pulse occurs one bit time after that. The first shift clocks a Stop bit (1) into the 9th bit position of the shift register to TXD. Thereafter, only zeros are clocked in. Thus, as data bits shift out to the right, zeros are clocked in from the left. When TB8 is at the output position of the shift register, the stop bit is just to the left of TB8, and all positions to the left of that contain zeros. This condition signals to the TX control unit to shift one more time and set TI while deactivating SEND. This occurs at the 11th divide-by-16 rollover after “write to SBUF”. Internal Bus 1 Write to SBUF Timer 1 Overflow S D CLK Timer 2 Overflow Q SBUF TXD ÷2 01 SMOD 0 ZERO DETECTOR 1 T CLK ÷16 Start Shift TX Control Unit Data TX Clock ÷16 0 RCLK 1 TI Send Serial Port Interrupt RI RX Control Unit Load SBUF SHIFT SAMPLE 1-0 T ransition Detector RX Clock Start RXD Bit Detector LOAD SBUF 9-Bit Shift R egister Shift SBUF READ SBUF Internal Bus Mode 2 and 3: Additional Information As mentioned earlier, for an operation in these modes, 11 bits are transmitted (through TXD) or received (through RXD). The signal comprises: a logical low Start bit, 8 data bits (LSB first), a programmable 9th data bit, and one logical high Stop bit. On transmit, (TB8 in SCON) can be assigned the value of 0 or 1. On receive; the 9th data bit goes into RB8 in SCON. The baud rate is programmable to either 1/32 or 1/64 the oscillator frequency in Mode 2. Mode 3 may have a variable baud rate generated from either Timer 1 or Timer 2 depending on the states of TCLK and RCLK. 1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4 Tel: (514) 871-2447 http://www.goalsemi.com 22 VERSA Datasheet Rev 1.3 VRS700 Reception (Mode 2 and 3) One to zero transitions at RXD initiate reception. It is for this reason that RXD is sampled at a rate of 16 multiplied by the baud rate that has been established. When a transition is detected, the 1FFh is written into the input shift register and the divide-by-16 counter is immediately reset. During the 7th, 8th and 9th counter states of each bit time, the bit detector samples the value of RXD. The accepted value is the value that was seen in at least two of the three samples. If the value accepted during the first bit time is not zero, the receive circuits are reset and the unit goes back to searching for another one to zero transition. If the start bit is valid, it is shifted into the input shift register, and the reception of the rest of the frame will proceed. For a receive operation, the data bits come in from the right as 1’s shift out on the left. As soon as the start bit arrives at the leftmost position in the shift register (9-bit register), it tells the RX control block to do one more shift, to set RI, and to load SBUF and RB8. The signal to set RI and to load SBUF and RB8 will be generated if, and only if, the following conditions are satisfied at the instance when the final shift pulse is generated: - Either SM2 = 0 or the received 9th bit is equal to 1 - RI = 0 If both conditions are met, the 9th data bit received goes into RB8, and the first 8 data bits go into SBUF. If one of these conditions is not met, the received frame is completely lost. One bit time later, whether the above conditions are met or not, the unit goes back to searching for a one to zero transition at the RXD input. Please note that the value of the received stop bit is unrelated to SBUF, RB8 or RI. 1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4 Tel: (514) 871-2447 http://www.goalsemi.com 23 VERSA Datasheet Rev 1.3 VRS700 Baud Rates In Mode 0, the baud rate is fixed and can be represented by the following formula: The value to put into the TH1 register is defined by the following formula: 2SMOD x Fosc 32 x 12x (Baud Rate) T H1 = 256 Mode 0 Baud Rate = Oscillator Frequency 12 In Mode 2, the baud rate depends on the value of the SMOD bit in the PCON SFR. From the formula below, we can see that if SMOD = 0 (which is the value on reset), the baud rate is 1/32 the oscillator frequency. It is possible to use Timer 1 in 16-bit mode to generate the baud rate for the serial port. To do this, leave the Timer 1 interrupt enabled, configure the timer to run as a 16-bit timer (high nibble of TMOD = 0001B), and use the Timer 1 interrupt to perform a 16-bit software reload. This can achieve very low baud rates. Generating Baud Rates with Timer 2 Mode 2 Baud Rate = 2SMOD x (Oscillator Frequency) 64 The Timer 1 and/or Timer 2 overflow rate determines the baud rates in modes 1 and 3. Generating Baud Rate with Timer 1 When Timer 1 functions as a baud rate generator, the baud rates in modes 1 and 3 are determined by the Timer 1 overflow rate. Timer 2 is often preferred to generate the baud rate, as it can be easily configured to operate as a 16-bit timer with auto reload. This allows for much better resolution than using Timer 1 in 8-bit auto reload mode. The baud rate using Timer 2 is defined as: Mode 1,3 Baud Rate = Timer 2 Overflow Rate 16 Mode 1,3 Baud Rate = 2SMOD x Timer 1 Overflow Rate 32 The timer can be configured as either a timer or a counter in any of its 3 running modes. In most typical application, it is configured as a timer (C/T2 is set to 0). To make the Timer 2 operate as a baud rate generator the TCLK and RCLK bits of the T2CON register must be set to 1. The baud rate generator mode is similar to the autoreload mode in that an overflow in TH2 causes the Timer 2 registers to be reloaded with the 16-bit value in registers RCAP2H and RCAP2L, which are preset by software. However, when Timer 2 is configured as a baud rate generator, its clock source is Osc/2. Timer 1 must be configured as an 8-bit timer (TL1) with auto reload with TH1 value when an overflow occurs (Mode 2). In this application, the Timer 1 interrupt should be disabled. The two following formulas can be used to calculate the baud rate and the reload value to put in the TH1 register. Mode 1,3 Baud Rate = 2SMOD x Fosc 32 x 12(256 – TH1) 1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4 Tel: (514) 871-2447 http://www.goalsemi.com 24 VERSA Datasheet Rev 1.3 VRS700 The following formula can be used to calculate the baud rate in modes 1 and 3 using the Timer 2: Modes 1, 3 Baud Rate = Oscillator Frequency 32x[65536 – (RCAP2H, RCAP2L)] The formula below is used to define the reload value to put into the RCAP2h, RCAP2L registers to achieve a given baud rate. (RCAP2H, RCAP2L) = 65536 - Fosc 32x[Baud Rate] In the above formula, RCAP2H and RCAP2L are the content of RCAP2H and RCAP2L taken as a 16-bit unsigned integer. Note that a rollover in TH2 does not set TF2, and will not generate an interrupt. Because of this, the Timer 2 interrupt does not have to be disabled when Timer 2 is configured in baud rate generator mode. Also, if EXEN2 is set, a 1-to-0 transition in T2EX will set EXF2 but will not cause a reload from RCAP2x to Tx2. Therefore, when Timer 2 is used as a baud rate generator, T2EX can be used as an extra external interrupt. Furthermore, when Timer 2 is running (TR2 is set to 1) as a timer in baud rate generator mode, the user should not try to read or write to TH2 or TL2. When operating under these conditions, the timer is being incremented every state time and the results of a read or write command may be inaccurate. The RCAP2 registers, however, may be read but should not be written to, because a write may overlap a reload operation and generate write and/or reload errors. In this case, before accessing the Timer 2 or RCAP2 registers, be sure to turn the timer off by clearing TR2. 1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4 Tel: (514) 871-2447 http://www.goalsemi.com 25 VERSA Datasheet Rev 1.3 VRS700 INTERRUPTS The VRS700 has 8 interrupt sources (9 if we include the WDT) and 7 interrupt vectors (including reset) to handle them. The interrupt can be enabled via the IE register shown below: TABLE 23: I E I NTERRUP T EN ABLE REGISTER –SFR A8H Interrupt Vectors Table 24 specifies each interrupt source, its flag and its vector address. TABLE 24: I NTERRUP T VECTOR A DDRESS Interrupt Source RESET (+ WDT) INT0 Timer 0 INT1 Timer 1 Serial Port Timer 2 Flag WDR IE0 TF0 IE1 TF1 RI+TI TF2+EXF2 EA 7 6 - ET2 5 ES 4 ET1 3 EX1 2 ET0 1 EX0 0 Bit 7 Mnemonic EA Description Disables All Interrupts 0: no interrupt acknowledgment 1: Each interrupt source is individually enabled or disabled by setting or clearing its enable bit. Reserved Timer 2 Interrupt Enable Bit Serial Port Interrupt Enable Bit Timer 1 Interrupt Enable Bit External Interrupt 1 Enable Bit Timer 0 Interrupt Enable Bit External Interrupt 0 Enable Bit Vector Address 0000h* 0003h 000Bh 0013h 001Bh 0023h 002Bh 5 4 3 2 1 0 6 ET2 ES ET1 EX1 ET0 EX0 - * If location 0000h = FFh, the PC jump to the ISP program. External Interrupts The VRS700 has two external interrupt inputs named INT0 and INT1. These interrupt lines are shared with P3.2 and P3.3. The bits IT0 and IT1 of the TCON register determine whether the external interrupts are level or edge sensitive. IF ITx = 1, the interrupt will be raised when a 1-> 0 transition occurs at the interrupt pin. The duration of the transition must be at least equal to 12 oscillator cycles. The following figure (Figure 19) illustrates the various interrupt sources on the VRS700. FIGURE 19: I NTERRUP T SOURCES INT0 IT0 IE0 IF ITx = 0, the interrupt will occur when a logic Low condition is present on the interrupt pin. TF0 INT1 IT1 IE1 INTERRUPT SOURCES The state of the external interrupt, when enabled, can be monitored using the flags, IE0 and IE1 of the TCON register that are set when the interrupt condition occurs. In the case where the interrupt was configured as edge sensitive, the associated flag is automatically cleared when the interrupt is serviced. If the interrupt is configured as level sensitive, then the interrupt flag must be cleared by the software. TF1 T1 RI TF2 EXF2 1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4 Tel: (514) 871-2447 http://www.goalsemi.com 26 VERSA Datasheet Rev 1.3 VRS700 Timer 0 and Timer 1 Interrupt Both Timer 0 and Timer 1 can be configured to generate an interrupt when a rollover of the timer/counter occurs (except Timer 0 in Mode 3). The TF0 and TF1 flags serve to monitor timer overflow occurring from Timer 0 and Timer 1. These interrupt flags are automatically cleared when the interrupt is serviced. Execution of an Interrupt When the processor acknowledges an enabled interrupt request, the processor automatically saves the return address (of the next instruction) on the stack and goes to the associated interrupt vector address where a jump to the interrupt routine (or the interrupt Service routine itself) is defined. In the process, an internal flag is set to indicate that an interrupt is taking place. An interrupt subroutine must always end with the RETI instruction. This instruction allows the processor to retrieve the return address previously placed on the stack. The RETI instruction also allows updating of the internal flag that will take into account an interrupt with the same priority. T imer 2 interrupt Timer 2 interrupt can occur if TF2 and/or EXF2 flags are set to 1 and if the Timer 2 interrupt is enabled. The TF2 flag is set when a rollover of Timer 2 Counter/Timer occurs. The EXF2 flag can be set by a 1->0 transition on the T2EX pin by the software. Note that neither flag is cleared by the hardware upon execution of the interrupt service routine. The interrupt service routine may have to determine whether it was TF2 or EXF2 that generated the interrupt and cleared it manually. Every bit that generates interrupts can either be cleared or set by the software, yielding the same result as when the operation is done by the hardware. In other words, pending interrupts can be cancelled and interrupts can be generated by the software. Interrupt Enable and Interrupt Priority When the VRS700 is initialized, all interrupt sources are inhibited by the bits of the IE register being reset to 0. It is necessary to start by enabling the interrupt sources that the application requires. This is achieved by setting bits in the IE register, as discussed previously. This register is part of the bit addressable internal RAM. For this reason, it is possible to modify each bit individually in one instruction without having to modify the other bits of the register. Setting EA to 0 inhibit all interrupts. The order in which interrupts are serviced is shown in the following table: TABLE 25: I NTERRUP T PRIORITY Serial Port Interrupt The serial port can generate an interrupt when the reception of a byte completes or once a byte transmission is completed. Those two conditions share the same interrupt vector and it is up to the interrupt service routine to find out what caused the interrupt by looking at the serial interrupt flags RI and TI. Note that neither of these flags is cleared by the hardware upon execution of the interrupt service routine. The interrupt service routine must define which of RI or TI flags caused the interrupt and clear it manually. Interrupt Source RESET + WDT (Highest Priority) IE0 TF0 IE1 TF1 RI+TI TF2+EXF2 (Lowest Priority) 1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4 Tel: (514) 871-2447 http://www.goalsemi.com 27 VERSA Datasheet Rev 1.3 VRS700 Modifying the Order of Priority The VRS700 allows the user to modify the natural priority of the interrupts. One may modify the order by programming the bits in the IP (Interrupt Priority) register. When any bit in this register is set to 1, it gives the corresponding source a greater priority than interrupts coming from sources that don’t have their corresponding IP bit set to 1. The IP register is represented in the table below. TABLE 26: I P I NTERRUP T PRIORITY REGISTER – SFR B8H sequentially written into the WDTKEY register. See the next section for more details. The Watch Dog Timer operation is enabled by setting the WDTE bit to 1. Once WDTE has been set to 1, the 16-bit counter will start to count with the RC oscillator. The user program must then make sure that the watch Dog Timer is cleared periodically before overflow. Otherwise, the WDT will cause a reset of the VRS700. Clearing the WDT is accomplished by setting the CLR bit of the WDTC to 1. This action will clear the contents of the 16-bit counter and force it to restart. The Watch Dog Timer will generate a reset signal if an overflow has taken place. The WDTE bit will be cleared to 0 automatically when VRS700 has been reset by either hardware or a WDT reset. If a WDT caused reset occurs, the WDR bit of the SCONF register will be set to 1. TABLE 27: W ATCH DOG TIM ER REGISTERS : WDTC – SFR 9FH 7 EA 6 - 5 ET2 4 ES 3 ET1 2 EX1 1 ET0 0 EX0 5 4 3 2 1 0 Bit 7 6 P T2 PS P T1 P X1 P T0 P X0 Mnemonic - Description Gives Timer 2 Interrupt Higher Priority Gives Serial Port Interrupt Higher Priority Gives Timer 1 Interrupt Higher Priority Gives INT1 Interrupt Higher Priority Gives Timer 0 Interrupt Higher Priority Gives INT0 Interrupt Higher Priority 7 WDTE 6 Unused Mnemonic WDTE Unused CLR Unused PS2 PS1 PS0 5 CLR 4 3 Unused 2 PS2 1 PS1 0 PS0 Watch Dog Timer The Watch Dog Timer (WDT) is a 16-bit free-running counter that generates a reset signal if the counter overflows. The WDT is useful for systems that are susceptible to noise, power glitches and other conditions that might cause the software to go into infinite loops or runaways. The WDT function gives the user software a recovery mechanism from abnormal software conditions. The WDT is different from Timer 0, Timer 1 and Timer 2 of the standard 80C52. Once the WDT is enabled, the user software must clear it periodically. In the case where the WDT is not cleared, its overflow will trigger a reset of the VRS700. The user should check the WDR bit of the SCONF register whenever an unpredicted reset has taken place. The VRS700 provides an on-chip RC oscillator running at approximately 250KHz. This oscillator is independent of the system clock. Note: T he Watch Dog Timer operation is controlled by the WDTC register and the WDTKEY register. By default, the WDTC register is Read Only. Writing into it is possible after the values 1Eh and E1h have been Bit 7 6 5 [4:3] 2 1 0 Description Watch Dog Timer Enable Bit Watch Dog Timer Counter Clear Bit Clock Source Divider Bit 2 Clock Source Divider Bit 1 Clock Source Divider Bit 0 The WDT timeout delay is adjustable from 2ms to 262ms. The value of the PS2, PS1 and PS0 bits of the WDTC register define the timeout value, as shown in Table 28 below. TABLE 28: TIME PERIOD AT 250K HZ PS [2:0] Divider (OSC in) Overflow Period (ms) 0 00 0 01 0 10 0 11 1 00 1 01 1 10 1 11 128 64 32 16 8 4 2 1 2.048 4.096 8.192 16.384 32.768 65.536 131.072 262.144 1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4 Tel: (514) 871-2447 http://www.goalsemi.com 28 VERSA Datasheet Rev 1.3 VRS700 Watch Dog Key Register (WDTKEY, 97h) As an extra security feature, the WDTC register is “Read-Only” by default. In order to write a value into the WDTC register, the user must write values 1Eh and E1h (sequentially) to enable the WDTC Write attribute. This may be accomplished by the following two lines of code: MOV WDTKEY, #1EH MOV WDTKEY, #E1H Once the WDTC is set, the user must write 1Eh and E1h (sequentially) to the WDTKEY (97h) register to disable the WDTC write attribute. This may be accomplished by the following two lines of code: MOV WDTKEY, #E1H MOV WDTKEY, #1EH The table below represents the Watch Dog key register. TABLE 29: W ATCH DOG KEY REGISTER (WDTKEY) – SFR 97H 7 WDTKEY7 3 WDTKEY3 6 WDTKEY6 2 WDTKEY2 5 WDTKEY5 1 WDTKEY1 4 WDTKEY4 0 WDTKEY0 1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4 Tel: (514) 871-2447 http://www.goalsemi.com 29 VERSA Datasheet Rev 1.3 VRS700 Specific Pulse Width Modulation (SPWM) The VRS700 has 8 PWM channels shared with the Port1 pins. Each channel can be configured to operate with a resolution of 5 bits or 8 bits. The PWM time base is derived from the oscillator frequency. Two SFR registers, SPWMCx and SPWMDx, are associated to each PWM channel. The SPWMCx register controls the resolution of the PWM output and its frequency and the SPWMDx register controls the duty cycle of the output. SPWM Control Registers – SPWMCx, Each one of the VRS700’s eight SPWMs has an independent control register. The addresses of these registers are provided in the table below. TABLE 31: SPWM CONTROL REGISTERS ADDRESSES SPWM Enable Register SPWME To activate the PWM channels, the corresponding bit in the SPWME Register must be set to 1. TABLE 30: SPWM ENABLE REGISTER SFR 9BH SPWM SPWM SPWM SPWM SPWM SPWM SPWM SPWM Control register Control register Control register Control register Control register Control register Control register Control register 0 1 2 3 4 5 6 7 Address D3h D4h D5h D6h DBh DCh DDh DEh 7 SPWM7E 3 SPWM3E Bit 7 6 5 4 3 2 1 0 Mnemonic SPWM7E SPWM6E SPWM5E SPWM4E SPWM3E SPWM2E SPWM1E SPWM0E 6 SPWM6E 2 SPWM2E 5 SPWM5E 1 SPWM1E 4 SPWM4E 0 SPWM0E The table below shows the configuration of a given SPWM control register. TABLE 32: SPWM CONTROL REGISTER CONFIGURA TION 7 Description Set to 1 to Enable Set to 1 to Enable Set to 1 to Enable Set to 1 to Enable Set to 1 to Enable Set to 1 to Enable Set to 1 to Enable Set to 1 to Enable PWM channel 7 PWM channel 6 PWM channel 5 PWM channel 4 PWM channel 3 PWM channel 2 PWM channel 1 PWM channel 0 3 Unused Bit 7 6 5 4 3 2 Mnemonic Unused Unused Unused Unused Unused PBSx 6 2 PBS[7:0] Unused 5 4 0 PFS[7:0]0 1 PFS[7:0]1 1 PFSx1 0 PFSx0 *X = 0 to 7 (8 PWM) Description This bit determines the channel bit resolution 1: 5-bit channel resolution 0: 8-bit channel resolution Used to set the input clock frequency divider. (See table below for details) 1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4 Tel: (514) 871-2447 http://www.goalsemi.com 30 VERSA Datasheet Rev 1.3 VRS700 The following table shows the relationship between the values of PFSx1 and PFSx0 and the value of the divider. Numerical values of the corresponding frequencies are also provided for a 10MHz & 20MHz oscillator. TABLE 33: RELATIONSHIP BETWEEN PFS AND THE DIVIDER PFS[7:0]1 PFS[7..0]0 Divider SPWM clock, Fosc=12MHz SPWM clock, F osc=20M Hz 0 0 1 1 0 1 0 1 0.5 1 2 4 20MHz 10MHz 5MHz 2.5MHz 40MHz 20MHz 10MHz 5MHz SPWM Data Registers The value put into the SPWM data register determines the duty cycle of the SPWM output waveform. There are 8 SPWM data registers in total. The table below gives the SFR address used by each of them. TABLE 34: SPWMS DATA REGISTERS ADDRESSES SPWM SPWM SPWM SPWM SPWM SPWM SPWM SPWM Data register Data register Data register Data register Data register Data register Data register Data register 0 1 2 3 4 5 6 7 Address B3h B4h B5h B6h BBh BCh BDh BEh Note: When a given SPWM is configured to operate with a resolution of 5 bits (PBSx =1), its corresponding data register only uses the 5 least significant bits. 1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4 Tel: (514) 871-2447 http://www.goalsemi.com 31 VERSA Datasheet Rev 1.3 VRS700 Example of SPWM Timing Diagram FIGURE 20: SPWM TIM ING DIAGRAM 5-BIT RESOLUTION CH ANNEL M=00h M=01h M=0Fh M=1Fh 32T Note: M = Content of SPWMDx SPWM clock frequency = 1/T = Fosc/Divider The SPWM output cycle frame frequency = SPWM clock frequency / 32 FIGURE 21: SPWM TIM ING DIAGRAM 8-BIT RESOLUTION CHA NNEL M=00h M=01h M=7Fh M=FFh 256T Note: M = Content of SPWMDx SPWM clock frequency = 1/T = Fosc/Divider The SPWM output cycle frame frequency = SPWM clock frequency / 256 1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4 Tel: (514) 871-2447 http://www.goalsemi.com 32 VERSA Datasheet Rev 1.3 VRS700 Crystal consideration The crystal connected to the VRS700 oscillator input should be of a parallel type operating in fundamental mode. The following table shows the value of the capacitors and the feedback resistor that must be used at different operating frequencies. Valid for VRS700 XTAL 3MHz C1 30 p C2 30 p R o pen XTAL C1 C2 R 12MHz 30 p 30 p o pen 6MHz 30 p 30 p open 16MHz 30 pF 30 pF open 9MHz 30 p 30 p open 23MHz 15 pF 15 pF 62K Crystals or ceramic resonator characteristics vary from one manufacturer to the other. The user should check the specific crystal or ceramic resonator technical literature available or contact the manufacturer to select the appropriate values for the external components. XTAL1 XTAL VRS700 XTAL2 R C1 C2 Note: Oscillator circuits may differ with different crystals or ceramic resonators in higher oscillation frequency. 1134 Ste Catherine Street West, Suite 900, Montreal, Quebec, Canada H3B 1H4 Tel: (514) 871-2447 http://www.goalsemi.com 33 VERSA Datasheet Rev 1.3 VRS700 Operating Conditions TABLE 35: OPERATING CONDI TIONS Symbol TA TS VCC3 F osc 25 Description Operating temperature Storage temperature S upply voltage Oscillator Frequency Min. 0 -55 3 3.0 Typ. 25 25 3.3 23 Max. 70 155 3.6 23 Unit ºC ºC V MHz Remarks Ambient temperature under bias DC Characteristics TABLE 36: DC CHARA C TERISTICS S ymbol V IL1 V IL2 V IH1 V I H2 VOL1 VOL2 VOH1 VOH2 IIL Parameter Input Low Voltage Input Low Voltage Input High Voltage Input High Voltage Output Low Voltage O utput Low Voltage Output High Voltage O utput High Voltage Logical 0 Input Current L ogical Transition Current Input Leakage Current Reset Pull-down Resistance Pin Capacitance Valid P o r t 0 ,1,2,3,4,#EA RES, XTAL1 P o r t 0,1,2,3,4,#EA RES, XTAL1 Port 0, ALE, #PSEN P o r t 1,2,3,4 Port 0 Port 1,2,3,4,ALE,#PSEN P o r t 1,2,3,4 P o r t 1,2,3,4 P o r t 0, #EA RES Min. -0.5 0 2.0 70% VCC Max. 1.0 0 .8 VCC+0.5 VCC+0.5 0.45 0.45 2 .4 90%VCC 2 .4 90% VCC -75 -650 + 10 50 300 10 15 10 7 .5 6 150 Unit V V V V V V V V V V uA uA uA Kohm pF mA mA mA mA uA Test Conditions VCC =3.3V VCC =3.3V VCC =3.3V VCC =3.3V IOL=3.2mA IOL=1.6mA IOH=-800uA IOH=-80uA IOH=-60uA IOH=-10uA Vin=0.45V Vin=2.O V 0.45V< Vin