AN221E04

AN221E04 Datasheet Dynamically Reconfigurable FPAA With Enhanced I/O www.anadigm.com DS030100-U006a -1- Disclaimer Anadigm reserves the right to make any changes without further notice to any products herein. Anadigm makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Anadigm assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including with out limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Anadigm does not in this document convey any license under its patent rights nor the rights of others. Anadigm software and associated products cannot be used except strictly in accordance with an Anadigm software license. The terms of the appropriate Anadigm software license shall prevail over the above terms to the extent of any inconsistency. © Anadigm® Ltd. 2003 © Anadigm®, Inc. 2003 All Rights Reserved. DS030100-U006a -2- AN221E04 Datasheet – Dynamically Reconfigurable FPAA With Enhanced I/O PRODUCT AND ARCHITECTURE OVERVIEW The AN221E04 device consists of a 2x2 matrix of fully Configurable Analog Blocks (CABs), surrounded by a fabric of programmable interconnect resources. Configuration data is stored in an on-chip SRAM configuration memory. Compared with the first-generation FPAAs, the Anadigmvortex architecture provides a significantly improved signal-to-noise ratio as well as higher bandwidth. These devices also accommodate nonlinear functions such as sensor response linearization and arbitrary waveform synthesis. The AN221E04 device features an advanced input/output structure that allows the FPAA to be programmed with up to six outputs – or triple the number provided by the ANx20E04 devices. The AN221E04 devices have four configurable I/O cells and two dedicated output cells. For I/O-intensive applications, this means a single FPAA can now be used to process multiple channels of analog signals where two or more such devices were previously needed. In addition, the AN221E04 devices allow designers to implement an integrated 8-bit analog-to-digital converter on the FPAA, eliminating the potential need for an external converter. Using this new device, designers can route the digital output of the A/D converter off-chip using one of the dedicated output cells. Figure 1: Architectural overview of the AN221E04 device With dynamic reconfigurability, the functionality of the AN221E04 can be reconfigured in-system by the designer or on-the-fly by a microprocessor. A single AN221E04 can thus be programmed to implement multiple analog functions and/or to adapt on-the-fly to maintain precision operation despite system degradation and aging. PRODUCT FEATURES • • • • • • • • • • • • • • Dynamic reconfiguration Four configurable I/O cells, two dedicated output cells 8-bit SAR analog–to–digital converter Fully differential architecture Fully differential I/O buffering with options for single ended to differential conversion Low input offset through chopper stabilized amplifiers 256 Byte Look-Up Table (LUT) for linearization and arbitrary signal generation 4:1 Input multiplexer Typical Signal Bandwidth: DC-2MHz (Bandwidth is CAM dependent) Signal to Noise Ratio: o Broadband 80dB o Narrowband (audio) 100dB Total Harmonic Distortion (THD): 80dB DC offset