AU6391

1 Data Book AU6391 USB2.0 to ATA/ATAPI Bridge Controller Technical Reference Manual Product Specification Official Release Revision 1.00W Public Feb 2007 Data book status Objective specification Preliminary specification Product specification This data book contains target specifications for product development. This data book contains preliminary supplementary data may be published later. data; This data book contains final product specifications. Revision History Date Feb 2007 Revision 1.00W Initial release Description Page 2 of 22 AU6391 USB2.0 to ATA/ATAPI Bridge Controller V1.00W Official Release _ Public Copyright Notice Copyright 1997 - 2007 Alcor Micro Corp. All Rights Reserved. Trademark Acknowledgements The company and product names mentioned in this document may be the trademarks or registered trademarks of their manufacturers. Disclaimer Alcor Micro Corp. reserves the right to change this product without prior notice. Alcor Micro Corp. makes no warranty for the use of its products and bears no responsibility for any error that appear in this document. Specifications are subject to change without prior notice. Contact Information: Web site: http://www.alcormicro.com/ Taiwan Alcor Micro Corp. 4F, No 200 Kang Chien Rd., Nei Hu, Taipei, Taiwan, R.O.C. Phone: 886-2-8751-1984 Fax: 886-2-2659-7723 China ShenZhen Office Rm.2407-08, Industrial Bank Building No.4013, Shennan Road ,ShenZhen,China. 518026 Phone: (0755) 8366-9039 Fax: (0755) 8366-9101 Santa Clara Office 2901 Tasman Drive, Suite 206 Santa Clara, CA 95054 USA Phone: (408) 845-9300 Fax: (408) 845-9086 Los Angeles Office 9070 Rancho Park Court Rancho Cucamonga, CA 91730 USA Phone: (909) 483-9900 Fax: (909) 944-0464 Page 3 of 22 AU6391 USB2.0 to ATA/ATAPI Bridge Controller V1.00W Official Release _ Public Table of Contents 1 Introduction…………………………………………………………….. 1.1 Description…………………………………………………………………………….. 1.2 Features…………………………………………………………………………………. 2 Application Block Diagram…………………………………………. 3 Pin Assignment………………………………………………………… 6 6 6 7 8 4 System Architecture and Reference Design………………….. 14 4.1 AU6391 Block Diagram…………………………………………………………. 14 5 Electrical Characteristics…………………………………………… 15 5.1 Absolute Maximum Ratings………………………………………………….. 15 5.2 Recommended Operating Conditions…………………………………… 5.4 DC Electrical Characteristics for 5 volts operation……………… 15 16 5.3 General DC Characteristics…………………………………………………… 15 5.5 USB Transceiver Characteristics…………………………………………… 17 6 Mechanical Information……………………………………………… 20 7 Abbreviations…………………..……………………………………… 21 Page 4 of 22 AU6391 USB2.0 to ATA/ATAPI Bridge Controller V1.00W Official Release _ Public List of Figures 2.1 Block Diagram………………………………………………………………………………….. 3.1 GBL bonding Pin Assignment Diagram…………………………………………….. 7 8 3.2 GEL bonding Pin Assignment Diagram……………………………………………. 11 4.1 AU6391 Block diagram……………………………………………………………………… 14 6.1 Mechanical Information Diagram…………………………………………………….. 20 List of Tables 3.1 3.2 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 GBL bonding Pin Descriptions……………………………………………………... 9 GEL bonding Pin Descriptions……………………………………………………… 12 Absolute Maximum Ratings…………………………………………………………. 15 Recommended Operating Conditions………………………………………….. 15 General DC Characteristics………………………………………………………….. 15 DC Electrical Characteristics of 3.3V I/O Cells……………………… 16 Recommended Operation Conditions………………………………………….. 17 Static characteristic：Digital in ………………………………………………….. 17 Static characteristic：Analog I/O pins（DP/DM）………………………… 18 Dynamic characteristic：Analog I/O pins（DP/DM）…………………… 19 Page 5 of 22 AU6391 USB2.0 to ATA/ATAPI Bridge Controller V1.00W Official Release _ Public 1.0 Introduction 1.1 Description The AU6391 is a single chip controller designed for bridgingg USB 2.0 to ATA/ATAPI bus interface. It is used as the primary controller of building an external USB 2.0 hard disk or CD/DVD drives. To maximize the data throughput and achieve the best compatibility, AU6391 is equipped with Alcor’s proprietary automatic speed negotiation (ASN) algorithm. The ASN algorithm allows AU6391 to select optimized operating mode that device can best support a reliable data transfer from PIO mode 0~4 and Ultra DMA mode 2/4. The silicon would work with the default device driver from Windows ME, Windows 2000, Windows XP and Mac OS X, however, vendor device driver provided by Alcor Micro would enable the built device working under Windows 98, Windows 2000 (SP1/SP2) and Mac OS 9. 1.2 Features Supports USB 2.0 specification and USB Device Class Definition for Mass Storage, Bulk-Transport V1.0 Supports ATA/ATAPI-6 specification Revision 1.0 PIO mode 0~4 UDMA mode 2/4 Supports ATA/ATAPI device configured in master or slave mode Supports 48-bit addressing for large capacity hard drive Hardware DMA engine integrated inside for performance enhancement Works with default device driver from Windows ME/2000/XP and Mac OS X. One spared LED pin for disk access indication Built-in voltage regulator 48-pin LQFP package Page 6 of 22 AU6391 USB2.0 to ATA/ATAPI Bridge Controller V1.00W Official Release _ Public 2.0 Application Block Diagram The following picture is an application diagram of a typical removable USB2.0 ATA/ATAPI device. With such kinds of devices, users can exchange recorded digital content between ATA/ATAPI device and PC (Notebook) via USB. 2.1 Block Diagram PC with USB Host Controller HD AU6391 CD-ROM, CD-R/W DVD-ROM, VCD-R/W Page 7 of 22 AU6391 USB2.0 to ATA/ATAPI Bridge Controller V1.00W Official Release _ Public 3.0 Pin Assignment There are two different form factor packages available to choose from. The following figure shows signal names for each pin and the table in the page after describes each pin in details. Figure 3.1 GBL bonding Pin Assignment Diagram ATADMACKN ATADATA15 ATADATA14 ATADATA13 ATADATA12 ATADMARQ 48 GNDU VDDU DM DP REXT VDD33 VSS33P VSSA XI XO VDDA GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 AVDD5V ATADIOWN 47 VDD3V ATADIORN 46 V18 45 AU6391 USB2.0 to ATA/ATAPI Bridge Controller V1.00W ATAIORDY ATAAD2 ATAINTRQ ATACS1N ATACS0N 44 43 42 41 40 39 38 37 36 ATADATA11 ATADATA10 ATADATA9 ATADATA8 ATADATA7 ATADATA6 ATADATA5 ATADATA4 ATADATA3 ATADATA2 ATADATA1 ATADATA0 35 34 33 32 ALCOR MICRO AU6391-GBL 48PIN LQFP 31 30 29 28 27 26 25 ATAAD1 ATAAD0 ATARESETN EEPDATA EEPCLK GPI3 CHIPRESETN GPON7 Page 8 of 22 Official Release _ Public Table 3.1 GBL bonding Pin Descriptions Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Pin Name GNDU VDDU DM DP REXT VDD33 VSS33P VSSA XI XO VDDA GND AVDD5V VDD3V V18 ATAAD2 ATAAD1 ATAAD0 ATARESETN EEPDATA EEPCLK GPI3 CHIPRESETN GPON7 I O PWR O O O O B B I I O I/O PWR PWR I/O I/O I PWR PWR PWR I O PWR Description GND for UTMI Power Power for UTMI core USB DM USB DP Connect pull-low resistor for impedance match UTMI power 3.3V UTMI power GND Analog GND 12 MHz crystal input. 12 MHz crystal output. Analog 1.8V power GND for IO pad 5V power supply input 3.3V Power Out 1.8 V output for core power ATA Address bus 2 ATA Address bus 1 ATA Address bus 0 ATA Reset EEPDATA EEPCLK GPI for customized software triggle Reset (low active to reset the whole chip), must be pull up with RC. LED indicator Page 9 of 22 AU6391 USB2.0 to ATA/ATAPI Bridge Controller V1.00W Official Release _ Public Pin # 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Pin Name ATADATA0 ATADATA1 ATADATA2 ATADATA3 ATADATA4 ATADATA5 ATADATA6 ATADATA7 ATADATA8 ATADATA9 ATADATA10 ATADATA11 ATACS0N ATACS1N ATADATA12 ATADATA13 ATADATA14 ATADATA15 ATAINTRQ ATADMACKN ATAIORDY ATADIORN ATADIOWN ATADMARQ I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O O I/O I/O I/O I/O I O I O O I ATA Data Bus 0 ATA Data Bus 1 ATA Data Bus 2 ATA Data Bus 3 ATA Data Bus 4 ATA Data Bus 5 ATA Data Bus 6 ATA Data Bus 7 ATA Data Bus 8 ATA Data Bus 9 ATA Data Bus 10 ATA Data Bus 11 ATA Chip Select0 ATA Chip Select1 ATA Data Bus 12 ATA Data Bus 13 ATA Data Bus 14 ATA Data Bus 15 Description ATA Interput request ATA Control Signal DMACKN ATA Control Signal IORDY ATA Control Signal DIORN ATA Control Signal DIOWN ATA Control Signal DMARQ Page 10 of 22 AU6391 USB2.0 to ATA/ATAPI Bridge Controller V1.00W Official Release _ Public The following figure shows signal names of each pin of the 48-pin package and the table in the page after describes each pin in details. Figure 3.1 GEL bonding Pin Assignment Diagram ATADMACKN ATADATA15 ATADATA14 ATADATA13 ATADATA12 ATADMARQ 48 GNDU VDD VDDU DM DP REXT VDD33 VSS33P VSSA XI XO VDDA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 AGND5V ATADIOWN 47 AVDD5V ATADIORN 46 VDD3V 45 AU6391 USB2.0 to ATA/ATAPI Bridge Controller V1.00W ATAIORDY V18 ATAINTRQ ATACS1N ATACS0N 44 43 42 41 40 39 38 37 36 ATADATA11 ATADATA10 ATADATA9 ATADATA8 ATADATA7 ATADATA6 ATADATA5 ATADATA4 ATADATA3 ATADATA2 ATADATA1 ATADATA0 35 34 33 32 ALCOR MICRO AU6391-GEL 48PIN LQFP 31 30 29 28 27 26 25 VSSHM ATAAD2 ATAAD1 ATAAD0 ATARESETN GPI3 CHIPRESETN GPON7 Page 11 of 22 Official Release _ Public Table 3.1 GEL bonding Pin Descriptions Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Pin Name GNDU VDD VDDU DM DP REXT VDD33 VSS33P VSSA XI XO VDDA AGND5V AVDD5V VDD3V V18 VSSHM ATAAD2 ATAAD1 ATAAD0 ATARESETN GPI3 CHIPRESETN GPON7 ATADATA0 I/O GND PWR PWR I/O I/O I PWR PWR PWR I O PWR GND I O PWR GND O O O O I I O I/O Ground 1.8V Power for UTMI core USB DM USB DP Connect pull-low resistor for impedance match 3.3V UTMI power GND Analog GND 12 MHz crystal input. 12 MHz crystal output. 1.8V Ground 5V Power Source 3.3 V Power Out 1.8 V output for core power Ground ATA Address bus [2] ATA Address bus [1] ATA Address bus [0] ATA Reset General Purpose Input. Reset (low active to reset the whole chip), must be pull up with RC. General Purpose Output. ATA Data Bus [0] Page 12 of 22 AU6391 USB2.0 Description to ATA/ATAPI Bridge Controller V1.00W Official Release _ Public Pin # 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Pin Name ATADATA1 ATADATA2 ATADATA3 ATADATA4 ATADATA5 ATADATA6 ATADATA7 ATADATA8 ATADATA9 ATADATA10 ATADATA11 ATACS0N ATACS1N ATADATA12 ATADATA13 ATADATA14 ATADATA15 ATAINTRQ ATADMACKN ATAIORDY ATADIORN ATADIOWN ATADMARQ I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O O I/O I/O I/O I/O I O I O O I ATA Data Bus [1] ATA Data Bus [2] ATA Data Bus [3] ATA Data Bus [4] ATA Data Bus [5] ATA Data Bus [6] ATA Data Bus [7] ATA Data Bus [8] ATA Data Bus [9] ATA Data Bus [10] ATA Data Bus [11] ATA Chip Select0 ATA Chip Select1 ATA Data Bus [12] ATA Data Bus [13] ATA Data Bus [14] ATA Data Bus [15] Description ATA Interput request ATA Control Signal DMACKN ATA Control Signal IORDY ATA Control Signal DIORN ATA Control Signal DIOWN ATA Control Signal DMARQ Page 13 of 22 AU6391 USB2.0 to ATA/ATAPI Bridge Controller V1.00W Official Release _ Public 4.0 System Architecture and Reference Design 4.1 AU6391 Block Diagram Figure 4.1 AU6391 Block Diagram USB Upstream Port USB XCVR SIE RAM ATA Control FIFO ATA Processor ROM Arbitrator 1.8 V 3.3 V 3.3V and 1.8V Voltage Regulator /Power Switch 5V 12MHz XTAL Page 14 of 22 AU6391 USB2.0 to ATA/ATAPI Bridge Controller V1.00W Official Release _ Public 5.0 Electrical Characteristics 5.1 Absolute Maximum Ratings Table 5.1 Absolute Maximum Ratings SYMBOL VDDHM VIN VOUT TSTG PARAMETER Power Supply Input signal Voltage Output signal Voltage Storage Temperature RATING -0.3 to VDDHM +0.3 -0.3 to 3.6 -0.3 to VDDHM +0.3 -40 to 150 UNITS V V V O C 5.2 Recommended Operating Conditions Table 5.2 Recommended Operating Conditions SYMBOL AVDD5V VDDHM VDD V18 VIN TOPR PARAMETER Power Supply Power Supply Digital Supply Input signal Voltage Operating Temperature MIN 4.75 3.0 1.62 0 0 TYP 5.0 3.3 1.8 3.3 MAX 5.25 3.6 1.98 3.6 70 UNITS V V V V O C 5.3 Leakage Current and Capacitance Table 5.3 General DC Characteristics SYMBOL IIN IOZ CIN COUT CBID PARAMETER Input current Tri-state leakage current Input capacitance Output capacitance Bi-directional buffer capacitance Pad Limit Pad Limit Pad Limit CONDITIONS no pull-up or pull-down MIN -10 -10 TYP ±1 ±1 2.8 2.8 2.8 MAX UNITS 10 10 µA µA ρF ρF ρF Page 15 of 22 AU6391 USB2.0 to ATA/ATAPI Bridge Controller V1.00W Official Release _ Public 5.4 DC Electrical Characteristics of 3.3V I/O Cells Table 5.4 DC Electrical Characteristics of 3.3V I/O Cells Limits SYMBOL PARAMETER CONDITIONS MIN TYP VDDHM Vil Vih Vol Voh Rpu Rpd Iin Ioz Power supply Input low voltage LVTTL Input high voltage Output low voltage Output high voltage Input pull-up resistance ∣Iol∣=2~16mA ∣Ioh∣=2~16mA PU=high, PD=low 2.4 55 40 -10 -10 75 75 ±1 ±1 110 150 10 10 2.0 0.4 V V V KΩ KΩ μA μA 3.3V I/O 3.0 3.0 MAX 3.6 0.8 UNIT V V Input pull-down resistance PU=low, PD=high Input leakage current Tri-state output leakage current Vin= VDDHM or 0 Page 16 of 22 AU6391 USB2.0 to ATA/ATAPI Bridge Controller V1.00W Official Release _ Public 5.5 USB Transceiver Characteristics Table 5.5 Electrical characteristics Symbol VDD33 VDD V18 ICC Parameter Analog supply voltage Digital supply voltage Operating supply current High speed operating at 480 MHz In suspend mode, current with 1.5kΩ Suspend supply current pull-up resistor on pin RPU disconnected Conditions Min. 3.0 1.62 Typ. 3.3 1.8 Max. 3.6 1.98 55 Unit V V mA ICC(susp) 120 µA Table 5.6 Static characteristic：Digital pin Symbol Parameter Conditions Input levels VIL VIH Low-level input voltage High-level input voltage Output levels VOL VOH Low-level output voltage High-level output voltage VDDH*-0.2 0.2 V V 2.0 0.8 V V Min. Typ. Max. Unit Page 17 of 22 AU6391 USB2.0 to ATA/ATAPI Bridge Controller V1.00W Official Release _ Public Table 5.7 Static characteristic：Analog I/O pins（DP/DM） Symbol Conditions Min. USB2.0 Transceiver（HS） Input Levels（differential receiver） ∣VI（DP）-VI（DM）∣ High speed differential measured at the 300 input sensitivity connection as application circuit High speed data signaling common mode voltage -50 range High speed squelch detection threshold High speed disconnection detection threshold Squelch detected No squelch detected Disconnection detected Disconnection not detected Output Levels 150 625 525 Parameter Typ. Max. Unit VHSDIFF mV VHSCM 500 100 mV mV mV mV mV VHSSQ VHSDSC VHSOI VHSOL VHSOH VCHIRPJ VCHIRPK High speed idle level output voltage(differential) High speed low level output voltage(differential) High speed high level output voltage(differential) Chirp-J output voltage （differential） Chirp-K output voltage （differential） -10 -10 -360 700 -900 10 10 400 1100 -500 mV mV mV mV mV RDRV VTERM VDI VCM Resistance Equivalent resistance 3 used as internal chip only Driver output impedance Overall resistance 40.5 including external resistor Termination Termination voltage for 3.0 pull-up resistor on pin RPU USB1.1 Transceiver（FS/LS） Input Levels（differential receiver） Differential input ∣VI（DP）-VI（DM）∣ 0.2 sensitivity Differential common 0.8 mode voltage Input Levels（single-ended receivers） to ATA/ATAPI Bridge Controller V1.00W 6 45 9 Ω 49.5 3.6 V V 2.5 V Page 18 of 22 AU6391 USB2.0 Official Release _ Public VSE VOL VOH Single ended receiver threshold Output levels Low-level output voltage High-level output voltage 0.8 0 2.8 2.0 0.3 3.6 V V V Table 5.8 Dynamic characteristic：Analog I/O pins（DP/DM） Symbol Parameter Conditions Driver Characteristics High-Speed Mode tHSR tHSF High-speed differential rise time High-speed differential fall time Full-Speed Mode tFR tFF tFRMA VCRS CL=50pF；10 to 90﹪ of∣VOH-VOL∣； CL=50pF；90 to 10﹪ Fall time of∣VOH-VOL∣； Excluding the first Differential rise/fall time transition from idle matching（tFR / tFF） mode Excluding the first Output signal crossover transition from idle voltage mode Rise time Low-Speed Mode tLR CL=200pF-600pF； 10 to 90﹪of ∣VOH-VOL∣； CL=200pF-600pF； 90 to 10﹪of Fall time ∣VOH-VOL∣； Excluding the first Differential rise/fall time transition from idle matching（tLR / tLF） mode Excluding the first Output signal crossover transition from idle voltage mode Rise time High-level output voltage 75 300 ns 4 4 90 1.3 20 20 110 2.0 ns ns ％ 500 500 ps ps Min. Typ. Max. Unit V tLF 75 300 ns tLRMA VCRS VOH 80 1.3 2.8 125 2.0 3.6 ％ V V Page 19 of 22 AU6391 USB2.0 to ATA/ATAPI Bridge Controller V1.00W Official Release _ Public 6.0 Mechanical Information Figure 6.1 Mechanical Information Diagram Page 20 of 22 AU6391 USB2.0 to ATA/ATAPI Bridge Controller V1.00W Official Release _ Public 7.0 Abbreviations This chapter lists and defines terms and abbreviations used throughout this specification. SIE ATA UTMI Serial Interface Engine Advanced Technology Attachment USB Transceiver Macrocell Interface Page 21 of 22 AU6391 USB2.0 to ATA/ATAPI Bridge Controller V1.00W Official Release _ Public 【MEMO】 About Alcor Micro, Corp Alcor Micro, Corp. designs, develops and markets highly integrated and advanced peripheral semiconductor, and software driver solutions for the personal computer and consumer electronics markets worldwide. We specialize in USB solutions and focus on emerging technology such as USB and IEEE 1394. The company offers a range of semiconductors including controllers for USB hub, integrated keyboard/USB hub and USB Flash memory card reader…etc. Alcor Micro, Corp. is based in Taipei, Taiwan, with sales offices in Taipei, Japan, Korea and California. Alcor Micro is distinguished by its ability to provide innovative solutions for spec-driven products. Innovations like single chip solutions for traditional multiple chip products and on-board voltage regulators enable the company to provide cost-efficiency solutions for the computer peripheral device OEM customers worldwide. Page 22 of 22 AU6391 USB2.0 to ATA/ATAPI Bridge Controller V1.00W Official Release _ Public