C2472

C2472, C2473 and C24 74 Datasheet RDFC Controllers for Offline Applications ADVANTAGES       Low system component count High average efficiency Low standby power consumption EMI compliance without extra components High isolation & surge voltage withstand High power density in very small size C2474PW1 PDIP-8 C2472PX2 SOT23-6 FEATURES       Highly integrated CMOS control ler IC Low cost package options Drive suitable for low cost bipolar power transistors Resonant switching for high efficiency and low EMI Frequency optimised for power circuit parasitics Protection against overload, over-temperature and under-voltage C2473PX1 SOP-8 APPLICATIONS External AC/DC charger/adaptor (single voltage input) e.g. cordless phones, portable electric tools. Embedded PSU (single voltage input) e.g. set -top boxes, DVD players, audio product s, domestic appliances. OVERVIEW T he C2472, C2473 and C2474 controllers use CamSemi’s Resonant D iscontinuous Forward Converter (RDFC) topology to create a high efficiency, low cost alternative to line-frequency transformer PSUs. B y operating in resonant mode, EMI is greatly reduced, enabling the replacement of linear PSUs in demanding applications such as audio products and cordless phone chargers. T he C2472, C 2473 and C2474 c ontrollers also offer overload protection which is usually associated with more expensive switch mode solutions. VDD Vdd Vdd regulator AUX Switch saturation sensing COL Resonance sensing Base drive CS Current sensing RDFC Control BAS GND Figure 1: Block Diagram of the C 2472, C2473 and C2474 Controller ICs Product data © Cambridge Semiconductor Ltd 2007 Page 1 of 18 DS-1423-0709C 26-Sep-2007 C2472, C2473 and C2474 Datasheet RDFC Controllers for Offline Applications PIN DEFINITIONS Figure 2: C 2472, C2473 and C2474 Pin Assignment (drawings are not t o scale) VDD Pin T he VDD pin supplies power to the controller and is maintained at the correct voltage (nominally 3.3 V) by an internal shunt regulator. COL Pin T he COL pin is used to sense the collector voltage of the primary switching transistor, via a c oupling capacitor, to control the timing and current levels of the signals produced on the BAS pin. CS Pin T he CS pin senses the primary switch current via the current sensing resistor. The voltage sensed on this pin is used to control the operating modes to manage standby and overload protection. Operating characteristics are programmed via two external resistors. AUX Pin T he AUX pin provides the supply current for the internal base driver block. In most applications, the AUX pin is connected to the exter nal supply rail via an NPN transistor and a current-limiting resistor to set the m aximum base current; however, in low power applications the AUX pin can be connected to the VDD pin via the limiting resistor , with some compromise on the standby power consu mption. B AS Pin T he BAS pin switches the external bipolar primary switch transistor on and off. The current supplied to the switch transistor is controlled to minimize the switching losses and thereby help optimize overall system efficiency. GND Pin GND pins provide the ground reference. Where the device has multiple GND pins, all must be connected to a common, low impedance path. Product data © Cambridge Semiconductor Ltd 2007 Page 2 of 18 DS-1423-0709C 26-Sep-2007 C2472, C2473 and C2474 Datasheet RDFC Controllers for Offline Applications TYPICAL APPLICATION CIRCUIT T he C2472, C2473 and C2474 controllers are intended primarily for single input voltage AC/DC applications, such as replac ement of line frequency linear transformer power supplies. T hese versatile controllers support a wide range of applications at low cost. A typical circuit configuration is s hown in Figure 3. Figure 3: Typical RDFC Application Schematic Typical 12 W Charger Performance Input Output Efficiency No-load power input 115 V ac 12 V, 1 A dc > 80% < 150 mW Typical Maximum Application Rated Power Power Switch (Q1) Gain Standard High 115 Vac 20 W 40 W 230 Vac 40 W 60 W Product data © Cambridge Semiconductor Ltd 2007 Page 3 of 18 DS-1423-0709C 26-Sep-2007 C2472, C2473 and C2474 Datasheet RDFC Controllers for Offline Applications PRINCIPLE OF OPERATION Power-Up/Power-Down Sequences T he C2472, C2473 and C2474 controllers are powered via the ir VDD pins. W hen mains voltage is first applied, a small amount of current (I DDSLEEP) is drawn from the rectified mains input via high value start up resistors (Rht1 and Rht2 in Figure 3). W hen the voltage on the VDD pin (VDD) reaches a level VOVDTHR the controller wakes up, demands more supply current (I DDWAKE) and enters the Start-up state (see Figure 4). T he controller stays in Start -up for a short time during which internal circuit bloc ks are enabled and then changes to Active operation. In both Start-up and Active states , the controller uses an internal shunt regulator to regulate the V DD rail v oltage; the regulator is disabled in Sleep. A higher regulation voltage is applied during Start-up (VDDREG(S)) than during Active operation (VDDREG(R)) to help provide s ufficient VDD before the Auxiliary supply from the transformer rises to maintain VDD . If the VDD pin voltage drops below V UVDTHR the controller goes back to Sleep, redu cing the sup ply current demand. The system will restart when input power is restored. T o achieve a smooth power up sequence the VDD reservoir capacitor needs to be large enough to sustain the supply above V UVDTHR over the Start-up period. Figure 4: VDD Pin W aveform (VDD) During Initial Power-up and Power-down State Sleep Description From initial application of power or from Active state if VDD falls below VUVDTHR, the controller changes to Sleep state. Non-essential controller circuits are powered down and the external switching transistor (Q1) is held off. Exit from Sleep state occurs when VDD rises above VOVDTHR and the controller m oves to the Start-up state. W hen the Start-up state is entered, internal controller circuits are activated and power conversion begins (Standby mode – see Table 2). In Start-up the on-chip shunt regulator stabilises VDD to an intermediate value, VDDREG(S). After a preset time, the controller changes from Start-up to Active operation. Converter operation continues, the shunt regulator controls VDD to the lower VDDREG(R). If VDD falls below VUVDTHR the controller ceases converter operation and reverts to Sleep state. Start-up Active T able 1: Summary of RDFC Controller States Product data © Cambridge Semiconductor Ltd 2007 Page 4 of 18 VDDREG(R) VDDREG(S) DS-1423-0709C 26-Sep-2007 C2472, C2473 and C2474 Datasheet RDFC Controllers for Offline Applications Start-up and Active State Power Conversion Modes In the Start-up and Active state s the C2472, C2473 and C2474 ICs have several m odes for controlling pow er conversion that are designed to achieve maximum efficiency and to limit power (current) across a wide range of loads. R efer to T able 2 for a summary of each mode. M ode Standby T ypical Load Range IOUT ≥ 0% to ~20% of rated current Description Standby mode reduces power consumption at low loads. It achieves this by progressively reducing the on-time then by increasing the off-time as the load decreases. As load increases, the converter duty is increased until the controller returns to Normal mode. Typically, mains ripple causes change of operating mode during each m ains half-cycle, with the converter moving to lower-power modes between peaks of the mains voltage. Normal m ode is used for steady state power delivery. During Normal mode the power device switches in a fully resonant m inimum -voltage-switching waveform, with the offtime determined by the transformer resonance (TRES) and the on-time being equal to 75% of the off time. A low level of primary switch current, sensed via the CS pin voltage, causes the controller to change to Standby mode and a high level to Overload m ode. Overload mode is activated at high output loads. In this m ode the on-time of the primary switch is terminated early (before 75% of TRES) when the primary current exceeds a preset maximum, thereby protecting the primary switch and limiting the output current. This results in reduction of the output voltage. Heavy overload (sensed by the on-period of the primary switch reducing below a preset time) causes Foldback m ode to be entered. Foldback mode is entered from the Overload m ode. In this mode the controller reduces the on/off duty cycle to protect the power supply and any connected load by both shortening the on-period and increasing the off-period of the primary switch. Converter cycles continue to maintain auxiliary power to the controller. The controller exits the Foldback mode and enters the Power Burst mode after a fixed number of power conversion cycles. Power Burst mode is entered periodically from Foldback mode in order to restart the power supply output. In Power Burst m ode, the controller operates at maximum delivered power for a set number of power converter cycles. At the end of the burst, if the load is not excessive, the converter goes to Normal mode; otherwise it reverts to Foldback mode. Normal IOUT > ~20% to 100% of rated current Overload IOUT >~100% rated current Foldback VOUT < ~70% rated output Power Burst VOUT < ~70% rated output T able 2: Summ ary of Active Operating Modes W hen the controller goes from Sleep to Start -up state, its power conversion mode is set to Standby. Typically the converter output voltage is low at this time so the primary switch current is high during the first few converter cycles. This causes the operating mode to change quickly to Normal or Overload mode. Product data © Cambridge Semiconductor Ltd 2007 Page 5 of 18 DS-1423-0709C 26-Sep-2007 C2472, C2473 and C2474 Datasheet RDFC Controllers for Offline Applications RDFC Power Supply I-V Characteristic Figure 5 illustrates a typical RDFC power supply characteristic with the various Active state m odes of operation identified. INOM and VNOM are the nominal output voltage and current drawn by the load at the rated power of the application circuit. Figure 5: Typical RDFC Power Supply Characteristic Indicating Different Active M odes of Operation T he exact thresholds for transition between modes depend on specific application characteristics, controller internal clock frequency ( FCLK) and CS pin thresholds (VOCPH and VOCPL). T hese parameters and their effect s are explained later. Product data © Cambridge Semiconductor Ltd 2007 Page 6 of 18 DS-1423-0709C 26-Sep-2007 C2472, C2473 and C2474 Datasheet RDFC Controllers for Offline Applications Switching Waveforms T he collector voltage (VCE) and current (IC) waveforms of the primary switching transistor (Q1 in Figure 3) are shown in F igure 6. T RES is the duration of the transformer resonance during the off period. Note that i n Overload m ode, the primary switch Q1 is turned off when the current exceeds the protection level OCPH (sensed by the CS pin voltage). O verload St an dby Nor mal Figure 6: T ypical Switch (Q1) Collector Voltage (VCE) and Current (IC) W aveforms Product data © Cambridge Semiconductor Ltd 2007 Page 7 of 18 DS-1423-0709C 26-Sep-2007 C2472, C2473 and C2474 Datasheet RDFC Controllers for Offline Applications Resonance Control T he natural resonance of the transformer and associated components is deduced from the current flowing into and out of the COL pin via the collector coupling capacitor. T he voltage sensed on the COL pin is used to control saturation of the primary switch transistor (Q1 in Figure 3) during the on-period (see “Optimised Base Drive ”). During the off -period, timing of the resonance is detected via the current in and out of the pin , which has a low impedance path to GND during th is time. Rate of change of voltage at the transformer primary causes current into or out of the COL pin, which is processed to measure the resonance period T RES and to find the optimum turn -on time for the following conversion c ycle. T he resonant period is also used to determine the maximum on -time of the primary switch transistor , so that T ON = 0.75 x T RES T he maximum duty cycle (DNORMAL) is therefore nominally 4 3%. On-time of the switch is controlled to manage power delivery and is reduced in both low -load and overload conditions. The minimum on -time in overload is determined by the internal CS blanking, specified as T CSBLANK. At turn -on of the primary switching transistor, its collector voltage can fall very rapidly, with correspondingly large current out of or in to the COL pin via the coupling capacitor (Ccol). An on-chip c lamp transistor, controlled by an internal signal called ACTICLAMP, provides a low resis tance path to GND. This transistor is turned on shortly before turn -on of the primary switch and remains on until time T ACT after turn -on of the primary switch. It is then turn ed off during the remainder of the primary switch on -period. In some applications, the current through the coupling capacitor may develop sufficient voltage across the clamp transistor to cause conduction of the ESD protection diodes. This is permissible up to a limit ICOL which is specified in ABSOLUTE MAXIMUM RATINGS . If , due to application design, the capacitor current could exceed this level, external protection diodes and a resistor must be provided ( Dcol1, Dcol2 and Rcol in Figure 3). Product data © Cambridge Semiconductor Ltd 2007 Page 8 of 18 DS-1423-0709C 26-Sep-2007 C2472, C2473 and C2474 Datasheet RDFC Controllers for Offline Applications Optimised Base Drive T o minimize losses in the primary switching transistor (Q1) its base current is carefully controlled . To m inimize turn -on losses, the base current is initially forced to a maximum value I BASMAX for a time T FON (the force-on or “FON” pulse) . For the remainder of the on -time the b ase current is reduced to a lower value such that the on -state collector voltage is maintained at a preset target voltage, thereby m inimizing turn-off time and consequent losses. During this period, T PBD, the so called “proportional base drive” (PBD) current is referred to as IBASPBD. Aux Supply Bypass transistor Raux AUX Qon PBD FON BAS Q1 T PBD Qoff GND 0V Figure 7: Primary Switch (Q1) Base Drive T he BAS pin (see F igure 7) is driven by two transistors, Qon and Qoff. Qon provides I BASMAX during T FON and IBASPBD during the remainder of the on -period. Transistor Qoff provides a low -resistance (RBASCLAMP) path to GND during the off-period to ensure rapid turn -off of the primary switch, Q1. I BASPBD is set by the P BD system within the controller but IBASMAX is determine d by the external resistor Raux and the Aux Supply voltage. IBASMAX IBAS VCE T FON T PBD Figure 8: Base Driver Current Waveforms Product data © Cambridge Semiconductor Ltd 2007 Page 9 of 18 DS-1423-0709C 26-Sep-2007 C2472, C2473 and C2474 Datasheet RDFC Controllers for Offline Applications IBASPBD is controlled by monitoring the voltage at the COL pin during T PBD; base curren t is increased progressively as VCOL rises above threshold V CREF(see Figure 9). T he desired on-state VCE of the switching transistor is set b y capacitors Cp and Ccol (see Figure 3), the COL pin capacitanc e (CINCOL) and VCREF. IB A S P B D V C R EF VC O L Figure 9: IBASPBD characteristic Power Control Load conditions are sensed on a cycle-by-cycle basis via the CS pin. When low levels of output power demand are detected, the controller progressively reduces the switching duty cycle to reduce power consumption and to improve output voltage regulation. Power demand causes increase in duty up to the m aximum, or until Overload is detected. T he voltage at the CS pin is compared to two thresholds, one nominally a t GND voltage (VOCPL) to generate an internal s ignal OCPL and the other at a negative threshold (VOCPH) to generate an internal signal OCPH. T he controller samples OCPL a short time (T OCPL) after turn -on of the primary switch . A negative voltage at the CS pin indicates power demand so the controller increases the switching duty up to the maximum; conversely a positive voltage causes a decrease in duty. Excessive primary switch current, detected via OCPH, terminates the on -period of the primary switch to li mit power delivery (Overload mode) . H igh levels of overload ( when the converter output voltage held is low by the load) causes OCPH to trigger soon after turn -on of the primary switch. This condition is detected by the controller sampling OCPH at time T FBTHR after turn -on. If OCPH triggers within this time, the controller changes to Foldback mode. To prevent mis -triggering, OCPH is blanked for a short period T CSBLANK after turn-on. Product data © Cambridge Semiconductor Ltd 2007 Page 10 of 18 DS-1423-0709C 26-Sep-2007 C2472, C2473 and C2474 Datasheet RDFC Controllers for Offline Applications T he effective thresholds for current through the primary switch for both power reduction (OCPL) and overload (OCPH) are programmed by the current-sense resistors connected to the CS pin as shown in Figure 10. ICSBIAS OCPH threshold (-ve) OCPH Current sense comparators GND OCPL CS R2 Rcs GND Primary switch current Figure 10: Current Sense Diagram T he internal current source (ICSBIAS) develops an offset voltage across the series resistor (R2 in Figure 10) so setting OCPL current threshold. Switch current in excess of overload (OCPH) is detected using a fixed threshold voltage but th e contribution from the offset voltage across R2 has to be taken into account. IOCPL threshold current = (V OCPL + ICSBIAS.R2)/Rcs IOCPH threshold current = (V OCPH + ICSBIAS.R2)/Rcs R2  VOCPH  I OCPL  VOCPL  I OCPH I OCPH  I CSBIAS  I OCPL  I CSBIAS VOCPH  VOCPL I OCPH  I OCPL Rcs  Note: IOCPL, I OCPH, VOCPH ICSBIAS are all positive magnitude in these formulae Product data © Cambridge Semiconductor Ltd 2007 Page 11 of 18 DS-1423-0709C 26-Sep-2007 C2472, C2473 and C2474 Datasheet RDFC Controllers for Offline Applications Protection Features Collector De -saturation (Over Voltage) Protection (COVP) T o protect the primary switch from excessive power dissipation , the on-state voltage of the primary switching transistor is lim ited by the controller. The controller will go to Foldback m ode if the COL pin voltage is greater than VCOVP at the end of the on -time for four consecutive cycles. Over-temperature Protection (OTP) T emperature sensing is integrated with the controller. If the temperature of the die rises above the shutdown temperature, T SH, the BAS output is inhibited. It restarts once the temperature has fallen more than T SH (HYST) below T SH. In typical applications “hiccup” operation will occur. While BAS is inhibited, t he device is active and draws IDDW AKE. T his causes VDD to fall since auxiliary power is not provided by the transformer. Once VDD reaches VUVDTHR, the controller enters the Sleep state and IDD falls to IDDSLEEP allowing VDD to rise again (via the resistors Vht1 and Vht2) . When VDD reaches VOVDTHR reset occurs and the controller re -starts. If the die temperature is below T SH, BAS operation continues but if it is still above T SH, BAS operation ceases after a short period and the hiccup cycle repeats. Primary Switch Over-current Protection (OCP) T o protect the primary switch, the base drive is turned off if the primary switch current rises too high, sensed via the CS input voltage falling below a preset negative threshold VOCPH. See also Power Control on page 10. Output Overload/Short -circuit Protection If the application circuit is overloaded beyond a certain limit the controller goes into Foldback mode with reduced duty cycle, protecting the primary swit ch by reducing its power dissipation. T ransition to Foldback m ode is triggered by the CS pin voltage crossing the VOCPH threshold within a time T FBTHR of the start of the FON pulse. This typically happens when the load holds the output voltage low. See also Power C ontrol on page 10. Under Voltage Protection T he controller is prevented from operating if the V DD supply is inadequate (VDD < V UVDTHR). Once the controller has stopped operation it will not r estart until the VDD supply voltage rises above V OVDTHR. Product data © Cambridge Semiconductor Ltd 2007 Page 12 of 18 DS-1423-0709C 26-Sep-2007 C2472, C2473 and C2474 Datasheet RDFC Controllers for Offline Applications ABSOLUTE MAXIMUM RATINGS CAUTION: Permanent damage may result if a device is subjected to operating conditions at or in excess of absolute maximum ratings. Parameter Supply voltage Input voltage AUX Input voltage BAS Input voltage CS Input voltage COL Pin current VDD Pin current AUX S ymbol VDD VAUX VBAS VCS VCOL IDD IAUX All other conditions Pin current BAS IBAS W hile Qoff is on (Figure 7), base duty < 30% Tj < 125 °C Tj < 100 °C -0.5 -0.5 -0.5 -0.5 -100 -100 -100 -100 -100 -100 During PBD: ESD diode limit, input is high impedance Pin current COL ICOL During turn-on transient (ACTICLAMP active) During resonance off period Junction temperature Storage temperature Lead temperature (soldering, 10 s) ESD withstand TJ TSTOR TL Human body model, JESD22-A114 Charged device model, ANSI-ESD-STM5.3.1 -100 -250 -125 -25 -40 Condition M in M ax 4 .6 VDD + 0.5 VDD + 0.5 VDD + 0.5 VDD + 0.5 30 100 100 1 Units V V V V V mA mA mA mA mA mA mA mA mA o 220 400 100 100 250 250 125 150 260 2 500 Pin current CS ICS C C C o o kV V 1 IBAS can be higher if controller is active and not in PBD or FON, up to V BAS = VDD Product data © Cambridge Semiconductor Ltd 2007 Page 13 of 18 DS-1423-0709C 26-Sep-2007 C2472, C2473 and C2474 Datasheet RDFC Controllers for Offline Applications NORMAL OPERATING CONDITIONS Parameter Supply voltage Junction temperature Internal digital clock frequency Switching frequency, Normal mode Transformer resonance time Supply current S ymbol VDD TJ FCLK FCLKTC FMAX FMIN TRESMIN TRESMAX IDD Condition VDD pin, limited by internal regulator Over temperature protection operates at higher temperatures Tj = 25 C, VDD=VDDREG(R) Temperature coefficient Determined by TRES (FCLK in MHz) Natural resonance of transformer and associated capacitances. FCLK in MHz. Limit externally M in 3.1 -25 9.7 -35 FCLK / 61 FCLK / 490 35 / FCLK 280 / FCLK 30 T yp 3.3 25 12.1 M ax 3.5 100 14.5 5 Units V ºC MHz kHzC MHz MHz µs  µs  mA -1 ELECTRICAL CHARACTERISTICS Unless otherwise stated: 1. Min and Max electrical characteristics apply over normal operating conditions . 2. T ypical electrical characteristics apply at T J = T JTYP and VDD = VDDTYP 3. Functionality and performance is not defined when a device is subjected to conditions outside the range of normal operating conditions and device reliability may be compromised. 4. For parameters dependent on F CLK, the value of F CLK,in MHz should be used in calculations. VDD Pin Parameter Regulation voltage Quiescent current Residual supply current OVD threshold, Sleep UVD threshold VDDREG(R) - VUVDTHR S ymbol VDDREG(R) VDDREG(S) IDDSLEEP IDDW AKE VOVDTHR VUVDTHR Condition Active state, 2.5 m A < IDD < 30 mA Start-up state, 2.5 m A < IDD < 30 mA Sleep state, VDD < VUVDTHR Start-up & Active states, Normal mode (VDDREG(R) – 300 mV) < VDD and VDD < (VDDREG(R) - 100 mV) Sleep state Start-up and Active states IDD < 30 mA 0.5 3 .5 2.7 150 M in 3.1 T yp 3.3 4 8 2.5 4 .6 3.2 M ax 3.5 Units V V µA mA V V mV AUX Pin Parameter Input current AUX pin voltage S ymbol IAUXMAX VAUXFON BAS = 800 mV 0 C < TJ < 100 C IAUX = 10 mA IAUX = 80mA 0.84 1.2 Condition M in T yp M ax 100 1.22 1.64 Units mA V V Product data © Cambridge Semiconductor Ltd 2007 Page 14 of 18 DS-1423-0709C 26-Sep-2007 C2472, C2473 and C2474 Datasheet RDFC Controllers for Offline Applications CS Pin Parameter OCPH comparator threshold OCPL comparator threshold OCPH comparator response time Bias current OCPL sampling time Blanking period Foldback threshold time S ymbol VOCPH VOCPL TOCP ICSBIAS Step CS input from VCS > -200 mV to VCS < -300 mV 0 C < TJ < 100 C T j = 2 5 C TOCPL TCSBLANK TFBTHR FCLK in MHz FCLK in MHz FCLK in MHz 40 41.5 19 / FCLK - 0.06 4 / FCLK - 0.06 26 / FCLK - 0.06 Condition 0 C < TJ < 100 C M in -260 -5 T yp M ax -235 5 0.1 67.5 59.5 Units mV m V µs µA µA µs µs µs B AS Pin Parameter Base drive current Base clamp turn-off resistance Duty cycle Force-on period (depends on FCLK) Minimum on-period Maximum off-period S ymbol IBASMAX RBASCLAMP DNORMAL Condition Limit by external resistor VBAS = 400 mV Normal mode Standby mode 0 C < TJ < 100 C Normal, Foldback & Power Burst m odes. 0 C < TJ < 100 C Standby (FCLK in MHz) Standby (FCLK in MHz) Burst length, number of converter cycles Minimum converter cycle period in 2 Power Burst m ode (FCLK in MHz) Foldback duration between bursts, number of converter cycles Converter period in Foldback m ode (FCLK in MHz) E xtended off time (FCLK in MHz) 3 M in T yp M ax 100 8.5 Units mA Ω % 43 100 400 20 / FCLK 1920 / FCLK + TRES 22144 39 / FCLK 18326 900 / FCLK + TRES 896 / FCLK 230 705 ns ns µs µs cycles µs cycles µs µs  TFON TONMIN TOFFMAX NBURST Power Burst mode TBURSTCYCMIN NFOLD Foldback mode TFOLDCYCMIN TOFFEXTMIN 2 3 Minimum converter period = T RES + T ONMIN Minimum converter period = T RES + T OFFEXT + T ONMIN Product data © Cambridge Semiconductor Ltd 2007 Page 15 of 18 DS-1423-0709C 26-Sep-2007 C2472, C2473 and C2474 Datasheet RDFC Controllers for Offline Applications COL Pin Parameter Rising edge comparator threshold Falling edge comparator threshold Collector overvoltage comparator threshold PBD threshold voltage PBD transconductance Input leakage current Input capacitance ACTICLAMP duration after FON CINCOL TJ < 100  C VCOL = 1 V Standby mode (FCLK in MHz) TACT Normal, Foldback and Power Burst m odes (FCLK in MHz) -650 25 28 3 / FCLK – 0.06 4 / FCLK – 0.06 S ymbol ICRISE Condition M in T yp 0 .4 M ax Units mA ICFALL -0.4 mA VCOVP Intercept of characteristic 10 m A < IBAS < 80mA (see Figure 11) 0.7VDD 0.9VDD V VCREF 0.76 200 1.1 V m AV -1 650 31 nA pF µs µs IBAS (mA) 100 80 60 40 20 1.0 V CREF Figure 11: COL/BAS Transconductance (typical, at 25 °C) V COL (V) 2.0 Product data © Cambridge Semiconductor Ltd 2007 Page 16 of 18 DS-1423-0709C 26-Sep-2007 C2472, C2473 and C2474 Datasheet RDFC Controllers for Offline Applications THERMAL CIRCUIT PROTECTION Parameter Thermal shutdown temperature Thermal shutdown hysteresis S ymbol TSH TSH (HYST) Condition At junction At junction M in 105 T yp 115 35 M ax 125 Units o C C o PACKAGE THERMAL RESISTANCE CHARACTERISTICS Conditions: 1. Controller IC mounted on typical PCB (1.6 mm thick , 35 µm copper, CEM1) ; 2. θJP m easured to pin terminal of device at the surface of the PCB. Package SOT23-6 SOP-8 PDIP-8 Junction-to-pin θJP (Typical) 60 70 35 Junction-to-ambient θJA (Typical) 170 140 105 Units °C / W °C / W °C / W PACKAGE AND ORDERING INFORMATION Package Marking T he PDIP-8 (C2474PW1) and SOP -8 (C2473PX1) packages are marked with the full product type number. T he SOT23-6 package (C2472PX2) is marked with a short code F A as illustrated in Figure 12. C2472PX2 product short code F A FAXX Lot dependent code XX (varies) Figure 12: C2472PX2 SOT23 -6 Package Marking Ordering T ype C2472PX2 C2473PX1 C2474PW1 Package SOT23-6 SOP-8 PDIP-8 Packing Form 7” Tape & Reel 13” Tape & Reel 7” Tape & Reel 13” Tape & Reel Tube Order C2472PX2-TR7 C2472PX2-TR13 C2473PX1-TR7 C2473PX1-TR13 C2474PW1-T1 For further package and ordering information please c ontact CamSemi. Product data © Cambridge Semiconductor Ltd 2007 Page 17 of 18 DS-1423-0709C 26-Sep-2007 C2472, C2473 and C2474 Datasheet RDFC Controllers for Offline Applications DATASHEET STATUS T he status of this Datasheet is shown in the footer. Always refer to the most current version. Datasheet Status Product preview Product Status In development Definition The Datasheet contains target specifications relating to design and development of the described IC product. Application circuits are illustrative only. Specifications are subject to change without notice. The Datasheet contains preliminary specifications relating to functionality and performance of the described IC product. Application circuits are illustrative only. Specifications are subject to change without notice. The Datasheet contains specifications relating to functionality and performance of the described IC product. Application circuits are illustrative only. Specifications are subject to change without notice. Preliminary In qualification Product data In production CONTACT DETAILS Cambridge Semiconductor Ltd St Andrew’s House St Andrew’s Road Cambridge CB4 1DL United Kingdom Phone: Fax: Email: W eb: +44 (0)1223 446450 +44 (0)1223 446451 sales.enqu iries@camsemi.com www.camsemi.com DISCLAIMER The product information provided herein is believed to be accurate and is provided on an “as is” basis. Cambridge Semiconductor Ltd (CamSemi) assumes no responsibili ty or liability for the direct or indirect consequences of use of the information in respect of any infringement of patents or other rights of third parties. Cambridge Semiconductor Ltd does not grant any licence under its patent or intellectual property rights or the rights of other parties. A ny application circuits described herein are for illustrative purposes only. In respect of any application of the product described herein Cambridge Semiconductor Ltd expressly disclaims all warranties of any kind, wh ether express or implied, including, but not limited to, the implied warranties of merchantability, fitness for a particular purpose and non-infringement. No advice or information, whether oral or written, obtained from Cambridge Semiconductor Ltd shall cr eate any warranty of any kind. Cambridge Semiconductor Ltd shall not be liable for any direct, indirect, incidental, special, consequential or exemplary damages, howsoever caused including but not limited to, damages for loss of profits, goodwill, use, dat a or other intangible losses. The products and circuits described herein are subject to the usage conditions and end application exclusions as outlined in Cambridge S emiconductor Ltd Terms and Conditions of Sale which can be found at www.camsemi.com/legal . Cambridge Semiconductor Ltd reserves the right to change specifications without notice. To obtain the most current product information available visit www.camsemi.com or contact us at the address shown above. Product data © Cambridge Semiconductor Ltd 2007 Page 18 of 18 DS-1423-0709C 26-Sep-2007