EM620FT8CU-45LL

EM620FV8BS Series Low Power, 256Kx8 SRAM Document Title 256K x8 bit Low Power and Low Voltage Full CMOS Static RAM Revision History Revision No. 0.0 0.1 History Initial Draft 0.1 Revision Revised VOH(2.2v to 2.4v),tOH(15ns to 10ns), tOE-55(30ns to 25ns), tWP-55(45ns to 40ns), tWP-70(55ns to 50ns), tWHZ-70(25ns to 20ns), ICC(2mA to 3mA), ICC1(2mA to 3mA) VIH level change from 2.0V to 2.2V Fix typo error Draft Date June 28, 2007 July 2, 2007 Remark 0.2 0.3 0.2 Revision 0.3 Revision Aug. 16, 2007 Nov. 13, 2007 4F Korea Construction Financial Cooperative B/D, 301-1 Yeon-Dong, Jeju-Si, Jeju-Do, Rep.of Korea Tel : +82-64-740-1712 Fax : +82-64-740-1749~1750 / Homepage : www.emlsi.com Emerging Memory & Logic Solutions Inc. Zip Code : 690-719 The attached data sheets are provided by EMLSI reserve the right to change the specifications and products. EMLSI will answer to your questions about device. If you have any questions, please contact the EMLSI office. 1 EM620FV8BS Series Low Power, 256Kx8 SRAM 256K x8 Bit Low Power and Low Voltage CMOS Static RAM FEATURES - Process Technology : 0.15mm Full CMOS - Organization :256K x8 - Power Supply Voltage => EM620FV8BS Series : 2.7V~3.6V - Low Data Retention Voltage : 1.5V (MIN) - Three state output and TTL Compatible - Packaged product designed for 45/55/70ns - Package Type: 32-sTSOP1 PRODUCT FAMILY Product Family EM620FV8BS-45LF EM620FV8BS-55LF EM620FV8BS-70LF Operating Temperature Industrial (-40 ~ 85oC) Industrial (-40 ~ 85oC) Industrial (-40 ~ 85oC) Power Dissipation Vcc Range Speed Standby (ISB1, Typ.) 1 µA 1 µA 1 µA Operating (ICC1.Max) 3mA 3mA 3mA PKG Type GENERAL DESCRIPTION The EM620FV8BS series are fabricated by EMLSI’s advanced full CMOS process technology. The families support industrial temperature range and Chip Scale Package for user flexibility of system design. The families also supports low data retention voltage for battery back-up operation with low data retention current. The EM620FV8BS series are available in KGD, JEDEC standard 32 pin 8mm x 13.4mm sTSOP package. 2.7V~3.6V 2.7V~3.6V 2.7V~3.6V 45ns 55ns 70ns 32-sTSOP 32-sTSOP 32-sTSOP PIN DESCRIPTION FUNCTIONAL BLOCK DIAGRAM Pre-charge Circuit A11 A9 A8 A13 WE CS2 A15 VCC A17 A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 EM620FV8BS-45LF 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CS1 I/O 7 I/O 6 I/O 5 I/O 4 I/O 3 VSS I/O 2 I/O 1 I/O 0 A0 A1 A2 A3 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 VCC VSS Row Select Memory Array 1024 x 2048 I/O0 ~ I/O7 Data Cont I/O Circuit Column Select A10 A11 A12 A13 A14 A15 A16 A17 Name CS1,CS2 OE WE A0~A17 I/O0~I/O7 Function Chip select inputs Output Enable input Write Enable input Address Inputs Data Inputs/Outputs Name Vcc Vss NC Function Power Supply Ground No Connection WE OE CS1 CS2 Control Logic 2 EM620FV8BS Series Low Power, 256Kx8 SRAM ABSOLUTE MAXIMUM RATINGS * Parameter Voltage on Any Pin Relative to Vss Voltage on Vcc supply relative to Vss Power Dissipation Operating Temperature Symbol VIN, VOUT VCC PD TA Minimum -0.2 to 4.0V -0.2 to 4.0V 1.0 -40 to 85 Unit V V W o C * Stresses greater than those listed above “Absolute Maximum Ratings” may cause permanent damage to the device. Functional oper- ation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability. FUNCTIONAL DESCRIPTION CS1 H X L L L CS2 X L H H H OE X X H L X WE X X H H L I/O0-7 High-Z High-Z High-Z Data Out Data In Mode Deselected Deselected Output Disabled Read Write Power Stand by Stand by Active Active Active Note: X means don’t care. (Must be low or high state) 3 EM620FV8BS Series Low Power, 256Kx8 SRAM RECOMMENDED DC OPERATING CONDITIONS 1) Parameter Supply voltage Ground Input high voltage Input low voltage 1. 2. 3. 4. Symbol VCC VSS VIH VIL Min 2.7 0 2.2 -0.23) Typ 3.3 0 - Max 3.6 0 VCC + 0.22) 0.6 Unit V V V V TA= -40 to 85oC, otherwise specified Overshoot: VCC +2.0 V in case of pulse width < 20ns Undershoot: -2.0 V in case of pulse width < 20ns Overshoot and undershoot are sampled, not 100% tested. CAPACITANCE1) (f =1MHz, TA=25oC) Item Input capacitance Input/Ouput capacitance 1. Capacitance is sampled, not 100% tested. Symbol CIN CIO Test Condition VIN=0V VIO=0V Min - Max 8 10 Unit pF pF DC AND OPERATING CHARACTERISTICS Parameter Input leakage current Output leakage current Operating power supply Symbol ILI ILO ICC ICC1 Average operating current ICC2 VOL VOH ISB VIN=VSS to VCC CS1=VIH or CS2=VIL or OE=VIH or WE=VIL VIO=VSS to VCC IIO=0mA, CS1=VIL, CS2=WE=VIH, VIN=VIH or VIL Cycle time=1µs, 100% duty, IIO=0mA, CS1VCC-0.2V, VINVCC-0.2V Cycle time = Min, IIO=0mA, 100% duty, CS1=VIL, CS2=VIH, VIN=VIL or VIH IOL = 2.1mA IOH = -1.0mA CS1=VIH, CS2=VIL, Other inputs=VIH or VIL CS1>VCC-0.2V, CS2>VCC-0.2V (CS1 controlled) or 0V