FS450AC

FS450, FS451 i-Net TV Interface Video Processor Features has a programmable down scaler to fit the incoming resolution to the output display format. The CCIR 656 ports allow external interface to other video chips. The sync control block generates frame reset for genlocking other video components. Required external components are minimal: a single 27 MHz oscillator or crystal and passive parts. Digital progressive RGB inputs are downscaled or upscaled to the CCIR-656 horizontal pixel count and converted to the 656 format. Vertical scaling and flicker filtering are done in 656 format. The Flicker Filter is an advanced 2 dimensional filter that enhances text quality. Flicker Filter and Sharpness parameters are programmable. A digital video encoder that generates analog Y/C and Composite Video outputs is part of the FS450. For the composite output in NTSC, YNotch and C-Bandpass filters are available. For RGB and YUV outputs, the encoder may be bypassed via a YUV to RGB transcoder for SCART compatible video. Scaling and clock parameters are automatically programmed by the driver, so the system remains genlocked with resolution changes. The input parameters to the automatic scaling are TV viewable area, PAL or NTSC, and the GCC CRT Control Registers’ settings. The FS451's encoder incorporates Macrovision 7 anti-copy protection technology. All parameters can be read and written via the I2C compatible serial port. Power is derived from +3.3V digital and analog supplies. The package is 100-lead Quad Flat Pack (PQFP). • • • – – – • • • – – – – • – – • • • • • • • • ‡ Flexible clock, data, and electrical interfaces allows glue-less digital interface to Intel 82810, National Geode and most other graphic controller chips ("GCC") Capable of operating as clock master, pseudo-master, and slave and supports both single and differential master clocks Programmable 2D scaling † Variable horizontal up and down scale Variable vertical downscale Output format can be tuned to the exact dimensions of the TV Advanced 2-D flicker filter † Supports Multiple Progressive Input Resolutions 640x480 to 1024x768 Multiple Output Standards NTSC, NTSC-EIAJ, PAL-B/D/G/H/I/M/N Composite, S-Video, RGB SCART Composite Y-Notch and C-Bandpass Filters Genlock the GCC and incoming Video Provides the pixel clock to the GCC generated from a single 27MHz clock Provides frame synchronization output signal for other video components CCIR 656 outputs CCIR 656 input to the encoder 10-bit output D/A converters Macrovision 7 compliant (FS451 only) I2C‡ compatible port controls High level programming interface 100 pin PQFP package 3.3V operation †Note: Covered under US Patent # 5,862,268 and/or patents pending. Note: I2C is a registered trademark of Philips Corporation. The FS450 SIO bus is similar but not identical to Philips I2C bus. Applications Description The i-Net TV FS450 is a fourth generation video scan converter. It accepts many input resolutions, rates and formats and converts them to NTSC or PAL standards compliant with SMPTE-170M and CCIR-656 standards. The chip JUNE, 2000, VERSION 1.2 1 • • • • • • Internet Set Top Boxes PC video out (TV Ready PCs) Cable/DVD Player Set Top Boxes Web Appliances Information Appliances Video Kiosks COPYRIGHT © 1999, 2000 FOCUS ENHANCEMENTS, INC. PRELIMINARY INFORM ATION Typical System Architectural Block Diagram OSC DVD 656 Synch Control VGA Synchs YUV to RGB DACs GCC Chip RGB Color Space Converter Horz and Vertical Down Scaler Flicker Filter 656 Encoder Composite and Y/C VGA Pixel Clock PLL FS450 Figure 1: Typical System Block Diagram JUNE, 2000, VERSION 1.2 2 COPYRIGHT © 1999, 2000 FOCUS ENHANCEMENTS, INC. PRELIMINARY INFORM ATION FS450, FS451 PRELIMINARY PRODUCT DESCRIPTION 1. Table of Contents, Figures & Tables 1. 2. Table of Contents, Figures & Tables 3 Architectural Overview 5 2.1 Oscillators and PLLs ........................... 5 2.2 Serial Control Port ............................... 6 2.3 Sync Control....................................... 6 2.4 Input and Output Frame Formats .......... 6 2.5 Color Space Converter and Scaler......... 7 2.6 Flicker Filter........................................ 7 2.7 Encoder.............................................. 7 2.8 YUV to RGB Converter......................... 7 Typical System Configurations 8 3.1 GCC ⇒ TV Output Only....................... 8 3.2 GCC or DVD Output Switched ⇒ TV..... 9 3.3 Multiple Digital Video Sources Blended ⇒ TV ............................................... 10 Pin Assignments 11 4.1 FS450 ⇔ GCC Pin Mapping............... 12 Pin Descriptions 13 Control Register Definitions 16 6.1 Control Register Map ......................... 16 6.2 Control Register Definitions ................ 20 6.2.1 IHO - Input Horizontal Offset ...... 20 6.2.2 IVO - Input Vertical Offset.......... 20 6.2.3 IHW - Input Horizontal Width ..... 21 6.2.4 VSC – Vertical Scaling Coefficient21 6.2.5 HDSC, HUSC – Horizontal Down/Up Scaling Coefficients .... 22 6.2.6 CR - Command Register ........... 23 6.2.7 SP - Status Port....................... 25 6.2.8 NCON - Numerator of NCO Word26 6.2.9 NCOD - Denominator of NCO Word ............................................... 27 6.2.10 APO, ALO, AFO - Auxiliary Pixel, Line, and Field Offsets .............. 28 6.2.11 HSOUTWID, HSOUTST, HSOUTEND - HSync Out Width, Starting and Ending Edge.......... 29 6.2.12 SHP, FLK - Sharpness and Flicker Filter ....................................... 32 6.2.13 REV - Revision Number............. 33 6.2.14 MISC - Miscellaneous Bits 34, 35 Register................................... 34 6.2.15 FIFOL, FIFOH - FIFO Status Port Full/Empty............................... 35 6.2.16 FFO_LAT - FIFO Latency.......... 35 6.2.17 VSOUTWID, VSOUTST, VSOUTEND - VSync Out Width, Starting and Ending Edge.......... 36 6.2.18 CHR_FREQ - Chroma Subcarrier Frequency ............................... 37 6.2.19 Chroma Phase, Miscellaneous Bits 45 ........................................... 38 6.2.20 Miscellaneous Bits Registers 46 and 47..................................... 39 6.2.21 HSync Width (48), Burst Width (49) ......................................... 40 6.2.22 Back Porch Width (4A), Cb Burst Amplitude (4B)......................... 40 6.2.23 Cr Burst Amplitude (4C), Miscellaneous Bits Register 4D . 41 6.2.24 Black Level (4E)....................... 41 6.2.25 Blank Level (50)........................ 42 6.2.26 Number of Lines (57-58) ............ 42 6.2.27 White Level (5E)....................... 43 6.2.28 Cb Color Saturation (60)............ 43 6.2.29 Cr Color Saturation (62)............. 43 6.2.30 Tint (65)................................... 44 6.2.31 Width of Breezeway (69) ........... 44 6.2.32 Front Porch (6C)....................... 44 6.2.33 Active Video Line (71-72), First Video Line (73)......................... 45 6.2.34 Miscellaneous Bits 74, Sync Level (75) ......................................... 46 6.2.35 VBI Blank Level (7C)................. 47 6.2.36 SOFT_RST, ENC_VER - Encoder Soft Reset, Encoder Version ..... 47 6.2.37 Misc. Bit Reg. 80, WSS Clock (8182), WSS Data F1(83-85).......... 48 6.2.38 WSS Data Field 0(86-88), WSS Line Number Field 1 (89) ........... 49 6.2.39 WSS Field 0 Line Number, WSS Level, Misc. Bits Reg. 8D (8A-8D)50 7. Design and Layout Considerations 52 7.1 Pixel Phase Lock Loop ...................... 52 7.2 Video Output Filters........................... 52 7.3 Analog Power Supply Bypassing, Filtering, and Isolation........................ 52 7.4 Power and Ground............................. 52 7.5 Interfacing to the FS450 in a Mixed Voltage Environment .......................... 53 7.5.1 Interfacing to the SIO bus.......... 53 8. Specifications 55 8.1 Absolute Maximum and Recommended Ratings............................................. 55 8.2 Electrical Characteristics ................... 56 8.3 Switching Characteristics................... 57 9. Mechanical Dimensions 58 9.1 100-Lead PQFP (KH) Package ........... 58 10. Revision History 59 11. Order Information 59 3. 4. 5. 6. JUNE, 2000, VERSION 1.2 3 COPYRIGHT © 1999,2000 FOCUS ENHANCEMENTS, INC. PRELIMINARY INFORM ATION FS450, FS451 PRELIMINARY PRODUCT DESCRIPTION Figure 1: Typical System Block Diagram ................ 2 Figure 2: FS450 Functional Block Diagram ............. 5 Figure 3: GCC Frame Format ................................ 6 Figure 4: CCIR 601/656 Field Format...................... 7 Figure 5: GCC ⇒ TV Output Only .......................... 8 Figure 6: GCC or DVD output switched ⇒ TV ......... 9 Figure 7: Multiple digital video sources blended ⇒ TV ......................................................... 10 Figure 8: CCIR 656 Timing Block Diagram ............ 30 Figure 9: Auxiliary NTSC Reference Signals.......... 31 Figure 10: Auxiliary PAL Reference Signals .......... 31 Figure 11. SIO Translation Using Long-tail Resistors D1 = 1N4148................................ 53 Figure 12. SIO Translation Using Current Mirrors D1 = 1N4148, Q1 = 2N3906, Q2 = 2N3904 .... 54 Figure 13: Package Outline & Dimensions ............ 58 Table 1: FS45x Pin Assignments......................... 11 Table 2: FS450 to GCC Pin Mapping.................... 12 Table 3: SAV and EAV Control Words.................. 24 Table 4: GCC Port Mapping (UIM_MOD)............... 24 Table 5: NCO_LOAD Control Bits......................... 34 Table 6: NOTCH_FRQ Values.............................. 50 Table 7: Typical Register Values for Various Standards ................................................... 51 JUNE, 2000, VERSION 1.2 4 COPYRIGHT © 1999, 2000 FOCUS ENHANCEMENTS, INC. PRELIMINARY INFORM ATION FS450, FS451 PRELIMINARY PRODUCT DESCRIPTION 2. Architectural Overview The FS450 i-Net TV Video Interface Processor provides NTSC or PAL TV out for Intel's 82810 Video Coprocessor and many other 3D graphic controller ("GCC") chips. It accepts digital RGB in, converts it to CCIR 656 digital video, provides interfaces to external 656 digital DVD systems, windowing hardware, alpha blenders, et al and outputs very high quality RGB, YUV, S-Video, or Composite Video. The chip consists of the following major sections: • • • • RED GRN BLU ERED EGRN EBLU VSync HSync Blank Oscillators and PLLs Serial Control Port Sync Control Input and Output Frame Formats Universal Input Mux & Prescaler • • • • Color Space Converter & Scaler Flicker Filter Encoder YUV to RGB Converter /12 /24 H /24 Cache /24 RGB to YUV CCIR656 Formatter /16 V /16 Flicker /32 Filter FIFO /32 H /16 /8 CCIR 656 Out /6 /3 /3 VGA Timing Generator YUV to RGB /16 CCIR 656 Timing Generator /30 Multiplexer /2 HBlank Out VBlank Out Field Out Auxiliary HREF VREF /10 /10 /10 DAC DAC DAC RED/LUMA GRN/CVBS BLU/CHRMA CCIR 656 In Demux /8 H Encoder /30 HBlank In VBlank In Field In /3 Decoder 27 MHz Clock NCO Divider ow VCO CPU VGA Clock Divider Figure 2: FS450 Functional Block Diagram 2.1 Oscillators and PLLs The FS450 synthesizes a 27 to 85 MHz clock off of the 27 MHz Television clock and supplies this clock (VGA_CKOUT) to the GCC. This clock is buffered and returned to the FS450 (VGA_CKIN) synchronous to the RGB data and Sync information. This clock has a 1½ Hz resolution and must be adjusted so the GCC scaled input data rate exactly matches the CCIR 656 data output rate. The VG_CKOUT Phase Lock Loop (PLL) synthesizer uses Numerically Controlled Oscillator (NCO) to fine adjust the 27MHz oscillator to a clock precisely matched to the digital RGB data coming from the GCC. Additionally, the PLL itself can be controlled by programming the numerator (M) and denominator (N) of the PLL itself. The combination of the PLL synthesizer and NCO are used to precisely match the input to the output. JUNE, 2000, VERSION 1.2 5 COPYRIGHT © 1999,2000 FOCUS ENHANCEMENTS, INC. PRELIMINARY INFORM ATION FS450, FS451 PRELIMINARY PRODUCT DESCRIPTION 2.2 Serial Control Port FS450 setup is programmed by registers that are accessible via the I2C‡ compatible serial port (SIO). Status and Revision ID can also be read from the registers. ‡ Note: I2C is a registered trademark of Philips Corporation. The FS450 SIO bus is similar but not identical to Philips I2C bus. 2.3 Sync Control The FS450 operates in a slave mode, pseudo-master mode or full master mode. In pseudo-master mode, the GCC graphic controller derives the VGA pixel clock, horizontal sync, and vertical sync from VGA_CLKOUT supplied by the FS450. The syncs are used inside the FS450 to capture the computer video and are regenerated to supply to external devices such as genlocked video from a DVD player or tuner. In full master mode, the FS450 supplies to the GCC horizontal and vertical sync in addition to the VGA pixel clock. 2.4 Input and Output Frame Formats The FS450 does not contain a frame memory. Therefore, the FS450 output frame rate must be synchronous to the input frame rate. To accomplish this, the active video portion in the output stream must overlay the corresponding active video time in the input stream. Several registers on the FS450 control this timing as illustrated in the following figures: VGA_HSYNC IHO VGA_VSYNC IVO C A Blank Blank Blank D IVO + IVW Blank Blank Blank Black Black Black Blank Blank Black Active Video Black Blank B Blank Black Black Black Blank IHO + IHW Blank Blank Blank Blank Blank Figure 3: GCC Frame Format IHO = OHO / Hscale IHW = OHW / Hscale IVO = OVO / Vscale IVW = OVW / Vscale The output frame timing is determined by the CCIR601 and 656 specifications. Input parameters IHO, IVO, and IHW must be set correctly so that when the image is scaled to the 656 output frame, the timing requirements are met. Parameters A, B, C, and D are determined by the amount of underscan the user wants on the target television screen. JUNE, 2000, VERSION 1.2 6 COPYRIGHT © 1999, 2000 FOCUS ENHANCEMENTS, INC. PRELIMINARY INFORM ATION FS450, FS451 PRELIMINARY PRODUCT DESCRIPTION 656_HSYNC OHO 656_VSYNC OVO C^ A^ Blank Blank Blank D^ OVO + OVW Blank Blank Blank Black Black Black Blank Blank Black Active Video Black Blank B^ OHO + OHW Blank Black Black Black Blank Figure 4: CCIR 601/656 Field Format OHO = 139 NTSC, 145 PAL OHW = 720 OVO = 20 NTSC, 23 PAL OVW = 487 NTSC, 576 PAL 2.5 Color Space Converter and Scaler The digital RGB from the GCC is horizontally compressed, stored into a line buffer cache. As the data is pulled from the line buffer cache, it is converted to 656 YUV and compressed vertically. 2.6 Flicker Filter The FS450 flicker filter provides significantly more control over the display characteristics than a typical 3 line average flicker filter. The FS450's flicker filter consists of both horizontal (Sharpness) and vertical (Flicker) controls. Thus, it is called a 2D flicker filter. Both the Sharpness and Flicker registers can be programmed over a wide range to allow the user to tradeoff flicker and sharpness for readability and reduced eye fatigue. 2.7 Encoder The FS450 contains a high quality 2x oversampled video encoder. The 656 luma information is up-sampled from 13.5 MHz sample rate to 27 MHz with a 19 tap filter which offers excellent flatness to 6MHz and 50 dB image aliasing suppression. Chrominance information is up-sampled from 6.75MHz sample rate to 27 MHz with four user selectable bandwidths. The encoder has programmable width and frequency luma notch filter. The encoder subcarrier is programmable in frequency and phase and with the independence of color format, vsync, and number of lines allows for the support of the many video standards, including all South American variations. The FS450 video encoder outputs NTSC M, J and PAL B, D, G, H, I, M, N, Combination N formats with 10 bits of resolution. Both Composite and S-Video outputs are available simultaneously. 2.8 YUV to RGB Converter As an alternative to encoded PAL or NTSC, the user may select analog RGB outputs. Each channel of RGB has 10 bits of resolution. JUNE, 2000, VERSION 1.2 7 COPYRIGHT © 1999,2000 FOCUS ENHANCEMENTS, INC. PRELIMINARY INFORM ATION FS450, FS451 PRELIMINARY PRODUCT DESCRIPTION 3. Typical System Configurations There are 3 "typical" system configurations envisioned for the FS450: 1) GCC ⇒ TV output only; 2) GCC or DVD output switched ⇒ TV; 3) Multiple digital video sources blended ⇒ TV. 3.1 GCC ⇒ TV Output Only 27 MHz OSC Synch Control VGA Synchs Color Space Converter Horz and Down Vertical Scaler YUV to RGB DACs GCC RGB Flicker Filter Encoder Composite and Y/C VGA Pixel Clock PLL FS450 Figure 5: GCC ⇒ TV Output Only JUNE, 2000, VERSION 1.2 8 COPYRIGHT © 1999, 2000 FOCUS ENHANCEMENTS, INC. PRELIMINARY INFORM ATION FS450, FS451 PRELIMINARY PRODUCT DESCRIPTION 3.2 GCC or DVD Output Switched ⇒ T V OSC DVD 656 Synch Control VGA Synchs YUV to RGB DACs GCC RGB Color Space Converter Horz and Vertical Down Scaler Flicker Filter 656 Encoder Composite and Y/C VGA Pixel Clock PLL FS450 Figure 6: GCC or DVD output switched ⇒ TV JUNE, 2000, VERSION 1.2 9 COPYRIGHT © 1999,2000 FOCUS ENHANCEMENTS, INC. PRELIMINARY INFORM ATION FS450, FS451 PRELIMINARY PRODUCT DESCRIPTION 3.3 Multiple Digital Video Sources Blended ⇒ T V MPEG2 Decoder CCIR 656 Video Decoder CCIR 656 Video Syncs Frame Memory CCIR 656 Output Control CCIR 656 Alpha Blend 27 MHz Decoder Clk CCIR 656 Crystal Osc 27 MHz Encoder Clk CCIR 656 Sync Control VGA Syncs YUV to RGB RGB DA Cs VGA Controller RGB Color Space Converter Horz and Vertical Down Scaler Flicker Filter Encoder Composite and Y/C VGA Clk In VGA Clk Out NCO and PLL Houston Figure 7: Multiple digital video sources blended ⇒ TV JUNE, 2000, VERSION 1.2 10 COPYRIGHT © 1999, 2000 FOCUS ENHANCEMENTS, INC. PRELIMINARY INFORM ATION FS450, FS451 PRELIMINARY PRODUCT DESCRIPTION 4. Pin Assignments 80 51 81 50 100 31 1 30 Pin 1. 2. 3. 4. 5. 6. 7. 8. 9. R O R R G N R R R Name TV_CKIN XTAL V DDOSC V SSOSC Reserved (GND) Reserved (open) V SSDA V REF RREF V DDDA CBYPASS Y/Red V DDDA V SSDA CVBS/Green V DDDA C/Blue V DDDA CSYNC Reserved (open) Reserved (open) V DDPA SCLK SDATA SA 10/7 SA 0 V SSPA RESET Reserved (GND) Reserved (GND) Pin 31. P 32. R 33. R 34. O 35. O 36. S 37. O 38. R 39. O 40. O 41. O 42. O 43. O 44. R 45. R 46. R 47. R 48. R 49. R 50. R Name VGA_CKOUT V SS V DD Reserved (open) Reserved (open) E5 E4 V SS VGA_CKOUTTL E3 E2 E1 E0 BLANK V DD VSYNC_IN HSYNC_IN P0 P1 V SS Pin 51. R 52. R 53. R 54. R 55. R 56. R 57. R 58. R 59. R 60. R 61. R 62. R 63. R 64. R 65. R 66. R 67. O 68. O 69. O 70. R 71. O 72. O 73. O 74. R 75. O 76. O 77. O 78. R 79. O 80. O Name P2 P3 P4 P5 GTL_REF V DD P6 P7 P8 P9 V SS P10 P11 VGA_NCKIN VGA_PCKIN V DD AVREF VSYNC_OUT AHREF V SS HSYNC_OUT FIELD_OUT VBNK_OUT V DD HBNK_OUT V656_OUT0 V656_OUT1 V SS V656_OUT2 V656_OUT3 Pin 81. O 82. R 83. O 84. O 85. O 86. R 87. S 88. S 89. S 90. R 91. S 92. S 93. S 94. S 95. R 96. S 97. S 98. S 99. S 100. N Name V656_OUT4 V DD V656_OUT5 V656_OUT6 V656_OUT7 V SS FIELD_IN VBNK_IN HBNK_IN V DD V656_IN0 V656_IN1 V656_IN2 V656_IN3 V SS V656_IN4 V656_IN5 V656_IN6 V656_IN7 Reserved (open) 10. R 11. R 12. O 13. R 14. R 15. O 16. R 17. O 18. R 19. O 20. N 21. N 22. R 23. R 24. R 25. R 26. R 27. R 28. R 29. G 30. G Table 1: FS45x Pin Assignments R = Signal Required O = Signal if used, else no connect S = Signal if used, else ground G = Always Ground N = Always No Connect JUNE, 2000, VERSION 1.2 11 COPYRIGHT © 1999,2000 FOCUS ENHANCEMENTS, INC. PRELIMINARY INFORM ATION FS450, FS451 PRELIMINARY PRODUCT DESCRIPTION 4.1 FS450 ⇔ GCC Pin Mapping The following table maps the FS450/1 pins to the host GCC controller chip. Please contact your FOCUS representative to obtain the most up-to-date reference schematics before initiating a design. FS450 Pin # FS450/1 Pin Name Intel 82810 Pin Name UIM_MOD=0 TVCLKIN TVCLK CLKOUT0 CLKOUT1 TVHSYNC TVVSYNC FP_CLK FP_HSYNC_OUT FP_VSYNC_OUT National Cx5530 MediaGX UIM_MOD=3 nVidia Riva TNT Pin Name UIM_MOD=1 S3 Savage Pin Name UIM_MOD=1 31 39 65 64 47 46 71 68 44 48 49 51 52 53 54 57 58 59 60 62 63 43 42 41 40 37 36 23 24 VGA_CKOUT VGA_CKOUTTL TVCLKIN TVCLKOUT TVCLK TVCLKR TVHS TVVS VGA_PCKIN VGA_NCKIN HSYNC_IN VSYNC_IN HSYNC_OUT VSYNC_OUT BLANK P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 E0 E1 E2 E3 E4 E5 SCLK SDATA TVHSYNC TVVSYNC BLANK LTVDATA0 LTVDATA1 LTVDATA2 LTVDATA3 LTVDATA4 LTVDATA5 LTVDATA6 LTVDATA7 LTVDATA8 LTVDATA9 LTVDATA10 LTVDATA11 FP_DATA6 FP_DATA7 FP_DATA8 FP_DATA9 FP_DATA10 FP_DATA11 FP_DATA12 FP_DATA13 FP_DATA14 FP_DATA15 FP_DATA16 FP_DATA17 FP_DATA0 FP_DATA1 FP_DATA2 FP_DATA3 FP_DATA4 FP_DATA5 LTVCL LTVDA DDC_SCL DDC_SDA SPSCL SPSDA SPCLK1 SPD1 TVD0 TVD1 TVD2 TVD3 TVD4 TVD5 TVD6 TVD7 TVD8 TVD9 TVD10 TVD11 BLANK TVDAT0 TVDAT1 TVDAT2 TVDAT3 TVDAT4 TVDAT5 TVDAT6 TVDAT7 TVDAT8 TVDAT9 TVDAT10 TVDAT11 Table 2: FS450 to GCC Pin Mapping JUNE, 2000, VERSION 1.2 12 COPYRIGHT © 1999, 2000 FOCUS ENHANCEMENTS, INC. PRELIMINARY INFORM ATION FS450, FS451 PRELIMINARY PRODUCT DESCRIPTION 5. Pin Descriptions Pin Name Clocks VGA_CKOUT VGA_CKOUTTL Pin Number 31 39 65 Type/Value Pin Function Description GTLP output (open drain) LVTTL output GTLP input VGA_PCKIN VGA_NCKIN 64 GTLP input TV_CKIN XTAL HSYNC_OUT VSYNC_OUT 1 2 71 68 LVTTL input LVTTL output LVTTL output LVTTL output VGA Clock Output. Clock to GCC TVCLKIN. Synthesized from TV_CKIN. 27 to 85 MHz range. VGA Clock Output. Clock to GCC TVCLKIN. Synthesized from TV_CKIN. 27 to 85 MHz range. VGA Clock Input Positive Edge. Clock from GCC CLKOUT, buffered form of VGA_CKOUT. Used to latch rising edge RGB data. VGA Clock Input Negative Edge. Clock from GCC CLKOUT, buffered form of VGA_CKOUT. Used to latch negative edge RGB data. Television Clock Input. Clock for the CCIR 656 I/O and the video encoder. 27 MHz. Television Clock XTAL Output. Buffered version of TV_CKIN. For use with a 27 MHz crystal. HSYNC Output. Output from FS450 to GCC to support slave mode operation. VSYNC Output. Output from FS450 to GCC to support slave mode operation. Reset. Active Low. Resets internal state machines and initializes default register values. Reserved Inputs. Connect to VSS. Reserved Outputs. Do not connect. Global Controls and Reserved Pins RESET 28 TTL input (pull down) Reserved 5,29,30 TTL input (ground) Reserved 6,20,21, LVTTL output 34,35,100 (leave open) Digital RGB Inputs P11-P0 63,62,60,5 GTLP input 9,58,57,54 ,53,52,51, 49,48 E5-E0 36,37,40,4 GTLP input 1,42,43 GTL_REF 55 GTLP REF HSYNC_IN VSYNC_IN BLANK 47 46 44 GTLP input GTLP input GTLP input Digital GTLP port input. Digital video input, multiplexed or non-multiplexed. Connects to GCC's digital video out. Digital GTLP port input. Non-multiplexed extended digital video input. Connects to GCC's digital video out. Digital GTLP Reference input. Voltage threshold reference for GTLP inputs. Reference is 1.0 volts. Digital HSYNC VGA input. Connects to GCC TVHSYNC. Digital VSYNC VGA input. Connects to GCC TVVSYNC. Digital BLANK VGA input. True outside of GCC active area. Connects to GCC BLANK#. JUNE, 2000, VERSION 1.2 13 COPYRIGHT © 1999,2000 FOCUS ENHANCEMENTS, INC. PRELIMINARY INFORM ATION FS450, FS451 PRELIMINARY PRODUCT DESCRIPTION Pin Name Video Outputs Y/Red Pin Number 12 Type/Value Pin Function Description analog video CVBS/Green 15 analog video C/Blue 17 analog video CSYNC 19 LVTTL output Video output. As programmed by Command Register OFMT bit: 0 Luminance component Y of S-video. 1 Red component of RGB. Video output. As programmed by Command Register OFMT bit: 0 Composite video. 1 Green component of RGB. Video output. As programmed by Command Register OFMT bit: 0 Chrominance component of S-video. 1 Blue component of RGB. Composite sync output. Active high digital composite sync for SCART video outputs. Voltage reference input/output. If unconnected, except for a 0.1µF capacitor to ground for noise decoupling, the internal 1.276 Volt band-gap reference will be supplied to the three D/A Converters. An external 1.276 Volt reference connected to the VREF pin, will override the internal voltage reference. Reference resistor. Connected between RREF and ground, this resistor sets the current range of the D/A converters. Use 390Ω for a 37.5Ω load and 780Ω for a 75Ω load. Bypass Capacitor. A 0.1µF capacitor must be connected between CBYPR and VDDDA to reduce noise at the D/A outputs. Digital CCIR 656 port input. 8 bits wide. Y, Cr, Cb multiplexed digital input port Digital TV Horizontal Blank input. Horizontal Blank for use with the V656_IN ports. Digital TV Vertical Blank input. Vertical Blank for use with the V656_IN ports. Digital TV Field input. Field bit for use with the V656_IN ports. Voltage Reference VREF 8 +1.276 V RREF 9 390/780Ω 0.1 µF CBYPASS 11 CCIR 656 Input Port V656_IN7-0 99,98,97,9 TTL input 6,94,93,92 (pull down) ,91 HBNK_IN 89 TTL input (pull down) VBNK_IN 88 TTL input (pull down) FIELD_IN 87 TTL input (pull down) JUNE, 2000, VERSION 1.2 14 COPYRIGHT © 1999, 2000 FOCUS ENHANCEMENTS, INC. PRELIMINARY INFORM ATION FS450, FS451 PRELIMINARY PRODUCT DESCRIPTION Pin Pin Type/Value Name Number CCIR 656 Output Port V656_OUT7-0 85,84,83,8 LVTTL output 1,80,79,77 ,76 HBNK_OUT 75 LVTTL output VBNK_OUT FIELD_OUT AHREF 73 72 69 LVTTL output LVTTL output LVTTL output Pin Function Description Digital CCIR 656 port output. 8 bits wide. Y, Cr, Cb multiplexed digital output port Digital TV Horizontal Blank output. Horizontal Blank for use with the V656_OUT ports. Digital TV Vertical Blank output. Vertical Blank for use with the V656_OUT ports. Digital TV Field output. Field bit for use with the V656_OUT ports. Digital Auxiliary Horizontal Reference output. Horizontal Sync for external hardware. Programmable advance or retard. Digital Auxiliary Vertical Reference output. Vertical Sync for external hardware. Programmable advance or retard. Serial address length select. Selects the length of the serial address: SA10/7 = H: 10-bits SA10/7 = L: 7-bits Serial data address bit 0. . Selects the serial bus address: SA0 = H: 0x6A, 276 SA0 = L: 0x4A, 224 Serial data. Data line of the serial port. Connect to GCC LTVDA. Serial clock. Clock line of the serial port. Connect to GCC LTVCL. VGA_CKOUT Phase-locked loop Power. Filtered +3.3 volt power for VGA_CKOUT phase locked loop. TV Crystal Oscillator Power. Filtered +3.3 volt power for TV XTAL oscillator. Digital Power. 3.3 volt power for digital section of chip. D/A Converter Power. Filtered +3.3 volt power for 10 bit video D/A converters. VGA_CKOUT phase-locked loop ground. TV Crystal Oscillator ground. Digital ground. +3.3 volt power return. AVREF Serial Port SA10/7 67 LVTTL output 25 TTL input (pull down) SA0 26 TTL input (pull down) TTL I/0 (open drain) TTL Input SDATA SCLK 24 23 Power and Ground VDDPA 22 VDDOSC VDD VDDDA VSSPA VSSOSC VSS 3 33,45,56,6 6,74,82,90 10,13,16,1 8 27 4 32,38,50,6 1,70,78,86 ,95 7,14 +3.3 V +3.3 V +3.3 V +3.3 V 0V 0V 0V VSSDA 0V D/A Converter Ground. JUNE, 2000, VERSION 1.2 15 COPYRIGHT © 1999,2000 FOCUS ENHANCEMENTS, INC. PRELIMINARY INFORM ATION FS450, FS451 PRELIMINARY PRODUCT DESCRIPTION 6. Control Register Definitions 6.1 Control Register Map Function Reg. Bit # Name Type Input Horizontal Offset 0 7-0 IHO7-0 R/W 1 2-0 IHO10-8 R/W Input Vertical Offset 2 7-0 IVO7-0 R/W 3 2-0 IVO10-8 R/W Input Horizontal Width 4 7-0 IHW 7-0 R/W 5 1-0 IHW 9-8 R/W Vertical Scaling Coefficient 6 7-0 VSC7-0 R/W 7 7-0 VSC15-8 R/W Horizontal Down/Up Scaling Coefficients 8 7-0 HDSC7-0 R/W (Down) 9 7-0 HUSC7-0 R/W (Up) Command Register C 7-0 CR7-0 R/W D 7-0 CR15-8 R/W Status Port E 7-0 SP7-0 R F R Numerator of NCO Low Word 10 7-0 NCON7-0 R/W 11 7-0 NCON15-8 R/W Numerator of NCO High Word 12 7-0 NCON23-16 R/W 13 Denominator of NCO Low Word 14 7-0 NCOD7-0 R/W 15 7-0 NCOD15-8 R/W Denominator of NCO High Word 16 7-0 NCOD23-16 R/W 17 Auxiliary Pixel Offset 18 7-0 APO7-0 R/W 19 1-0 APO9-8 R/W Auxiliary Line Offset 1A 6-0 ALO6-0 R/W 1B R/W Auxiliary Field Offset 1C 0 AFO R/W 1D HSync Pulse Width 1E 7-0 HSOUTWID7-0 R/W 1F 2-0 HSOUTWID 10-8 R/W JUNE, 2000, VERSION 1.2 16 Reset Value 00 00 00 00 D0 (720.) 02 00 00 00 00 00 10 00 00 00 (131,072.) 00 02 00 (524,288.) 00 08 00 00 00 00 00 00 00 00 COPYRIGHT © 1999, 2000 FOCUS ENHANCEMENTS, INC. PRELIMINARY INFORM ATION FS450, FS451 PRELIMINARY PRODUCT DESCRIPTION Function Reg. Bit # Name Type HSync Starting Edge 20 7-0 HSOUTST7-0 R/W 21 2-0 HSOUTST10-8 R/W HSync Ending Edge 22 7-0 HSOUTEND7-0 R/W 23 2-0 HSOUTEND10-8 R/W Flicker Filter Sharpness 24 4-0 SHP 4-0 R/W 25 Flicker Filter 26 4-0 FLK 4-0 R/W 27 Part Revision 32 7-0 REV7-0 R/W 33 7-0 REV15-8 R/W Misc Register 34 7-0 MISC7-0 R/W 35 7-0 MISC15-8 R/W FIFO Status Port Full/FIFO Status Port Empty 36 7-0 FIFOF7-0 R/W 37 7-0 FIFOE7-0 R/W FIFO Latency 38 7-0 FIFOL7-0 R/W 39 7-0 FIFOL15-8 R/W VSync Pulse Width 3A 7-0 VSOUTWID7-0 R/W 3B 2-0 VSOUTWID 10-8 R/W VSync Starting Edge 3C 7-0 VSOUTST7-0 R/W 3D 2-0 VSOUTST10-8 R/W VSync Ending Edge 3E 7-0 VSOUTEND7-0 R/W 3F 2-0 VSOUTEND10-8 R/W Reset Value 00 00 00 00 00 00 00 00 01 00 00 80 00 00 00 00 00 00 00 00 00 00 JUNE, 2000, VERSION 1.2 17 COPYRIGHT © 1999,2000 FOCUS ENHANCEMENTS, INC. PRELIMINARY INFORM ATION FS450, FS451 PRELIMINARY PRODUCT DESCRIPTION Function Reg. Bit # Name Type Chroma Frequency CHR_FREQ31-24 R/W 40 7-0 CHR_FREQ23-16 R/W 41 7-0 CHR_FREQ15-8 R/W 42 7-0 CHR_FREQ7-0 43 7-0 R/W Chroma Phase, Miscellaneous Bits 45 CHR_PHASE7-0 R/W 44 7-0 45 1,0 MISC45 R/W Miscellaneous Bits 46, 47 46 7-0 MISC46 R/W 47 3-0 MISC47 R/W HSync Width, Burst Width HSYNC_WID 7-0 R/W 48 7-0 BURST_WID 6-0 R/W 49 6-0 Backporch Width, CB Burst Level BPORCH7-0 4A 7-0 R/W CB_BURST7-0 4B 7-0 R/W CR Burst Level, Miscellaneous Bits 4D CR_BURST7-0 4C 7-0 R/W 4D 1-0 MISC4D R/W Black Level 4E 7-0 BLACK_LVL9-2 R/W 4F 1-0 BLACK_LVL1-0 R/W Blank Level 50 7-0 BLANK_LVL9-2 R/W 51 1-0 BLANK_LVL1-0 R/W Number Lines LINE_FRAME 9-2 R/W 57 7-0 LINE_FRAME 1-0 R/W 58 1-0 White Level 5E 7-0 WHITE_LVL9-2 R/W 5F 1-0 WHITE_LVL1-0 R/W Cb Gain 60 7-0 CB_GAIN7-0 R/W 61 R/W Cr Gain 62 7-0 CR_GAIN7-0 R/W 63 R/W Chroma Tint Adjustment 64 R/W 65 7-0 TINT7-0 R/W Status Port 68 R/W 69 4-0 BREEZE_WAY4-0 R/W Status Port 6C 5-0 FRNT_PORCH5-0 R/W 6D R/W Reset Value 21 (569,408,543.) F0 7C 1F 00 00 05 00 7E (126.) 44 (68.) 76 (118.) 3B (59.) 00 00 86 (282.) 02 3C (240.) 00 83 (525.) 01 C8 (800.) 00 22 (137.) 01 22 (137.) 01 00 00 00 16 (22.) 20 (32.) 00 JUNE, 2000, VERSION 1.2 18 COPYRIGHT © 1999, 2000 FOCUS ENHANCEMENTS, INC. PRELIMINARY INFORM ATION FS450, FS451 PRELIMINARY PRODUCT DESCRIPTION Function Reg. Bit # Name Type Reset Value ActiveLine ACTIVELINE10-3 R/W 71 7-0 B4 (1440.) ACTIVELINE2-0 72 2-0 R/W 00 Chroma Phase FIRST_LINE7-0 73 7-0 R/W 15 (21.) Miscellaneous Bits 74, Sync Level 74 7-0 MISC74 R/W 02 75 7-0 SYNC_LVL7-0 R/W 48 (72.) VBI Blank Level VBIBLNK_LVL9-2 7C 7-0 R/W 4A (296.) VBIBLNK_LVL1-0 7D 1-0 R/W 00 Reset, Encoder Version 7E 0 SOFT_RST R/W 1 7F 7-0 ENC_VER7-0 R 20 Miscellaneous Bits 80, WSS Clock Frequency (upper) 80 6-0 MISC80 R/W 7 81 7-0 WSS_CLK 11-4 R/W 2F (759.) WSS Clock Frequency (lower), WSS Data Field 1 (upper) 82 3-0 WSS_CLK 3-0 R/W 07 WSS_DAT1 19-12 R/W 83 7-0 00 WSS Data Field 1 (lower) WSS_DAT1 11-4 R/W 84 7-0 00 85 3-0 WSS_DAT1 3-0 R/W 00 WSS Data Field 0 (upper) WSS_DAT0 19-12 R/W 86 7-0 00 WSS_DAT0 11-4 R/W 87 7-0 00 WSS Data Field 0 (lower), WSS Line 1 Delay 88 3-0 WSS_DAT0 3-0 R/W 00 89 7-0 WSS_LINF17-0 R/W 00 WSS Level (lower) 8A 7-0 WSS_LINF07-0 R/W 00 8B 7-0 WSS_LVL9-2 R/W FF (1023.) WSS Level (upper), Miscellaneous Bits 8D 8C 1-0 WSS_LVL1-0 R/W 03 8D 4-0 MISC8D4-0 R/W 00 JUNE, 2000, VERSION 1.2 19 COPYRIGHT © 1999,2000 FOCUS ENHANCEMENTS, INC. PRELIMINARY INFORM ATION FS450, FS451 PRELIMINARY PRODUCT DESCRIPTION 6.2 Control Register Definitions In the following definitions, range is defined as: {min value : [max value]} Please note that registers 0-3F use the little endian numbering scheme while registers 40-8D use the big endian numbering scheme. 6.2.1 IHO - Input Horizontal Offset Input Horizontal Offset Low (0) 7 IHO7 6 IHO6 5 IHO5 4 IHO4 3 IHO3 2 IHO2 1 IHO1 0 IHO0 Input Horizontal Offset High (1) 7 0 6 0 5 0 4 0 3 0 2 IHO10 1 IHO9 0 IHO8 Reg 1, 0 Bit# 2-0, 7-0 Bit Name IHO10-0 Description Input horizontal offset bits [10-0]. Horizontal displacement of the image in pixels from the leading edge of horizontal sync. IHO is an unsigned number. Range: {0 : [Total Pixels/Line]-1} 6.2.2 IVO - Input Vertical Offset Input Vertical Offset Low (2) 7 IVO7 6 IVO6 5 IVO5 4 IVO4 3 IVO3 2 IVO2 1 IVO1 0 IVO0 Input Vertical Offset High (3) 7 0 6 0 5 0 4 0 3 0 2 IVO10 1 IVO9 0 IVO8 Reg 3, 2 Bit# 2-0, 7-0 Bit Name IVO10-0 Description Input vertical offset bits [10:0]. Vertical displacement of the image in lines from the leading edge of vertical sync plus a one line bias. IVO is an unsigned number. Range: {0 : [Total Lines/Frame]-1} JUNE, 2000, VERSION 1.2 20 COPYRIGHT © 1999, 2000 FOCUS ENHANCEMENTS, INC. PRELIMINARY INFORM ATION FS450, FS451 PRELIMINARY PRODUCT DESCRIPTION 6.2.3 IHW - Input Horizontal Width Input Horizontal Width Low (4) 7 IHW 7 6 IHW 6 5 IHW 5 4 IHW 4 3 IHW 3 2 IHW 2 1 IHW 1 0 IHW 0 Input Horizontal Width High (5) 7 0 6 0 5 0 4 0 3 0 2 0 1 IHW 9 0 IHW 8 Reg 5, 4 Bit# 1-0, 7-0 Bit Name IHW 9-0 Description Input horizontal width [9:0]. Total number of active VGA pixels per line. IHW is an unsigned number. Range: {0 : 970} 6.2.4 VSC – Vertical Scaling Coefficient Vertical Scaling Coefficient (6) 7 VSC7 6 VSC6 5 VSC5 4 VSC4 3 VSC3 2 VSC2 1 VSC1 0 VSC0 Vertical Scaling Coefficient (7) 7 VSC15 6 VSC14 5 VSC13 4 VSC12 3 VSC11 2 VSC10 1 VSC9 0 VSC8 Reg 7, 6 Bit# 7-0 Bit Name VSC7-0 Description Vertical scaling coefficient bits [15:0]. Vertical down scaling factor = (1 + VSC/65,536). VSC is a two's complement number. If VSC => 0, then the image is not effected. Range: { [-32,769]:0} JUNE, 2000, VERSION 1.2 21 COPYRIGHT © 1999,2000 FOCUS ENHANCEMENTS, INC. PRELIMINARY INFORM ATION FS450, FS451 PRELIMINARY PRODUCT DESCRIPTION 6.2.5 HDSC, HUSC – Horizontal Down/Up Scaling Coefficients Horizontal Down Coefficient (8) 7 HDSC7 6 HDSC6 5 HDSC5 4 HDSC4 3 HDSC3 2 HDSC2 1 HDSC1 0 HDSC0 Horizontal Up Coefficient (9) 7 HUSC7 6 HUSC6 5 HUSC5 4 HUSC4 3 HUSC3 2 HUSC2 1 HUSC1 0 HUSC0 Reg 8 Bit# 7-0 Bit Name HDSC7-0 Description Horizontal down scaling coefficient bits [7:0]. Horizontal down scaling factor = (1 + VSC/128). HDSC is a two's complement number. If HDSC => 0, then the image is not effected. Horizontal up scaling coefficient bits [7:0]. Horizontal up scaling factor = (1 + VSC/128). HDSC is a two's complement number. If HDSC