GSM793E

GSM793E Syntek Semiconductor Co., Ltd. (80CH Segment Driver For Dot Matrix LCD) Introduction : GSM793E is a segment driver for dot matrix type LCD display. It features 80 channels with 40 X 2 bits bi-directional shift registers, data latches, LCD drivers and logic control circuits. It is fabricated by high voltage CMOS process with low current consumption. The GSM793E can convert serial data received from an LCD controller, such as GSM7980, into parallel data and send out LCD driving waveforms to the LCD panel. The GSM793E is designed for general purpose LCD drivers. It can drive both static and dynamic drive LCD. The LSI can be used as segment driver. The GSM793E has pin function compatibility with the KS0063(B) that allows the user to easily replace it with an GSM793E. Functions : l Dot matrix LCD driver with two 40 channel outputs l Bias voltage (V1 ~ V4) l input/output signals n n Input : Serial display data and control pulse from controller IC Output : 40 X 2 channels waveform for LCD driving Features : l Display driving bias : static to 1/5 l Power supply for logic : 2.7V ~ 5.5V l Power supply for LCD voltage (VDD~VEE) : 3V ~ 11V 100 Pin QFP package and bare chip available LCD Controller /Driver 1 /10 V1.1 GSM793E Syntek Semiconductor Co., Ltd. GSM793E FUNCTI ONAL BLOCK S1 ...................S40 S41… … … … S80 V1 V2 V3 V4 SEGMENT DRIVER SEGMENT DRIVER DATA LATCH(40BITs) DATA LATCH(40BITs) VDD VSS VE E BIDIRECTIONAL SHIFTER(40BITs) BI DIRECTIONAL SHIFTER(40BITs ) M CL1 CL2 CONTOL DL1 SHL1 DR1 DL2 SHL2 DR2 LCD Controller /Driver 2 /10 V1.1 GSM793E Syntek Semiconductor Co., Ltd. Pin Description : PIN NAME VDD VSS VEE V1 V2 V3 V4 S1-S40 SHL1 DL1, DR1 PURPOSE POWER GROUND LCD GND LCD output LCD output segment direction data in /out DESCRIPTION for logic for logic for LCD driving voltage used as select voltage level used as non select voltage level LCD driver output for part 1 direction control for part 1 segments If SHL1 = 1 then DL1=out, DR1=in If SHL1 = 0 then DL1=in, DR1=out I/O N/A N/A N/A I I O I I/O S41-S80 SHL2 DL2, DR2 segment direction data in/out LCD driver output for part 2 direction control for part 2 segments If SHL2 = 1 then DL2=out, DR2=in If SHL2 = 0 then DL2=in, DR2=out O I I/O M CL1 CL2 alternation latch clock shift clock Alternate the LCD driving waveform latch the data after shift is completed shift the data into the segments I I I LCD Controller /Driver 3 /10 V1.1 GSM793E 78 79 80 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 Syntek Semiconductor Co., Ltd. 81 82 83 84 85 86 87 88 89 90 91 92 93 46 45 44 43 42 (0,0) 40 39 38 Size: 38 00x26 00 um 2 Coor dinat e: center M in. PA D Pitch : 120um 37 36 34 94 95 96 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Circle here to find th e first PAD “GS M793E” Mark ing: Easy to find the PAD 33 32 GSM793E 31 24 25 26 27 28 29 30 LCD Controller /Driver PAD Arrangement 35 4 /10 41 V1.1 GSM793E Syntek Semiconductor Co., Ltd. PAD NAMES AND COORDINATES Pa Pad d Nam No e . 1 S42 2 S43 3 S44 4 S45 5 S46 6 S47 7 S48 8 S49 9 S50 10 S51 11 S52 12 S53 13 S54 14 S55 15 S56 16 S57 17 S58 18 S59 19 S60 20 S61 21 S62 22 S63 23 S64 24 S65 25 S66 26 S67 27 S68 28 S69 29 S70 30 S71 31 S72 32 S73 X Y Pa Pad d Name No . 33 S74 34 S75 35 S76 36 S77 37 S78 38 S79 39 S80 40 S40 41 S39 42 S38 43 S37 44 S36 45 S35 46 S34 47 S33 48 S32 49 S31 50 S30 51 S29 52 S28 53 S27 54 S26 55 S25 56 S24 57 S23 58 S22 59 S21 60 S20 61 S19 62 S18 63 S17 X Y Pa d No . 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 Pad Nam e S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 VEE V1 V2 V3 V4 VSS CL1 SHL1 SHL2 VDD CL2 DL1 DR1 DL2 X Y 64 S16 -60 1160 -1760 -1630 -1500 -1380 -1260 -1140 -1020 -900 -780 -660 -540 -420 -300 -180 -60 60 180 300 420 540 660 780 900 1020 1140 1260 1380 1500 1630 1760 1760 1760 -1160 -1160 -1160 -1160 -1160 -1160 -1160 -1160 -1160 -1160 -1160 -1160 -1160 -1160 -1160 -1160 -1160 -1160 -1160 -1160 -1160 -1160 -1160 -1160 -1160 -1160 -1160 -1160 -1160 -1160 -1030 -900 1760 1760 1760 1760 1760 1760 1760 1760 1760 1760 1760 1760 1760 1760 1760 1760 1760 1630 1500 1380 1260 1140 1020 900 780 660 540 420 300 180 60 -780 -660 -540 -420 -300 -180 -60 60 180 300 420 540 660 780 900 1030 1160 1160 1160 1160 1160 1160 1160 1160 1160 1160 1160 1160 1160 1160 1160 -180 -300 -420 -540 -660 -780 -900 -1020 -1140 -1260 -1380 -1500 -1630 -1760 -1760 -1760 -1760 -1760 -1760 -1760 -1760 -1760 -1760 -1760 -1760 -1760 -1760 -1760 -1760 1160 1160 1160 1160 1160 1160 1160 1160 1160 1160 1160 1160 1160 1160 1030 900 780 660 540 420 300 180 60 -60 -180 -300 -420 -540 -660 LCD Controller /Driver 5 /10 V1.1 GSM793E Syntek Semiconductor Co., Ltd. 94 95 96 DR2 M S41 -1760 -780 -1760 -900 -1760 -1030 LCD Controller /Driver 6 /10 V1.1 GSM793E Syntek Semiconductor Co., Ltd. Functional Description : Clock The CL1 is the clock to latch data on the falling edge. It latches the data input from the bidirectional shift register at the falling edge of CL1 and transfers its outputs to the LCD driver circuit. The CL2 is the clock to shift data on the falling edge. It shifts the serial data at the falling of CL2 and transfers the output of each bit of the register to the latch circuit. Shift Registers And Data I/O The GSM793E supplies two sets of 40-bit shift register, which controls the shift direction by SHL1 & SHL2. The SHL1 controls the 1st 40-bit shift register, and SHL2 controls the 2nd 40-bit shift register. When SHL1 is connected to VDD, the 1st shift direction is from S40 to S1; when SHL1 is connected to VSS, the shift direction changes from S1 to S40. When SHL2 is connected to VDD, the 2nd shift direction is from S80 to S41; when SHL2 is connected to VSS, the shift direction changes from S41 to S80. The DL1, DR1, DL2, DR2 are data input or output option function. Shift Direction of Channel 1 SHL1 0 1 Shift Direction S1 à S40 S40 à S1 DL1 IN OUT DR1 OUT IN Shift Direction of Channel 2 SHL2 0 1 Shift Direction S41 à S80 S80 à S41 DL2 IN OUT DR2 OUT IN LCD Controller /Driver 7 /10 V1.1 GSM793E Syntek Semiconductor Co., Ltd. LCD Output Waveforms : Output of LATCH (DATA) M V2 V4 Output (S1 ~ S80) V1 V3 V1 V2 V4 V3 Timing Characteristics : VIH CL2 VIL TWCKH TR TWCKL TF TDH TSU Data in (DL1, DL2) (DR1, DR2) TD Data out (DL1, DL2) (DR1, DR2) VOH TSL VOL TLS TLS CL1 TR TSU M TWCKH LCD Controller /Driver 8 /10 V1.1 GSM793E Syntek Semiconductor Co., Ltd. D.C Characteristics: Symbol VDD VLCD VIH VIL ILKG VOH VOL IDD IV Parameter Operating Voltage Driver Supply Voltage Input High Voltage Input Low Voltage Input Leakage Current Output High Voltage Output Low Voltage Operating Current Leakage Current Test Condition VDD-VEE VIN = 0 ~ VDD I OH = -0.4mA I OL = +0.4mA FCL2 = 400KHZ VIN = VDD ~ VEE Min. 2.7 3 0.7VDD 0 -5 VDD-0.4 -10 Typ. 100 - Max. 5.5 11 VDD 0.3VDD 5 0.4 300 10 Unit V V V V uA V V uA uA Applicable pin CL1,CL2,M,SHL1,SHL2 DL1,DL2,DR1,DR2 DL1,DL2,DR1,DR2 V1~V4, S1~S80 VDD,VEE V1 ~ V4 A.C Characteristics : Symbol FCL TWCKH TWCKL TSL TLS TR/TF TSU TDH TD Parameter Data Shift Frequency Clock High Level Width Clock Low Level Width Clock Set-up Time Clock Set-up Time Clock Rise/Fall Time Data Set-up Time Data Hold Time Data Delay Time Test Condition Min. CL2 à CL1 CL1 à CL2 CL = 15 P F 800 800 500 500 300 300 - Max. 400 200 500 Unit KHZ ns ns ns ns ns ns ns ns Applicable pin CL2 CL1,CL2 CL2 CL1,CL2 CL1,CL2 CL1,CL2 DL1,DL2,DR1,DR2 DL1,DL2,DR1,DR2 DL1,DL2,DR1,DR2 Maximum Absolute Ratings : Symbol VDD T OPR T STG Parameters Supply Voltage Operating Temperature Storage Temperature Min. -0.3 -20 -55 Max. 7 75 125 Unit V 0 C C 0 LCD Controller /Driver 9 /10 V1.1 GSM793E Dot Matrix LCD Panel Syntek Semiconductor Co., Ltd. COM116 D SHL1 SHL2 GND VEE DL1 VDD DR2 DL2 DR1 CL1 CL2 M SEG140 S1-S80 DL1 VDD SHL1 SHL2 GND VEE S1-S80 DR2 DL2 DR1 CL1 CL2 M GSM793E GSM793E Application Circuit : (2Line x 40Word) GSM7980 V1 V2 V3 V4 V1 V2 V3 V4 DB0-DB7 Reg. To MPU Vdd (+5V/+3V ) Reg. Reg. Reg. Reg. Reg. -V or GND LCD Controller /Driver Vdd GND CL2 CL1 M V1 V2 V3 V4 V5 Note: R= 2.2K ~ 10K, VR= 1K~30K 10 /10 V1.1