KXPS5

AN 009 Getting Started with the KXPS5 Introduction This application note will help users quickly implement proof-of-concept designs using the I2C or SPI digital interfaces of the KXPS5 tri-axis accelerometer. Please refer to the KXPS5 Data Sheet for additional implementation guidelines. Circuit Schematics This section shows recommended wiring schematics for the KXPS5 when operating in both I2C and SPI modes. It also describes an RC method for enabling the KXPS5 upon power up. Please refer to the KXPS5 Data Sheet for all pin descriptions. Note: these schematics are recommendations based on proven KXPS5 operation. Your specific application may require modifications from these recommendations. I2C Schematic Vdd 14 1 R1, R2 = 2.1Kohm Vdd 13 2 R2 MOT Enable 12 C1 Logic Input Logic Output R1 Vdd(1) or GND(0) Bi-directional Data Master Clock 3 ADDR 4 SDA 5 SCL 6 Enable X 7 FF/MOT 11 KXPS5 IC 2 GND 10 Z9 C4 Logic Input or RC Y8 C3 C2 Figure 1. Schematic for I2C Operation 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax: 607-257-1146 www.kionix.com - info@kionix.com © 2006 Kionix, Inc. 9 March 2006 Page 1 of 6 AN 009 SPI Schematic Vd d 14 1 Logic Input Logic Input Logic O u tput Vd d 13 2 CS 3 SDI 4 SD O 5 SC L K 6 E nable M O T E nable 12 C1 Logic Input Logic O u tput FF/M O T 11 KXPS5 SPI GN D 10 M a ster C lock Lo gic Input o r R C Z9 C4 Y8 X 7 C3 C2 Figure 2. Schematic for SPI Operation RC Enable A good design practice is to control the KXPS5 Enable pin (6) with a microprocessor, but it is also possible to enable the KXPS5 using the RC circuit shown in Figure 3. This circuit will transition the Enable pin high at power on, properly enabling the accelerometer after power has been supplied. Note that the RC values are just recommendations, therefore the final schematic may differ based on application needs. Vdd 10Kohm 6 Enable 0.1uf Figure 3. Schematic for RC Enable © Kionix 2006 9 March 2006 Page 2 of 6 AN 009 Filter Cap Recommendations To be effective in many applications, such as HDD protection, the KXPS5 needs to respond to changes in acceleration as quickly as possible. The accelerometer’s bandwidth, and in turn its response time, is largely determined by the external filter capacitance. Therefore, the filter capacitance should be as small as the application will allow. Table 1 shows several commonly used bandwidths and the associated capacitor values for C2, C3, and C4 in the circuits shown above. For most applications, 500Hz (0.01uF) should be a good starting point. Also, the KXPS5 has an internal 1000Hz 1st order low pass filter that allows for operation without any external capacitors. Bandwidth (Hz) 50 250 500 Capacitance (uF) 0.10 0.02 0.01 Table 1. Bandwidth (Hz) and Capacitance (uF) Quick Start Implementation The KXPS5 offers the user a powerful range of operating options and features, mostly controlled by setting appropriate values in registers. This section is not a comprehensive guide to all of the options and features. Rather it is intended to guide the user to an implementation of the KXPS5 that will get the device up and running as quickly as possible. Once up and running, the user should experiment with different setting and options to reach the optimum performance for their specific application. The registers shown in Table 2 need to be set to get the KXPS5 up and running: Address Hex Binary 0x0D 0000 1101 0x0C 0000 1100 0x08 0000 1000 0x09 0000 1001 0x0A 0000 1010 0x0B 0000 1011 Recommended Value Hex Binary 0x42 0100 0010 0x00 0000 0000 0x0E 0000 1110 0x14 0001 0100 0x55 0101 0101 0x14 0001 0100 Register Name CTRL_REGB CTRL_REGC FF_INT FF_DELAY MOT_INT MOT_DELAY Table 2. KXPS5 Registers For each register, a set of initial recommended values is provided that will ensure the KXPS5 is configured to a known operational state. Note that these conditions just provide a starting point, and the values should vary as users refine their application requirements. © Kionix 2006 9 March 2006 Page 3 of 6 AN 009 Register Recommendations CTRL_REGB CLKhld ENABLE 0 1 ST 0 X 0 X 0 X 0 FFIen 1 XI 0 Figure 4. Operational Starting Point for CTRL_REGB CLKhld = 0: The KXPS5 will not hold the I2C clock during A/D conversions. ENABLE = 1: The KXPS5 is enabled/operational. ST = 0: The KXPS5 self-test function is not enabled/operational. FFIen = 1: Free-fall detection interrupt is enabled/operational. CTRL_REGC X 0 X 0 X 0 FFLatch MOTLatch 0 0 X 0 IntSpd1 IntSpd0 0 0 Figure 5. Operational Starting Point for CTRL_REGC FFLatch = 0: The free-fall interrupt output will go high whenever the criterion for free-fall detection is met. The output will return low when the criterion is not met. MOTLatch = 0: The motion interrupt output will go high whenever the criterion for motion detection is met. The output will return low when the criterion is not met. IntSpd1 and IntSpd0 = 0: The interrupt sampling frequency is 250 samples/second. Therefore, the interrupt delay times can be calculated using Equation 1. Free-fall Delay (sec) = FF_Delay (# of samples) / 250 (samples/sec) High-g Motion Delay (sec) = MOT_Delay (# of samples) / 250 (samples/sec) Equation 1. Free-fall and Motion Delay Calculations Thresholds and Delays The following are some suggested acceleration thresholds and delay (or dwell) times appropriate for many HDD protection applications. For each suggested parameter the appropriate register value is provided in binary and hexadecimal. Free fall Detection Threshold = 0.4g FF_INT = (0000 1110 or 0x0E) Delay Time = 80mS FF_DELAY = (0001 0100 or 0x14) High-g Motion Detection Threshold = 2.5g MOT_INT = (0101 0101 or 0x55) © Kionix 2006 9 March 2006 Page 4 of 6 AN 009 Delay Time = 80mS MOT_DELAY = (0001 0100 or 0x14) Expected Results When the registers are loaded with the recommended values and the MOT Enable pin (12) is pulled high, the KXPS5 becomes armed for HDD protection. This means that the FF/MOT interrupt will be triggered if the accelerometer experiences an event that exceeds any of the above described thresholds and delays. In this case, FF/MOT will go high if all accelerometer axis (X, Y, and Z) simultaneously drop below 0.4g for more than 80mS or if any accelerometer axis (X, Y, or Z) go rise above 2.5g for more than 80mS. Figures 6 and 7 show how the KXPS5 interrupts will react to a typical event. By monitoring the interrupt pin (11), or repeatedly reading the status register, CTRL_REGA (0x0C), the user will be notified of a harmful event and must park/unload the HDD head for protection. Note that the interrupts are selected to be unlatched, so they will return low after the event has concluded. For additional information, please refer to the KXPS5 Data Sheet. © Kionix 2006 9 March 2006 Page 5 of 6 AN 009 Typical Motion Interrupt Example (Unlatched) 255 Pos. Motion limit Pos. Freefall limit 0g Neg. Freefall limit Neg. Motion limit 213 142 128 114 43 0 Motion debounce timer 20 Set to 20 counts. = 2 counts = 8 ms Motion Interrupt Figure 6. Typical Motion Interrupt Example (MOTLatch = 0) Typical Freefall Interrupt Example (Unlatched) 255 Pos. Motion limit Pos. Freefall limit 0g Neg. Freefall limit Neg. Motion limit 213 142 128 114 43 0 Freefall debounce timer 20 Set to 20 counts. = 2 counts = 8 ms Freefall Interrupt Figure 7. Typical Free-fall Interrupt Example (FFLatch = 0) © Kionix 2006 9 March 2006 Page 6 of 6