LM3S2016-IRN25-B0T

P R E L IMI NAR Y LM3S2016 Microcontroller D ATA SH E E T D S -LM3 S 2 016 - 1 9 7 2 Copyr i ght © 2007 Lum i nar y M i c ro, Inc. Legal Disclaimers and Trademark Information INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH LUMINARY MICRO PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN LUMINARY MICRO'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, LUMINARY MICRO ASSUMES NO LIABILITY WHATSOEVER, AND LUMINARY MICRO DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF LUMINARY MICRO'S PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. LUMINARY MICRO'S PRODUCTS ARE NOT INTENDED FOR USE IN MEDICAL, LIFE SAVING, OR LIFE-SUSTAINING APPLICATIONS. Luminary Micro may make changes to specifications and product descriptions at any time, without notice. Contact your local Luminary Micro sales office or your distributor to obtain the latest specifications before placing your product order. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Luminary Micro reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. Copyright © 2007 Luminary Micro, Inc. All rights reserved. Stellaris, Luminary Micro, and the Luminary Micro logo are registered trademarks of Luminary Micro, Inc. or its subsidiaries in the United States and other countries. ARM and Thumb are registered trademarks and Cortex is a trademark of ARM Limited. Other names and brands may be claimed as the property of others. Luminary Micro, Inc. 108 Wild Basin, Suite 350 Austin, TX 78746 Main: +1-512-279-8800 Fax: +1-512-279-8879 http://www.luminarymicro.com 2 Preliminary November 30, 2007 LM3S2016 Microcontroller Table of Contents About This Document .................................................................................................................... 18 Audience .............................................................................................................................................. About This Manual ................................................................................................................................ Related Documents ............................................................................................................................... Documentation Conventions .................................................................................................................. 18 18 18 18 20 25 25 26 27 27 28 28 30 30 31 31 34 34 34 35 35 35 35 35 1 1.1 1.2 1.3 1.4 1.4.1 1.4.2 1.4.3 1.4.4 1.4.5 1.4.6 1.4.7 1.4.8 Architectural Overview ...................................................................................................... 20 Product Features ...................................................................................................................... Target Applications .................................................................................................................... High-Level Block Diagram ......................................................................................................... Functional Overview .................................................................................................................. ARM Cortex™-M3 ..................................................................................................................... Motor Control Peripherals .......................................................................................................... Analog Peripherals .................................................................................................................... Serial Communications Peripherals ............................................................................................ System Peripherals ................................................................................................................... Memory Peripherals .................................................................................................................. Additional Features ................................................................................................................... Hardware Details ...................................................................................................................... Block Diagram .......................................................................................................................... Functional Description ............................................................................................................... Serial Wire and JTAG Debug ..................................................................................................... Embedded Trace Macrocell (ETM) ............................................................................................. Trace Port Interface Unit (TPIU) ................................................................................................. ROM Table ............................................................................................................................... Memory Protection Unit (MPU) ................................................................................................... Nested Vectored Interrupt Controller (NVIC) ................................................................................ 2 2.1 2.2 2.2.1 2.2.2 2.2.3 2.2.4 2.2.5 2.2.6 ARM Cortex-M3 Processor Core ...................................................................................... 33 3 4 5 5.1 5.2 5.2.1 5.2.2 5.2.3 5.2.4 5.3 5.4 5.4.1 5.4.2 Memory Map ....................................................................................................................... 39 Interrupts ............................................................................................................................ 41 JTAG Interface .................................................................................................................... 43 Block Diagram .......................................................................................................................... Functional Description ............................................................................................................... JTAG Interface Pins .................................................................................................................. JTAG TAP Controller ................................................................................................................. Shift Registers .......................................................................................................................... Operational Considerations ........................................................................................................ Initialization and Configuration ................................................................................................... Register Descriptions ................................................................................................................ Instruction Register (IR) ............................................................................................................. Data Registers .......................................................................................................................... 44 44 45 46 47 47 50 50 50 52 6 6.1 6.1.1 6.1.2 System Control ................................................................................................................... 54 Functional Description ............................................................................................................... 54 Device Identification .................................................................................................................. 54 Reset Control ............................................................................................................................ 54 November 30, 2007 Preliminary 3 Table of Contents 6.1.3 6.1.4 6.1.5 6.2 6.3 6.4 Power Control ........................................................................................................................... Clock Control ............................................................................................................................ System Control ......................................................................................................................... Initialization and Configuration ................................................................................................... Register Map ............................................................................................................................ Register Descriptions ................................................................................................................ 57 57 59 59 60 61 7 7.1 7.2 7.2.1 7.2.2 7.3 7.3.1 7.3.2 7.4 7.5 7.6 Internal Memory ............................................................................................................... 109 Block Diagram ........................................................................................................................ 109 Functional Description ............................................................................................................. 109 SRAM Memory ........................................................................................................................ 109 Flash Memory ......................................................................................................................... 110 Flash Memory Initialization and Configuration ........................................................................... 111 Flash Programming ................................................................................................................. 111 Nonvolatile Register Programming ........................................................................................... 112 Register Map .......................................................................................................................... 112 Flash Register Descriptions (Flash Control Offset) ..................................................................... 113 Flash Register Descriptions (System Control Offset) .................................................................. 120 8 8.1 8.1.1 8.1.2 8.1.3 8.1.4 8.1.5 8.1.6 8.2 8.3 8.4 General-Purpose Input/Outputs (GPIOs) ....................................................................... 133 Functional Description ............................................................................................................. 133 Data Control ........................................................................................................................... 134 Interrupt Control ...................................................................................................................... 135 Mode Control .......................................................................................................................... 136 Commit Control ....................................................................................................................... 136 Pad Control ............................................................................................................................. 136 Identification ........................................................................................................................... 136 Initialization and Configuration ................................................................................................. 136 Register Map .......................................................................................................................... 137 Register Descriptions .............................................................................................................. 139 9 9.1 9.2 9.2.1 9.2.2 9.2.3 9.3 9.3.1 9.3.2 9.3.3 9.3.4 9.3.5 9.3.6 9.4 9.5 General-Purpose Timers ................................................................................................. 174 Block Diagram ........................................................................................................................ Functional Description ............................................................................................................. GPTM Reset Conditions .......................................................................................................... 32-Bit Timer Operating Modes .................................................................................................. 16-Bit Timer Operating Modes .................................................................................................. Initialization and Configuration ................................................................................................. 32-Bit One-Shot/Periodic Timer Mode ....................................................................................... 32-Bit Real-Time Clock (RTC) Mode ......................................................................................... 16-Bit One-Shot/Periodic Timer Mode ....................................................................................... 16-Bit Input Edge Count Mode ................................................................................................. 16-Bit Input Edge Timing Mode ................................................................................................ 16-Bit PWM Mode ................................................................................................................... Register Map .......................................................................................................................... Register Descriptions .............................................................................................................. 174 175 175 176 177 181 181 182 182 183 183 184 184 185 10 10.1 10.2 10.3 Watchdog Timer ............................................................................................................... 210 Block Diagram ........................................................................................................................ 210 Functional Description ............................................................................................................. 210 Initialization and Configuration ................................................................................................. 211 4 Preliminary November 30, 2007 LM3S2016 Microcontroller 10.4 10.5 Register Map .......................................................................................................................... 211 Register Descriptions .............................................................................................................. 212 11 11.1 11.2 11.2.1 11.2.2 11.2.3 11.2.4 11.2.5 11.3 11.3.1 11.3.2 11.4 11.5 Analog-to-Digital Converter (ADC) ................................................................................. 233 Block Diagram ........................................................................................................................ 234 Functional Description ............................................................................................................. 234 Sample Sequencers ................................................................................................................ 234 Module Control ........................................................................................................................ 235 Hardware Sample Averaging Circuit ......................................................................................... 236 Analog-to-Digital Converter ...................................................................................................... 236 Test Modes ............................................................................................................................. 236 Initialization and Configuration ................................................................................................. 236 Module Initialization ................................................................................................................. 236 Sample Sequencer Configuration ............................................................................................. 236 Register Map .......................................................................................................................... 237 Register Descriptions .............................................................................................................. 238 12 12.1 12.2 12.2.1 12.2.2 12.2.3 12.2.4 12.2.5 12.2.6 12.2.7 12.2.8 12.3 12.4 12.5 Universal Asynchronous Receivers/Transmitters (UARTs) ......................................... 265 Block Diagram ........................................................................................................................ Functional Description ............................................................................................................. Transmit/Receive Logic ........................................................................................................... Baud-Rate Generation ............................................................................................................. Data Transmission .................................................................................................................. Serial IR (SIR) ......................................................................................................................... FIFO Operation ....................................................................................................................... Interrupts ................................................................................................................................ Loopback Operation ................................................................................................................ IrDA SIR block ........................................................................................................................ Initialization and Configuration ................................................................................................. Register Map .......................................................................................................................... Register Descriptions .............................................................................................................. Block Diagram ........................................................................................................................ Functional Description ............................................................................................................. Bit Rate Generation ................................................................................................................. FIFO Operation ....................................................................................................................... Interrupts ................................................................................................................................ Frame Formats ....................................................................................................................... Initialization and Configuration ................................................................................................. Register Map .......................................................................................................................... Register Descriptions .............................................................................................................. Block Diagram ........................................................................................................................ Functional Description ............................................................................................................. I2C Bus Functional Overview .................................................................................................... Available Speed Modes ........................................................................................................... Interrupts ................................................................................................................................ Loopback Operation ................................................................................................................ Command Sequence Flow Charts ............................................................................................ 266 266 266 267 268 268 269 269 270 270 270 271 272 306 306 307 307 307 308 315 316 317 343 343 344 346 347 347 348 13 13.1 13.2 13.2.1 13.2.2 13.2.3 13.2.4 13.3 13.4 13.5 Synchronous Serial Interface (SSI) ................................................................................ 306 14 14.1 14.2 14.2.1 14.2.2 14.2.3 14.2.4 14.2.5 Inter-Integrated Circuit (I2C) Interface ............................................................................ 343 November 30, 2007 Preliminary 5 Table of Contents 14.3 14.4 14.5 14.6 Initialization and Configuration ................................................................................................. I2C Register Map ..................................................................................................................... Register Descriptions (I2C Master) ........................................................................................... Register Descriptions (I2C Slave) ............................................................................................. 354 355 356 369 378 378 379 380 380 381 381 381 382 382 383 383 383 383 384 384 385 385 387 389 391 15 Controller Area Network (CAN) Module ......................................................................... 378 15.1 Controller Area Network Overview ............................................................................................ 15.2 Controller Area Network Features ............................................................................................ 15.3 Controller Area Network Block Diagram .................................................................................... 15.4 Controller Area Network Functional Description ......................................................................... 15.4.1 Initialization ............................................................................................................................. 15.4.2 Operation ............................................................................................................................... 15.4.3 Transmitting Message Objects ................................................................................................. 15.4.4 Configuring a Transmit Message Object .................................................................................... 15.4.5 Updating a Transmit Message Object ....................................................................................... 15.4.6 Accepting Received Message Objects ...................................................................................... 15.4.7 Receiving a Data Frame .......................................................................................................... 15.4.8 Receiving a Remote Frame ...................................................................................................... 15.4.9 Receive/Transmit Priority ......................................................................................................... 15.4.10 Configuring a Receive Message Object .................................................................................... 15.4.11 Handling of Received Message Objects .................................................................................... 15.4.12 Handling of Interrupts .............................................................................................................. 15.4.13 Bit Timing Configuration Error Considerations ........................................................................... 15.4.14 Bit Time and Bit Rate ............................................................................................................... 15.4.15 Calculating the Bit Timing Parameters ...................................................................................... 15.5 Controller Area Network Register Map ...................................................................................... 15.6 Register Descriptions .............................................................................................................. 16 17 18 19 19.1 19.1.1 19.1.2 19.1.3 19.1.4 19.1.5 19.2 19.2.1 19.2.2 19.2.3 19.2.4 19.2.5 19.2.6 19.2.7 19.2.8 Pin Diagram ...................................................................................................................... 419 Signal Tables .................................................................................................................... 420 Operating Characteristics ............................................................................................... 432 Electrical Characteristics ................................................................................................ 433 DC Characteristics .................................................................................................................. 433 Maximum Ratings ................................................................................................................... 433 Recommended DC Operating Conditions .................................................................................. 433 On-Chip Low Drop-Out (LDO) Regulator Characteristics ............................................................ 434 Power Specifications ............................................................................................................... 434 Flash Memory Characteristics .................................................................................................. 435 AC Characteristics ................................................................................................................... 436 Load Conditions ...................................................................................................................... 436 Clocks .................................................................................................................................... 436 Analog-to-Digital Converter ...................................................................................................... 437 I2C ......................................................................................................................................... 437 Synchronous Serial Interface (SSI) ........................................................................................... 438 JTAG and Boundary Scan ........................................................................................................ 439 General-Purpose I/O ............................................................................................................... 441 Reset ..................................................................................................................................... 441 6 Preliminary November 30, 2007 LM3S2016 Microcontroller 20 A A.1 A.2 A.2.1 A.2.2 A.3 A.3.1 A.3.2 A.3.3 A.4 A.4.1 A.4.2 A.4.3 A.4.4 A.4.5 A.4.6 Package Information ........................................................................................................ 444 Serial Flash Loader .......................................................................................................... 446 Serial Flash Loader ................................................................................................................. Interfaces ............................................................................................................................... UART ..................................................................................................................................... SSI ......................................................................................................................................... Packet Handling ...................................................................................................................... Packet Format ........................................................................................................................ Sending Packets ..................................................................................................................... Receiving Packets ................................................................................................................... Commands ............................................................................................................................. COMMAND_PING (0X20) ........................................................................................................ COMMAND_GET_STATUS (0x23) ........................................................................................... COMMAND_DOWNLOAD (0x21) ............................................................................................. COMMAND_SEND_DATA (0x24) ............................................................................................. COMMAND_RUN (0x22) ......................................................................................................... COMMAND_RESET (0x25) ..................................................................................................... 446 446 446 446 447 447 447 447 448 448 448 448 449 449 449 B C C.1 C.2 C.3 C.4 Register Quick Reference ............................................................................................... 451 Ordering and Contact Information ................................................................................. 467 Ordering Information ................................................................................................................ Kits ......................................................................................................................................... Company Information .............................................................................................................. Support Information ................................................................................................................. 467 467 467 468 November 30, 2007 Preliminary 7 Table of Contents List of Figures Figure 1-1. Figure 2-1. Figure 2-2. Figure 5-1. Figure 5-2. Figure 5-3. Figure 5-4. Figure 5-5. Figure 6-1. Figure 7-1. Figure 8-1. Figure 8-2. Figure 8-3. Figure 9-1. Figure 9-2. Figure 9-3. Figure 9-4. Figure 10-1. Figure 11-1. Figure 12-1. Figure 12-2. Figure 12-3. Figure 13-1. Figure 13-2. Figure 13-3. Figure 13-4. Figure 13-5. Figure 13-6. Figure 13-7. Figure 13-8. Figure 13-9. Figure 13-10. Figure 13-11. Figure 13-12. Figure 14-1. Figure 14-2. Figure 14-3. Figure 14-4. Figure 14-5. Figure 14-6. Figure 14-7. Figure 14-8. Figure 14-9. Figure 14-10. Figure 14-11. Stellaris 2000 Series High-Level Block Diagram ............................................................... 26 CPU Block Diagram ......................................................................................................... 34 TPIU Block Diagram ........................................................................................................ 35 JTAG Module Block Diagram ............................................................................................ 44 Test Access Port State Machine ....................................................................................... 47 IDCODE Register Format ................................................................................................. 52 BYPASS Register Format ................................................................................................ 53 Boundary Scan Register Format ....................................................................................... 53 External Circuitry to Extend Reset .................................................................................... 55 Flash Block Diagram ...................................................................................................... 109 GPIO Port Block Diagram ............................................................................................... 134 GPIODATA Write Example ............................................................................................. 135 GPIODATA Read Example ............................................................................................. 135 GPTM Module Block Diagram ........................................................................................ 175 16-Bit Input Edge Count Mode Example .......................................................................... 179 16-Bit Input Edge Time Mode Example ........................................................................... 180 16-Bit PWM Mode Example ............................................................................................ 181 WDT Module Block Diagram .......................................................................................... 210 ADC Module Block Diagram ........................................................................................... 234 UART Module Block Diagram ......................................................................................... 266 UART Character Frame ................................................................................................. 267 IrDA Data Modulation ..................................................................................................... 269 SSI Module Block Diagram ............................................................................................. 306 TI Synchronous Serial Frame Format (Single Transfer) .................................................... 308 TI Synchronous Serial Frame Format (Continuous Transfer) ............................................ 309 Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 ...................................... 310 Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .............................. 310 Freescale SPI Frame Format with SPO=0 and SPH=1 ..................................................... 311 Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ........................... 312 Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 .................... 312 Freescale SPI Frame Format with SPO=1 and SPH=1 ..................................................... 313 MICROWIRE Frame Format (Single Frame) .................................................................... 314 MICROWIRE Frame Format (Continuous Transfer) ......................................................... 315 MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ........................ 315 I2C Block Diagram ......................................................................................................... 343 I2C Bus Configuration .................................................................................................... 344 START and STOP Conditions ......................................................................................... 344 Complete Data Transfer with a 7-Bit Address ................................................................... 345 R/S Bit in First Byte ........................................................................................................ 345 Data Validity During Bit Transfer on the I2C Bus ............................................................... 345 Master Single SEND ...................................................................................................... 348 Master Single RECEIVE ................................................................................................. 349 Master Burst SEND ....................................................................................................... 350 Master Burst RECEIVE .................................................................................................. 351 Master Burst RECEIVE after Burst SEND ........................................................................ 352 ® 8 Preliminary November 30, 2007 LM3S2016 Microcontroller Figure 14-12. Figure 14-13. Figure 15-1. Figure 15-2. Figure 16-1. Figure 19-1. Figure 19-2. Figure 19-3. Figure 19-4. Figure 19-5. Figure 19-6. Figure 19-7. Figure 19-8. Figure 19-9. Figure 19-10. Figure 19-11. Figure 19-12. Figure 19-13. Figure 20-1. Master Burst SEND after Burst RECEIVE ........................................................................ 353 Slave Command Sequence ............................................................................................ 354 CAN Module Block Diagram ........................................................................................... 379 CAN Bit Time ................................................................................................................ 386 Pin Connection Diagram ................................................................................................ 419 Load Conditions ............................................................................................................ 436 I2C Timing ..................................................................................................................... 438 SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement .............. 438 SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ............................. 439 SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ................................................. 439 JTAG Test Clock Input Timing ......................................................................................... 440 JTAG Test Access Port (TAP) Timing .............................................................................. 441 JTAG TRST Timing ........................................................................................................ 441 External Reset Timing (RST) .......................................................................................... 442 Power-On Reset Timing ................................................................................................. 442 Brown-Out Reset Timing ................................................................................................ 442 Software Reset Timing ................................................................................................... 443 Watchdog Reset Timing ................................................................................................. 443 100-Pin LQFP Package .................................................................................................. 444 November 30, 2007 Preliminary 9 Table of Contents List of Tables Table 1. Table 3-1. Table 4-1. Table 4-2. Table 5-1. Table 5-2. Table 6-1. Table 7-1. Table 7-2. Table 7-3. Table 8-1. Table 8-2. Table 8-3. Table 9-1. Table 9-2. Table 9-3. Table 10-1. Table 11-1. Table 11-2. Table 12-1. Table 13-1. Table 14-1. Table 14-2. Table 14-3. Table 15-1. Table 15-2. Table 15-3. Table 15-4. Table 17-1. Table 17-2. Table 17-3. Table 17-4. Table 18-1. Table 18-2. Table 19-1. Table 19-2. Table 19-3. Table 19-4. Table 19-5. Table 19-6. Table 19-7. Table 19-8. Table 19-9. Table 19-10. Table 19-11. Table 19-12. Documentation Conventions ............................................................................................ 18 Memory Map ................................................................................................................... 39 Exception Types .............................................................................................................. 41 Interrupts ........................................................................................................................ 42 JTAG Port Pins Reset State ............................................................................................. 45 JTAG Instruction Register Commands ............................................................................... 50 System Control Register Map ........................................................................................... 60 Flash Protection Policy Combinations ............................................................................. 111 Flash Resident Registers ............................................................................................... 112 Flash Register Map ........................................................................................................ 112 GPIO Pad Configuration Examples ................................................................................. 137 GPIO Interrupt Configuration Example ............................................................................ 137 GPIO Register Map ....................................................................................................... 138 Available CCP Pins ........................................................................................................ 175 16-Bit Timer With Prescaler Configurations ..................................................................... 178 Timers Register Map ...................................................................................................... 184 Watchdog Timer Register Map ........................................................................................ 211 Samples and FIFO Depth of Sequencers ........................................................................ 234 ADC Register Map ......................................................................................................... 237 UART Register Map ....................................................................................................... 271 SSI Register Map .......................................................................................................... 316 Examples of I2C Master Timer Period versus Speed Mode ............................................... 346 Inter-Integrated Circuit (I2C) Interface Register Map ......................................................... 355 Write Field Decoding for I2CMCS[3:0] Field (Sheet 1 of 3) ................................................ 360 Transmit Message Object Bit Settings ............................................................................. 382 Receive Message Object Bit Settings .............................................................................. 384 CAN Protocol Ranges .................................................................................................... 386 CAN Register Map ......................................................................................................... 389 Signals by Pin Number ................................................................................................... 420 Signals by Signal Name ................................................................................................. 423 Signals by Function, Except for GPIO ............................................................................. 427 GPIO Pins and Alternate Functions ................................................................................. 430 Temperature Characteristics ........................................................................................... 432 Thermal Characteristics ................................................................................................. 432 Maximum Ratings .......................................................................................................... 433 Recommended DC Operating Conditions ........................................................................ 433 LDO Regulator Characteristics ....................................................................................... 434 Detailed Power Specifications ........................................................................................ 435 Flash Memory Characteristics ........................................................................................ 435 Phase Locked Loop (PLL) Characteristics ....................................................................... 436 Clock Characteristics ..................................................................................................... 436 Crystal Characteristics ................................................................................................... 436 ADC Characteristics ....................................................................................................... 437 I2C Characteristics ......................................................................................................... 437 SSI Characteristics ........................................................................................................ 438 JTAG Characteristics ..................................................................................................... 439 10 Preliminary November 30, 2007 LM3S2016 Microcontroller Table 19-13. GPIO Characteristics ..................................................................................................... 441 Table 19-14. Reset Characteristics ..................................................................................................... 441 Table C-1. Part Ordering Information ............................................................................................... 467 November 30, 2007 Preliminary 11 Table of Contents List of Registers System Control .............................................................................................................................. 54 Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: Register 17: Register 18: Register 19: Register 20: Register 21: Register 22: Register 23: Register 24: Register 25: Register 26: Register 27: Register 28: Register 29: Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Device Identification 0 (DID0), offset 0x000 ....................................................................... 62 Brown-Out Reset Control (PBORCTL), offset 0x030 .......................................................... 64 LDO Power Control (LDOPCTL), offset 0x034 ................................................................... 65 Raw Interrupt Status (RIS), offset 0x050 ........................................................................... 66 Interrupt Mask Control (IMC), offset 0x054 ........................................................................ 67 Masked Interrupt Status and Clear (MISC), offset 0x058 .................................................... 68 Reset Cause (RESC), offset 0x05C .................................................................................. 69 Run-Mode Clock Configuration (RCC), offset 0x060 .......................................................... 70 XTAL to PLL Translation (PLLCFG), offset 0x064 .............................................................. 74 Run-Mode Clock Configuration 2 (RCC2), offset 0x070 ...................................................... 75 Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 .......................................... 77 Device Identification 1 (DID1), offset 0x004 ....................................................................... 78 Device Capabilities 0 (DC0), offset 0x008 ......................................................................... 80 Device Capabilities 1 (DC1), offset 0x010 ......................................................................... 81 Device Capabilities 2 (DC2), offset 0x014 ......................................................................... 83 Device Capabilities 3 (DC3), offset 0x018 ......................................................................... 85 Device Capabilities 4 (DC4), offset 0x01C ......................................................................... 87 Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100 .................................... 88 Sleep Mode Clock Gating Control Register 0 (SCGC0), offset 0x110 .................................. 90 Deep Sleep Mode Clock Gating Control Register 0 (DCGC0), offset 0x120 ......................... 92 Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104 .................................... 94 Sleep Mode Clock Gating Control Register 1 (SCGC1), offset 0x114 .................................. 96 Deep Sleep Mode Clock Gating Control Register 1 (DCGC1), offset 0x124 ......................... 98 Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108 ................................... 100 Sleep Mode Clock Gating Control Register 2 (SCGC2), offset 0x118 ................................. 102 Deep Sleep Mode Clock Gating Control Register 2 (DCGC2), offset 0x128 ....................... 104 Software Reset Control 0 (SRCR0), offset 0x040 ............................................................. 106 Software Reset Control 1 (SRCR1), offset 0x044 ............................................................. 107 Software Reset Control 2 (SRCR2), offset 0x048 ............................................................. 108 Flash Memory Address (FMA), offset 0x000 .................................................................... Flash Memory Data (FMD), offset 0x004 ......................................................................... Flash Memory Control (FMC), offset 0x008 ..................................................................... Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C ............................................ Flash Controller Interrupt Mask (FCIM), offset 0x010 ........................................................ Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014 ..................... USec Reload (USECRL), offset 0x140 ............................................................................ Flash Memory Protection Read Enable 0 (FMPRE0), offset 0x130 and 0x200 ................... Flash Memory Protection Program Enable 0 (FMPPE0), offset 0x134 and 0x400 ............... User Debug (USER_DBG), offset 0x1D0 ......................................................................... User Register 0 (USER_REG0), offset 0x1E0 .................................................................. User Register 1 (USER_REG1), offset 0x1E4 .................................................................. Flash Memory Protection Read Enable 1 (FMPRE1), offset 0x204 .................................... Flash Memory Protection Read Enable 2 (FMPRE2), offset 0x208 .................................... 114 115 116 118 119 120 121 122 123 124 125 126 127 128 Internal Memory ........................................................................................................................... 109 12 Preliminary November 30, 2007 LM3S2016 Microcontroller Register 15: Register 16: Register 17: Register 18: Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: Register 17: Register 18: Register 19: Register 20: Register 21: Register 22: Register 23: Register 24: Register 25: Register 26: Register 27: Register 28: Register 29: Register 30: Register 31: Register 32: Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Flash Memory Protection Read Enable 3 (FMPRE3), offset 0x20C ................................... Flash Memory Protection Program Enable 1 (FMPPE1), offset 0x404 ............................... Flash Memory Protection Program Enable 2 (FMPPE2), offset 0x408 ............................... Flash Memory Protection Program Enable 3 (FMPPE3), offset 0x40C ............................... 129 130 131 132 General-Purpose Input/Outputs (GPIOs) ................................................................................... 133 GPIO Data (GPIODATA), offset 0x000 ............................................................................ 140 GPIO Direction (GPIODIR), offset 0x400 ......................................................................... 141 GPIO Interrupt Sense (GPIOIS), offset 0x404 .................................................................. 142 GPIO Interrupt Both Edges (GPIOIBE), offset 0x408 ........................................................ 143 GPIO Interrupt Event (GPIOIEV), offset 0x40C ................................................................ 144 GPIO Interrupt Mask (GPIOIM), offset 0x410 ................................................................... 145 GPIO Raw Interrupt Status (GPIORIS), offset 0x414 ........................................................ 146 GPIO Masked Interrupt Status (GPIOMIS), offset 0x418 ................................................... 147 GPIO Interrupt Clear (GPIOICR), offset 0x41C ................................................................ 148 GPIO Alternate Function Select (GPIOAFSEL), offset 0x420 ............................................ 149 GPIO 2-mA Drive Select (GPIODR2R), offset 0x500 ........................................................ 151 GPIO 4-mA Drive Select (GPIODR4R), offset 0x504 ........................................................ 152 GPIO 8-mA Drive Select (GPIODR8R), offset 0x508 ........................................................ 153 GPIO Open Drain Select (GPIOODR), offset 0x50C ......................................................... 154 GPIO Pull-Up Select (GPIOPUR), offset 0x510 ................................................................ 155 GPIO Pull-Down Select (GPIOPDR), offset 0x514 ........................................................... 156 GPIO Slew Rate Control Select (GPIOSLR), offset 0x518 ................................................ 157 GPIO Digital Enable (GPIODEN), offset 0x51C ................................................................ 158 GPIO Lock (GPIOLOCK), offset 0x520 ............................................................................ 159 GPIO Commit (GPIOCR), offset 0x524 ............................................................................ 160 GPIO Peripheral Identification 4 (GPIOPeriphID4), offset 0xFD0 ....................................... 162 GPIO Peripheral Identification 5 (GPIOPeriphID5), offset 0xFD4 ....................................... 163 GPIO Peripheral Identification 6 (GPIOPeriphID6), offset 0xFD8 ....................................... 164 GPIO Peripheral Identification 7 (GPIOPeriphID7), offset 0xFDC ...................................... 165 GPIO Peripheral Identification 0 (GPIOPeriphID0), offset 0xFE0 ....................................... 166 GPIO Peripheral Identification 1 (GPIOPeriphID1), offset 0xFE4 ....................................... 167 GPIO Peripheral Identification 2 (GPIOPeriphID2), offset 0xFE8 ....................................... 168 GPIO Peripheral Identification 3 (GPIOPeriphID3), offset 0xFEC ...................................... 169 GPIO PrimeCell Identification 0 (GPIOPCellID0), offset 0xFF0 .......................................... 170 GPIO PrimeCell Identification 1 (GPIOPCellID1), offset 0xFF4 .......................................... 171 GPIO PrimeCell Identification 2 (GPIOPCellID2), offset 0xFF8 .......................................... 172 GPIO PrimeCell Identification 3 (GPIOPCellID3), offset 0xFFC ......................................... 173 GPTM Configuration (GPTMCFG), offset 0x000 .............................................................. GPTM TimerA Mode (GPTMTAMR), offset 0x004 ............................................................ GPTM TimerB Mode (GPTMTBMR), offset 0x008 ............................................................ GPTM Control (GPTMCTL), offset 0x00C ........................................................................ GPTM Interrupt Mask (GPTMIMR), offset 0x018 .............................................................. GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C ..................................................... GPTM Masked Interrupt Status (GPTMMIS), offset 0x020 ................................................ GPTM Interrupt Clear (GPTMICR), offset 0x024 .............................................................. GPTM TimerA Interval Load (GPTMTAILR), offset 0x028 ................................................. GPTM TimerB Interval Load (GPTMTBILR), offset 0x02C ................................................ 186 187 189 191 194 196 197 198 200 201 General-Purpose Timers ............................................................................................................. 174 November 30, 2007 Preliminary 13 Table of Contents Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: Register 17: Register 18: Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: Register 17: Register 18: Register 19: Register 20: Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: Register 17: Register 18: GPTM TimerA Match (GPTMTAMATCHR), offset 0x030 ................................................... GPTM TimerB Match (GPTMTBMATCHR), offset 0x034 .................................................. GPTM TimerA Prescale (GPTMTAPR), offset 0x038 ........................................................ GPTM TimerB Prescale (GPTMTBPR), offset 0x03C ....................................................... GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040 ........................................... GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044 ........................................... GPTM TimerA (GPTMTAR), offset 0x048 ........................................................................ GPTM TimerB (GPTMTBR), offset 0x04C ....................................................................... Watchdog Load (WDTLOAD), offset 0x000 ...................................................................... Watchdog Value (WDTVALUE), offset 0x004 ................................................................... Watchdog Control (WDTCTL), offset 0x008 ..................................................................... Watchdog Interrupt Clear (WDTICR), offset 0x00C .......................................................... Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 .................................................. Watchdog Masked Interrupt Status (WDTMIS), offset 0x014 ............................................. Watchdog Test (WDTTEST), offset 0x418 ....................................................................... Watchdog Lock (WDTLOCK), offset 0xC00 ..................................................................... Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0 ................................. Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4 ................................. Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8 ................................. Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC ................................ Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 ................................. Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 ................................. Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 ................................. Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC ................................. Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0 .................................... Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4 .................................... Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8 .................................... Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC .................................. 202 203 204 205 206 207 208 209 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 Watchdog Timer ........................................................................................................................... 210 Analog-to-Digital Converter (ADC) ............................................................................................. 233 ADC Active Sample Sequencer (ADCACTSS), offset 0x000 ............................................. 239 ADC Raw Interrupt Status (ADCRIS), offset 0x004 ........................................................... 240 ADC Interrupt Mask (ADCIM), offset 0x008 ..................................................................... 241 ADC Interrupt Status and Clear (ADCISC), offset 0x00C .................................................. 242 ADC Overflow Status (ADCOSTAT), offset 0x010 ............................................................ 243 ADC Event Multiplexer Select (ADCEMUX), offset 0x014 ................................................. 244 ADC Underflow Status (ADCUSTAT), offset 0x018 ........................................................... 247 ADC Sample Sequencer Priority (ADCSSPRI), offset 0x020 ............................................. 248 ADC Processor Sample Sequence Initiate (ADCPSSI), offset 0x028 ................................. 249 ADC Sample Averaging Control (ADCSAC), offset 0x030 ................................................. 250 ADC Sample Sequence Input Multiplexer Select 0 (ADCSSMUX0), offset 0x040 ............... 251 ADC Sample Sequence Control 0 (ADCSSCTL0), offset 0x044 ........................................ 253 ADC Sample Sequence Result FIFO 0 (ADCSSFIFO0), offset 0x048 ................................ 256 ADC Sample Sequence Result FIFO 1 (ADCSSFIFO1), offset 0x068 ................................ 256 ADC Sample Sequence Result FIFO 2 (ADCSSFIFO2), offset 0x088 ................................ 256 ADC Sample Sequence Result FIFO 3 (ADCSSFIFO3), offset 0x0A8 ............................... 256 ADC Sample Sequence FIFO 0 Status (ADCSSFSTAT0), offset 0x04C ............................. 257 ADC Sample Sequence FIFO 1 Status (ADCSSFSTAT1), offset 0x06C ............................. 257 14 Preliminary November 30, 2007 LM3S2016 Microcontroller Register 19: Register 20: Register 21: Register 22: Register 23: Register 24: Register 25: Register 26: Register 27: Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: Register 17: Register 18: Register 19: Register 20: Register 21: Register 22: Register 23: Register 24: Register 25: Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: ADC Sample Sequence FIFO 2 Status (ADCSSFSTAT2), offset 0x08C ............................ ADC Sample Sequence FIFO 3 Status (ADCSSFSTAT3), offset 0x0AC ............................ ADC Sample Sequence Input Multiplexer Select 1 (ADCSSMUX1), offset 0x060 ............... ADC Sample Sequence Input Multiplexer Select 2 (ADCSSMUX2), offset 0x080 ............... ADC Sample Sequence Control 1 (ADCSSCTL1), offset 0x064 ........................................ ADC Sample Sequence Control 2 (ADCSSCTL2), offset 0x084 ........................................ ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3), offset 0x0A0 ............... ADC Sample Sequence Control 3 (ADCSSCTL3), offset 0x0A4 ........................................ ADC Test Mode Loopback (ADCTMLB), offset 0x100 ....................................................... UART Data (UARTDR), offset 0x000 ............................................................................... UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 ........................... UART Flag (UARTFR), offset 0x018 ................................................................................ UART IrDA Low-Power Register (UARTILPR), offset 0x020 ............................................. UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 ............................................ UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 ....................................... UART Line Control (UARTLCRH), offset 0x02C ............................................................... UART Control (UARTCTL), offset 0x030 ......................................................................... UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 ........................................... UART Interrupt Mask (UARTIM), offset 0x038 ................................................................. UART Raw Interrupt Status (UARTRIS), offset 0x03C ...................................................... UART Masked Interrupt Status (UARTMIS), offset 0x040 ................................................. UART Interrupt Clear (UARTICR), offset 0x044 ............................................................... UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 ..................................... UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 ..................................... UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 ..................................... UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC ..................................... UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 ...................................... UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 ...................................... UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 ...................................... UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC ..................................... UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 ........................................ UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 ........................................ UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 ........................................ UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ........................................ SSI Control 0 (SSICR0), offset 0x000 .............................................................................. SSI Control 1 (SSICR1), offset 0x004 .............................................................................. SSI Data (SSIDR), offset 0x008 ...................................................................................... SSI Status (SSISR), offset 0x00C ................................................................................... SSI Clock Prescale (SSICPSR), offset 0x010 .................................................................. SSI Interrupt Mask (SSIIM), offset 0x014 ......................................................................... SSI Raw Interrupt Status (SSIRIS), offset 0x018 .............................................................. SSI Masked Interrupt Status (SSIMIS), offset 0x01C ........................................................ SSI Interrupt Clear (SSIICR), offset 0x020 ....................................................................... SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 ............................................. SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 ............................................. SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 ............................................. 257 257 258 258 259 259 261 262 263 273 275 277 279 280 281 282 284 286 288 290 291 292 294 295 296 297 298 299 300 301 302 303 304 305 318 320 322 323 325 326 328 329 330 331 332 333 Universal Asynchronous Receivers/Transmitters (UARTs) ..................................................... 265 Synchronous Serial Interface (SSI) ............................................................................................ 306 November 30, 2007 Preliminary 15 Table of Contents Register 13: Register 14: Register 15: Register 16: Register 17: Register 18: Register 19: Register 20: Register 21: Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: Register 17: Register 18: Register 19: Register 20: SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ............................................ SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 ............................................. SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 ............................................. SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 ............................................. SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ............................................ SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 ............................................... SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 ............................................... SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 ............................................... SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC ............................................... I2C Master Slave Address (I2CMSA), offset 0x000 ........................................................... I2C Master Control/Status (I2CMCS), offset 0x004 ........................................................... I2C Master Data (I2CMDR), offset 0x008 ......................................................................... I2C Master Timer Period (I2CMTPR), offset 0x00C ........................................................... I2C Master Interrupt Mask (I2CMIMR), offset 0x010 ......................................................... I2C Master Raw Interrupt Status (I2CMRIS), offset 0x014 ................................................. I2C Master Masked Interrupt Status (I2CMMIS), offset 0x018 ........................................... I2C Master Interrupt Clear (I2CMICR), offset 0x01C ......................................................... I2C Master Configuration (I2CMCR), offset 0x020 ............................................................ I2C Slave Own Address (I2CSOAR), offset 0x000 ............................................................ I2C Slave Control/Status (I2CSCSR), offset 0x004 ........................................................... I2C Slave Data (I2CSDR), offset 0x008 ........................................................................... I2C Slave Interrupt Mask (I2CSIMR), offset 0x00C ........................................................... I2C Slave Raw Interrupt Status (I2CSRIS), offset 0x010 ................................................... I2C Slave Masked Interrupt Status (I2CSMIS), offset 0x014 .............................................. I2C Slave Interrupt Clear (I2CSICR), offset 0x018 ............................................................ 334 335 336 337 338 339 340 341 342 357 358 362 363 364 365 366 367 368 370 371 373 374 375 376 377 Inter-Integrated Circuit (I2C) Interface ........................................................................................ 343 Controller Area Network (CAN) Module ..................................................................................... 378 CAN Control (CANCTL), offset 0x000 ............................................................................. 392 CAN Status (CANSTS), offset 0x004 ............................................................................... 394 CAN Error Counter (CANERR), offset 0x008 ................................................................... 397 CAN Bit Timing (CANBIT), offset 0x00C .......................................................................... 398 CAN Interrupt (CANINT), offset 0x010 ............................................................................. 400 CAN Test (CANTST), offset 0x014 .................................................................................. 401 CAN Baud Rate Prescalar Extension (CANBRPE), offset 0x018 ....................................... 403 CAN IF1 Command Request (CANIF1CRQ), offset 0x020 ................................................ 404 CAN IF2 Command Request (CANIF2CRQ), offset 0x080 ................................................ 404 CAN IF1 Command Mask (CANIF1CMSK), offset 0x024 .................................................. 405 CAN IF2 Command Mask (CANIF2CMSK), offset 0x084 .................................................. 405 CAN IF1 Mask 1 (CANIF1MSK1), offset 0x028 ................................................................ 408 CAN IF2 Mask 1 (CANIF2MSK1), offset 0x088 ................................................................ 408 CAN IF1 Mask 2 (CANIF1MSK2), offset 0x02C ................................................................ 409 CAN IF2 Mask 2 (CANIF2MSK2), offset 0x08C ................................................................ 409 CAN IF1 Arbitration 1 (CANIF1ARB1), offset 0x030 ......................................................... 410 CAN IF2 Arbitration 1 (CANIF2ARB1), offset 0x090 ......................................................... 410 CAN IF1 Arbitration 2 (CANIF1ARB2), offset 0x034 ......................................................... 411 CAN IF2 Arbitration 2 (CANIF2ARB2), offset 0x094 ......................................................... 411 CAN IF1 Message Control (CANIF1MCTL), offset 0x038 .................................................. 412 16 Preliminary November 30, 2007 LM3S2016 Microcontroller Register 21: Register 22: Register 23: Register 24: Register 25: Register 26: Register 27: Register 28: Register 29: Register 30: Register 31: Register 32: Register 33: Register 34: Register 35: Register 36: Register 37: CAN IF2 Message Control (CANIF2MCTL), offset 0x098 .................................................. 412 CAN IF1 Data A1 (CANIF1DA1), offset 0x03C ................................................................. 414 CAN IF1 Data A2 (CANIF1DA2), offset 0x040 ................................................................. 414 CAN IF1 Data B1 (CANIF1DB1), offset 0x044 ................................................................. 414 CAN IF1 Data B2 (CANIF1DB2), offset 0x048 ................................................................. 414 CAN IF2 Data A1 (CANIF2DA1), offset 0x09C ................................................................. 414 CAN IF2 Data A2 (CANIF2DA2), offset 0x0A0 ................................................................. 414 CAN IF2 Data B1 (CANIF2DB1), offset 0x0A4 ................................................................. 414 CAN IF2 Data B2 (CANIF2DB2), offset 0x0A8 ................................................................. 414 CAN Transmission Request 1 (CANTXRQ1), offset 0x100 ................................................ 415 CAN Transmission Request 2 (CANTXRQ2), offset 0x104 ................................................ 415 CAN New Data 1 (CANNWDA1), offset 0x120 ................................................................. 416 CAN New Data 2 (CANNWDA2), offset 0x124 ................................................................. 416 CAN Message 1 Interrupt Pending (CANMSG1INT), offset 0x140 ..................................... 417 CAN Message 2 Interrupt Pending (CANMSG2INT), offset 0x144 ..................................... 417 CAN Message 1 Valid (CANMSG1VAL), offset 0x160 ....................................................... 418 CAN Message 2 Valid (CANMSG2VAL), offset 0x164 ....................................................... 418 November 30, 2007 Preliminary 17 About This Document About This Document This data sheet provides reference information for the LM3S2016 microcontroller, describing the functional blocks of the system-on-chip (SoC) device designed around the ARM® Cortex™-M3 core. Audience This manual is intended for system software developers, hardware designers, and application developers. About This Manual This document is organized into sections that correspond to each major feature. Related Documents The following documents are referenced by the data sheet, and available on the documentation CD or from the Luminary Micro web site at www.luminarymicro.com: ■ ARM® Cortex™-M3 Technical Reference Manual ■ ARM® CoreSight Technical Reference Manual ■ ARM® v7-M Architecture Application Level Reference Manual The following related documents are also referenced: ■ IEEE Standard 1149.1-Test Access Port and Boundary-Scan Architecture This documentation list was current as of publication date. Please check the Luminary Micro web site for additional documentation, including application notes and white papers. Documentation Conventions This document uses the conventions shown in Table 1 on page 18. Table 1. Documentation Conventions Notation Meaning General Register Notation REGISTER APB registers are indicated in uppercase bold. For example, PBORCTL is the Power-On and Brown-Out Reset Control register. If a register name contains a lowercase n, it represents more than one register. For example, SRCRn represents any (or all) of the three Software Reset Control registers: SRCR0, SRCR1 , and SRCR2. A single bit in a register. Two or more consecutive and related bits. A hexadecimal increment to a register's address, relative to that module's base address as specified in “Memory Map” on page 39. Registers are numbered consecutively throughout the document to aid in referencing them. The register number has no meaning to software. bit bit field offset 0xnnn Register N 18 Preliminary November 30, 2007 LM3S2016 Microcontroller Notation reserved Meaning Register bits marked reserved are reserved for future use. In most cases, reserved bits are set to 0; however, user software should not rely on the value of a reserved bit. To provide software compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. The range of register bits inclusive from xx to yy. For example, 31:15 means bits 15 through 31 in that register. This value in the register bit diagram indicates whether software running on the controller can change the value of the bit field. Software can read this field. The bit or field is cleared by hardware after reading the bit/field. Software can read this field. Always write the chip reset value. Software can read or write this field. Software can read or write this field. A write of a 0 to a W1C bit does not affect the bit value in the register. A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged. This register type is primarily used for clearing interrupt status bits where the read operation provides the interrupt status and the write of the read value clears only the interrupts being reported at the time the register was read. yy:xx Register Bit/Field Types RC RO R/W R/W1C W1C Software can write this field. A write of a 0 to a W1C bit does not affect the bit value in the register. A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged. A read of the register returns no meaningful data. This register is typically used to clear the corresponding bit in an interrupt register. WO Register Bit/Field Reset Value 0 1 Pin/Signal Notation [] pin signal assert a signal Only a write by software is valid; a read of the register returns no meaningful data. This value in the register bit diagram shows the bit/field value after any reset, unless noted. Bit cleared to 0 on chip reset. Bit set to 1 on chip reset. Nondeterministic. Pin alternate function; a pin defaults to the signal without the brackets. Refers to the physical connection on the package. Refers to the electrical signal encoding of a pin. Change the value of the signal from the logically False state to the logically True state. For active High signals, the asserted signal value is 1 (High); for active Low signals, the asserted signal value is 0 (Low). The active polarity (High or Low) is defined by the signal name (see SIGNAL and SIGNAL below). Change the value of the signal from the logically True state to the logically False state. Signal names are in uppercase and in the Courier font. An overbar on a signal name indicates that it is active Low. To assert SIGNAL is to drive it Low; to deassert SIGNAL is to drive it High. Signal names are in uppercase and in the Courier font. An active High signal has no overbar. To assert SIGNAL is to drive it High; to deassert SIGNAL is to drive it Low. deassert a signal SIGNAL SIGNAL Numbers X An uppercase X indicates any of several values is allowed, where X can be any legal pattern. For example, a binary value of 0X00 can be either 0100 or 0000, a hex value of 0xX is 0x0 or 0x1, and so on. Hexadecimal numbers have a prefix of 0x. For example, 0x00FF is the hexadecimal number FF. All other numbers within register tables are assumed to be binary. Within conceptual information, binary numbers are indicated with a b suffix, for example, 1011b, and decimal numbers are written without a prefix or suffix. 0x November 30, 2007 Preliminary 19 Architectural Overview 1 Architectural Overview The Luminary Micro Stellaris family of microcontrollers—the first ARM® Cortex™-M3 based controllers—brings high-performance 32-bit computing to cost-sensitive embedded microcontroller applications. These pioneering parts deliver customers 32-bit performance at a cost equivalent to legacy 8- and 16-bit devices, all in a package with a small footprint. The Stellaris family offers efficient performance and extensive integration, favorably positioning the device into cost-conscious applications requiring significant control-processing and connectivity ® ® capabilities. The Stellaris LM3S1000 series extends the Stellaris family with larger on-chip ® memories, enhanced power management, and expanded I/O and control capabilities. The Stellaris LM3S2000 series, designed for Controller Area Network (CAN) applications, extends the Stellaris family with Bosch CAN networking technology, the golden standard in short-haul industrial networks. ® The Stellaris LM3S2000 series also marks the first integration of CAN capabilities with the ® revolutionary Cortex-M3 core. The Stellaris LM3S6000 series combines both a 10/100 Ethernet Media Access Control (MAC) and Physical (PHY) layer, marking the first time that integrated connectivity is available with an ARM Cortex-M3 MCU and the only integrated 10/100 Ethernet MAC ® and PHY available in an ARM architecture MCU. The Stellaris LM3S8000 series combines Bosch Controller Area Network technology with both a 10/100 Ethernet Media Access Control (MAC) and Physical (PHY) layer. The LM3S2016 microcontroller is targeted for industrial applications, including remote monitoring, electronic point-of-sale machines, test and measurement equipment, network appliances and switches, factory automation, HVAC and building control, gaming equipment, motion control, medical instrumentation, and fire and security. In addition, the LM3S2016 microcontroller offers the advantages of ARM's widely available development tools, System-on-Chip (SoC) infrastructure IP applications, and a large user community. Additionally, the microcontroller uses ARM's Thumb®-compatible Thumb-2 instruction set to reduce memory requirements and, thereby, cost. Finally, the LM3S2016 microcontroller is code-compatible ® to all members of the extensive Stellaris family; providing flexibility to fit our customers' precise needs. Luminary Micro offers a complete solution to get to market quickly, with evaluation and development boards, white papers and application notes, an easy-to-use peripheral driver library, and a strong support, sales, and distributor network. ® ® 1.1 Product Features The LM3S2016 microcontroller includes the following product features: ■ 32-Bit RISC Performance – 32-bit ARM® Cortex™-M3 v7M architecture optimized for small-footprint embedded applications – System timer (SysTick), providing a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism – Thumb®-compatible Thumb-2-only instruction set processor core for high code density – 50-MHz operation – Hardware-division and single-cycle-multiplication 20 Preliminary November 30, 2007 LM3S2016 Microcontroller – Integrated Nested Vectored Interrupt Controller (NVIC) providing deterministic interrupt handling – 24 interrupts with eight priority levels – Memory protection unit (MPU), providing a privileged mode for protected operating system functionality – Unaligned data access, enabling data to be efficiently packed into memory – Atomic bit manipulation (bit-banding), delivering maximum memory utilization and streamlined peripheral control ■ Internal Memory – 64 KB single-cycle flash • • • User-managed flash block protection on a 2-KB block basis User-managed flash data programming User-defined and managed flash-protection block – 8 KB single-cycle SRAM ■ General-Purpose Timers – Two General-Purpose Timer Modules (GPTM), each of which provides two 16-bit timers. Each GPTM can be configured to operate independently: • • • • As a single 32-bit timer As one 32-bit Real-Time Clock (RTC) to event capture For Pulse Width Modulation (PWM) To trigger analog-to-digital conversions – 32-bit Timer modes • • • • • Programmable one-shot timer Programmable periodic timer Real-Time Clock when using an external 32.768-KHz clock as the input User-enabled stalling in periodic and one-shot mode when the controller asserts the CPU Halt flag during debug ADC event trigger – 16-bit Timer modes • • General-purpose timer function with an 8-bit prescaler Programmable one-shot timer November 30, 2007 Preliminary 21 Architectural Overview • • • Programmable periodic timer User-enabled stalling when the controller asserts CPU Halt flag during debug ADC event trigger – 16-bit Input Capture modes • • Input edge count capture Input edge time capture – 16-bit PWM mode • Simple PWM mode with software-programmable output inversion of the PWM signal ■ ARM FiRM-compliant Watchdog Timer – 32-bit down counter with a programmable load register – Separate watchdog clock with an enable – Programmable interrupt generation logic with interrupt masking – Lock register protection from runaway software – Reset generation logic with an enable/disable – User-enabled stalling when the controller asserts the CPU Halt flag during debug ■ Controller Area Network (CAN) – Supports CAN protocol version 2.0 part A/B – Bit rates up to 1Mb/s – 32 message objects, each with its own identifier mask – Maskable interrupt – Disable automatic retransmission mode for TTCAN – Programmable loop-back mode for self-test operation ■ Synchronous Serial Interface (SSI) – Master or slave operation – Programmable clock bit rate and prescale – Separate transmit and receive FIFOs, 16 bits wide, 8 locations deep – Programmable interface operation for Freescale SPI, MICROWIRE, or Texas Instruments synchronous serial interfaces – Programmable data frame size from 4 to 16 bits 22 Preliminary November 30, 2007 LM3S2016 Microcontroller – Internal loopback test mode for diagnostic/debug testing ■ UART – Two fully programmable 16C550-type UARTs with IrDA support – Separate 16x8 transmit (TX) and 16x12 receive (RX) FIFOs to reduce CPU interrupt service loading – Programmable baud-rate generator with fractional divider – Programmable FIFO length, including 1-byte deep operation providing conventional double-buffered interface – FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8 – Standard asynchronous communication bits for start, stop, and parity – False-start-bit detection – Line-break generation and detection ■ ADC – Single- and differential-input configurations – Four 10-bit channels (inputs) when used as single-ended inputs – Sample rate of 500 thousand samples/second – Flexible, configurable analog-to-digital conversion – Four programmable sample conversion sequences from one to eight entries long, with corresponding conversion result FIFOs – Each sequence triggered by software or internal event (timers, or GPIO) ■ I2C – Master and slave receive and transmit operation with transmission speed up to 100 Kbps in Standard mode and 400 Kbps in Fast mode – Interrupt generation – Master with arbitration and clock synchronization, multimaster support, and 7-bit addressing mode ■ GPIOs – 18-39 GPIOs, depending on configuration – 5-V-tolerant input/outputs – Programmable interrupt generation as either edge-triggered or level-sensitive – Bit masking in both read and write operations through address lines November 30, 2007 Preliminary 23 Architectural Overview – Can initiate an ADC sample sequence – Programmable control for GPIO pad configuration: • • • • • ■ Power – On-chip Low Drop-Out (LDO) voltage regulator, with programmable output user-adjustable from 2.25 V to 2.75 V – Low-power options on controller: Sleep and Deep-sleep modes – Low-power options for peripherals: software controls shutdown of individual peripherals – User-enabled LDO unregulated voltage detection and automatic reset – 3.3-V supply brown-out detection and reporting via interrupt or reset ■ Flexible Reset Sources – Power-on reset (POR) – Reset pin assertion – Brown-out (BOR) detector alerts to system power drops – Software reset – Watchdog timer reset – Internal low drop-out (LDO) regulator output goes unregulated ■ Additional Features – Six reset sources – Programmable clock source control – Clock gating to individual peripherals for power savings – IEEE 1149.1-1990 compliant Test Access Port (TAP) controller – Debug access via JTAG and Serial Wire interfaces – Full JTAG boundary scan ■ Industrial-range 100-pin RoHS-compliant LQFP package Weak pull-up or pull-down resistors 2-mA, 4-mA, and 8-mA pad drive Slew rate control for the 8-mA drive Open drain enables Digital input enables 24 Preliminary November 30, 2007 LM3S2016 Microcontroller 1.2 Target Applications ■ Remote monitoring ■ Electronic point-of-sale (POS) machines ■ Test and measurement equipment ■ Network appliances and switches ■ Factory automation ■ HVAC and building control ■ Gaming equipment ■ Motion control ■ Medical instrumentation ■ Fire and security ■ Power and energy ■ Transportation 1.3 High-Level Block Diagram Figure 1-1 on page 26 represents the full set of features in the Stellaris 2000 series of devices; not all features may be available on the LM3S2016 microcontroller. ® November 30, 2007 Preliminary 25 Architectural Overview Figure 1-1. Stellaris 2000 Series High-Level Block Diagram ® 1.4 Functional Overview The following sections provide an overview of the features of the LM3S2016 microcontroller. The page number in parenthesis indicates where that feature is discussed in detail. Ordering and support information can be found in “Ordering and Contact Information” on page 467. 26 Preliminary November 30, 2007 LM3S2016 Microcontroller 1.4.1 1.4.1.1 ARM Cortex™-M3 Processor Core (see page 33) All members of the Stellaris product family, including the LM3S2016 microcontroller, are designed around an ARM Cortex™-M3 processor core. The ARM Cortex-M3 processor provides the core for a high-performance, low-cost platform that meets the needs of minimal memory implementation, reduced pin count, and low-power consumption, while delivering outstanding computational performance and exceptional system response to interrupts. “ARM Cortex-M3 Processor Core” on page 33 provides an overview of the ARM core; the core is detailed in the ARM® Cortex™-M3 Technical Reference Manual. ® 1.4.1.2 System Timer (SysTick) Cortex-M3 includes an integrated system timer, SysTick. SysTick provides a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter can be used in several different ways, for example: ■ An RTOS tick timer which fires at a programmable rate (for example, 100 Hz) and invokes a SysTick routine. ■ A high-speed alarm timer using the system clock. ■ A variable rate alarm or signal timer—the duration is range-dependent on the reference clock used and the dynamic range of the counter. ■ A simple counter. Software can use this to measure time to completion and time used. ■ An internal clock source control based on missing/meeting durations. The COUNTFLAG bit-field in the control and status register can be used to determine if an action completed within a set duration, as part of a dynamic clock management control loop. 1.4.1.3 Nested Vectored Interrupt Controller (NVIC) The LM3S2016 controller includes the ARM Nested Vectored Interrupt Controller (NVIC) on the ARM Cortex-M3 core. The NVIC and Cortex-M3 prioritize and handle all exceptions. All exceptions are handled in Handler Mode. The processor state is automatically stored to the stack on an exception, and automatically restored from the stack at the end of the Interrupt Service Routine (ISR). The vector is fetched in parallel to the state saving, which enables efficient interrupt entry. The processor supports tail-chaining, which enables back-to-back interrupts to be performed without the overhead of state saving and restoration. Software can set eight priority levels on 7 exceptions (system handlers) and 24 interrupts. “Interrupts” on page 41 provides an overview of the NVIC controller and the interrupt map. Exceptions and interrupts are detailed in the ARM® Cortex™-M3 Technical Reference Manual. 1.4.2 1.4.2.1 Motor Control Peripherals To enhance motor control, the LM3S2016 controller features Pulse Width Modulation (PWM) outputs. PWM Pulse width modulation (PWM) is a powerful technique for digitally encoding analog signal levels. High-resolution counters are used to generate a square wave, and the duty cycle of the square wave is modulated to encode an analog signal. Typical applications include switching power supplies and motor control. November 30, 2007 Preliminary 27 Architectural Overview On the LM3S2016, PWM motion control functionality can be achieved through: ■ The motion control features of the general-purpose timers using the CCP pins CCP Pins (see page 180) The General-Purpose Timer Module's CCP (Capture Compare PWM) pins are software programmable to support a simple PWM mode with a software-programmable output inversion of the PWM signal. 1.4.3 Analog Peripherals To handle analog signals, the LM3S2016 microcontroller offers an Analog-to-Digital Converter (ADC). 1.4.3.1 ADC (see page 233) An analog-to-digital converter (ADC) is a peripheral that converts a continuous analog voltage to a discrete digital number. The LM3S2016 ADC module features 10-bit conversion resolution and supports four input channels. Four buffered sample sequences allow rapid sampling of up to eight analog input sources without controller intervention. Each sample sequence provides flexible programming with fully configurable input source, trigger events, interrupt generation, and sequence priority. 1.4.4 Serial Communications Peripherals The LM3S2016 controller supports both asynchronous and synchronous serial communications with: ■ Two fully programmable 16C550-type UARTs ■ One SSI module ■ One I2C module ■ One CAN unit 1.4.4.1 UART (see page 265) A Universal Asynchronous Receiver/Transmitter (UART) is an integrated circuit used for RS-232C serial communications, containing a transmitter (parallel-to-serial converter) and a receiver (serial-to-parallel converter), each clocked separately. The LM3S2016 controller includes two fully programmable 16C550-type UARTs that support data transfer speeds up to 460.8 Kbps. (Although similar in functionality to a 16C550 UART, it is not register-compatible.) In addition, each UART is capable of supporting IrDA. Separate 16x8 transmit (TX) and 16x12 receive (RX) FIFOs reduce CPU interrupt service loading. The UART can generate individually masked interrupts from the RX, TX, modem status, and error conditions. The module provides a single combined interrupt when any of the interrupts are asserted and are unmasked. 1.4.4.2 SSI (see page 306) Synchronous Serial Interface (SSI) is a four-wire bi-directional communications interface. The LM3S2016 controller includes one SSI module that provides the functionality for synchronous serial communications with peripheral devices, and can be configured to use the Freescale SPI, 28 Preliminary November 30, 2007 LM3S2016 Microcontroller MICROWIRE, or TI synchronous serial interface frame formats. The size of the data frame is also configurable, and can be set between 4 and 16 bits, inclusive. The SSI module performs serial-to-parallel conversion on data received from a peripheral device, and parallel-to-serial conversion on data transmitted to a peripheral device. The TX and RX paths are buffered with internal FIFOs, allowing up to eight 16-bit values to be stored independently. The SSI module can be configured as either a master or slave device. As a slave device, the SSI module can also be configured to disable its output, which allows a master device to be coupled with multiple slave devices. The SSI module also includes a programmable bit rate clock divider and prescaler to generate the output serial clock derived from the SSI module's input clock. Bit rates are generated based on the input clock and the maximum bit rate is determined by the connected peripheral. 1.4.4.3 I2C (see page 343) The Inter-Integrated Circuit (I2C) bus provides bi-directional data transfer through a two-wire design (a serial data line SDA and a serial clock line SCL). The I2C bus interfaces to external I2C devices such as serial memory (RAMs and ROMs), networking devices, LCDs, tone generators, and so on. The I2C bus may also be used for system testing and diagnostic purposes in product development and manufacture. The LM3S2016 controller includes one I2C module that provides the ability to communicate to other IC devices over an I2C bus. The I2C bus supports devices that can both transmit and receive (write and read) data. Devices on the I2C bus can be designated as either a master or a slave. The I2C module supports both sending and receiving data as either a master or a slave, and also supports the simultaneous operation as both a master and a slave. The four I2C modes are: Master Transmit, Master Receive, Slave Transmit, and Slave Receive. A Stellaris I2C module can operate at two speeds: Standard (100 Kbps) and Fast (400 Kbps). Both the I2C master and slave can generate interrupts. The I2C master generates interrupts when a transmit or receive operation completes (or aborts due to an error). The I2C slave generates interrupts when data has been sent or requested by a master. ® 1.4.4.4 Controller Area Network (see page 378) Controller Area Network (CAN) is a multicast shared serial-bus standard for connecting electronic control units (ECUs). CAN was specifically designed to be robust in electromagnetically noisy environments and can utilize a differential balanced line like RS-485 or a more robust twisted-pair wire. Originally created for automotive purposes, now it is used in many embedded control applications (for example, industrial or medical). Bit rates up to 1Mb/s are possible at network lengths below 40 meters. Decreased bit rates allow longer network distances (for example, 125 Kb/s at 500m). A transmitter sends a message to all CAN nodes (broadcasting). Each node decides on the basis of the identifier received whether it should process the message. The identifier also determines the priority that the message enjoys in competition for bus access. Each CAN message can transmit from 0 to 8 bytes of user information. The LM3S2016 includes one CAN units. November 30, 2007 Preliminary 29 Architectural Overview 1.4.5 1.4.5.1 System Peripherals Programmable GPIOs (see page 133) General-purpose input/output (GPIO) pins offer flexibility for a variety of connections. The Stellaris GPIO module is composed of eight physical GPIO blocks, each corresponding to an individual GPIO port. The GPIO module is FiRM-compliant (compliant to the ARM Foundation IP for Real-Time Microcontrollers specification) and supports 18-39 programmable input/output pins. The number of GPIOs available depends on the peripherals being used (see “Signal Tables” on page 420 for the signals available to each GPIO pin). The GPIO module features programmable interrupt generation as either edge-triggered or level-sensitive on all pins, programmable control for GPIO pad configuration, and bit masking in both read and write operations through address lines. ® 1.4.5.2 Two Programmable Timers (see page 174) Programmable timers can be used to count or time external events that drive the Timer input pins. The Stellaris General-Purpose Timer Module (GPTM) contains two GPTM blocks. Each GPTM block provides two 16-bit timers/counters that can be configured to operate independently as timers or event counters, or configured to operate as one 32-bit timer or one 32-bit Real-Time Clock (RTC). Timers can also be used to trigger analog-to-digital (ADC) conversions. When configured in 32-bit mode, a timer can run as a Real-Time Clock (RTC), one-shot timer or periodic timer. When in 16-bit mode, a timer can run as a one-shot timer or periodic timer, and can extend its precision by using an 8-bit prescaler. A 16-bit timer can also be configured for event capture or Pulse Width Modulation (PWM) generation. ® 1.4.5.3 Watchdog Timer (see page 210) A watchdog timer can generate nonmaskable interrupts (NMIs) or a reset when a time-out value is reached. The watchdog timer is used to regain control when a system has failed due to a software error or to the failure of an external device to respond in the expected way. The Stellaris Watchdog Timer module consists of a 32-bit down counter, a programmable load register, interrupt generation logic, and a locking register. The Watchdog Timer can be configured to generate an interrupt to the controller on its first time-out, and to generate a reset signal on its second time-out. Once the Watchdog Timer has been configured, the lock register can be written to prevent the timer configuration from being inadvertently altered. ® 1.4.6 1.4.6.1 Memory Peripherals The LM3S2016 controller offers both single-cycle SRAM and single-cycle Flash memory. SRAM (see page 109) The LM3S2016 static random access memory (SRAM) controller supports 8 KB SRAM. The internal ® SRAM of the Stellaris devices is located at offset 0x0000.0000 of the device memory map. To reduce the number of time-consuming read-modify-write (RMW) operations, ARM has introduced bit-banding technology in the new Cortex-M3 processor. With a bit-band-enabled processor, certain regions in the memory map (SRAM and peripheral space) can use address aliases to access individual bits in a single, atomic operation. 30 Preliminary November 30, 2007 LM3S2016 Microcontroller 1.4.6.2 Flash (see page 110) The LM3S2016 Flash controller supports 64 KB of flash memory. The flash is organized as a set of 1-KB blocks that can be individually erased. Erasing a block causes the entire contents of the block to be reset to all 1s. These blocks are paired into a set of 2-KB blocks that can be individually protected. The blocks can be marked as read-only or execute-only, providing different levels of code protection. Read-only blocks cannot be erased or programmed, protecting the contents of those blocks from being modified. Execute-only blocks cannot be erased or programmed, and can only be read by the controller instruction fetch mechanism, protecting the contents of those blocks from being read by either the controller or by a debugger. 1.4.7 1.4.7.1 Additional Features Memory Map (see page 39) A memory map lists the location of instructions and data in memory. The memory map for the LM3S2016 controller can be found in “Memory Map” on page 39. Register addresses are given as a hexadecimal increment, relative to the module's base address as shown in the memory map. The ARM® Cortex™-M3 Technical Reference Manual provides further information on the memory map. 1.4.7.2 JTAG TAP Controller (see page 43) The Joint Test Action Group (JTAG) port provides a standardized serial interface for controlling the Test Access Port (TAP) and associated test logic. The TAP, JTAG instruction register, and JTAG data registers can be used to test the interconnects of assembled printed circuit boards, obtain manufacturing information on the components, and observe and/or control the inputs and outputs of the controller during normal operation. The JTAG port provides a high degree of testability and chip-level access at a low cost. The JTAG port is comprised of the standard five pins: TRST, TCK, TMS, TDI, and TDO. Data is transmitted serially into the controller on TDI and out of the controller on TDO. The interpretation of this data is dependent on the current state of the TAP controller. For detailed information on the operation of the JTAG port and TAP controller, please refer to the IEEE Standard 1149.1-Test Access Port and Boundary-Scan Architecture. The Luminary Micro JTAG controller works with the ARM JTAG controller built into the Cortex-M3 core. This is implemented by multiplexing the TDO outputs from both JTAG controllers. ARM JTAG instructions select the ARM TDO output while Luminary Micro JTAG instructions select the Luminary Micro TDO outputs. The multiplexer is controlled by the Luminary Micro JTAG controller, which has comprehensive programming for the ARM, Luminary Micro, and unimplemented JTAG instructions. 1.4.7.3 System Control and Clocks (see page 54) System control determines the overall operation of the device. It provides information about the device, controls the clocking of the device and individual peripherals, and handles reset detection and reporting. 1.4.8 Hardware Details Details on the pins and package can be found in the following sections: ■ “Pin Diagram” on page 419 ■ “Signal Tables” on page 420 November 30, 2007 Preliminary 31 Architectural Overview ■ “Operating Characteristics” on page 432 ■ “Electrical Characteristics” on page 433 ■ “Package Information” on page 444 32 Preliminary November 30, 2007 LM3S2016 Microcontroller 2 ARM Cortex-M3 Processor Core The ARM Cortex-M3 processor provides the core for a high-performance, low-cost platform that meets the needs of minimal memory implementation, reduced pin count, and low power consumption, while delivering outstanding computational performance and exceptional system response to interrupts. Features include: ■ Compact core. ■ Thumb-2 instruction set, delivering the high-performance expected of an ARM core in the memory size usually associated with 8- and 16-bit devices; typically in the range of a few kilobytes of memory for microcontroller class applications. ■ Rapid application execution through Harvard architecture characterized by separate buses for instruction and data. ■ Exceptional interrupt handling, by implementing the register manipulations required for handling an interrupt in hardware. ■ Memory protection unit (MPU) to provide a privileged mode of operation for complex applications. ■ Migration from the ARM7™ processor family for better performance and power efficiency. ■ Full-featured debug solution with a: – Serial Wire JTAG Debug Port (SWJ-DP) – Flash Patch and Breakpoint (FPB) unit for implementing breakpoints – Data Watchpoint and Trigger (DWT) unit for implementing watchpoints, trigger resources, and system profiling – Instrumentation Trace Macrocell (ITM) for support of printf style debugging – Trace Port Interface Unit (TPIU) for bridging to a Trace Port Analyzer The Stellaris family of microcontrollers builds on this core to bring high-performance 32-bit computing to cost-sensitive embedded microcontroller applications, such as factory automation and control, industrial control power devices, building and home automation, and stepper motors. For more information on the ARM Cortex-M3 processor core, see the ARM® Cortex™-M3 Technical Reference Manual. For information on SWJ-DP, see the ARM® CoreSight Technical Reference Manual. ® November 30, 2007 Preliminary 33 ARM Cortex-M3 Processor Core 2.1 Block Diagram Figure 2-1. CPU Block Diagram Nested Vectored Interrupt Controller Interrupts Sleep Debug Instructions Memory Protection Unit Data Trace Port Interface Unit CM3 Core ARM Cortex-M3 Serial Wire Output Trace Port (SWO) Flash Patch and Breakpoint Instrumentation Data Watchpoint Trace Macrocell and Trace Private Peripheral Bus (external) ROM Table Private Peripheral Bus (internal) Bus Matrix Adv. Peripheral Bus I-code bus D-code bus System bus Serial Wire JTAG Debug Port Adv. HighPerf. Bus Access Port 2.2 Functional Description Important: The ARM® Cortex™-M3 Technical Reference Manual describes all the features of an ARM Cortex-M3 in detail. However, these features differ based on the implementation. ® This section describes the Stellaris implementation. Luminary Micro has implemented the ARM Cortex-M3 core as shown in Figure 2-1 on page 34. As noted in the ARM® Cortex™-M3 Technical Reference Manual, several Cortex-M3 components are flexible in their implementation: SW/JTAG-DP, ETM, TPIU, the ROM table, the MPU, and the Nested Vectored Interrupt Controller (NVIC). Each of these is addressed in the sections that follow. 2.2.1 Serial Wire and JTAG Debug Luminary Micro has replaced the ARM SW-DP and JTAG-DP with the ARM CoreSight™-compliant Serial Wire JTAG Debug Port (SWJ-DP) interface. This means Chapter 12, “Debug Port,” of the ® ARM® Cortex™-M3 Technical Reference Manual does not apply to Stellaris devices. The SWJ-DP interface combines the SWD and JTAG debug ports into one module. See the CoreSight™ Design Kit Technical Reference Manual for details on SWJ-DP. 34 Preliminary November 30, 2007 LM3S2016 Microcontroller 2.2.2 Embedded Trace Macrocell (ETM) ETM was not implemented in the Stellaris devices. This means Chapters 15 and 16 of the ARM® Cortex™-M3 Technical Reference Manual can be ignored. ® 2.2.3 Trace Port Interface Unit (TPIU) The TPIU acts as a bridge between the Cortex-M3 trace data from the ITM, and an off-chip Trace ® Port Analyzer. The Stellaris devices have implemented TPIU as shown in Figure 2-2 on page 35. This is similar to the non-ETM version described in the ARM® Cortex™-M3 Technical Reference Manual, however, SWJ-DP only provides SWV output for the TPIU. Figure 2-2. TPIU Block Diagram Debug ATB Slave Port ATB Interface Asynchronous FIFO Trace Out (serializer) Serial Wire Trace Port (SWO) APB Slave Port APB Interface 2.2.4 ROM Table The default ROM table was implemented as described in the ARM® Cortex™-M3 Technical Reference Manual. 2.2.5 Memory Protection Unit (MPU) The Memory Protection Unit (MPU) is included on the LM3S2016 controller and supports the standard ARMv7 Protected Memory System Architecture (PMSA) model. The MPU provides full support for protection regions, overlapping protection regions, access permissions, and exporting memory attributes to the system. 2.2.6 Nested Vectored Interrupt Controller (NVIC) The Nested Vectored Interrupt Controller (NVIC): ■ Facilitates low-latency exception and interrupt handling ■ Controls power management ■ Implements system control registers November 30, 2007 Preliminary 35 ARM Cortex-M3 Processor Core The NVIC supports up to 240 dynamically reprioritizable interrupts each with up to 256 levels of priority. The NVIC and the processor core interface are closely coupled, which enables low latency interrupt processing and efficient processing of late arriving interrupts. The NVIC maintains knowledge of the stacked (nested) interrupts to enable tail-chaining of interrupts. You can only fully access the NVIC from privileged mode, but you can pend interrupts in user-mode if you enable the Configuration Control Register (see the ARM® Cortex™-M3 Technical Reference Manual). Any other user-mode access causes a bus fault. All NVIC registers are accessible using byte, halfword, and word unless otherwise stated. All NVIC registers and system debug registers are little endian regardless of the endianness state of the processor. 2.2.6.1 Interrupts The ARM® Cortex™-M3 Technical Reference Manual describes the maximum number of interrupts and interrupt priorities. The LM3S2016 microcontroller supports 24 interrupts with eight priority levels. 2.2.6.2 System Timer (SysTick) Cortex-M3 includes an integrated system timer, SysTick. SysTick provides a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter can be used in several different ways, for example: ■ An RTOS tick timer which fires at a programmable rate (for example, 100 Hz) and invokes a SysTick routine. ■ A high-speed alarm timer using the system clock. ■ A variable rate alarm or signal timer—the duration is range-dependent on the reference clock used and the dynamic range of the counter. ■ A simple counter. Software can use this to measure time to completion and time used. ■ An internal clock source control based on missing/meeting durations. The COUNTFLAG bit-field in the control and status register can be used to determine if an action completed within a set duration, as part of a dynamic clock management control loop. Functional Description The timer consists of three registers: ■ A control and status counter to configure its clock, enable the counter, enable the SysTick interrupt, and determine counter status. ■ The reload value for the counter, used to provide the counter's wrap value. ■ The current value of the counter. A fourth register, the SysTick Calibration Value Register, is not implemented in the Stellaris devices. When enabled, the timer counts down from the reload value to zero, reloads (wraps) to the value in the SysTick Reload Value register on the next clock edge, then decrements on subsequent clocks. Writing a value of zero to the Reload Value register disables the counter on the next wrap. When the counter reaches zero, the COUNTFLAG status bit is set. The COUNTFLAG bit clears on reads. ® 36 Preliminary November 30, 2007 LM3S2016 Microcontroller Writing to the Current Value register clears the register and the COUNTFLAG status bit. The write does not trigger the SysTick exception logic. On a read, the current value is the value of the register at the time the register is accessed. If the core is in debug state (halted), the counter will not decrement. The timer is clocked with respect to a reference clock. The reference clock can be the core clock or an external clock source. SysTick Control and Status Register Use the SysTick Control and Status Register to enable the SysTick features. The reset is 0x0000.0000. Bit/Field 31:17 Name reserved Type Reset Description RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Returns 1 if timer counted to 0 since last time this was read. Clears on read by application. If read by the debugger using the DAP, this bit is cleared on read-only if the MasterType bit in the AHB-AP Control Register is set to 0. Otherwise, the COUNTFLAG bit is not changed by the debugger read. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 = external reference clock. (Not implemented for Stellaris microcontrollers.) 1 = core clock. If no reference clock is provided, it is held at 1 and so gives the same time as the core clock. The core clock must be at least 2.5 times faster than the reference clock. If it is not, the count values are unpredictable. 1 TICKINT R/W 0 1 = counting down to 0 pends the SysTick handler. 0 = counting down to 0 does not pend the SysTick handler. Software can use the COUNTFLAG to determine if ever counted to 0. 0 ENABLE R/W 0 1 = counter operates in a multi-shot way. That is, counter loads with the Reload value and then begins counting down. On reaching 0, it sets the COUNTFLAG to 1 and optionally pends the SysTick handler, based on TICKINT. It then loads the Reload value again, and begins counting. 0 = counter disabled. 16 COUNTFLAG R/W 0 15:3 reserved RO 0 2 CLKSOURCE R/W 0 SysTick Reload Value Register Use the SysTick Reload Value Register to specify the start value to load into the current value register when the counter reaches 0. It can be any value between 1 and 0x00FF.FFFF. A start value of 0 is possible, but has no effect because the SysTick interrupt and COUNTFLAG are activated when counting from 1 to 0. Therefore, as a multi-shot timer, repeated over and over, it fires every N+1 clock pulse, where N is any value from 1 to 0x00FF.FFFF. So, if the tick interrupt is required every 100 clock pulses, 99 must be written into the RELOAD. If a new value is written on each tick interrupt, so treated as single shot, then the actual count down must be written. For example, if a tick is next required after 400 clock pulses, 400 must be written into the RELOAD. Bit/Field 31:24 Name reserved Type Reset Description RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. November 30, 2007 Preliminary 37 ARM Cortex-M3 Processor Core Bit/Field 23:0 Name Type Reset Description Value to load into the SysTick Current Value Register when the counter reaches 0. RELOAD W1C SysTick Current Value Register Use the SysTick Current Value Register to find the current value in the register. Bit/Field 31:24 Name reserved Type Reset Description RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Current value at the time the register is accessed. No read-modify-write protection is provided, so change with care. This register is write-clear. Writing to it with any value clears the register to 0. Clearing this register also clears the COUNTFLAG bit of the SysTick Control and Status Register. 23:0 CURRENT W1C - SysTick Calibration Value Register The SysTick Calibration Value register is not implemented. 38 Preliminary November 30, 2007 LM3S2016 Microcontroller 3 Memory Map The memory map for the LM3S2016 controller is provided in Table 3-1 on page 39. In this manual, register addresses are given as a hexadecimal increment, relative to the module’s base address as shown in the memory map. See also Chapter 4, “Memory Map” in the ARM® Cortex™-M3 Technical Reference Manual. Important: In Table 3-1 on page 39, addresses not listed are reserved. Table 3-1. Memory Map Start a End Description For details on registers, see page ... b c Memory 0x0000.0000 0x2000.0000 0x2010.0000 0x2200.0000 0x2400.0000 FiRM Peripherals 0x4000.0000 0x4000.4000 0x4000.5000 0x4000.6000 0x4000.7000 0x4000.8000 0x4000.C000 0x4000.D000 Peripherals 0x4002.0000 0x4002.0800 0x4002.4000 0x4002.5000 0x4002.6000 0x4002.7000 0x4003.0000 0x4003.1000 0x4003.8000 0x4004.0000 0x400F.D000 0x400F.E000 0x4200.0000 Private Peripheral Bus 0x4002.07FF 0x4002.0FFF 0x4002.4FFF 0x4002.5FFF 0x4002.6FFF 0x4002.7FFF 0x4003.0FFF 0x4003.1FFF 0x4003.8FFF 0x4004.0FFF 0x400F.DFFF 0x400F.EFFF 0x43FF.FFFF I2C Master 0 I2C Slave 0 GPIO Port E GPIO Port F GPIO Port G GPIO Port H Timer0 Timer1 ADC CAN0 Controller Flash control System control Bit-banded alias of 0x4000.0000 through 0x400F.FFFF 356 369 139 139 139 139 185 185 238 391 113 61 0x4000.0FFF 0x4000.4FFF 0x4000.5FFF 0x4000.6FFF 0x4000.7FFF 0x4000.8FFF 0x4000.CFFF 0x4000.DFFF Watchdog timer GPIO Port A GPIO Port B GPIO Port C GPIO Port D SSI0 UART0 UART1 212 139 139 139 139 317 272 272 0x0000.FFFF 0x2000.1FFF 0x21FF.FFFF 0x23FF.FFFF 0x3FFF.FFFF On-chip flash 113 113 109 - Bit-banded on-chip SRAM Reserved non-bit-banded SRAM space Bit-band alias of 0x2000.0000 through 0x200F.FFFF Reserved non-bit-banded SRAM space November 30, 2007 Preliminary 39 Memory Map Start End Description For details on registers, see page ... ARM® Cortex™-M3 Technical Reference Manual 0xE000.0000 0xE000.1000 0xE000.2000 0xE000.3000 0xE000.E000 0xE000.F000 0xE004.0000 0xE004.1000 0xE004.2000 0xE010.0000 0xE000.0FFF 0xE000.1FFF 0xE000.2FFF 0xE000.DFFF 0xE000.EFFF 0xE003.FFFF 0xE004.0FFF 0xE004.1FFF 0xE00F.FFFF 0xFFFF.FFFF Instrumentation Trace Macrocell (ITM) Data Watchpoint and Trace (DWT) Flash Patch and Breakpoint (FPB) Reserved Nested Vectored Interrupt Controller (NVIC) Reserved Trace Port Interface Unit (TPIU) Reserved Reserved Reserved for vendor peripherals - a. All reserved space returns a bus fault when read or written. b. The unavailable flash will bus fault throughout this range. c. The unavailable SRAM will bus fault throughout this range. 40 Preliminary November 30, 2007 LM3S2016 Microcontroller 4 Interrupts The ARM Cortex-M3 processor and the Nested Vectored Interrupt Controller (NVIC) prioritize and handle all exceptions. All exceptions are handled in Handler Mode. The processor state is automatically stored to the stack on an exception, and automatically restored from the stack at the end of the Interrupt Service Routine (ISR). The vector is fetched in parallel to the state saving, which enables efficient interrupt entry. The processor supports tail-chaining, which enables back-to-back interrupts to be performed without the overhead of state saving and restoration. Table 4-1 on page 41 lists all the exceptions. Software can set eight priority levels on seven of these exceptions (system handlers) as well as on 24 interrupts (listed in Table 4-2 on page 42). Priorities on the system handlers are set with the NVIC System Handler Priority registers. Interrupts are enabled through the NVIC Interrupt Set Enable register and prioritized with the NVIC Interrupt Priority registers. You can also group priorities by splitting priority levels into pre-emption priorities and subpriorities. All the interrupt registers are described in Chapter 8, “Nested Vectored Interrupt Controller” in the ARM® Cortex™-M3 Technical Reference Manual. Internally, the highest user-settable priority (0) is treated as fourth priority, after a Reset, NMI, and a Hard Fault. Note that 0 is the default priority for all the settable priorities. If you assign the same priority level to two or more interrupts, their hardware priority (the lower the position number) determines the order in which the processor activates them. For example, if both GPIO Port A and GPIO Port B are priority level 1, then GPIO Port A has higher priority. See Chapter 5, “Exceptions” and Chapter 8, “Nested Vectored Interrupt Controller” in the ARM® Cortex™-M3 Technical Reference Manual for more information on exceptions and interrupts. Note: In Table 4-2 on page 42 interrupts not listed are reserved. Table 4-1. Exception Types Exception Type Reset Position 0 1 Priority a Description Stack top is loaded from first entry of vector table on reset. -3 (highest) Invoked on power up and warm reset. On first instruction, drops to lowest priority (and then is called the base level of activation). This is asynchronous. -2 Cannot be stopped or preempted by any exception but reset. This is asynchronous. An NMI is only producible by software, using the NVIC Interrupt Control State register. Non-Maskable Interrupt (NMI) 2 Hard Fault Memory Management 3 4 -1 settable All classes of Fault, when the fault cannot activate due to priority or the configurable fault handler has been disabled. This is synchronous. MPU mismatch, including access violation and no match. This is synchronous. The priority of this exception can be changed. Bus Fault 5 settable Pre-fetch fault, memory access fault, and other address/memory related faults. This is synchronous when precise and asynchronous when imprecise. You can enable or disable this fault. Usage Fault SVCall 6 7-10 11 settable settable Usage fault, such as undefined instruction executed or illegal state transition attempt. This is synchronous. Reserved. System service call with SVC instruction. This is synchronous. November 30, 2007 Preliminary 41 Interrupts Exception Type Debug Monitor Position 12 Priority a Description Debug monitor (when not halting). This is synchronous, but only active when enabled. It does not activate if lower priority than the current activation. Reserved. Pendable request for system service. This is asynchronous and only pended by software. System tick timer has fired. This is asynchronous. Asserted from outside the ARM Cortex-M3 core and fed through the NVIC (prioritized). These are all asynchronous. Table 4-2 on page 42 lists the interrupts on the LM3S2016 controller. settable PendSV SysTick Interrupts 13 14 15 16 and above settable settable settable a. 0 is the default priority for all the settable priorities. Table 4-2. Interrupts Interrupt (Bit in Interrupt Registers) Description 0 1 2 3 4 5 6 7 8 14 15 16 17 18 19 20 21 22 28 29 30 31 32 39 GPIO Port A GPIO Port B GPIO Port C GPIO Port D GPIO Port E UART0 UART1 SSI0 I2C0 ADC Sequence 0 ADC Sequence 1 ADC Sequence 2 ADC Sequence 3 Watchdog timer Timer0 A Timer0 B Timer1 A Timer1 B System Control Flash Control GPIO Port F GPIO Port G GPIO Port H CAN0 42 Preliminary November 30, 2007 LM3S2016 Microcontroller 5 JTAG Interface The Joint Test Action Group (JTAG) port is an IEEE standard that defines a Test Access Port and Boundary Scan Architecture for digital integrated circuits and provides a standardized serial interface for controlling the associated test logic. The TAP, Instruction Register (IR), and Data Registers (DR) can be used to test the interconnections of assembled printed circuit boards and obtain manufacturing information on the components. The JTAG Port also provides a means of accessing and controlling design-for-test features such as I/O pin observation and control, scan testing, and debugging. The JTAG port is comprised of the standard five pins: TRST, TCK, TMS, TDI, and TDO. Data is transmitted serially into the controller on TDI and out of the controller on TDO. The interpretation of this data is dependent on the current state of the TAP controller. For detailed information on the operation of the JTAG port and TAP controller, please refer to the IEEE Standard 1149.1-Test Access Port and Boundary-Scan Architecture. The Luminary Micro JTAG controller works with the ARM JTAG controller built into the Cortex-M3 core. This is implemented by multiplexing the TDO outputs from both JTAG controllers. ARM JTAG instructions select the ARM TDO output while Luminary Micro JTAG instructions select the Luminary Micro TDO outputs. The multiplexer is controlled by the Luminary Micro JTAG controller, which has comprehensive programming for the ARM, Luminary Micro, and unimplemented JTAG instructions. The JTAG module has the following features: ■ IEEE 1149.1-1990 compatible Test Access Port (TAP) controller ■ Four-bit Instruction Register (IR) chain for storing JTAG instructions ■ IEEE standard instructions: – BYPASS instruction – IDCODE instruction – SAMPLE/PRELOAD instruction – EXTEST instruction – INTEST instruction ■ ARM additional instructions: – APACC instruction – DPACC instruction – ABORT instruction ■ Integrated ARM Serial Wire Debug (SWD) See the ARM® Cortex™-M3 Technical Reference Manual for more information on the ARM JTAG controller. November 30, 2007 Preliminary 43 JTAG Interface 5.1 Block Diagram Figure 5-1. JTAG Module Block Diagram TRST TCK TMS TDI TAP Controller Instruction Register (IR) BYPASS Data Register Boundar y Scan Data Register IDCODE Data Register ABORT Data Register DPACC Data Register APACC Data Register TDO Cor tex-M3 Debug Por t 5.2 Functional Description A high-level conceptual drawing of the JTAG module is shown in Figure 5-1 on page 44. The JTAG module is composed of the Test Access Port (TAP) controller and serial shift chains with parallel update registers. The TAP controller is a simple state machine controlled by the TRST, TCK and TMS inputs. The current state of the TAP controller depends on the current value of TRST and the sequence of values captured on TMS at the rising edge of TCK. The TAP controller determines when the serial shift chains capture new data, shift data from TDI towards TDO, and update the parallel load registers. The current state of the TAP controller also determines whether the Instruction Register (IR) chain or one of the Data Register (DR) chains is being accessed. The serial shift chains with parallel load registers are comprised of a single Instruction Register (IR) chain and multiple Data Register (DR) chains. The current instruction loaded in the parallel load register determines which DR chain is captured, shifted, or updated during the sequencing of the TAP controller. Some instructions, like EXTEST and INTEST, operate on data currently in a DR chain and do not capture, shift, or update any of the chains. Instructions that are not implemented decode to the BYPASS instruction to ensure that the serial path between TDI and TDO is always connected (see Table 5-2 on page 50 for a list of implemented instructions). See “JTAG and Boundary Scan” on page 439 for JTAG timing diagrams. 44 Preliminary November 30, 2007 LM3S2016 Microcontroller 5.2.1 JTAG Interface Pins The JTAG interface consists of five standard pins: TRST, TCK, TMS, TDI, and TDO. These pins and their associated reset state are given in Table 5-1 on page 45. Detailed information on each pin follows. Table 5-1. JTAG Port Pins Reset State Pin Name TRST TCK TMS TDI TDO Data Direction Input Input Input Input Output Internal Pull-Up Enabled Enabled Enabled Enabled Enabled Internal Pull-Down Disabled Disabled Disabled Disabled Disabled Drive Strength N/A N/A N/A N/A 2-mA driver Drive Value N/A N/A N/A N/A High-Z 5.2.1.1 Test Reset Input (TRST) The TRST pin is an asynchronous active Low input signal for initializing and resetting the JTAG TAP controller and associated JTAG circuitry. When TRST is asserted, the TAP controller resets to the Test-Logic-Reset state and remains there while TRST is asserted. When the TAP controller enters the Test-Logic-Reset state, the JTAG Instruction Register (IR) resets to the default instruction, IDCODE. By default, the internal pull-up resistor on the TRST pin is enabled after reset. Changes to the pull-up resistor settings on GPIO Port B should ensure that the internal pull-up resistor remains enabled on PB7/TRST; otherwise JTAG communication could be lost. 5.2.1.2 Test Clock Input (TCK) The TCK pin is the clock for the JTAG module. This clock is provided so the test logic can operate independently of any other system clocks. In addition, it ensures that multiple JTAG TAP controllers that are daisy-chained together can synchronously communicate serial test data between components. During normal operation, TCK is driven by a free-running clock with a nominal 50% duty cycle. When necessary, TCK can be stopped at 0 or 1 for extended periods of time. While TCK is stopped at 0 or 1, the state of the TAP controller does not change and data in the JTAG Instruction and Data Registers is not lost. By default, the internal pull-up resistor on the TCK pin is enabled after reset. This assures that no clocking occurs if the pin is not driven from an external source. The internal pull-up and pull-down resistors can be turned off to save internal power as long as the TCK pin is constantly being driven by an external source. 5.2.1.3 Test Mode Select (TMS) The TMS pin selects the next state of the JTAG TAP controller. TMS is sampled on the rising edge of TCK. Depending on the current TAP state and the sampled value of TMS, the next state is entered. Because the TMS pin is sampled on the rising edge of TCK, the IEEE Standard 1149.1 expects the value on TMS to change on the falling edge of TCK. Holding TMS high for five consecutive TCK cycles drives the TAP controller state machine to the Test-Logic-Reset state. When the TAP controller enters the Test-Logic-Reset state, the JTAG Instruction Register (IR) resets to the default instruction, IDCODE. Therefore, this sequence can be used as a reset mechanism, similar to asserting TRST. The JTAG Test Access Port state machine can be seen in its entirety in Figure 5-2 on page 47. November 30, 2007 Preliminary 45 JTAG Interface By default, the internal pull-up resistor on the TMS pin is enabled after reset. Changes to the pull-up resistor settings on GPIO Port C should ensure that the internal pull-up resistor remains enabled on PC1/TMS; otherwise JTAG communication could be lost. 5.2.1.4 Test Data Input (TDI) The TDI pin provides a stream of serial information to the IR chain and the DR chains. TDI is sampled on the rising edge of TCK and, depending on the current TAP state and the current instruction, presents this data to the proper shift register chain. Because the TDI pin is sampled on the rising edge of TCK, the IEEE Standard 1149.1 expects the value on TDI to change on the falling edge of TCK. By default, the internal pull-up resistor on the TDI pin is enabled after reset. Changes to the pull-up resistor settings on GPIO Port C should ensure that the internal pull-up resistor remains enabled on PC2/TDI; otherwise JTAG communication could be lost. 5.2.1.5 Test Data Output (TDO) The TDO pin provides an output stream of serial information from the IR chain or the DR chains. The value of TDO depends on the current TAP state, the current instruction, and the data in the chain being accessed. In order to save power when the JTAG port is not being used, the TDO pin is placed in an inactive drive state when not actively shifting out data. Because TDO can be connected to the TDI of another controller in a daisy-chain configuration, the IEEE Standard 1149.1 expects the value on TDO to change on the falling edge of TCK. By default, the internal pull-up resistor on the TDO pin is enabled after reset. This assures that the pin remains at a constant logic level when the JTAG port is not being used. The internal pull-up and pull-down resistors can be turned off to save internal power if a High-Z output value is acceptable during certain TAP controller states. 5.2.2 JTAG TAP Controller The JTAG TAP controller state machine is shown in Figure 5-2 on page 47. The TAP controller state machine is reset to the Test-Logic-Reset state on the assertion of a Power-On-Reset (POR) or the assertion of TRST. Asserting the correct sequence on the TMS pin allows the JTAG module to shift in new instructions, shift in data, or idle during extended testing sequences. For detailed information on the function of the TAP controller and the operations that occur in each state, please refer to IEEE Standard 1149.1. 46 Preliminary November 30, 2007 LM3S2016 Microcontroller Figure 5-2. Test Access Port State Machine Test Logic Reset 1 0 Run Test Idle 1 Select DR Scan 0 1 Capture DR 0 Shift DR 1 Exit 1 DR 0 Pause DR 1 0 Exit 2 DR 1 Update DR 1 0 0 0 0 1 1 1 Select IR Scan 0 Capture IR 0 Shift IR 1 Exit 1 IR 0 Pause IR 1 Exit 2 IR 1 Update IR 1 0 0 0 1 1 0 5.2.3 Shift Registers The Shift Registers consist of a serial shift register chain and a parallel load register. The serial shift register chain samples specific information during the TAP controller ’s CAPTURE states and allows this information to be shifted out of TDO during the TAP controller ’s SHIFT states. While the sampled data is being shifted out of the chain on TDO, new data is being shifted into the serial shift register on TDI. This new data is stored in the parallel load register during the TAP controller ’s UPDATE states. Each of the shift registers is discussed in detail in “Register Descriptions” on page 50. 5.2.4 Operational Considerations There are certain operational considerations when using the JTAG module. Because the JTAG pins can be programmed to be GPIOs, board configuration and reset conditions on these pins must be considered. In addition, because the JTAG module has integrated ARM Serial Wire Debug, the method for switching between these two operational modes is described below. November 30, 2007 Preliminary 47 JTAG Interface 5.2.4.1 GPIO Functionality When the controller is reset with either a POR or RST, the JTAG/SWD port pins default to their JTAG/SWD configurations. The default configuration includes enabling digital functionality (setting GPIODEN to 1), enabling the pull-up resistors (setting GPIOPUR to 1), and enabling the alternate hardware function (setting GPIOAFSEL to 1) for the PB7 and PC[3:0] JTAG/SWD pins. It is possible for software to configure these pins as GPIOs after reset by writing 0s to PB7 and PC[3:0] in the GPIOAFSEL register. If the user does not require the JTAG/SWD port for debugging or board-level testing, this provides five more GPIOs for use in the design. Caution – If the JTAG pins are used as GPIOs in a design, PB7 and PC2 cannot have external pull-down resistors connected to both of them at the same time. If both pins are pulled Low during reset, the controller has unpredictable behavior. If this happens, remove one or both of the pull-down resistors, and apply RST or power-cycle the part. In addition, it is possible to create a software sequence that prevents the debugger from connecting to the Stellaris® microcontroller. If the program code loaded into flash immediately changes the JTAG pins to their GPIO functionality, the debugger may not have enough time to connect and halt the controller before the JTAG pin functionality switches. This may lock the debugger out of the part. This can be avoided with a software routine that restores JTAG functionality based on an external or software trigger. The commit control registers provide a layer of protection against accidental programming of critical hardware peripherals. Writes to protected bits of the GPIO Alternate Function Select (GPIOAFSEL) register (see page 149) are not committed to storage unless the GPIO Lock (GPIOLOCK) register (see page 159) has been unlocked and the appropriate bits of the GPIO Commit (GPIOCR) register (see page 160) have been set to 1. Recovering a "Locked" Device If software configures any of the JTAG/SWD pins as GPIO and loses the ability to communicate with the debugger, there is a debug sequence that can be used to recover the device. Performing a total of ten JTAG-to-SWD and SWD-to-JTAG switch sequences while holding the device in reset mass erases the flash memory. The sequence to recover the device is: 1. Assert and hold the RST signal. 2. Perform the JTAG-to-SWD switch sequence. 3. Perform the SWD-to-JTAG switch sequence. 4. Perform the JTAG-to-SWD switch sequence. 5. Perform the SWD-to-JTAG switch sequence. 6. Perform the JTAG-to-SWD switch sequence. 7. Perform the SWD-to-JTAG switch sequence. 8. Perform the JTAG-to-SWD switch sequence. 9. Perform the SWD-to-JTAG switch sequence. 10. Perform the JTAG-to-SWD switch sequence. 11. Perform the SWD-to-JTAG switch sequence. 48 Preliminary November 30, 2007 LM3S2016 Microcontroller 12. Release the RST signal. The JTAG-to-SWD and SWD-to-JTAG switch sequences are described in “ARM Serial Wire Debug (SWD)” on page 49. When performing switch sequences for the purpose of recovering the debug capabilities of the device, only steps 1 and 2 of the switch sequence need to be performed. 5.2.4.2 ARM Serial Wire Debug (SWD) In order to seamlessly integrate the ARM Serial Wire Debug (SWD) functionality, a serial-wire debugger must be able to connect to the Cortex-M3 core without having to perform, or have any knowledge of, JTAG cycles. This is accomplished with a SWD preamble that is issued before the SWD session begins. The preamble used to enable the SWD interface of the SWJ-DP module starts with the TAP controller in the Test-Logic-Reset state. From here, the preamble sequences the TAP controller through the following states: Run Test Idle, Select DR, Select IR, Test Logic Reset, Test Logic Reset, Run Test Idle, Run Test Idle, Select DR, Select IR, Test Logic Reset, Test Logic Reset, Run Test Idle, Run Test Idle, Select DR, Select IR, and Test Logic Reset states. Stepping through this sequences of the TAP state machine enables the SWD interface and disables the JTAG interface. For more information on this operation and the SWD interface, see the ARM® Cortex™-M3 Technical Reference Manual and the ARM® CoreSight Technical Reference Manual. Because this sequence is a valid series of JTAG operations that could be issued, the ARM JTAG TAP controller is not fully compliant to the IEEE Standard 1149.1. This is the only instance where the ARM JTAG TAP controller does not meet full compliance with the specification. Due to the low probability of this sequence occurring during normal operation of the TAP controller, it should not affect normal performance of the JTAG interface. JTAG-to-SWD Switching To switch the operating mode of the Debug Access Port (DAP) from JTAG to SWD mode, the external debug hardware must send a switch sequence to the device. The 16-bit switch sequence for switching to SWD mode is defined as b1110011110011110, transmitted LSB first. This can also be represented as 16'hE79E when transmitted LSB first. The complete switch sequence should consist of the following transactions on the TCK/SWCLK and TMS/SWDIO signals: 1. Send at least 50 TCK/SWCLK cycles with TMS/SWDIO set to 1. This ensures that both JTAG and SWD are in their reset/idle states. 2. Send the 16-bit JTAG-to-SWD switch sequence, 16'hE79E. 3. Send at least 50 TCK/SWCLK cycles with TMS/SWDIO set to 1. This ensures that if SWJ-DP was already in SWD mode, before sending the switch sequence, the SWD goes into the line reset state. SWD-to-JTAG Switching To switch the operating mode of the Debug Access Port (DAP) from SWD to JTAG mode, the external debug hardware must send a switch sequence to the device. The 16-bit switch sequence for switching to JTAG mode is defined as b1110011110011110, transmitted LSB first. This can also be represented as 16'hE73C when transmitted LSB first. The complete switch sequence should consist of the following transactions on the TCK/SWCLK and TMS/SWDIO signals: 1. Send at least 50 TCK/SWCLK cycles with TMS/SWDIO set to 1. This ensures that both JTAG and SWD are in their reset/idle states. November 30, 2007 Preliminary 49 JTAG Interface 2. Send the 16-bit SWD-to-JTAG switch sequence, 16'hE73C. 3. Send at least 5 TCK/SWCLK cycles with TMS/SWDIO set to 1. This ensures that if SWJ-DP was already in JTAG mode, before sending the switch sequence, the JTAG goes into the Test Logic Reset state. 5.3 Initialization and Configuration After a Power-On-Reset or an external reset (RST), the JTAG pins are automatically configured for JTAG communication. No user-defined initialization or configuration is needed. However, if the user application changes these pins to their GPIO function, they must be configured back to their JTAG functionality before JTAG communication can be restored. This is done by enabling the five JTAG pins (PB7 and PC[3:0]) for their alternate function using the GPIOAFSEL register. 5.4 Register Descriptions There are no APB-accessible registers in the JTAG TAP Controller or Shift Register chains. The registers within the JTAG controller are all accessed serially through the TAP Controller. The registers can be broken down into two main categories: Instruction Registers and Data Registers. 5.4.1 Instruction Register (IR) The JTAG TAP Instruction Register (IR) is a four-bit serial scan chain with a parallel load register connected between the JTAG TDI and TDO pins. When the TAP Controller is placed in the correct states, bits can be shifted into the Instruction Register. Once these bits have been shifted into the chain and updated, they are interpreted as the current instruction. The decode of the Instruction Register bits is shown in Table 5-2 on page 50. A detailed explanation of each instruction, along with its associated Data Register, follows. Table 5-2. JTAG Instruction Register Commands IR[3:0] 0000 0001 0010 1000 1010 1011 1110 1111 All Others Instruction EXTEST INTEST Description Drives the values preloaded into the Boundary Scan Chain by the SAMPLE/PRELOAD instruction onto the pads. Drives the values preloaded into the Boundary Scan Chain by the SAMPLE/PRELOAD instruction into the controller. SAMPLE / PRELOAD Captures the current I/O values and shifts the sampled values out of the Boundary Scan Chain while new preload data is shifted in. ABORT DPACC APACC IDCODE BYPASS Reserved Shifts data into the ARM Debug Port Abort Register. Shifts data into and out of the ARM DP Access Register. Shifts data into and out of the ARM AC Access Register. Loads manufacturing information defined by the IEEE Standard 1149.1 into the IDCODE chain and shifts it out. Connects TDI to TDO through a single Shift Register chain. Defaults to the BYPASS instruction to ensure that TDI is always connected to TDO. 5.4.1.1 EXTEST Instruction The EXTEST instruction does not have an associated Data Register chain. The EXTEST instruction uses the data that has been preloaded into the Boundary Scan Data Register using the SAMPLE/PRELOAD instruction. When the EXTEST instruction is present in the Instruction Register, the preloaded data in the Boundary Scan Data Register associated with the outputs and output enables are used to drive the GPIO pads rather than the signals coming from the core. This allows 50 Preliminary November 30, 2007 LM3S2016 Microcontroller tests to be developed that drive known values out of the controller, which can be used to verify connectivity. 5.4.1.2 INTEST Instruction The INTEST instruction does not have an associated Data Register chain. The INTEST instruction uses the data that has been preloaded into the Boundary Scan Data Register using the SAMPLE/PRELOAD instruction. When the INTEST instruction is present in the Instruction Register, the preloaded data in the Boundary Scan Data Register associated with the inputs are used to drive the signals going into the core rather than the signals coming from the GPIO pads. This allows tests to be developed that drive known values into the controller, which can be used for testing. It is important to note that although the RST input pin is on the Boundary Scan Data Register chain, it is only observable. 5.4.1.3 SAMPLE/PRELOAD Instruction The SAMPLE/PRELOAD instruction connects the Boundary Scan Data Register chain between TDI and TDO. This instruction samples the current state of the pad pins for observation and preloads new test data. Each GPIO pad has an associated input, output, and output enable signal. When the TAP controller enters the Capture DR state during this instruction, the input, output, and output-enable signals to each of the GPIO pads are captured. These samples are serially shifted out of TDO while the TAP controller is in the Shift DR state and can be used for observation or comparison in various tests. While these samples of the inputs, outputs, and output enables are being shifted out of the Boundary Scan Data Register, new data is being shifted into the Boundary Scan Data Register from TDI. Once the new data has been shifted into the Boundary Scan Data Register, the data is saved in the parallel load registers when the TAP controller enters the Update DR state. This update of the parallel load register preloads data into the Boundary Scan Data Register that is associated with each input, output, and output enable. This preloaded data can be used with the EXTEST and INTEST instructions to drive data into or out of the controller. Please see “Boundary Scan Data Register” on page 53 for more information. 5.4.1.4 ABORT Instruction The ABORT instruction connects the associated ABORT Data Register chain between TDI and TDO. This instruction provides read and write access to the ABORT Register of the ARM Debug Access Port (DAP). Shifting the proper data into this Data Register clears various error bits or initiates a DAP abort of a previous request. Please see the “ABORT Data Register” on page 53 for more information. 5.4.1.5 DPACC Instruction The DPACC instruction connects the associated DPACC Data Register chain between TDI and TDO. This instruction provides read and write access to the DPACC Register of the ARM Debug Access Port (DAP). Shifting the proper data into this register and reading the data output from this register allows read and write access to the ARM debug and status registers. Please see “DPACC Data Register” on page 53 for more information. 5.4.1.6 APACC Instruction The APACC instruction connects the associated APACC Data Register chain between TDI and TDO. This instruction provides read and write access to the APACC Register of the ARM Debug Access Port (DAP). Shifting the proper data into this register and reading the data output from this register allows read and write access to internal components and buses through the Debug Port. Please see “APACC Data Register” on page 53 for more information. November 30, 2007 Preliminary 51 JTAG Interface 5.4.1.7 IDCODE Instruction The IDCODE instruction connects the associated IDCODE Data Register chain between TDI and TDO. This instruction provides information on the manufacturer, part number, and version of the ARM core. This information can be used by testing equipment and debuggers to automatically configure their input and output data streams. IDCODE is the default instruction that is loaded into the JTAG Instruction Register when a power-on-reset (POR) is asserted, TRST is asserted, or the Test-Logic-Reset state is entered. Please see “IDCODE Data Register” on page 52 for more information. 5.4.1.8 BYPASS Instruction The BYPASS instruction connects the associated BYPASS Data Register chain between TDI and TDO. This instruction is used to create a minimum length serial path between the TDI and TDO ports. The BYPASS Data Register is a single-bit shift register. This instruction improves test efficiency by allowing components that are not needed for a specific test to be bypassed in the JTAG scan chain by loading them with the BYPASS instruction. Please see “BYPASS Data Register” on page 52 for more information. 5.4.2 Data Registers The JTAG module contains six Data Registers. These include: IDCODE, BYPASS, Boundary Scan, APACC, DPACC, and ABORT serial Data Register chains. Each of these Data Registers is discussed in the following sections. 5.4.2.1 IDCODE Data Register The format for the 32-bit IDCODE Data Register defined by the IEEE Standard 1149.1 is shown in Figure 5-3 on page 52. The standard requires that every JTAG-compliant device implement either the IDCODE instruction or the BYPASS instruction as the default instruction. The LSB of the IDCODE Data Register is defined to be a 1 to distinguish it from the BYPASS instruction, which has an LSB of 0. This allows auto configuration test tools to determine which instruction is the default instruction. The major uses of the JTAG port are for manufacturer testing of component assembly, and program development and debug. To facilitate the use of auto-configuration debug tools, the IDCODE instruction outputs a value of 0x3BA00477. This value indicates an ARM Cortex-M3, Version 1 processor. This allows the debuggers to automatically configure themselves to work correctly with the Cortex-M3 during debug. Figure 5-3. IDCODE Register Format 5.4.2.2 BYPASS Data Register The format for the 1-bit BYPASS Data Register defined by the IEEE Standard 1149.1 is shown in Figure 5-4 on page 53. The standard requires that every JTAG-compliant device implement either the BYPASS instruction or the IDCODE instruction as the default instruction. The LSB of the BYPASS Data Register is defined to be a 0 to distinguish it from the IDCODE instruction, which has an LSB of 1. This allows auto configuration test tools to determine which instruction is the default instruction. 52 Preliminary November 30, 2007 LM3S2016 Microcontroller Figure 5-4. BYPASS Register Format 5.4.2.3 Boundary Scan Data Register The format of the Boundary Scan Data Register is shown in Figure 5-5 on page 53. Each GPIO pin, in a counter-clockwise direction from the JTAG port pins, is included in the Boundary Scan Data Register. Each GPIO pin has three associated digital signals that are included in the chain. These signals are input, output, and output enable, and are arranged in that order as can be seen in the figure. In addition to the GPIO pins, the controller reset pin, RST, is included in the chain. Because the reset pin is always an input, only the input signal is included in the Data Register chain. When the Boundary Scan Data Register is accessed with the SAMPLE/PRELOAD instruction, the input, output, and output enable from each digital pad are sampled and then shifted out of the chain to be verified. The sampling of these values occurs on the rising edge of TCK in the Capture DR state of the TAP controller. While the sampled data is being shifted out of the Boundary Scan chain in the Shift DR state of the TAP controller, new data can be preloaded into the chain for use with the EXTEST and INTEST instructions. These instructions either force data out of the controller, with the EXTEST instruction, or into the controller, with the INTEST instruction. Figure 5-5. Boundary Scan Register Format TDI I N O U T G PIO PB6 O E ... I N O U T GP IO m O E I N RST I N O U T GPIO m+ 1 O E ... I N O U T G PIO n O TDO E For detailed information on the order of the input, output, and output enable bits for each of the ® GPIO ports, please refer to the Stellaris Family Boundary Scan Description Language (BSDL) files, downloadable from www.luminarymicro.com. 5.4.2.4 APACC Data Register The format for the 35-bit APACC Data Register defined by ARM is described in the ARM® Cortex™-M3 Technical Reference Manual. 5.4.2.5 DPACC Data Register The format for the 35-bit DPACC Data Register defined by ARM is described in the ARM® Cortex™-M3 Technical Reference Manual. 5.4.2.6 ABORT Data Register The format for the 35-bit ABORT Data Register defined by ARM is described in the ARM® Cortex™-M3 Technical Reference Manual. November 30, 2007 Preliminary 53 System Control 6 System Control System control determines the overall operation of the device. It provides information about the device, controls the clocking to the core and individual peripherals, and handles reset detection and reporting. 6.1 Functional Description The System Control module provides the following capabilities: ■ Device identification, see “Device Identification” on page 54 ■ Local control, such as reset (see “Reset Control” on page 54), power (see “Power Control” on page 57) and clock control (see “Clock Control” on page 57) ■ System control (Run, Sleep, and Deep-Sleep modes), see “System Control” on page 59 6.1.1 Device Identification Seven read-only registers provide software with information on the microcontroller, such as version, part number, SRAM size, flash size, and other features. See the DID0, DID1, and DC0-DC4 registers. 6.1.2 Reset Control This section discusses aspects of hardware functions during reset as well as system software requirements following the reset sequence. 6.1.2.1 CMOD0 and CMOD1 Test-Mode Control Pins Two pins, CMOD0 and CMOD1, are defined for use by Luminary Micro for testing the devices during manufacture. They have no end-user function and should not be used. The CMOD pins should be connected to ground. 6.1.2.2 Reset Sources The controller has five sources of reset: 1. External reset input pin (RST) assertion, see “RST Pin Assertion” on page 54. 2. Power-on reset (POR), see “Power-On Reset (POR)” on page 55. 3. Internal brown-out (BOR) detector, see “Brown-Out Reset (BOR)” on page 55. 4. Software-initiated reset (with the software reset registers), see “Software Reset” on page 56. 5. A watchdog timer reset condition violation, see “Watchdog Timer Reset” on page 56. After a reset, the Reset Cause (RESC) register is set with the reset cause. The bits in this register are sticky and maintain their state across multiple reset sequences, except when an internal POR is the cause, and then all the other bits in the RESC register are cleared except for the POR indicator. 6.1.2.3 RST Pin Assertion The external reset pin (RST) resets the controller. This resets the core and all the peripherals except the JTAG TAP controller (see “JTAG Interface” on page 43). The external reset sequence is as follows: 54 Preliminary November 30, 2007 LM3S2016 Microcontroller 1. The external reset pin (RST) is asserted and then de-asserted. 2. The internal reset is released and the core loads from memory the initial stack pointer, the initial program counter, the first instruction designated by the program counter, and begins execution. A few clocks cycles from RST de-assertion to the start of the reset sequence is necessary for synchronization. The external reset timing is shown in Figure 19-9 on page 442. 6.1.2.4 Power-On Reset (POR) The Power-On Reset (POR) circuit monitors the power supply voltage (VDD). The POR circuit generates a reset signal to the internal logic when the power supply ramp reaches a threshold value (VTH). If the application only uses the POR circuit, the RST input needs to be connected to the power supply (VDD) through a pull-up resistor (1K to 10K Ω). The device must be operating within the specified operating parameters at the point when the on-chip power-on reset pulse is complete. The 3.3-V power supply to the device must reach 3.0 V within 10 msec of it crossing 2.0 V to guarantee proper operation. For applications that require the use of an external reset to hold the device in reset longer than the internal POR, the RST input may be used with the circuit as shown in Figure 6-1 on page 55. Figure 6-1. External Circuitry to Extend Reset Stellaris D1 R1 RST C1 R2 The R1 and C1 components define the power-on delay. The R2 resistor mitigates any leakage from the RST input. The diode (D1) discharges C1 rapidly when the power supply is turned off. The Power-On Reset sequence is as follows: 1. The controller waits for the later of external reset (RST) or internal POR to go inactive. 2. The internal reset is released and the core loads from memory the initial stack pointer, the initial program counter, the first instruction designated by the program counter, and begins execution. The internal POR is only active on the initial power-up of the controller. The Power-On Reset timing is shown in Figure 19-10 on page 442. Note: The power-on reset also resets the JTAG controller. An external reset does not. 6.1.2.5 Brown-Out Reset (BOR) A drop in the input voltage resulting in the assertion of the internal brown-out detector can be used to reset the controller. This is initially disabled and may be enabled by software. The system provides a brown-out detection circuit that triggers if the power supply (VDD) drops below a brown-out threshold voltage (VBTH). If a brown-out condition is detected, the system may generate a controller interrupt or a system reset. November 30, 2007 Preliminary 55 System Control Brown-out resets are controlled with the Power-On and Brown-Out Reset Control (PBORCTL) register. The BORIOR bit in the PBORCTL register must be set for a brown-out condition to trigger a reset. The brown-out reset is equivelent to an assertion of the external RST input and the reset is held active until the proper VDD level is restored. The RESC register can be examined in the reset interrupt handler to determine if a Brown-Out condition was the cause of the reset, thus allowing software to determine what actions are required to recover. The internal Brown-Out Reset timing is shown in Figure 19-11 on page 442. 6.1.2.6 Software Reset Software can reset a specific peripheral or generate a reset to the entire system . Peripherals can be individually reset by software via three registers that control reset signals to each peripheral (see the SRCRn registers). If the bit position corresponding to a peripheral is set and subsequently cleared, the peripheral is reset. The encoding of the reset registers is consistent with the encoding of the clock gating control for peripherals and on-chip functions (see “System Control” on page 59). Note that all reset signals for all clocks of the specified unit are asserted as a result of a software-initiated reset. The entire system can be reset by software by setting the SYSRESETREQ bit in the Cortex-M3 Application Interrupt and Reset Control register resets the entire system including the core. The software-initiated system reset sequence is as follows: 1. A software system reset is initiated by writing the SYSRESETREQ bit in the ARM Cortex-M3 Application Interrupt and Reset Control register. 2. An internal reset is asserted. 3. The internal reset is deasserted and the controller loads from memory the initial stack pointer, the initial program counter, and the first instruction designated by the program counter, and then begins execution. The software-initiated system reset timing is shown in Figure 19-12 on page 443. 6.1.2.7 Watchdog Timer Reset The watchdog timer module's function is to prevent system hangs. The watchdog timer can be configured to generate an interrupt to the controller on its first time-out, and to generate a reset signal on its second time-out. After the first time-out event, the 32-bit counter is reloaded with the value of the Watchdog Timer Load (WDTLOAD) register, and the timer resumes counting down from that value. If the timer counts down to its zero state again before the first time-out interrupt is cleared, and the reset signal has been enabled, the watchdog timer asserts its reset signal to the system. The watchdog timer reset sequence is as follows: 1. The watchdog timer times out for the second time without being serviced. 2. An internal reset is asserted. 3. The internal reset is released and the controller loads from memory the initial stack pointer, the initial program counter, the first instruction designated by the program counter, and begins execution. 56 Preliminary November 30, 2007 LM3S2016 Microcontroller The watchdog reset timing is shown in Figure 19-13 on page 443. 6.1.3 Power Control The Stellaris microcontroller provides an integrated LDO regulator that may be used to provide power to the majority of the controller's internal logic. The LDO regulator provides software a mechanism to adjust the regulated value, in small increments (VSTEP), over the range of 2.25 V to 2.75 V (inclusive)—or 2.5 V ± 10%. The adjustment is made by changing the value of the VADJ field in the LDO Power Control (LDOPCTL) register. Note: The use of the LDO is optional. The internal logic may be supplied by the on-chip LDO or by an external regulator. If the LDO is used, the LDO output pin is connected to the VDD25 pins on the printed circuit board. The LDO requires decoupling capacitors on the printed circuit board. If an external regulator is used, it is strongly recommended that the external regulator supply the controller only and not be shared with other devices on the printed circuit board. ® 6.1.4 6.1.4.1 Clock Control System control determines the control of clocks in this part. Fundamental Clock Sources There are four clock sources for use in the device: ■ Internal Oscillator (IOSC): The internal oscillator is an on-chip clock source. It does not require the use of any external components. The frequency of the internal oscillator is 12 MHz ± 30%. Applications that do not depend on accurate clock sources may use this clock source to reduce system cost. The internal oscillator is the clock source the device uses during and following POR. If the main oscillator is required, software must enable the main oscillator following reset and allow the main oscillator to stabilize before changing the clock reference. ■ Main Oscillator: The main oscillator provides a frequency-accurate clock source by one of two means: an external single-ended clock source is connected to the OSC0 input pin, or an external crystal is connected across the OSC0 input and OSC1 output pins. The crystal value allowed depends on whether the main oscillator is used as the clock reference source to the PLL. If so, the crystal must be one of the supported frequencies between 3.579545 MHz through 8.192 MHz (inclusive). If the PLL is not being used, the crystal may be any one of the supported frequencies between 1 MHz and 8.192 MHz. The single-ended clock source range is from DC through the specified speed of the device. The supported crystals are listed in the XTAL bit in the RCC register (see page 70). ■ Internal 30-kHz Oscillator: The internal 30-kHz oscillator is similar to the internal oscillator, except that it provides an operational frequency of 30 kHz ± 30%. It is intended for use during Deep-Sleep power-saving modes. This power-savings mode benefits from reduced internal switching and also allows the main oscillator to be powered down. The internal system clock (sysclk), is derived from any of the four sources plus two others: the output of the internal PLL, and the internal oscillator divided by four (3 MHz ± 30%). The frequency of the PLL clock reference must be in the range of 3.579545 MHz to 8.192 MHz (inclusive). The Run-Mode Clock Configuration (RCC) and Run-Mode Clock Configuration 2 (RCC2) registers provide control for the system clock. The RCC2 register is provided to extend fields that offer additional encodings over the RCC register. When used, the RCC2 register field values are November 30, 2007 Preliminary 57 System Control used by the logic over the corresponding field in the RCC register. In particular, RCC2 provides for a larger assortment of clock configuration options. 6.1.4.2 Crystal Configuration for the Main Oscillator (MOSC) The main oscillator supports the use of a select number of crystals. If the main oscillator is used by the PLL as a reference clock, the supported range of crystals is 3.579545 to 8.192 MHz, otherwise, the range of supported crystals is 1 to 8.192 MHz. The XTAL bit in the RCC register (see page 70) describes the available crystal choices and default programming values. Software configures the RCC register XTAL field with the crystal number. If the PLL is used in the design, the XTAL field value is internally translated to the PLL settings. 6.1.4.3 PLL Frequency Configuration The PLL is disabled by default during power-on reset and is enabled later by software if required. Software configures the PLL input reference clock source, specifies the output divisor to set the system clock frequency, and enables the PLL to drive the output. If the main oscillator provides the clock reference to the PLL, the translation provided by hardware and used to program the PLL is available for software in the XTAL to PLL Translation (PLLCFG) register (see page 74). The internal translation provides a translation within ± 1% of the targeted PLL VCO frequency. The Crystal Value field (XTAL) on page 70 describes the available crystal choices and default programming of the PLLCFG register. The crystal number is written into the XTAL field of the Run-Mode Clock Configuration (RCC) register. Any time the XTAL field changes, the new settings are translated and the internal PLL settings are updated. 6.1.4.4 PLL Modes The PLL has two modes of operation: Normal and Power-Down ■ Normal: The PLL multiplies the input clock reference and drives the output. ■ Power-Down: Most of the PLL internal circuitry is disabled and the PLL does not drive the output. The modes are programmed using the RCC/RCC2 register fields (see page 70 and page 75). 6.1.4.5 PLL Operation If the PLL configuration is changed, the PLL output frequency is unstable until it reconverges (relocks) to the new setting. The time between the configuration change and relock is TREADY (see Table 19-6 on page 436). During this time, the PLL is not usable as a clock reference. The PLL is changed by one of the following: ■ Change to the XTAL value in the RCC register—writes of the same value do not cause a relock. ■ Change in the PLL from Power-Down to Normal mode. A counter is defined to measure the TREADY requirement. The counter is clocked by the main oscillator. The range of the main oscillator has been taken into account and the down counter is set to 0x1200 (that is, ~600 μs at an 8.192 MHz external oscillator clock). . Hardware is provided to keep the PLL from being used as a system clock until the TREADY condition is met after one of the 58 Preliminary November 30, 2007 LM3S2016 Microcontroller two changes above. It is the user's responsibility to have a stable clock source (like the main oscillator) before the RCC/RCC2 register is switched to use the PLL. 6.1.5 System Control For power-savings purposes, the RCGCn , SCGCn , and DCGCn registers control the clock gating logic for each peripheral or block in the system while the controller is in Run, Sleep, and Deep-Sleep mode, respectively. In Run mode, the processor executes code. In Sleep mode, the clock frequency of the active peripherals is unchanged, but the processor is not clocked and therefore no longer executes code. In Deep-Sleep mode, the clock frequency of the active peripherals may change (depending on the Run mode clock configuration) in addition to the processor clock being stopped. An interrupt returns the device to Run mode from one of the sleep modes; the sleep modes are entered on request from the code. Each mode is described in more detail below. There are four levels of operation for the device defined as: ■ Run Mode. Run mode provides normal operation of the processor and all of the peripherals that are currently enabled by the RCGCn registers. The system clock can be any of the available clock sources including the PLL. ■ Sleep Mode. Sleep mode is entered by the Cortex-M3 core executing a WFI (Wait for Interrupt) instruction. Any properly configured interrupt event in the system will bring the processor back into Run mode. See the system control NVIC section of the ARM® Cortex™-M3 Technical Reference Manual for more details. In Sleep mode, the Cortex-M3 processor core and the memory subsystem are not clocked. Peripherals are clocked that are enabled in the SCGCn register when auto-clock gating is enabled (see the RCC register) or the RCGCn register when the auto-clock gating is disabled. The system clock has the same source and frequency as that during Run mode. ■ Deep-Sleep Mode. Deep-Sleep mode is entered by first writing the Deep Sleep Enable bit in the ARM Cortex-M3 NVIC system control register and then executing a WFI instruction. Any properly configured interrupt event in the system will bring the processor back into Run mode. See the system control NVIC section of the ARM® Cortex™-M3 Technical Reference Manual for more details. The Cortex-M3 processor core and the memory subsystem are not clocked. Peripherals are clocked that are enabled in the DCGCn register when auto-clock gating is enabled (see the RCC register) or the RCGCn register when auto-clock gating is disabled. The system clock source is the main oscillator by default or the internal oscillator specified in the DSLPCLKCFG register if one is enabled. When the DSLPCLKCFG register is used, the internal oscillator is powered up, if necessary, and the main oscillator is powered down. If the PLL is running at the time of the WFI instruction, hardware will power the PLL down and override the SYSDIV field of the active RCC/RCC2 register to be /16 or /64, respectively. When the Deep-Sleep exit event occurs, hardware brings the system clock back to the source and frequency it had at the onset of Deep-Sleep mode before enabling the clocks that had been stopped during the Deep-Sleep duration. 6.2 Initialization and Configuration The PLL is configured using direct register writes to the RCC/RCC2 register. If the RCC2 register is being used, the USERCC2 bit must be set and the appropriate RCC2 bit/field is used. The steps required to successfully change the PLL-based system clock are: November 30, 2007 Preliminary 59 System Control 1. Bypass the PLL and system clock divider by setting the BYPASS bit and clearing the USESYS bit in the RCC register. This configures the system to run off a “raw” clock source (using the main oscillator or internal oscillator) and allows for the new PLL configuration to be validated before switching the system clock to the PLL. 2. Select the crystal value (XTAL) and oscillator source (OSCSRC), and clear the PWRDN bit in RCC/RCC2. Setting the XTAL field automatically pulls valid PLL configuration data for the appropriate crystal, and clearing the PWRDN bit powers and enables the PLL and its output. 3. Select the desired system divider (SYSDIV) in RCC/RCC2 and set the USESYS bit in RCC. The SYSDIV field determines the system frequency for the microcontroller. 4. Wait for the PLL to lock by polling the PLLLRIS bit in the Raw Interrupt Status (RIS) register. 5. Enable use of the PLL by clearing the BYPASS bit in RCC/RCC2. 6.3 Register Map Table 6-1 on page 60 lists the System Control registers, grouped by function. The offset listed is a hexadecimal increment to the register ’s address, relative to the System Control base address of 0x400F.E000. Note: Spaces in the System Control register space that are not used are reserved for future or internal use by Luminary Micro, Inc. Software should not modify any reserved memory address. Table 6-1. System Control Register Map Offset 0x000 0x004 0x008 0x010 0x014 0x018 0x01C 0x030 0x034 0x040 0x044 0x048 0x050 0x054 0x058 0x05C Name DID0 DID1 DC0 DC1 DC2 DC3 DC4 PBORCTL LDOPCTL SRCR0 SRCR1 SRCR2 RIS IMC MISC RESC Type RO RO RO RO RO RO RO R/W R/W R/W R/W R/W RO R/W R/W1C R/W Reset 0x001F.001F 0x0101.329F 0x0003.1013 0x0F0F.0000 0x0000.00FF 0x0000.7FFD 0x0000.0000 0x00000000 0x00000000 0x00000000 0x0000.0000 0x0000.0000 0x0000.0000 Description Device Identification 0 Device Identification 1 Device Capabilities 0 Device Capabilities 1 Device Capabilities 2 Device Capabilities 3 Device Capabilities 4 Brown-Out Reset Control LDO Power Control Software Reset Control 0 Software Reset Control 1 Software Reset Control 2 Raw Interrupt Status Interrupt Mask Control Masked Interrupt Status and Clear Reset Cause See page 62 78 80 81 83 85 87 64 65 106 107 108 66 67 68 69 60 Preliminary November 30, 2007 LM3S2016 Microcontroller Offset 0x060 0x064 0x070 0x100 0x104 0x108 0x110 0x114 0x118 0x120 0x124 0x128 0x144 Name RCC PLLCFG RCC2 RCGC0 RCGC1 RCGC2 SCGC0 SCGC1 SCGC2 DCGC0 DCGC1 DCGC2 DSLPCLKCFG Type R/W RO R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0x07A0.3AD1 0x0780.2800 0x00000040 0x00000000 0x00000000 0x00000040 0x00000000 0x00000000 0x00000040 0x00000000 0x00000000 0x0780.0000 Description Run-Mode Clock Configuration XTAL to PLL Translation Run-Mode Clock Configuration 2 Run Mode Clock Gating Control Register 0 Run Mode Clock Gating Control Register 1 Run Mode Clock Gating Control Register 2 Sleep Mode Clock Gating Control Register 0 Sleep Mode Clock Gating Control Register 1 Sleep Mode Clock Gating Control Register 2 Deep Sleep Mode Clock Gating Control Register 0 Deep Sleep Mode Clock Gating Control Register 1 Deep Sleep Mode Clock Gating Control Register 2 Deep Sleep Clock Configuration See page 70 74 75 88 94 100 90 96 102 92 98 104 77 6.4 Register Descriptions All addresses given are relative to the System Control base address of 0x400F.E000. November 30, 2007 Preliminary 61 System Control Register 1: Device Identification 0 (DID0), offset 0x000 This register identifies the version of the device. Device Identification 0 (DID0) Base 0x400F.E000 Offset 0x000 Type RO, reset 31 reserved Type Reset RO 0 15 RO 0 14 30 29 VER RO 0 13 RO 1 12 MAJOR Type Reset RO RO RO RO RO RO RO RO RO RO RO RO 0 11 28 27 26 25 24 23 22 21 20 CLASS RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 MINOR RO RO RO RO RO RO 0 3 RO 0 2 RO 0 1 RO 1 0 19 18 17 16 reserved RO 0 10 RO 0 9 Bit/Field 31 Name reserved Type RO Reset 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. DID0 Version This field defines the DID0 register format version. The version number is numeric. The value of the VER field is encoded as follows: Value Description 0x1 First revision of the DID0 register format, for Stellaris® Fury-class devices . 30:28 VER RO 0x1 27:24 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Device Class The CLASS field value identifies the internal design from which all mask sets are generated for all devices in a particular product line. The CLASS field value is changed for new product lines, for changes in fab process (for example, a remap or shrink), or any case where the MAJOR or MINOR fields require differentiation from prior devices. The value of the CLASS field is encoded as follows (all other encodings are reserved): Value Description 0x0 0x1 Stellaris® Sandstorm-class devices. Stellaris® Fury-class devices. 23:16 CLASS RO 0x1 62 Preliminary November 30, 2007 LM3S2016 Microcontroller Bit/Field 15:8 Name MAJOR Type RO Reset - Description Major Revision This field specifies the major revision number of the device. The major revision reflects changes to base layers of the design. The major revision number is indicated in the part number as a letter (A for first revision, B for second, and so on). This field is encoded as follows: Value Description 0x0 0x1 0x2 Revision A (initial device) Revision B (first base layer revision) Revision C (second base layer revision) and so on. 7:0 MINOR RO Minor Revision This field specifies the minor revision number of the device. The minor revision reflects changes to the metal layers of the design. The MINOR field value is reset when the MAJOR field is changed. This field is numeric and is encoded as follows: Value Description 0x0 0x1 0x2 Initial device, or a major revision update. First metal layer change. Second metal layer change. and so on. November 30, 2007 Preliminary 63 System Control Register 2: Brown-Out Reset Control (PBORCTL), offset 0x030 This register is responsible for controlling reset conditions after initial power-on reset. Brown-Out Reset Control (PBORCTL) Base 0x400F.E000 Offset 0x030 Type R/W, reset 0x0000.7FFD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 BORIOR reserved R/W 0 RO 0 Bit/Field 31:2 Name reserved Type RO Reset 0x0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. BOR Interrupt or Reset This bit controls how a BOR event is signaled to the controller. If set, a reset is signaled. Otherwise, an interrupt is signaled. 1 BORIOR R/W 0 0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 64 Preliminary November 30, 2007 LM3S2016 Microcontroller Register 3: LDO Power Control (LDOPCTL), offset 0x034 The VADJ field in this register adjusts the on-chip output voltage (VOUT). LDO Power Control (LDOPCTL) Base 0x400F.E000 Offset 0x034 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 VADJ RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:6 Name reserved Type RO Reset 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. LDO Output Voltage This field sets the on-chip output voltage. The programming values for the VADJ field are provided below. Value 0x00 0x01 0x02 0x03 0x04 0x05 VOUT (V) 2.50 2.45 2.40 2.35 2.30 2.25 5:0 VADJ R/W 0x0 0x06-0x3F Reserved 0x1B 0x1C 0x1D 0x1E 0x1F 2.75 2.70 2.65 2.60 2.55 November 30, 2007 Preliminary 65 System Control Register 4: Raw Interrupt Status (RIS), offset 0x050 Central location for system control raw interrupts. These are set and cleared by hardware. Raw Interrupt Status (RIS) Base 0x400F.E000 Offset 0x050 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 PLLLRIS RO 0 RO 0 RO 0 5 RO 0 4 reserved RO 0 RO 0 RO 0 RO 0 3 RO 0 2 RO 0 1 RO 0 0 BORRIS reserved RO 0 RO 0 Bit/Field 31:7 Name reserved Type RO Reset 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. PLL Lock Raw Interrupt Status This bit is set when the PLL TREADY Timer asserts. 6 PLLLRIS RO 0 5:2 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Brown-Out Reset Raw Interrupt Status This bit is the raw interrupt status for any brown-out conditions. If set, a brown-out condition is currently active. This is an unregistered signal from the brown-out detection circuit. An interrupt is reported if the BORIM bit in the IMC register is set and the BORIOR bit in the PBORCTL register is cleared. 1 BORRIS RO 0 0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 66 Preliminary November 30, 2007 LM3S2016 Microcontroller Register 5: Interrupt Mask Control (IMC), offset 0x054 Central location for system control interrupt masks. Interrupt Mask Control (IMC) Base 0x400F.E000 Offset 0x054 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 PLLLIM R/W 0 RO 0 RO 0 5 RO 0 4 reserved RO 0 RO 0 RO 0 RO 0 3 RO 0 2 RO 0 1 BORIM R/W 0 RO 0 0 reserved RO 0 Bit/Field 31:7 Name reserved Type RO Reset 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. PLL Lock Interrupt Mask This bit specifies whether a current limit detection is promoted to a controller interrupt. If set, an interrupt is generated if PLLLRIS in RIS is set; otherwise, an interrupt is not generated. 6 PLLLIM R/W 0 5:2 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Brown-Out Reset Interrupt Mask This bit specifies whether a brown-out condition is promoted to a controller interrupt. If set, an interrupt is generated if BORRIS is set; otherwise, an interrupt is not generated. 1 BORIM R/W 0 0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. November 30, 2007 Preliminary 67 System Control Register 6: Masked Interrupt Status and Clear (MISC), offset 0x058 Central location for system control result of RIS AND IMC to generate an interrupt to the controller. All of the bits are R/W1C and this action also clears the corresponding raw interrupt bit in the RIS register (see page 66). Masked Interrupt Status and Clear (MISC) Base 0x400F.E000 Offset 0x058 Type R/W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 PLLLMIS R/W1C 0 RO 0 RO 0 5 RO 0 4 reserved RO 0 RO 0 RO 0 RO 0 3 RO 0 2 RO 0 1 RO 0 0 BORMIS reserved R/W1C 0 RO 0 Bit/Field 31:7 Name reserved Type RO Reset 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. PLL Lock Masked Interrupt Status This bit is set when the PLL TREADY timer asserts. The interrupt is cleared by writing a 1 to this bit. 6 PLLLMIS R/W1C 0 5:2 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. BOR Masked Interrupt Status The BORMIS is simply the BORRIS ANDed with the mask value, BORIM. 1 BORMIS R/W1C 0 0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 68 Preliminary November 30, 2007 LM3S2016 Microcontroller Register 7: Reset Cause (RESC), offset 0x05C This register is set with the reset cause after reset. The bits in this register are sticky and maintain their state across multiple reset sequences, except when an external reset is the cause, and then all the other bits in the RESC register are cleared. Reset Cause (RESC) Base 0x400F.E000 Offset 0x05C Type R/W, reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 LDO RO 0 RO 0 RO 0 RO 0 R/W RO 0 4 SW R/W RO 0 3 WDT R/W RO 0 2 BOR R/W RO 0 1 POR R/W RO 0 0 EXT R/W - reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:6 Name reserved Type RO Reset 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. LDO Reset When set, indicates the LDO circuit has lost regulation and has generated a reset event. 5 LDO R/W - 4 SW R/W - Software Reset When set, indicates a software reset is the cause of the reset event. 3 WDT R/W - Watchdog Timer Reset When set, indicates a watchdog reset is the cause of the reset event. 2 BOR R/W - Brown-Out Reset When set, indicates a brown-out reset is the cause of the reset event. 1 POR R/W - Power-On Reset When set, indicates a power-on reset is the cause of the reset event. 0 EXT R/W - External Reset When set, indicates an external reset (RST assertion) is the cause of the reset event. November 30, 2007 Preliminary 69 System Control Register 8: Run-Mode Clock Configuration (RCC), offset 0x060 This register is defined to provide source control and frequency speed. Run-Mode Clock Configuration (RCC) Base 0x400F.E000 Offset 0x060 Type R/W, reset 0x07A0.3AD1 31 30 29 28 27 ACG RO 0 12 R/W 0 11 R/W 1 10 26 25 24 23 22 USESYSDIV 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 SYSDIV R/W 1 9 R/W 1 8 XTAL R/W 1 R/W 0 R/W 1 R/W 1 7 reserved RO 0 5 RO 0 4 RO 0 3 reserved RO 0 RO 0 RO 0 2 RO 0 1 RO 0 0 R/W 0 6 reserved Type Reset RO 0 RO 0 PWRDN reserved BYPASS reserved R/W 1 RO 1 R/W 1 RO 0 OSCSRC R/W 1 R/W 0 R/W 1 IOSCDIS MOSCDIS R/W 0 R/W 1 Bit/Field 31:28 Name reserved Type RO Reset 0x0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Auto Clock Gating This bit specifies whether the system uses the Sleep-Mode Clock Gating Control (SCGCn) registers and Deep-Sleep-Mode Clock Gating Control (DCGCn) registers if the controller enters a Sleep or Deep-Sleep mode (respectively). If set, the SCGCn or DCGCn registers are used to control the clocks distributed to the peripherals when the controller is in a sleep mode. Otherwise, the Run-Mode Clock Gating Control (RCGCn) registers are used when the controller enters a sleep mode. The RCGCn registers are always used to control the clocks in Run mode. This allows peripherals to consume less power when the controller is in a sleep mode and the peripheral is unused. 27 ACG R/W 0 70 Preliminary November 30, 2007 LM3S2016 Microcontroller Bit/Field 26:23 Name SYSDIV Type R/W Reset 0xF Description System Clock Divisor Specifies which divisor is used to generate the system clock from the PLL output. The PLL VCO frequency is 400 MHz. Value Divisor (BYPASS=1) Frequency (BYPASS=0) 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF reserved /2 /3 /4 /5 /6 /7 /8 /9 /10 /11 /12 /13 /14 /15 /16 reserved reserved reserved 50 MHz 40 MHz 33.33 MHz 28.57 MHz 25 MHz 22.22 MHz 20 MHz 18.18 MHz 16.67 MHz 15.38 MHz 14.29 MHz 13.33 MHz 12.5 MHz (default) When reading the Run-Mode Clock Configuration (RCC) register (see page 70), the SYSDIV value is MINSYSDIV if a lower divider was requested and the PLL is being used. This lower value is allowed to divide a non-PLL source. 22 USESYSDIV R/W 0 Enable System Clock Divider Use the system clock divider as the source for the system clock. The system clock divider is forced to be used when the PLL is selected as the source. 21:14 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. PLL Power Down This bit connects to the PLL PWRDN input. The reset value of 1 powers down the PLL. 12 reserved RO 1 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 13 PWRDN R/W 1 November 30, 2007 Preliminary 71 System Control Bit/Field 11 Name BYPASS Type R/W Reset 1 Description PLL Bypass Chooses whether the system clock is derived from the PLL output or the OSC source. If set, the clock that drives the system is the OSC source. Otherwise, the clock that drives the system is the PLL output clock divided by the system divider. Note: The ADC must be clocked from the PLL or directly from a 14-MHz to 18-MHz clock source to operate properly. While the ADC works in a 14-18 MHz range, to maintain a 1 M sample/second rate, the ADC must be provided a 16-MHz clock source. 10 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Crystal Value This field specifies the crystal value attached to the main oscillator. The encoding for this field is provided below. Value 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF Crystal Frequency (MHz) Not Using the PLL 1.000 1.8432 2.000 2.4576 3.579545 MHz 3.6864 MHz 4 MHz 4.096 MHz 4.9152 MHz 5 MHz 5.12 MHz 6 MHz (reset value) 6.144 MHz 7.3728 MHz 8 MHz 8.192 MHz Crystal Frequency (MHz) Using the PLL reserved reserved reserved reserved 9:6 XTAL R/W 0xB 5:4 OSCSRC R/W 0x1 Oscillator Source Picks among the four input sources for the OSC. The values are: Value Input Source 0x0 0x1 0x2 0x3 Main oscillator (default) Internal oscillator (default) Internal oscillator / 4 (this is necessary if used as input to PLL) reserved 72 Preliminary November 30, 2007 LM3S2016 Microcontroller Bit/Field 3:2 Name reserved Type RO Reset 0x0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Internal Oscillator Disable 0: Internal oscillator (IOSC) is enabled. 1: Internal oscillator is disabled. 1 IOSCDIS R/W 0 0 MOSCDIS R/W 1 Main Oscillator Disable 0: Main oscillator is enabled. 1: Main oscillator is disabled (default). November 30, 2007 Preliminary 73 System Control Register 9: XTAL to PLL Translation (PLLCFG), offset 0x064 This register provides a means of translating external crystal frequencies into the appropriate PLL settings. This register is initialized during the reset sequence and updated anytime that the XTAL field changes in the Run-Mode Clock Configuration (RCC) register (see page 70). The PLL frequency is calculated using the PLLCFG field values, as follows: PLLFreq = OSCFreq * F / (R + 1) XTAL to PLL Translation (PLLCFG) Base 0x400F.E000 Offset 0x064 Type RO, reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 F RO RO RO RO RO RO RO RO RO RO RO RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 R RO RO RO RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 Bit/Field 31:14 Name reserved Type RO Reset 0x0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. PLL F Value This field specifies the value supplied to the PLL’s F input. 13:5 F RO - 4:0 R RO - PLL R Value This field specifies the value supplied to the PLL’s R input. 74 Preliminary November 30, 2007 LM3S2016 Microcontroller Register 10: Run-Mode Clock Configuration 2 (RCC2), offset 0x070 This register overrides the RCC equivalent register fields when the USERCC2 bit is set. This allows RCC2 to be used to extend the capabilities, while also providing a means to be backward-compatible to previous parts. The fields within the RCC2 register occupy the same bit positions as they do within the RCC register as LSB-justified. The SYSDIV2 field is wider so that additional larger divisors are possible. This allows a lower system clock frequency for improved Deep Sleep power consumption. Run-Mode Clock Configuration 2 (RCC2) Base 0x400F.E000 Offset 0x070 Type R/W, reset 0x0780.2800 31 USERCC2 Type Reset R/W 0 15 30 29 28 27 26 25 24 23 22 21 20 19 reserved R/W 1 8 reserved RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 1 7 RO 0 6 RO 0 5 OSCSRC2 R/W 0 R/W 0 RO 0 RO 0 4 RO 0 3 RO 0 2 reserved RO 0 RO 0 RO 0 RO 0 1 RO 0 0 18 17 16 reserved RO 0 14 RO 0 13 R/W 0 12 R/W 0 11 SYSDIV2 R/W 1 10 R/W 1 9 reserved Type Reset RO 0 RO 0 PWRDN2 reserved BYPASS2 R/W 1 RO 0 R/W 1 Bit/Field 31 Name USERCC2 Type R/W Reset 0 Description Use RCC2 When set, overrides the RCC register fields. 30:29 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. System Clock Divisor Specifies which divisor is used to generate the system clock from the PLL output. The PLL VCO frequency is 400 MHz. This field is wider than the RCC register SYSDIV field in order to provide additional divisor values. This permits the system clock to be run at much lower frequencies during Deep Sleep mode. For example, where the RCC register SYSDIV encoding of 1111 provides /16, the RCC2 register SYSDIV2 encoding of 111111 provides /64. 28:23 SYSDIV2 R/W 0x0F 22:14 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Power-Down PLL When set, powers down the PLL. 13 PWRDN2 R/W 1 12 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Bypass PLL When set, bypasses the PLL for the clock source. 11 BYPASS2 R/W 1 November 30, 2007 Preliminary 75 System Control Bit/Field 10:7 Name reserved Type RO Reset 0x0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. System Clock Source Value Description 0x0 0x1 0x2 0x3 0x7 Main oscillator (MOSC) Internal oscillator (IOSC) Internal oscillator / 4 30 kHz internal oscillator 32 kHz external oscillator 6:4 OSCSRC2 R/W 0x0 3:0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 76 Preliminary November 30, 2007 LM3S2016 Microcontroller Register 11: Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 This register provides configuration information for the hardware control of Deep Sleep Mode. Deep Sleep Clock Configuration (DSLPCLKCFG) Base 0x400F.E000 Offset 0x144 Type R/W, reset 0x0780.0000 31 30 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 R/W 0 12 R/W 0 11 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 29 28 27 26 25 24 23 22 21 20 19 reserved R/W 1 8 R/W 1 7 RO 0 6 RO 0 5 DSOSCSRC R/W 0 R/W 0 RO 0 RO 0 4 RO 0 3 RO 0 2 reserved RO 0 RO 0 RO 0 RO 0 1 RO 0 0 18 17 16 DSDIVORIDE R/W 1 10 R/W 1 9 Bit/Field 31:29 Name reserved Type RO Reset 0x0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Divider Field Override 6-bit system divider field to override when Deep-Sleep occurs with PLL running. 28:23 DSDIVORIDE R/W 0x0F 22:7 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Clock Source When set, forces IOSC to be clock source during Deep Sleep mode. Value Name 0x0 0x1 0x3 0x7 Description 6:4 DSOSCSRC R/W 0x0 NOORIDE No override to the oscillator clock source is done IOSC 30kHz 32kHz Use internal 12 MHz oscillator as source Use 30 kHz internal oscillator Use 32 kHz external oscillator 3:0 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. November 30, 2007 Preliminary 77 System Control Register 12: Device Identification 1 (DID1), offset 0x004 This register identifies the device family, part number, temperature range, pin count, and package type. Device Identification 1 (DID1) Base 0x400F.E000 Offset 0x004 Type RO, reset 31 30 VER Type Reset RO 0 15 RO 0 14 PINCOUNT Type Reset RO 0 RO 1 RO 0 RO 0 RO 0 RO 0 13 RO 1 12 RO 0 11 RO 0 10 reserved RO 0 RO 0 RO 0 RO 0 29 28 27 26 FAM RO 0 9 RO 0 8 RO 1 7 RO 1 6 TEMP RO 0 RO 1 RO 0 RO 0 5 25 24 23 22 21 20 19 18 17 16 PARTNO RO 1 4 PKG RO 1 RO 0 3 RO 1 2 ROHS RO 1 RO RO 0 1 QUAL RO RO 0 0 Bit/Field 31:28 Name VER Type RO Reset 0x1 Description DID1 Version This field defines the DID1 register format version. The version number is numeric. The value of the VER field is encoded as follows (all other encodings are reserved): Value Description 0x1 First revision of the DID1 register format, indicating a Stellaris Fury-class device. 27:24 FAM RO 0x0 Family This field provides the family identification of the device within the Luminary Micro product portfolio. The value is encoded as follows (all other encodings are reserved): Value Description 0x0 Stellaris family of microcontollers, that is, all devices with external part numbers starting with LM3S. 23:16 PARTNO RO 0xD4 Part Number This field provides the part number of the device within the family. The value is encoded as follows (all other encodings are reserved): Value Description 0xD4 LM3S2016 15:13 PINCOUNT RO 0x2 Package Pin Count This field specifies the number of pins on the device package. The value is encoded as follows (all other encodings are reserved): Value Description 0x2 100-pin package 78 Preliminary November 30, 2007 LM3S2016 Microcontroller Bit/Field 12:8 Name reserved Type RO Reset 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Temperature Range This field specifies the temperature rating of the device. The value is encoded as follows (all other encodings are reserved): Value Description 0x1 Industrial temperature range (-40°C to 85°C) 7:5 TEMP RO 0x1 4:3 PKG RO 0x1 Package Type This field specifies the package type. The value is encoded as follows (all other encodings are reserved): Value Description 0x1 LQFP package 2 ROHS RO 1 RoHS-Compliance This bit specifies whether the device is RoHS-compliant. A 1 indicates the part is RoHS-compliant. 1:0 QUAL RO - Qualification Status This field specifies the qualification status of the device. The value is encoded as follows (all other encodings are reserved): Value Description 0x0 0x1 0x2 Engineering Sample (unqualified) Pilot Production (unqualified) Fully Qualified November 30, 2007 Preliminary 79 System Control Register 13: Device Capabilities 0 (DC0), offset 0x008 This register is predefined by the part and can be used to verify features. Device Capabilities 0 (DC0) Base 0x400F.E000 Offset 0x008 Type RO, reset 0x001F.001F 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SRAMSZ Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 1 4 RO 1 3 RO 1 2 RO 1 1 RO 1 0 FLASHSZ Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 1 RO 1 RO 1 RO 1 Bit/Field 31:16 Name SRAMSZ Type RO Reset 0x001F Description SRAM Size Indicates the size of the on-chip SRAM memory. Value Description 0x001F 8 KB of SRAM 15:0 FLASHSZ RO 0x001F Flash Size Indicates the size of the on-chip flash memory. Value Description 0x001F 64 KB of Flash 80 Preliminary November 30, 2007 LM3S2016 Microcontroller Register 14: Device Capabilities 1 (DC1), offset 0x010 This register provides a list of features available in the system. The Stellaris family uses this register format to indicate the availability of the following family features in the specific device: CANs, PWM, ADC, Watchdog timer, Hibernation module, and debug capabilities. This register also indicates the maximum clock frequency and maximum ADC sample rate. The format of this register is consistent with the RCGC0, SCGC0, and DCGC0 clock control registers and the SRCR0 software reset control register. Device Capabilities 1 (DC1) Base 0x400F.E000 Offset 0x010 Type RO, reset 0x0101.329F 31 30 29 28 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 27 26 25 24 CAN0 RO 1 8 RO 0 7 MPU RO 0 RO 1 RO 0 6 reserved RO 0 RO 0 RO 0 5 23 22 21 20 reserved RO 0 4 PLL RO 1 RO 0 3 WDT RO 1 RO 0 2 SWO RO 1 RO 0 1 SWD RO 1 19 18 17 16 ADC RO 1 0 JTAG RO 1 MINSYSDIV Type Reset RO 0 RO 0 RO 1 RO 1 RO 0 MAXADCSPD RO 0 RO 1 Bit/Field 31:25 Name reserved Type RO Reset 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. CAN Module 0 Present When set, indicates that CAN unit 0 is present. 24 CAN0 RO 1 23:17 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. ADC Module Present When set, indicates that the ADC module is present. 16 ADC RO 1 15:12 MINSYSDIV RO 0x3 System Clock Divider Minimum 4-bit divider value for system clock. The reset value is hardware-dependent. See the RCC register for how to change the system clock divisor using the SYSDIV bit. Value Description 0x3 Specifies a 50-MHz CPU clock with a PLL divider of 4. 11:8 MAXADCSPD RO 0x2 Max ADC Speed Indicates the maximum rate at which the ADC samples data. Value Description 0x2 500K samples/second November 30, 2007 Preliminary 81 System Control Bit/Field 7 Name MPU Type RO Reset 1 Description MPU Present When set, indicates that the Cortex-M3 Memory Protection Unit (MPU) module is present. See the ARM Cortex-M3 Technical Reference Manual for details on the MPU. 6:5 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. PLL Present When set, indicates that the on-chip Phase Locked Loop (PLL) is present. 4 PLL RO 1 3 WDT RO 1 Watchdog Timer Present When set, indicates that a watchdog timer is present. 2 SWO RO 1 SWO Trace Port Present When set, indicates that the Serial Wire Output (SWO) trace port is present. 1 SWD RO 1 SWD Present When set, indicates that the Serial Wire Debugger (SWD) is present. 0 JTAG RO 1 JTAG Present When set, indicates that the JTAG debugger interface is present. 82 Preliminary November 30, 2007 LM3S2016 Microcontroller Register 15: Device Capabilities 2 (DC2), offset 0x014 This register provides a list of features available in the system. The Stellaris family uses this register format to indicate the availability of the following family features in the specific device: Analog Comparators, General-Purpose Timers, I2Cs, QEIs, SSIs, and UARTs. The format of this register is consistent with the RCGC1, SCGC1, and DCGC1 clock control registers and the SRCR1 software reset control register. Device Capabilities 2 (DC2) Base 0x400F.E000 Offset 0x014 Type RO, reset 0x0003.1013 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 TIMER1 RO 0 7 RO 0 6 RO 0 5 RO 0 4 SSI0 RO 0 RO 0 RO 0 RO 1 RO 0 3 reserved RO 0 RO 0 RO 0 2 RO 1 1 UART1 RO 1 16 TIMER0 RO 1 0 UART0 RO 1 reserved Type Reset RO 0 15 RO 0 14 reserved Type Reset RO 0 RO 0 RO 0 RO 0 13 RO 0 12 I2C0 RO 1 RO 0 RO 0 RO 0 RO 0 11 RO 0 10 RO 0 9 RO 0 8 reserved RO 0 Bit/Field 31:18 Name reserved Type RO Reset 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Timer 1 Present When set, indicates that General-Purpose Timer module 1 is present. 17 TIMER1 RO 1 16 TIMER0 RO 1 Timer 0 Present When set, indicates that General-Purpose Timer module 0 is present. 15:13 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. I2C Module 0 Present When set, indicates that I2C module 0 is present. 12 I2C0 RO 1 11:5 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SSI0 Present When set, indicates that SSI module 0 is present. 4 SSI0 RO 1 3:2 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. UART1 Present When set, indicates that UART module 1 is present. 1 UART1 RO 1 November 30, 2007 Preliminary 83 System Control Bit/Field 0 Name UART0 Type RO Reset 1 Description UART0 Present When set, indicates that UART module 0 is present. 84 Preliminary November 30, 2007 LM3S2016 Microcontroller Register 16: Device Capabilities 3 (DC3), offset 0x018 This register provides a list of features available in the system. The Stellaris family uses this register format to indicate the availability of the following family features in the specific device: Analog Comparator I/Os, CCP I/Os, ADC I/Os, and PWM I/Os. Device Capabilities 3 (DC3) Base 0x400F.E000 Offset 0x018 Type RO, reset 0x0F0F.0000 31 30 29 28 27 CCP3 RO 0 12 RO 1 11 26 CCP2 RO 1 10 25 CCP1 RO 1 9 24 CCP0 RO 1 8 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 23 22 21 20 19 ADC3 RO 0 4 RO 1 3 18 ADC2 RO 1 2 17 ADC1 RO 1 1 16 ADC0 RO 1 0 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 reserved RO 0 6 RO 0 5 Bit/Field 31:28 Name reserved Type RO Reset 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. CCP3 Pin Present When set, indicates that Capture/Compare/PWM pin 3 is present. 27 CCP3 RO 1 26 CCP2 RO 1 CCP2 Pin Present When set, indicates that Capture/Compare/PWM pin 2 is present. 25 CCP1 RO 1 CCP1 Pin Present When set, indicates that Capture/Compare/PWM pin 1 is present. 24 CCP0 RO 1 CCP0 Pin Present When set, indicates that Capture/Compare/PWM pin 0 is present. 23:20 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. ADC3 Pin Present When set, indicates that ADC pin 3 is present. 19 ADC3 RO 1 18 ADC2 RO 1 ADC2 Pin Present When set, indicates that ADC pin 2 is present. 17 ADC1 RO 1 ADC1 Pin Present When set, indicates that ADC pin 1 is present. 16 ADC0 RO 1 ADC0 Pin Present When set, indicates that ADC pin 0 is present. November 30, 2007 Preliminary 85 System Control Bit/Field 15:0 Name reserved Type RO Reset 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 86 Preliminary November 30, 2007 LM3S2016 Microcontroller Register 17: Device Capabilities 4 (DC4), offset 0x01C This register provides a list of features available in the system. The Stellaris family uses this register format to indicate the availability of the following family features in the specific device: Ethernet MAC and PHY, GPIOs, and CCP I/Os. The format of this register is consistent with the RCGC2, SCGC2, and DCGC2 clock control registers and the SRCR2 software reset control register. Device Capabilities 4 (DC4) Base 0x400F.E000 Offset 0x01C Type RO, reset 0x0000.00FF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 GPIOH RO 0 RO 0 RO 0 RO 1 RO 0 6 GPIOG RO 1 RO 0 5 GPIOF RO 1 RO 0 4 GPIOE RO 1 RO 0 3 GPIOD RO 1 RO 0 2 GPIOC RO 1 RO 0 1 GPIOB RO 1 RO 0 0 GPIOA RO 1 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPIO Port H Present When set, indicates that GPIO Port H is present. 7 GPIOH RO 1 6 GPIOG RO 1 GPIO Port G Present When set, indicates that GPIO Port G is present. 5 GPIOF RO 1 GPIO Port F Present When set, indicates that GPIO Port F is present. 4 GPIOE RO 1 GPIO Port E Present When set, indicates that GPIO Port E is present. 3 GPIOD RO 1 GPIO Port D Present When set, indicates that GPIO Port D is present. 2 GPIOC RO 1 GPIO Port C Present When set, indicates that GPIO Port C is present. 1 GPIOB RO 1 GPIO Port B Present When set, indicates that GPIO Port B is present. 0 GPIOA RO 1 GPIO Port A Present When set, indicates that GPIO Port A is present. November 30, 2007 Preliminary 87 System Control Register 18: Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100 This register controls the clock gating logic. Each bit controls a clock enable for a given interface, function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or units to control. This is to assure reasonable code compatibility with other family and future parts. RCGC0 is the clock configuration register for running operation, SCGC0 for Sleep operation, and DCGC0 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep modes. Run Mode Clock Gating Control Register 0 (RCGC0) Base 0x400F.E000 Offset 0x100 Type R/W, reset 0x00000040 31 30 29 28 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 27 26 25 24 CAN0 R/W 0 8 RO 0 7 RO 0 6 reserved R/W 0 RO 0 RO 0 RO 0 RO 0 RO 0 5 23 22 21 20 reserved RO 0 4 RO 0 3 WDT R/W 0 RO 0 RO 0 2 RO 0 1 reserved RO 0 RO 0 19 18 17 16 ADC R/W 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 R/W 0 MAXADCSPD R/W 0 R/W 0 Bit/Field 31:25 Name reserved Type RO Reset 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. CAN0 Clock Gating Control This bit controls the clock gating for CAN unit 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. 24 CAN0 R/W 0 23:17 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. ADC0 Clock Gating Control This bit controls the clock gating for SAR ADC module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, a read or write to the unit generates a bus fault. 16 ADC R/W 0 15:12 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 88 Preliminary November 30, 2007 LM3S2016 Microcontroller Bit/Field 11:8 Name MAXADCSPD Type R/W Reset 0 Description ADC Sample Speed This field sets the rate at which the ADC samples data. You cannot set the rate higher than the maximum rate. You can set the sample rate by setting the MAXADCSPD bit as follows: Value Description 0x2 0x1 0x0 500K samples/second 250K samples/second 125K samples/second 7:4 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. WDT Clock Gating Control This bit controls the clock gating for the WDT module. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, a read or write to the unit generates a bus fault. 3 WDT R/W 0 2:0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. November 30, 2007 Preliminary 89 System Control Register 19: Sleep Mode Clock Gating Control Register 0 (SCGC0), offset 0x110 This register controls the clock gating logic. Each bit controls a clock enable for a given interface, function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or units to control. This is to assure reasonable code compatibility with other family and future parts. RCGC0 is the clock configuration register for running operation, SCGC0 for Sleep operation, and DCGC0 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep modes. Sleep Mode Clock Gating Control Register 0 (SCGC0) Base 0x400F.E000 Offset 0x110 Type R/W, reset 0x00000040 31 30 29 28 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 27 26 25 24 CAN0 R/W 0 8 RO 0 7 RO 0 6 reserved R/W 0 RO 0 RO 0 RO 0 RO 0 RO 0 5 23 22 21 20 reserved RO 0 4 RO 0 3 WDT R/W 0 RO 0 RO 0 2 RO 0 1 reserved RO 0 RO 0 19 18 17 16 ADC R/W 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 R/W 0 MAXADCSPD R/W 0 R/W 0 Bit/Field 31:25 Name reserved Type RO Reset 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. CAN0 Clock Gating Control This bit controls the clock gating for CAN unit 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. 24 CAN0 R/W 0 23:17 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. ADC0 Clock Gating Control This bit controls the clock gating for SAR ADC module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, a read or write to the unit generates a bus fault. 16 ADC R/W 0 15:12 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 90 Preliminary November 30, 2007 LM3S2016 Microcontroller Bit/Field 11:8 Name MAXADCSPD Type R/W Reset 0 Description ADC Sample Speed This field sets the rate at which the ADC samples data. You cannot set the rate higher than the maximum rate. You can set the sample rate by setting the MAXADCSPD bit as follows: Value Description 0x2 0x1 0x0 500K samples/second 250K samples/second 125K samples/second 7:4 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. WDT Clock Gating Control This bit controls the clock gating for the WDT module. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, a read or write to the unit generates a bus fault. 3 WDT R/W 0 2:0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. November 30, 2007 Preliminary 91 System Control Register 20: Deep Sleep Mode Clock Gating Control Register 0 (DCGC0), offset 0x120 This register controls the clock gating logic. Each bit controls a clock enable for a given interface, function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or units to control. This is to assure reasonable code compatibility with other family and future parts. RCGC0 is the clock configuration register for running operation, SCGC0 for Sleep operation, and DCGC0 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep modes. Deep Sleep Mode Clock Gating Control Register 0 (DCGC0) Base 0x400F.E000 Offset 0x120 Type R/W, reset 0x00000040 31 30 29 28 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 27 26 25 24 CAN0 R/W 0 8 RO 0 7 RO 0 6 reserved R/W 0 RO 0 RO 0 RO 0 RO 0 RO 0 5 23 22 21 20 reserved RO 0 4 RO 0 3 WDT R/W 0 RO 0 RO 0 2 RO 0 1 reserved RO 0 RO 0 19 18 17 16 ADC R/W 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 R/W 0 MAXADCSPD R/W 0 R/W 0 Bit/Field 31:25 Name reserved Type RO Reset 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. CAN0 Clock Gating Control This bit controls the clock gating for CAN unit 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. 24 CAN0 R/W 0 23:17 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. ADC0 Clock Gating Control This bit controls the clock gating for SAR ADC module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, a read or write to the unit generates a bus fault. 16 ADC R/W 0 15:12 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 92 Preliminary November 30, 2007 LM3S2016 Microcontroller Bit/Field 11:8 Name MAXADCSPD Type R/W Reset 0 Description ADC Sample Speed This field sets the rate at which the ADC samples data. You cannot set the rate higher than the maximum rate. You can set the sample rate by setting the MAXADCSPD bit as follows: Value Description 0x2 0x1 0x0 500K samples/second 250K samples/second 125K samples/second 7:4 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. WDT Clock Gating Control This bit controls the clock gating for the WDT module. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, a read or write to the unit generates a bus fault. 3 WDT R/W 0 2:0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. November 30, 2007 Preliminary 93 System Control Register 21: Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104 This register controls the clock gating logic. Each bit controls a clock enable for a given interface, function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or units to control. This is to assure reasonable code compatibility with other family and future parts. RCGC1 is the clock configuration register for running operation, SCGC1 for Sleep operation, and DCGC1 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep modes. Run Mode Clock Gating Control Register 1 (RCGC1) Base 0x400F.E000 Offset 0x104 Type R/W, reset 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 TIMER1 RO 0 7 RO 0 6 RO 0 5 RO 0 4 SSI0 RO 0 RO 0 RO 0 R/W 0 RO 0 3 reserved RO 0 RO 0 RO 0 2 R/W 0 1 UART1 R/W 0 16 TIMER0 R/W 0 0 UART0 R/W 0 reserved Type Reset RO 0 15 RO 0 14 reserved Type Reset RO 0 RO 0 RO 0 RO 0 13 RO 0 12 I2C0 R/W 0 RO 0 RO 0 RO 0 RO 0 11 RO 0 10 RO 0 9 RO 0 8 reserved RO 0 Bit/Field 31:18 Name reserved Type RO Reset 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Timer 1 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 1. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 17 TIMER1 R/W 0 16 TIMER0 R/W 0 Timer 0 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 15:13 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. I2C0 Clock Gating Control This bit controls the clock gating for I2C module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 12 I2C0 R/W 0 11:5 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 94 Preliminary November 30, 2007 LM3S2016 Microcontroller Bit/Field 4 Name SSI0 Type R/W Reset 0 Description SSI0 Clock Gating Control This bit controls the clock gating for SSI module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 3:2 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. UART1 Clock Gating Control This bit controls the clock gating for UART module 1. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 1 UART1 R/W 0 0 UART0 R/W 0 UART0 Clock Gating Control This bit controls the clock gating for UART module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. November 30, 2007 Preliminary 95 System Control Register 22: Sleep Mode Clock Gating Control Register 1 (SCGC1), offset 0x114 This register controls the clock gating logic. Each bit controls a clock enable for a given interface, function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or units to control. This is to assure reasonable code compatibility with other family and future parts. RCGC1 is the clock configuration register for running operation, SCGC1 for Sleep operation, and DCGC1 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep modes. Sleep Mode Clock Gating Control Register 1 (SCGC1) Base 0x400F.E000 Offset 0x114 Type R/W, reset 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 TIMER1 RO 0 7 RO 0 6 RO 0 5 RO 0 4 SSI0 RO 0 RO 0 RO 0 R/W 0 RO 0 3 reserved RO 0 RO 0 RO 0 2 R/W 0 1 UART1 R/W 0 16 TIMER0 R/W 0 0 UART0 R/W 0 reserved Type Reset RO 0 15 RO 0 14 reserved Type Reset RO 0 RO 0 RO 0 RO 0 13 RO 0 12 I2C0 R/W 0 RO 0 RO 0 RO 0 RO 0 11 RO 0 10 RO 0 9 RO 0 8 reserved RO 0 Bit/Field 31:18 Name reserved Type RO Reset 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Timer 1 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 1. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 17 TIMER1 R/W 0 16 TIMER0 R/W 0 Timer 0 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 15:13 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. I2C0 Clock Gating Control This bit controls the clock gating for I2C module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 12 I2C0 R/W 0 96 Preliminary November 30, 2007 LM3S2016 Microcontroller Bit/Field 11:5 Name reserved Type RO Reset 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SSI0 Clock Gating Control This bit controls the clock gating for SSI module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 4 SSI0 R/W 0 3:2 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. UART1 Clock Gating Control This bit controls the clock gating for UART module 1. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 1 UART1 R/W 0 0 UART0 R/W 0 UART0 Clock Gating Control This bit controls the clock gating for UART module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. November 30, 2007 Preliminary 97 System Control Register 23: Deep Sleep Mode Clock Gating Control Register 1 (DCGC1), offset 0x124 This register controls the clock gating logic. Each bit controls a clock enable for a given interface, function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or units to control. This is to assure reasonable code compatibility with other family and future parts. RCGC1 is the clock configuration register for running operation, SCGC1 for Sleep operation, and DCGC1 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep modes. Deep Sleep Mode Clock Gating Control Register 1 (DCGC1) Base 0x400F.E000 Offset 0x124 Type R/W, reset 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 TIMER1 RO 0 7 RO 0 6 RO 0 5 RO 0 4 SSI0 RO 0 RO 0 RO 0 R/W 0 RO 0 3 reserved RO 0 RO 0 RO 0 2 R/W 0 1 UART1 R/W 0 16 TIMER0 R/W 0 0 UART0 R/W 0 reserved Type Reset RO 0 15 RO 0 14 reserved Type Reset RO 0 RO 0 RO 0 RO 0 13 RO 0 12 I2C0 R/W 0 RO 0 RO 0 RO 0 RO 0 11 RO 0 10 RO 0 9 RO 0 8 reserved RO 0 Bit/Field 31:18 Name reserved Type RO Reset 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Timer 1 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 1. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 17 TIMER1 R/W 0 16 TIMER0 R/W 0 Timer 0 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 15:13 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. I2C0 Clock Gating Control This bit controls the clock gating for I2C module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 12 I2C0 R/W 0 98 Preliminary November 30, 2007 LM3S2016 Microcontroller Bit/Field 11:5 Name reserved Type RO Reset 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SSI0 Clock Gating Control This bit controls the clock gating for SSI module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 4 SSI0 R/W 0 3:2 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. UART1 Clock Gating Control This bit controls the clock gating for UART module 1. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 1 UART1 R/W 0 0 UART0 R/W 0 UART0 Clock Gating Control This bit controls the clock gating for UART module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. November 30, 2007 Preliminary 99 System Control Register 24: Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108 This register controls the clock gating logic. Each bit controls a clock enable for a given interface, function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or units to control. This is to assure reasonable code compatibility with other family and future parts. RCGC2 is the clock configuration register for running operation, SCGC2 for Sleep operation, and DCGC2 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep modes. Run Mode Clock Gating Control Register 2 (RCGC2) Base 0x400F.E000 Offset 0x108 Type R/W, reset 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 GPIOH RO 0 RO 0 RO 0 R/W 0 RO 0 6 GPIOG R/W 0 RO 0 5 GPIOF R/W 0 RO 0 4 GPIOE R/W 0 RO 0 3 GPIOD R/W 0 RO 0 2 GPIOC R/W 0 RO 0 1 GPIOB R/W 0 RO 0 0 GPIOA R/W 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Port H Clock Gating Control This bit controls the clock gating for Port H. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 7 GPIOH R/W 0 6 GPIOG R/W 0 Port G Clock Gating Control This bit controls the clock gating for Port G. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 5 GPIOF R/W 0 Port F Clock Gating Control This bit controls the clock gating for Port F. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 4 GPIOE R/W 0 Port E Clock Gating Control This bit controls the clock gating for Port E. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 100 Preliminary November 30, 2007 LM3S2016 Microcontroller Bit/Field 3 Name GPIOD Type R/W Reset 0 Description Port D Clock Gating Control This bit controls the clock gating for Port D. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 2 GPIOC R/W 0 Port C Clock Gating Control This bit controls the clock gating for Port C. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 1 GPIOB R/W 0 Port B Clock Gating Control This bit controls the clock gating for Port B. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 GPIOA R/W 0 Port A Clock Gating Control This bit controls the clock gating for Port A. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. November 30, 2007 Preliminary 101 System Control Register 25: Sleep Mode Clock Gating Control Register 2 (SCGC2), offset 0x118 This register controls the clock gating logic. Each bit controls a clock enable for a given interface, function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or units to control. This is to assure reasonable code compatibility with other family and future parts. RCGC2 is the clock configuration register for running operation, SCGC2 for Sleep operation, and DCGC2 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep modes. Sleep Mode Clock Gating Control Register 2 (SCGC2) Base 0x400F.E000 Offset 0x118 Type R/W, reset 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 GPIOH RO 0 RO 0 RO 0 R/W 0 RO 0 6 GPIOG R/W 0 RO 0 5 GPIOF R/W 0 RO 0 4 GPIOE R/W 0 RO 0 3 GPIOD R/W 0 RO 0 2 GPIOC R/W 0 RO 0 1 GPIOB R/W 0 RO 0 0 GPIOA R/W 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Port H Clock Gating Control This bit controls the clock gating for Port H. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 7 GPIOH R/W 0 6 GPIOG R/W 0 Port G Clock Gating Control This bit controls the clock gating for Port G. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 5 GPIOF R/W 0 Port F Clock Gating Control This bit controls the clock gating for Port F. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 4 GPIOE R/W 0 Port E Clock Gating Control This bit controls the clock gating for Port E. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 102 Preliminary November 30, 2007 LM3S2016 Microcontroller Bit/Field 3 Name GPIOD Type R/W Reset 0 Description Port D Clock Gating Control This bit controls the clock gating for Port D. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 2 GPIOC R/W 0 Port C Clock Gating Control This bit controls the clock gating for Port C. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 1 GPIOB R/W 0 Port B Clock Gating Control This bit controls the clock gating for Port B. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 GPIOA R/W 0 Port A Clock Gating Control This bit controls the clock gating for Port A. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. November 30, 2007 Preliminary 103 System Control Register 26: Deep Sleep Mode Clock Gating Control Register 2 (DCGC2), offset 0x128 This register controls the clock gating logic. Each bit controls a clock enable for a given interface, function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or units to control. This is to assure reasonable code compatibility with other family and future parts. RCGC2 is the clock configuration register for running operation, SCGC2 for Sleep operation, and DCGC2 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep modes. Deep Sleep Mode Clock Gating Control Register 2 (DCGC2) Base 0x400F.E000 Offset 0x128 Type R/W, reset 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 GPIOH RO 0 RO 0 RO 0 R/W 0 RO 0 6 GPIOG R/W 0 RO 0 5 GPIOF R/W 0 RO 0 4 GPIOE R/W 0 RO 0 3 GPIOD R/W 0 RO 0 2 GPIOC R/W 0 RO 0 1 GPIOB R/W 0 RO 0 0 GPIOA R/W 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Port H Clock Gating Control This bit controls the clock gating for Port H. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 7 GPIOH R/W 0 6 GPIOG R/W 0 Port G Clock Gating Control This bit controls the clock gating for Port G. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 5 GPIOF R/W 0 Port F Clock Gating Control This bit controls the clock gating for Port F. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 4 GPIOE R/W 0 Port E Clock Gating Control This bit controls the clock gating for Port E. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 104 Preliminary November 30, 2007 LM3S2016 Microcontroller Bit/Field 3 Name GPIOD Type R/W Reset 0 Description Port D Clock Gating Control This bit controls the clock gating for Port D. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 2 GPIOC R/W 0 Port C Clock Gating Control This bit controls the clock gating for Port C. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 1 GPIOB R/W 0 Port B Clock Gating Control This bit controls the clock gating for Port B. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 GPIOA R/W 0 Port A Clock Gating Control This bit controls the clock gating for Port A. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. November 30, 2007 Preliminary 105 System Control Register 27: Software Reset Control 0 (SRCR0), offset 0x040 Writes to this register are masked by the bits in the Device Capabilities 1 (DC1) register. Software Reset Control 0 (SRCR0) Base 0x400F.E000 Offset 0x040 Type R/W, reset 0x00000000 31 30 29 28 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 9 27 26 25 24 CAN0 R/W 0 8 RO 0 7 RO 0 6 RO 0 5 23 22 21 20 reserved RO 0 4 RO 0 3 WDT R/W 0 RO 0 RO 0 2 RO 0 1 reserved RO 0 RO 0 19 18 17 16 ADC R/W 0 0 Bit/Field 31:25 Name reserved Type RO Reset 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. CAN0 Reset Control Reset control for CAN unit 0. 24 CAN0 R/W 0 23:17 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. ADC0 Reset Control Reset control for SAR ADC module 0. 16 ADC R/W 0 15:4 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. WDT Reset Control Reset control for Watchdog unit. 3 WDT R/W 0 2:0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 106 Preliminary November 30, 2007 LM3S2016 Microcontroller Register 28: Software Reset Control 1 (SRCR1), offset 0x044 Writes to this register are masked by the bits in the Device Capabilities 2 (DC2) register. Software Reset Control 1 (SRCR1) Base 0x400F.E000 Offset 0x044 Type R/W, reset 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 TIMER1 RO 0 7 RO 0 6 RO 0 5 RO 0 4 SSI0 RO 0 RO 0 RO 0 R/W 0 RO 0 3 reserved RO 0 RO 0 RO 0 2 R/W 0 1 UART1 R/W 0 16 TIMER0 R/W 0 0 UART0 R/W 0 reserved Type Reset RO 0 15 RO 0 14 reserved Type Reset RO 0 RO 0 RO 0 RO 0 13 RO 0 12 I2C0 R/W 0 RO 0 RO 0 RO 0 RO 0 11 RO 0 10 RO 0 9 RO 0 8 reserved RO 0 Bit/Field 31:18 Name reserved Type RO Reset 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Timer 1 Reset Control Reset control for General-Purpose Timer module 1. 17 TIMER1 R/W 0 16 TIMER0 R/W 0 Timer 0 Reset Control Reset control for General-Purpose Timer module 0. 15:13 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. I2C0 Reset Control Reset control for I2C unit 0. 12 I2C0 R/W 0 11:5 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SSI0 Reset Control Reset control for SSI unit 0. 4 SSI0 R/W 0 3:2 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. UART1 Reset Control Reset control for UART unit 1. 1 UART1 R/W 0 0 UART0 R/W 0 UART0 Reset Control Reset control for UART unit 0. November 30, 2007 Preliminary 107 System Control Register 29: Software Reset Control 2 (SRCR2), offset 0x048 Writes to this register are masked by the bits in the Device Capabilities 4 (DC4) register. Software Reset Control 2 (SRCR2) Base 0x400F.E000 Offset 0x048 Type R/W, reset 0x00000000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 GPIOH RO 0 RO 0 RO 0 R/W 0 RO 0 6 GPIOG R/W 0 RO 0 5 GPIOF R/W 0 RO 0 4 GPIOE R/W 0 RO 0 3 GPIOD R/W 0 RO 0 2 GPIOC R/W 0 RO 0 1 GPIOB R/W 0 RO 0 0 GPIOA R/W 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Port H Reset Control Reset control for GPIO Port H. 7 GPIOH R/W 0 6 GPIOG R/W 0 Port G Reset Control Reset control for GPIO Port G. 5 GPIOF R/W 0 Port F Reset Control Reset control for GPIO Port F. 4 GPIOE R/W 0 Port E Reset Control Reset control for GPIO Port E. 3 GPIOD R/W 0 Port D Reset Control Reset control for GPIO Port D. 2 GPIOC R/W 0 Port C Reset Control Reset control for GPIO Port C. 1 GPIOB R/W 0 Port B Reset Control Reset control for GPIO Port B. 0 GPIOA R/W 0 Port A Reset Control Reset control for GPIO Port A. 108 Preliminary November 30, 2007 LM3S2016 Microcontroller 7 Internal Memory The LM3S2016 microcontroller comes with 8 KB of bit-banded SRAM and 64 KB of flash memory. The flash controller provides a user-friendly interface, making flash programming a simple task. Flash protection can be applied to the flash memory on a 2-KB block basis. 7.1 Block Diagram Figure 7-1. Flash Block Diagram Flash Timing USECRL Flash Control ICode Cortex-M3 DCode FMA FMD FMC System Bus FCRIS FCIM FCMISC Bridge APB Flash Array Flash Protection FMPREn SRAM Array FMPPEn User Registers USER_DBG USER_REG0 USER_REG1 7.2 7.2.1 Functional Description This section describes the functionality of both the flash and SRAM memories. SRAM Memory The internal SRAM of the Stellaris devices is located at address 0x2000.0000 of the device memory map. To reduce the number of time consuming read-modify-write (RMW) operations, ARM has introduced bit-banding technology in the Cortex-M3 processor. With a bit-band-enabled processor, certain regions in the memory map (SRAM and peripheral space) can use address aliases to access individual bits in a single, atomic operation. The bit-band alias is calculated by using the formula: ® November 30, 2007 Preliminary 109 Internal Memory bit-band alias = bit-band base + (byte offset * 32) + (bit number * 4) For example, if bit 3 at address 0x2000.1000 is to be modified, the bit-band alias is calculated as: 0x2200.0000 + (0x1000 * 32) + (3 * 4) = 0x2202.000C With the alias address calculated, an instruction performing a read/write to address 0x2202.000C allows direct access to only bit 3 of the byte at address 0x2000.1000. For details about bit-banding, please refer to Chapter 4, “Memory Map” in the ARM® Cortex™-M3 Technical Reference Manual. 7.2.2 Flash Memory The flash is organized as a set of 1-KB blocks that can be individually erased. Erasing a block causes the entire contents of the block to be reset to all 1s. An individual 32-bit word can be programmed to change bits that are currently 1 to a 0. These blocks are paired into a set of 2-KB blocks that can be individually protected. The protection allows blocks to be marked as read-only or execute-only, providing different levels of code protection. Read-only blocks cannot be erased or programmed, protecting the contents of those blocks from being modified. Execute-only blocks cannot be erased or programmed, and can only be read by the controller instruction fetch mechanism, protecting the contents of those blocks from being read by either the controller or by a debugger. See also “Serial Flash Loader” on page 446 for a preprogrammed flash-resident utility used to download code to the flash memory of a device without the use of a debug interface. 7.2.2.1 Flash Memory Timing The timing for the flash is automatically handled by the flash controller. However, in order to do so, it must know the clock rate of the system in order to time its internal signals properly. The number of clock cycles per microsecond must be provided to the flash controller for it to accomplish this timing. It is software's responsibility to keep the flash controller updated with this information via the USec Reload (USECRL) register. On reset, the USECRL register is loaded with a value that configures the flash timing so that it works with the maximum clock rate of the part. If software changes the system operating frequency, the new operating frequency minus 1 (in MHz) must be loaded into USECRL before any flash modifications are attempted. For example, if the device is operating at a speed of 20 MHz, a value of 0x13 (20-1) must be written to the USECRL register. 7.2.2.2 Flash Memory Protection The user is provided two forms of flash protection per 2-KB flash blocks in one pair of 32-bit wide registers. The protection policy for each form is controlled by individual bits (per policy per block) in the FMPPEn and FMPREn registers. ■ Flash Memory Protection Program Enable (FMPPEn): If set, the block may be programmed (written) or erased. If cleared, the block may not be changed. ■ Flash Memory Protection Read Enable (FMPREn): If set, the block may be executed or read by software or debuggers. If cleared, the block may only be executed. The contents of the memory block are prohibited from being accessed as data and traversing the DCode bus. The policies may be combined as shown in Table 7-1 on page 111. 110 Preliminary November 30, 2007 LM3S2016 Microcontroller Table 7-1. Flash Protection Policy Combinations FMPPEn FMPREn Protection 0 1 0 1 0 0 1 1 Execute-only protection. The block may only be executed and may not be written or erased. This mode is used to protect code. The block may be written, erased or executed, but not read. This combination is unlikely to be used. Read-only protection. The block may be read or executed but may not be written or erased. This mode is used to lock the block from further modification while allowing any read or execute access. No protection. The block may be written, erased, executed or read. An access that attempts to program or erase a PE-protected block is prohibited. A controller interrupt may be optionally generated (by setting the AMASK bit in the FIM register) to alert software developers of poorly behaving software during the development and debug phases. An access that attempts to read an RE-protected block is prohibited. Such accesses return data filled with all 0s. A controller interrupt may be optionally generated to alert software developers of poorly behaving software during the development and debug phases. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This implements a policy of open access and programmability. The register bits may be changed by writing the specific register bit. The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. Details on programming these bits are discussed in “Nonvolatile Register Programming” on page 112. 7.3 7.3.1 Flash Memory Initialization and Configuration Flash Programming The Stellaris devices provide a user-friendly interface for flash programming. All erase/program operations are handled via three registers: FMA, FMD, and FMC. ® 7.3.1.1 To program a 32-bit word 1. Write source data to the FMD register. 2. Write the target address to the FMA register. 3. Write the flash write key and the WRITE bit (a value of 0xA442.0001) to the FMC register. 4. Poll the FMC register until the WRITE bit is cleared. 7.3.1.2 To perform an erase of a 1-KB page 1. Write the page address to the FMA register. 2. Write the flash write key and the ERASE bit (a value of 0xA442.0002) to the FMC register. 3. Poll the FMC register until the ERASE bit is cleared. 7.3.1.3 To perform a mass erase of the flash 1. Write the flash write key and the MERASE bit (a value of 0xA442.0004) to the FMC register. 2. Poll the FMC register until the MERASE bit is cleared. November 30, 2007 Preliminary 111 Internal Memory 7.3.2 Nonvolatile Register Programming This section discusses how to update registers that are resident within the flash memory itself. These registers exist in a separate space from the main flash array and are not affected by an ERASE or MASS ERASE operation. These nonvolatile registers are updated by using the COMT bit in the FMC register to activate a write operation. For the USER_DBG register, the data to be written must be loaded into the FMD register before it is "committed". All other registers are R/W and can have their operation tried before committing them to nonvolatile memory. Important: These registers can only have bits changed from 1 to 0 by the user and there is no mechanism for the user to erase them back to a 1 value. In addition, the USER_REG0, USER_REG1, and USER_DBG use bit 31 (NW) of their respective registers to indicate that they are available for user write. These three registers can only be written once whereas the flash protection registers may be written multiple times. Table 7-2 on page 112 provides the FMA address required for commitment of each of the registers and the source of the data to be written when the COMT bit of the FMC register is written with a value of 0xA442.0008. After writing the COMT bit, the user may poll the FMC register to wait for the commit operation to complete. Table 7-2. Flash Resident Registers Register to be Committed FMA Value FMPRE0 FMPRE1 FMPRE2 FMPRE3 FMPPE0 FMPPE1 FMPPE2 FMPPE3 USER_REG0 USER_REG1 USER_DBG a Data Source 0x0000.0000 FMPRE0 0x0000.0002 FMPRE1 0x0000.0004 FMPRE2 0x0000.0008 FMPRE3 0x0000.0001 FMPPE0 0x0000.0003 FMPPE1 0x0000.0005 FMPPE2 0x0000.0007 FMPPE3 0x8000.0000 USER_REG0 0x8000.0001 USER_REG1 0x7510.0000 FMD ® a. Which FMPREn and FMPPEn registers are available depend on the flash size of your particular Stellaris device. 7.4 Register Map Table 7-3 on page 112 lists the Flash memory and control registers. The offset listed is a hexadecimal increment to the register's address. The FMA, FMD, FMC, FCRIS, FCIM, and FCMISC registers are relative to the Flash control base address of 0x400F.D000. The FMPREn, FMPPEn, USECRL, USER_DBG, and USER_REGn registers are relative to the System Control base address of 0x400F.E000. Table 7-3. Flash Register Map Offset Name Type Reset Description See page Flash Control Offset 0x000 FMA R/W 0x0000.0000 Flash Memory Address 114 112 Preliminary November 30, 2007 LM3S2016 Microcontroller Offset 0x004 0x008 0x00C 0x010 0x014 Name FMD FMC FCRIS FCIM FCMISC Type R/W R/W RO R/W R/W1C Reset 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 Description Flash Memory Data Flash Memory Control Flash Controller Raw Interrupt Status Flash Controller Interrupt Mask Flash Controller Masked Interrupt Status and Clear See page 115 116 118 119 120 System Control Offset 0x130 0x200 0x134 0x400 0x140 0x1D0 0x1E0 0x1E4 0x204 0x208 0x20C 0x404 0x408 0x40C FMPRE0 FMPRE0 FMPPE0 FMPPE0 USECRL USER_DBG USER_REG0 USER_REG1 FMPRE1 FMPRE2 FMPRE3 FMPPE1 FMPPE2 FMPPE3 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0xFFFF.FFFF 0xFFFF.FFFF 0xFFFF.FFFF 0xFFFF.FFFF 0x31 0xFFFF.FFFE 0xFFFF.FFFF 0xFFFF.FFFF 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 Flash Memory Protection Read Enable 0 Flash Memory Protection Read Enable 0 Flash Memory Protection Program Enable 0 Flash Memory Protection Program Enable 0 USec Reload User Debug User Register 0 User Register 1 Flash Memory Protection Read Enable 1 Flash Memory Protection Read Enable 2 Flash Memory Protection Read Enable 3 Flash Memory Protection Program Enable 1 Flash Memory Protection Program Enable 2 Flash Memory Protection Program Enable 3 122 122 123 123 121 124 125 126 127 128 129 130 131 132 7.5 Flash Register Descriptions (Flash Control Offset) The remainder of this section lists and describes the Flash Memory registers, in numerical order by address offset. Registers in this section are relative to the Flash control base address of 0x400F.D000. November 30, 2007 Preliminary 113 Internal Memory Register 1: Flash Memory Address (FMA), offset 0x000 During a write operation, this register contains a 4-byte-aligned address and specifies where the data is written. During erase operations, this register contains a 1 KB-aligned address and specifies which page is erased. Note that the alignment requirements must be met by software or the results of the operation are unpredictable. Flash Memory Address (FMA) Base 0x400F.D000 Offset 0x000 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 OFFSET Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 Bit/Field 31:16 Name reserved Type RO Reset 0x0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Address Offset Address offset in flash where operation is performed, except for nonvolatile registers (see “Nonvolatile Register Programming” on page 112 for details on values for this field). 15:0 OFFSET R/W 0x0 114 Preliminary November 30, 2007 LM3S2016 Microcontroller Register 2: Flash Memory Data (FMD), offset 0x004 This register contains the data to be written during the programming cycle or read during the read cycle. Note that the contents of this register are undefined for a read access of an execute-only block. This register is not used during the erase cycles. Flash Memory Data (FMD) Base 0x400F.D000 Offset 0x004 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 DATA Type Reset R/W 0 15 R/W 0 14 R/W 0 13 R/W 0 12 R/W 0 11 R/W 0 10 R/W 0 9 R/W 0 8 DATA Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 23 22 21 20 19 18 17 16 Bit/Field 31:0 Name DATA Type R/W Reset 0x0 Description Data Value Data value for write operation. November 30, 2007 Preliminary 115 Internal Memory Register 3: Flash Memory Control (FMC), offset 0x008 When this register is written, the flash controller initiates the appropriate access cycle for the location specified by the Flash Memory Address (FMA) register (see page 114). If the access is a write access, the data contained in the Flash Memory Data (FMD) register (see page 115) is written. This is the final register written and initiates the memory operation. There are four control bits in the lower byte of this register that, when set, initiate the memory operation. The most used of these register bits are the ERASE and WRITE bits. It is a programming error to write multiple control bits and the results of such an operation are unpredictable. Flash Memory Control (FMC) Base 0x400F.D000 Offset 0x008 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 WRKEY Type Reset WO 0 15 WO 0 14 WO 0 13 WO 0 12 WO 0 11 WO 0 10 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 WO 0 9 WO 0 8 WO 0 7 WO 0 6 WO 0 5 WO 0 4 WO 0 3 COMT R/W 0 WO 0 2 WO 0 1 WO 0 0 WRITE R/W 0 MERASE ERASE R/W 0 R/W 0 Bit/Field 31:16 Name WRKEY Type WO Reset 0x0 Description Flash Write Key This field contains a write key, which is used to minimize the incidence of accidental flash writes. The value 0xA442 must be written into this field for a write to occur. Writes to the FMC register without this WRKEY value are ignored. A read of this field returns the value 0. 15:4 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Commit Register Value Commit (write) of register value to nonvolatile storage. A write of 0 has no effect on the state of this bit. If read, the state of the previous commit access is provided. If the previous commit access is complete, a 0 is returned; otherwise, if the commit access is not complete, a 1 is returned. This can take up to 50 μs. 3 COMT R/W 0 2 MERASE R/W 0 Mass Erase Flash Memory If this bit is set, the flash main memory of the device is all erased. A write of 0 has no effect on the state of this bit. If read, the state of the previous mass erase access is provided. If the previous mass erase access is complete, a 0 is returned; otherwise, if the previous mass erase access is not complete, a 1 is returned. This can take up to 250 ms. 116 Preliminary November 30, 2007 LM3S2016 Microcontroller Bit/Field 1 Name ERASE Type R/W Reset 0 Description Erase a Page of Flash Memory If this bit is set, the page of flash main memory as specified by the contents of FMA is erased. A write of 0 has no effect on the state of this bit. If read, the state of the previous erase access is provided. If the previous erase access is complete, a 0 is returned; otherwise, if the previous erase access is not complete, a 1 is returned. This can take up to 25 ms. 0 WRITE R/W 0 Write a Word into Flash Memory If this bit is set, the data stored in FMD is written into the location as specified by the contents of FMA. A write of 0 has no effect on the state of this bit. If read, the state of the previous write update is provided. If the previous write access is complete, a 0 is returned; otherwise, if the write access is not complete, a 1 is returned. This can take up to 50 µs. November 30, 2007 Preliminary 117 Internal Memory Register 4: Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C This register indicates that the flash controller has an interrupt condition. An interrupt is only signaled if the corresponding FCIM register bit is set. Flash Controller Raw Interrupt Status (FCRIS) Base 0x400F.D000 Offset 0x00C Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 PRIS RO 0 RO 0 0 ARIS RO 0 Bit/Field 31:2 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Programming Raw Interrupt Status This bit indicates the current state of the programming cycle. If set, the programming cycle completed; if cleared, the programming cycle has not completed. Programming cycles are either write or erase actions generated through the Flash Memory Control (FMC) register bits (see page 116). 1 PRIS RO 0 0 ARIS RO 0 Access Raw Interrupt Status This bit indicates if the flash was improperly accessed. If set, the program tried to access the flash counter to the policy as set in the Flash Memory Protection Read Enable (FMPREn) and Flash Memory Protection Program Enable (FMPPEn) registers. Otherwise, no access has tried to improperly access the flash. 118 Preliminary November 30, 2007 LM3S2016 Microcontroller Register 5: Flash Controller Interrupt Mask (FCIM), offset 0x010 This register controls whether the flash controller generates interrupts to the controller. Flash Controller Interrupt Mask (FCIM) Base 0x400F.D000 Offset 0x010 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 PMASK R/W 0 RO 0 0 AMASK R/W 0 Bit/Field 31:2 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Programming Interrupt Mask This bit controls the reporting of the programming raw interrupt status to the controller. If set, a programming-generated interrupt is promoted to the controller. Otherwise, interrupts are recorded but suppressed from the controller. 1 PMASK R/W 0 0 AMASK R/W 0 Access Interrupt Mask This bit controls the reporting of the access raw interrupt status to the controller. If set, an access-generated interrupt is promoted to the controller. Otherwise, interrupts are recorded but suppressed from the controller. November 30, 2007 Preliminary 119 Internal Memory Register 6: Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014 This register provides two functions. First, it reports the cause of an interrupt by indicating which interrupt source or sources are signalling the interrupt. Second, it serves as the method to clear the interrupt reporting. Flash Controller Masked Interrupt Status and Clear (FCMISC) Base 0x400F.D000 Offset 0x014 Type R/W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 PMISC R/W1C 0 RO 0 0 AMISC R/W1C 0 Bit/Field 31:2 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Programming Masked Interrupt Status and Clear This bit indicates whether an interrupt was signaled because a programming cycle completed and was not masked. This bit is cleared by writing a 1. The PRIS bit in the FCRIS register (see page 118) is also cleared when the PMISC bit is cleared. 1 PMISC R/W1C 0 0 AMISC R/W1C 0 Access Masked Interrupt Status and Clear This bit indicates whether an interrupt was signaled because an improper access was attempted and was not masked. This bit is cleared by writing a 1. The ARIS bit in the FCRIS register is also cleared when the AMISC bit is cleared. 7.6 Flash Register Descriptions (System Control Offset) The remainder of this section lists and describes the Flash Memory registers, in numerical order by address offset. Registers in this section are relative to the System Control base address of 0x400F.E000. 120 Preliminary November 30, 2007 LM3S2016 Microcontroller Register 7: USec Reload (USECRL), offset 0x140 Note: Offset is relative to System Control base address of 0x400F.E000 This register is provided as a means of creating a 1-μs tick divider reload value for the flash controller. The internal flash has specific minimum and maximum requirements on the length of time the high voltage write pulse can be applied. It is required that this register contain the operating frequency (in MHz -1) whenever the flash is being erased or programmed. The user is required to change this value if the clocking conditions are changed for a flash erase/program operation. USec Reload (USECRL) Base 0x400F.E000 Offset 0x140 Type R/W, reset 0x31 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 USEC RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 1 R/W 1 R/W 0 R/W 0 R/W 0 R/W 1 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Microsecond Reload Value MHz -1 of the controller clock when the flash is being erased or programmed. USEC should be set to 0x31 (50 MHz) whenever the flash is being erased or programmed. 7:0 USEC R/W 0x31 November 30, 2007 Preliminary 121 Internal Memory Register 8: Flash Memory Protection Read Enable 0 (FMPRE0), offset 0x130 and 0x200 Note: Note: This register is aliased for backwards compatability. Offset is relative to System Control base address of 0x400FE000. This register stores the read-only protection bits for each 2-KB flash block (FMPPEn stores the execute-only bits). This register is loaded during the power-on reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves a policy of open access and programmability. The register bits may be changed by writing the specific register bit. However, this register is R/W0; the user can only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. For additional information, see the "Flash Memory Protection" section. Flash Memory Protection Read Enable 0 (FMPRE0) Base 0x400F.D000 Offset 0x130 and 0x200 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 READ_ENABLE Type Reset R/W 1 15 R/W 1 14 R/W 1 13 R/W 1 12 R/W 1 11 R/W 1 10 R/W 1 9 R/W 1 8 R/W 1 7 R/W 1 6 R/W 1 5 R/W 1 4 R/W 1 3 R/W 1 2 R/W 1 1 R/W 1 0 READ_ENABLE Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 Bit/Field 31:0 Name READ_ENABLE Type R/W Reset Description 0xFFFFFFFF Flash Read Enable Enables 2-KB flash blocks to be executed or read. The policies may be combined as shown in the table “Flash Protection Policy Combinations”. Value Description 0xFFFFFFFF Enables 64 KB of flash. 122 Preliminary November 30, 2007 LM3S2016 Microcontroller Register 9: Flash Memory Protection Program Enable 0 (FMPPE0), offset 0x134 and 0x400 Note: Note: This register is aliased for backwards compatability. Offset is relative to System Control base address of 0x400FE000. This register stores the execute-only protection bits for each 2-KB flash block (FMPREn stores the execute-only bits). This register is loaded during the power-on reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves a policy of open access and programmability. The register bits may be changed by writing the specific register bit. However, this register is R/W0; the user can only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. For additional information, see the "Flash Memory Protection" section. Flash Memory Protection Program Enable 0 (FMPPE0) Base 0x400F.D000 Offset 0x134 and 0x400 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PROG_ENABLE Type Reset R/W 1 15 R/W 1 14 R/W 1 13 R/W 1 12 R/W 1 11 R/W 1 10 R/W 1 9 R/W 1 8 R/W 1 7 R/W 1 6 R/W 1 5 R/W 1 4 R/W 1 3 R/W 1 2 R/W 1 1 R/W 1 0 PROG_ENABLE Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 Bit/Field 31:0 Name PROG_ENABLE Type R/W Reset Description 0xFFFFFFFF Flash Programming Enable Configures 2-KB flash blocks to be execute only. The policies may be combined as shown in the table “Flash Protection Policy Combinations”. Value Description 0xFFFFFFFF Enables 64 KB of flash. November 30, 2007 Preliminary 123 Internal Memory Register 10: User Debug (USER_DBG), offset 0x1D0 Note: Offset is relative to System Control base address of 0x400FE000. This register provides a write-once mechanism to disable external debugger access to the device in addition to 27 additional bits of user-defined data. The DBG0 bit (bit 0) is set to 0 from the factory and the DBG1 bit (bit 1) is set to 1, which enables external debuggers. Changing the DBG1 bit to 0 disables any external debugger access to the device permanently, starting with the next power-up cycle of the device. The NOTWRITTEN bit (bit 31) indicates that the register is available to be written and is controlled through hardware to ensure that the register is only written once. User Debug (USER_DBG) Base 0x400F.E000 Offset 0x1D0 Type R/W, reset 0xFFFF.FFFE 31 NW Type Reset R/W 1 15 R/W 1 14 R/W 1 13 R/W 1 12 R/W 1 11 R/W 1 10 R/W 1 9 DATA Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 8 30 29 28 27 26 25 24 23 DATA R/W 1 7 R/W 1 6 R/W 1 5 R/W 1 4 R/W 1 3 R/W 1 2 R/W 1 1 DBG1 R/W 1 R/W 1 0 DBG0 R/W 0 22 21 20 19 18 17 16 Bit/Field 31 Name NW Type R/W Reset 1 Description User Debug Not Written Specifies that this 32-bit dword has not been written. 30:2 DATA R/W 0x1FFFFFFF User Data Contains the user data value. This field is initialized to all 1s and can only be written once. 1 DBG1 R/W 1 Debug Control 1 The DBG1 bit must be 1 and DBG0 must be 0 for debug to be available. 0 DBG0 R/W 0 Debug Control 0 The DBG1 bit must be 1 and DBG0 must be 0 for debug to be available. 124 Preliminary November 30, 2007 LM3S2016 Microcontroller Register 11: User Register 0 (USER_REG0), offset 0x1E0 Note: Offset is relative to System Control base address of 0x400FE000. This register provides 31 bits of user-defined data that is non-volatile and can only be written once. Bit 31 indicates that the register is available to be written and is controlled through hardware to ensure that the register is only written once. The write-once characteristics of this register are useful for keeping static information like communication addresses that need to be unique per part and would otherwise require an external EEPROM or other non-volatile device. User Register 0 (USER_REG0) Base 0x400F.E000 Offset 0x1E0 Type R/W, reset 0xFFFF.FFFF 31 NW Type Reset R/W 1 15 R/W 1 14 R/W 1 13 R/W 1 12 R/W 1 11 R/W 1 10 R/W 1 9 R/W 1 8 DATA Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 30 29 28 27 26 25 24 23 DATA R/W 1 7 R/W 1 6 R/W 1 5 R/W 1 4 R/W 1 3 R/W 1 2 R/W 1 1 R/W 1 0 22 21 20 19 18 17 16 Bit/Field 31 Name NW Type R/W Reset 1 Description Not Written Specifies that this 32-bit dword has not been written. 30:0 DATA R/W 0x7FFFFFFF User Data Contains the user data value. This field is initialized to all 1s and can only be written once. November 30, 2007 Preliminary 125 Internal Memory Register 12: User Register 1 (USER_REG1), offset 0x1E4 Note: Offset is relative to System Control base address of 0x400FE000. This register provides 31 bits of user-defined data that is non-volatile and can only be written once. Bit 31 indicates that the register is available to be written and is controlled through hardware to ensure that the register is only written once. The write-once characteristics of this register are useful for keeping static information like communication addresses that need to be unique per part and would otherwise require an external EEPROM or other non-volatile device. User Register 1 (USER_REG1) Base 0x400F.E000 Offset 0x1E4 Type R/W, reset 0xFFFF.FFFF 31 NW Type Reset R/W 1 15 R/W 1 14 R/W 1 13 R/W 1 12 R/W 1 11 R/W 1 10 R/W 1 9 R/W 1 8 DATA Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 30 29 28 27 26 25 24 23 DATA R/W 1 7 R/W 1 6 R/W 1 5 R/W 1 4 R/W 1 3 R/W 1 2 R/W 1 1 R/W 1 0 22 21 20 19 18 17 16 Bit/Field 31 Name NW Type R/W Reset 1 Description Not Written Specifies that this 32-bit dword has not been written. 30:0 DATA R/W 0x7FFFFFFF User Data Contains the user data value. This field is initialized to all 1s and can only be written once. 126 Preliminary November 30, 2007 LM3S2016 Microcontroller Register 13: Flash Memory Protection Read Enable 1 (FMPRE1), offset 0x204 Note: Offset is relative to System Control base address of 0x400FE000. This register stores the read-only protection bits for each 2-KB flash block (FMPPEn stores the execute-only bits). This register is loaded during the power-on reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves a policy of open access and programmability. The register bits may be changed by writing the specific register bit. However, this register is R/W0; the user can only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. For additional information, see the "Flash Memory Protection" section. Flash Memory Protection Read Enable 1 (FMPRE1) Base 0x400F.E000 Offset 0x204 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 READ_ENABLE Type Reset R/W 0 15 R/W 0 14 R/W 0 13 R/W 0 12 R/W 0 11 R/W 0 10 R/W 0 9 R/W 0 8 R/W 0 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 READ_ENABLE Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field 31:0 Name READ_ENABLE Type R/W Reset Description 0x00000000 Flash Read Enable Enables 2-KB flash blocks to be executed or read. The policies may be combined as shown in the table “Flash Protection Policy Combinations”. Value Description 0x00000000 Enables 64 KB of flash. November 30, 2007 Preliminary 127 Internal Memory Register 14: Flash Memory Protection Read Enable 2 (FMPRE2), offset 0x208 Note: Offset is relative to System Control base address of 0x400FE000. This register stores the read-only protection bits for each 2-KB flash block (FMPPEn stores the execute-only bits). This register is loaded during the power-on reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves a policy of open access and programmability. The register bits may be changed by writing the specific register bit. However, this register is R/W0; the user can only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. For additional information, see the "Flash Memory Protection" section. Flash Memory Protection Read Enable 2 (FMPRE2) Base 0x400F.E000 Offset 0x208 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 READ_ENABLE Type Reset R/W 0 15 R/W 0 14 R/W 0 13 R/W 0 12 R/W 0 11 R/W 0 10 R/W 0 9 R/W 0 8 R/W 0 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 READ_ENABLE Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field 31:0 Name READ_ENABLE Type R/W Reset Description 0x00000000 Flash Read Enable Enables 2-KB flash blocks to be executed or read. The policies may be combined as shown in the table “Flash Protection Policy Combinations”. Value Description 0x00000000 Enables 64 KB of flash. 128 Preliminary November 30, 2007 LM3S2016 Microcontroller Register 15: Flash Memory Protection Read Enable 3 (FMPRE3), offset 0x20C Note: Offset is relative to System Control base address of 0x400FE000. This register stores the read-only protection bits for each 2-KB flash block (FMPPEn stores the execute-only bits). This register is loaded during the power-on reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves a policy of open access and programmability. The register bits may be changed by writing the specific register bit. However, this register is R/W0; the user can only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. For additional information, see the "Flash Memory Protection" section. Flash Memory Protection Read Enable 3 (FMPRE3) Base 0x400F.E000 Offset 0x20C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 READ_ENABLE Type Reset R/W 0 15 R/W 0 14 R/W 0 13 R/W 0 12 R/W 0 11 R/W 0 10 R/W 0 9 R/W 0 8 R/W 0 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 READ_ENABLE Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field 31:0 Name READ_ENABLE Type R/W Reset Description 0x00000000 Flash Read Enable Enables 2-KB flash blocks to be executed or read. The policies may be combined as shown in the table “Flash Protection Policy Combinations”. Value Description 0x00000000 Enables 64 KB of flash. November 30, 2007 Preliminary 129 Internal Memory Register 16: Flash Memory Protection Program Enable 1 (FMPPE1), offset 0x404 Note: Offset is relative to System Control base address of 0x400FE000. This register stores the execute-only protection bits for each 2-KB flash block (FMPREn stores the execute-only bits). This register is loaded during the power-on reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves a policy of open access and programmability. The register bits may be changed by writing the specific register bit. However, this register is R/W0; the user can only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. For additional information, see the "Flash Memory Protection" section. Flash Memory Protection Program Enable 1 (FMPPE1) Base 0x400F.E000 Offset 0x404 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PROG_ENABLE Type Reset R/W 0 15 R/W 0 14 R/W 0 13 R/W 0 12 R/W 0 11 R/W 0 10 R/W 0 9 R/W 0 8 R/W 0 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 PROG_ENABLE Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field 31:0 Name PROG_ENABLE Type R/W Reset Description 0x00000000 Flash Programming Enable Configures 2-KB flash blocks to be execute only. The policies may be combined as shown in the table “Flash Protection Policy Combinations”. Value Description 0x00000000 Enables 64 KB of flash. 130 Preliminary November 30, 2007 LM3S2016 Microcontroller Register 17: Flash Memory Protection Program Enable 2 (FMPPE2), offset 0x408 Note: Offset is relative to System Control base address of 0x400FE000. This register stores the execute-only protection bits for each 2-KB flash block (FMPREn stores the execute-only bits). This register is loaded during the power-on reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves a policy of open access and programmability. The register bits may be changed by writing the specific register bit. However, this register is R/W0; the user can only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. For additional information, see the "Flash Memory Protection" section. Flash Memory Protection Program Enable 2 (FMPPE2) Base 0x400F.E000 Offset 0x408 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PROG_ENABLE Type Reset R/W 0 15 R/W 0 14 R/W 0 13 R/W 0 12 R/W 0 11 R/W 0 10 R/W 0 9 R/W 0 8 R/W 0 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 PROG_ENABLE Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field 31:0 Name PROG_ENABLE Type R/W Reset Description 0x00000000 Flash Programming Enable Configures 2-KB flash blocks to be execute only. The policies may be combined as shown in the table “Flash Protection Policy Combinations”. Value Description 0x00000000 Enables 64 KB of flash. November 30, 2007 Preliminary 131 Internal Memory Register 18: Flash Memory Protection Program Enable 3 (FMPPE3), offset 0x40C Note: Offset is relative to System Control base address of 0x400FE000. This register stores the execute-only protection bits for each 2-KB flash block (FMPREn stores the execute-only bits). This register is loaded during the power-on reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves a policy of open access and programmability. The register bits may be changed by writing the specific register bit. However, this register is R/W0; the user can only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. For additional information, see the "Flash Memory Protection" section. Flash Memory Protection Program Enable 3 (FMPPE3) Base 0x400F.E000 Offset 0x40C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PROG_ENABLE Type Reset R/W 0 15 R/W 0 14 R/W 0 13 R/W 0 12 R/W 0 11 R/W 0 10 R/W 0 9 R/W 0 8 R/W 0 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 PROG_ENABLE Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field 31:0 Name PROG_ENABLE Type R/W Reset Description 0x00000000 Flash Programming Enable Configures 2-KB flash blocks to be execute only. The policies may be combined as shown in the table “Flash Protection Policy Combinations”. Value Description 0x00000000 Enables 64 KB of flash. 132 Preliminary November 30, 2007 LM3S2016 Microcontroller 8 General-Purpose Input/Outputs (GPIOs) The GPIO module is composed of eight physical GPIO blocks, each corresponding to an individual GPIO port (Port A, Port B, Port C, Port D, Port E, Port F, Port G, and Port H). The GPIO module is FiRM-compliant and supports 18-39 programmable input/output pins, depending on the peripherals being used. The GPIO module has the following features: ■ Programmable control for GPIO interrupts – Interrupt generation masking – Edge-triggered on rising, falling, or both – Level-sensitive on High or Low values ■ 5-V-tolerant input/outputs ■ Bit masking in both read and write operations through address lines ■ Programmable control for GPIO pad configuration – Weak pull-up or pull-down resistors – 2-mA, 4-mA, and 8-mA pad drive – Slew rate control for the 8-mA drive – Open drain enables – Digital input enables 8.1 Functional Description Important: All GPIO pins are tri-stated by default (GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0, and GPIOPUR=0), with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]). The JTAG/SWD pins default to their JTAG/SWD functionality (GPIOAFSEL=1, GPIODEN=1 and GPIOPUR=1). A Power-On-Reset (POR) or asserting RST puts both groups of pins back to their default state. Each GPIO port is a separate hardware instantiation of the same physical block (see Figure 8-1 on page 134). The LM3S2016 microcontroller contains eight ports and thus eight of these physical GPIO blocks. November 30, 2007 Preliminary 133 General-Purpose Input/Outputs (GPIOs) Figure 8-1. GPIO Port Block Diagram Commit Control GPIOLOCK GPIOCR Alternate Input Alternate Output Alternate Output Enable Pad Output Mode Control GPIOAFSEL DEMUX MUX Pad Input Data Control GPIODATA GPIODIR GPIO Input GPIO Output Digital I/O Pad Package I/O Pin MUX GPIO Output Enable Pad Output Enable Interrupt Control Interrupt Pad Control GPIODR2R GPIODR4R GPIODR8R GPIOSLR GPIOPUR GPIOPDR GPIOODR GPIODEN GPIOIS GPIOIBE GPIOIEV GPIOIM GPIORIS GPIOMIS GPIOICR Identification Registers GPIOPeriphID0 GPIOPeriphID1 GPIOPeriphID2 GPIOPeriphID3 GPIOPeriphID4 GPIOPeriphID5 GPIOPeriphID6 GPIOPeriphID7 GPIOPCellID0 GPIOPCellID1 GPIOPCellID2 GPIOPCellID3 8.1.1 Data Control The data control registers allow software to configure the operational modes of the GPIOs. The data direction register configures the GPIO as an input or an output while the data register either captures incoming data or drives it out to the pads. 8.1.1.1 Data Direction Operation The GPIO Direction (GPIODIR) register (see page 141) is used to configure each individual pin as an input or output. When the data direction bit is set to 0, the GPIO is configured as an input and the corresponding data register bit will capture and store the value on the GPIO port. When the data direction bit is set to 1, the GPIO is configured as an output and the corresponding data register bit will be driven out on the GPIO port. 8.1.1.2 Data Register Operation To aid in the efficiency of software, the GPIO ports allow for the modification of individual bits in the GPIO Data (GPIODATA) register (see page 140) by using bits [9:2] of the address bus as a mask. This allows software drivers to modify individual GPIO pins in a single instruction, without affecting the state of the other pins. This is in contrast to the "typical" method of doing a read-modify-write operation to set or clear an individual GPIO pin. To accommodate this feature, the GPIODATA register covers 256 locations in the memory map. During a write, if the address bit associated with that data bit is set to 1, the value of the GPIODATA register is altered. If it is cleared to 0, it is left unchanged. 134 Preliminary November 30, 2007 LM3S2016 Microcontroller For example, writing a value of 0xEB to the address GPIODATA + 0x098 would yield as shown in Figure 8-2 on page 135, where u is data unchanged by the write. Figure 8-2. GPIODATA Write Example ADDR[9:2] 0x098 0xEB GPIODATA 9 0 8 0 7 1 6 0 5 0 4 1 3 1 2 0 1 1 0 0 1 1 1 0 1 0 1 1 u 7 u 6 1 5 u 4 u 3 0 2 1 1 u 0 During a read, if the address bit associated with the data bit is set to 1, the value is read. If the address bit associated with the data bit is set to 0, it is read as a zero, regardless of its actual value. For example, reading address GPIODATA + 0x0C4 yields as shown in Figure 8-3 on page 135. Figure 8-3. GPIODATA Read Example ADDR[9:2] 0x0C4 GPIODATA Returned Value 9 0 8 0 7 1 6 1 5 0 4 0 3 0 2 1 1 0 0 0 1 0 1 1 1 1 1 0 0 7 0 6 1 5 1 4 0 3 0 2 0 1 0 0 8.1.2 Interrupt Control The interrupt capabilities of each GPIO port are controlled by a set of seven registers. With these registers, it is possible to select the source of the interrupt, its polarity, and the edge properties. When one or more GPIO inputs cause an interrupt, a single interrupt output is sent to the interrupt controller for the entire GPIO port. For edge-triggered interrupts, software must clear the interrupt to enable any further interrupts. For a level-sensitive interrupt, it is assumed that the external source holds the level constant for the interrupt to be recognized by the controller. Three registers are required to define the edge or sense that causes interrupts: ■ GPIO Interrupt Sense (GPIOIS) register (see page 142) ■ GPIO Interrupt Both Edges (GPIOIBE) register (see page 143) ■ GPIO Interrupt Event (GPIOIEV) register (see page 144) Interrupts are enabled/disabled via the GPIO Interrupt Mask (GPIOIM) register (see page 145). When an interrupt condition occurs, the state of the interrupt signal can be viewed in two locations: the GPIO Raw Interrupt Status (GPIORIS) and GPIO Masked Interrupt Status (GPIOMIS) registers (see page 146 and page 147). As the name implies, the GPIOMIS register only shows interrupt conditions that are allowed to be passed to the controller. The GPIORIS register indicates that a GPIO pin meets the conditions for an interrupt, but has not necessarily been sent to the controller. November 30, 2007 Preliminary 135 General-Purpose Input/Outputs (GPIOs) In addition to providing GPIO functionality, PB4 can also be used as an external trigger for the ADC. If PB4 is configured as a non-masked interrupt pin (GPIOIM is set to 1), not only is an interrupt for PortB generated, but an external trigger signal is sent to the ADC. If the ADC Event Multiplexer Select (ADCEMUX) register is configured to use the external trigger, an ADC conversion is initiated. If no other PortB pins are being used to generate interrupts, the ARM Integrated Nested Vectored Interrupt Controller (NVIC) Interrupt Set Enable (SETNA) register can disable the PortB interrupts and the ADC interrupt can be used to read back the converted data. Otherwise, the PortB interrupt handler needs to ignore and clear interrupts on B4, and wait for the ADC interrupt or the ADC interrupt needs to be disabled in the SETNA register and the PortB interrupt handler polls the ADC registers until the conversion is completed. Interrupts are cleared by writing a 1 to the GPIO Interrupt Clear (GPIOICR) register (see page 148). When programming the following interrupt control registers, the interrupts should be masked (GPIOIM set to 0). Writing any value to an interrupt control register (GPIOIS, GPIOIBE, or GPIOIEV) can generate a spurious interrupt if the corresponding bits are enabled. 8.1.3 Mode Control The GPIO pins can be controlled by either hardware or software. When hardware control is enabled via the GPIO Alternate Function Select (GPIOAFSEL) register (see page 149), the pin state is controlled by its alternate function (that is, the peripheral). Software control corresponds to GPIO mode, where the GPIODATA register is used to read/write the corresponding pins. 8.1.4 Commit Control The commit control registers provide a layer of protection against accidental programming of critical hardware peripherals. Writes to protected bits of the GPIO Alternate Function Select (GPIOAFSEL) register (see page 149) are not committed to storage unless the GPIO Lock (GPIOLOCK) register (see page 159) has been unlocked and the appropriate bits of the GPIO Commit (GPIOCR) register (see page 160) have been set to 1. 8.1.5 Pad Control The pad control registers allow for GPIO pad configuration by software based on the application requirements. The pad control registers include the GPIODR2R, GPIODR4R, GPIODR8R, GPIOODR, GPIOPUR, GPIOPDR, GPIOSLR, and GPIODEN registers. 8.1.6 Identification The identification registers configured at reset allow software to detect and identify the module as a GPIO block. The identification registers include the GPIOPeriphID0-GPIOPeriphID7 registers as well as the GPIOPCellID0-GPIOPCellID3 registers. 8.2 Initialization and Configuration To use the GPIO, the peripheral clock must be enabled by setting the appropriate GPIO Port bit field (GPIOn) in the RCGC2 register. On reset, all GPIO pins (except for the five JTAG pins) are configured out of reset to be undriven (tristate): GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0, and GPIOPUR=0. Table 8-1 on page 137 shows all possible configurations of the GPIO pads and the control register settings required to achieve them. Table 8-2 on page 137 shows how a rising edge interrupt would be configured for pin 2 of a GPIO port. 136 Preliminary November 30, 2007 LM3S2016 Microcontroller Table 8-1. GPIO Pad Configuration Examples Configuration GPIO Register Bit Value AFSEL Digital Input (GPIO) Digital Output (GPIO) Open Drain Input (GPIO) Open Drain Output (GPIO) Open Drain Input/Output (I2C) Digital Input (Timer CCP) Digital Output (Timer PWM) Digital Input/Output (SSI) Digital Input/Output (UART) 0 0 0 0 1 1 1 1 1 DIR 0 1 0 1 X X X X X a ODR 0 0 1 1 1 0 0 0 0 DEN 1 1 1 1 1 1 1 1 1 PUR ? ? X X X ? ? ? ? PDR ? ? X X X ? ? ? ? DR2R X ? X ? ? X ? ? ? DR4R X ? X ? ? X ? ? ? DR8R X ? X ? ? X ? ? ? SLR X ? X ? ? X ? ? ? a. X=Ignored (don’t care bit) ?=Can be either 0 or 1, depending on the configuration Table 8-2. GPIO Interrupt Configuration Example Register Desired Interrupt Event Trigger 0=edge 1=level GPIOIBE 0=single edge 1=both edges GPIOIEV 0=Low level, or negative edge 1=High level, or positive edge GPIOIM 0=masked 1=not masked a. X=Ignored (don’t care bit) 0 0 0 0 0 1 0 0 X X X X X 1 X X X X X X X 0 X X Pin 2 Bit Value 7 6 a 5 4 3 2 1 0 GPIOIS X X X X X 0 X X 8.3 Register Map Table 8-3 on page 138 lists the GPIO registers. The offset listed is a hexadecimal increment to the register ’s address, relative to that GPIO port’s base address: ■ GPIO Port A: 0x4000.4000 November 30, 2007 Preliminary 137 General-Purpose Input/Outputs (GPIOs) ■ GPIO Port B: 0x4000.5000 ■ GPIO Port C: 0x4000.6000 ■ GPIO Port D: 0x4000.7000 ■ GPIO Port E: 0x4002.4000 ■ GPIO Port F: 0x4002.5000 ■ GPIO Port G: 0x4002.6000 ■ GPIO Port H: 0x4002.7000 Important: The GPIO registers in this chapter are duplicated in each GPIO block, however, depending on the block, all eight bits may not be connected to a GPIO pad. In those cases, writing to those unconnected bits has no effect and reading those unconnected bits returns no meaningful data. Note: The default reset value for the GPIOAFSEL, GPIOPUR, and GPIODEN registers are 0x0000.0000 for all GPIO pins, with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]). These five pins default to JTAG/SWD functionality. Because of this, the default reset value of these registers for GPIO Port B is 0x0000.0080 while the default reset value for Port C is 0x0000.000F. The default register type for the GPIOCR register is RO for all GPIO pins, with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]). These five pins are currently the only GPIOs that are protected by the GPIOCR register. Because of this, the register type for GPIO Port B7 and GPIO Port C[3:0] is R/W. The default reset value for the GPIOCR register is 0x0000.00FF for all GPIO pins, with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]). To ensure that the JTAG port is not accidentally programmed as a GPIO, these five pins default to non-commitable. Because of this, the default reset value of GPIOCR for GPIO Port B is 0x0000.007F while the default reset value of GPIOCR for Port C is 0x0000.00F0. Table 8-3. GPIO Register Map Offset 0x000 0x400 0x404 0x408 0x40C 0x410 0x414 0x418 0x41C Name GPIODATA GPIODIR GPIOIS GPIOIBE GPIOIEV GPIOIM GPIORIS GPIOMIS GPIOICR Type R/W R/W R/W R/W R/W R/W RO RO W1C Reset 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 Description GPIO Data GPIO Direction GPIO Interrupt Sense GPIO Interrupt Both Edges GPIO Interrupt Event GPIO Interrupt Mask GPIO Raw Interrupt Status GPIO Masked Interrupt Status GPIO Interrupt Clear See page 140 141 142 143 144 145 146 147 148 138 Preliminary November 30, 2007 LM3S2016 Microcontroller Offset 0x420 0x500 0x504 0x508 0x50C 0x510 0x514 0x518 0x51C 0x520 0x524 0xFD0 0xFD4 0xFD8 0xFDC 0xFE0 0xFE4 0xFE8 0xFEC 0xFF0 0xFF4 0xFF8 0xFFC Name GPIOAFSEL GPIODR2R GPIODR4R GPIODR8R GPIOODR GPIOPUR GPIOPDR GPIOSLR GPIODEN GPIOLOCK GPIOCR GPIOPeriphID4 GPIOPeriphID5 GPIOPeriphID6 GPIOPeriphID7 GPIOPeriphID0 GPIOPeriphID1 GPIOPeriphID2 GPIOPeriphID3 GPIOPCellID0 GPIOPCellID1 GPIOPCellID2 GPIOPCellID3 Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W RO RO RO RO RO RO RO RO RO RO RO RO Reset 0x0000.00FF 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0001 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0061 0x0000.0000 0x0000.0018 0x0000.0001 0x0000.000D 0x0000.00F0 0x0000.0005 0x0000.00B1 Description GPIO Alternate Function Select GPIO 2-mA Drive Select GPIO 4-mA Drive Select GPIO 8-mA Drive Select GPIO Open Drain Select GPIO Pull-Up Select GPIO Pull-Down Select GPIO Slew Rate Control Select GPIO Digital Enable GPIO Lock GPIO Commit GPIO Peripheral Identification 4 GPIO Peripheral Identification 5 GPIO Peripheral Identification 6 GPIO Peripheral Identification 7 GPIO Peripheral Identification 0 GPIO Peripheral Identification 1 GPIO Peripheral Identification 2 GPIO Peripheral Identification 3 GPIO PrimeCell Identification 0 GPIO PrimeCell Identification 1 GPIO PrimeCell Identification 2 GPIO PrimeCell Identification 3 See page 149 151 152 153 154 155 156 157 158 159 160 162 163 164 165 166 167 168 169 170 171 172 173 8.4 Register Descriptions The remainder of this section lists and describes the GPIO registers, in numerical order by address offset. November 30, 2007 Preliminary 139 General-Purpose Input/Outputs (GPIOs) Register 1: GPIO Data (GPIODATA), offset 0x000 The GPIODATA register is the data register. In software control mode, values written in the GPIODATA register are transferred onto the GPIO port pins if the respective pins have been configured as outputs through the GPIO Direction (GPIODIR) register (see page 141). In order to write to GPIODATA, the corresponding bits in the mask, resulting from the address bus bits [9:2], must be High. Otherwise, the bit values remain unchanged by the write. Similarly, the values read from this register are determined for each bit by the mask bit derived from the address used to access the data register, bits [9:2]. Bits that are 1 in the address mask cause the corresponding bits in GPIODATA to be read, and bits that are 0 in the address mask cause the corresponding bits in GPIODATA to be read as 0, regardless of their value. A read from GPIODATA returns the last bit value written if the respective pins are configured as outputs, or it returns the value on the corresponding input pin when these are configured as inputs. All bits are cleared by a reset. GPIO Data (GPIODATA) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 GPIO Port H base: 0x4002.7000 Offset 0x000 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 DATA RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPIO Data This register is virtually mapped to 256 locations in the address space. To facilitate the reading and writing of data to these registers by independent drivers, the data read from and the data written to the registers are masked by the eight address lines ipaddr[9:2]. Reads from this register return its current state. Writes to this register only affect bits that are not masked by ipaddr[9:2] and are configured as outputs. See “Data Register Operation” on page 134 for examples of reads and writes. 7:0 DATA R/W 0x00 140 Preliminary November 30, 2007 LM3S2016 Microcontroller Register 2: GPIO Direction (GPIODIR), offset 0x400 The GPIODIR register is the data direction register. Bits set to 1 in the GPIODIR register configure the corresponding pin to be an output, while bits set to 0 configure the pins to be inputs. All bits are cleared by a reset, meaning all GPIO pins are inputs by default. GPIO Direction (GPIODIR) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 GPIO Port H base: 0x4002.7000 Offset 0x400 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 DIR RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPIO Data Direction The DIR values are defined as follows: Value Description 0 1 Pins are inputs. Pins are outputs. 7:0 DIR R/W 0x00 November 30, 2007 Preliminary 141 General-Purpose Input/Outputs (GPIOs) Register 3: GPIO Interrupt Sense (GPIOIS), offset 0x404 The GPIOIS register is the interrupt sense register. Bits set to 1 in GPIOIS configure the corresponding pins to detect levels, while bits set to 0 configure the pins to detect edges. All bits are cleared by a reset. GPIO Interrupt Sense (GPIOIS) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 GPIO Port H base: 0x4002.7000 Offset 0x404 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 IS RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPIO Interrupt Sense The IS values are defined as follows: Value Description 0 1 Edge on corresponding pin is detected (edge-sensitive). Level on corresponding pin is detected (level-sensitive). 7:0 IS R/W 0x00 142 Preliminary November 30, 2007 LM3S2016 Microcontroller Register 4: GPIO Interrupt Both Edges (GPIOIBE), offset 0x408 The GPIOIBE register is the interrupt both-edges register. When the corresponding bit in the GPIO Interrupt Sense (GPIOIS) register (see page 142) is set to detect edges, bits set to High in GPIOIBE configure the corresponding pin to detect both rising and falling edges, regardless of the corresponding bit in the GPIO Interrupt Event (GPIOIEV) register (see page 144). Clearing a bit configures the pin to be controlled by GPIOIEV. All bits are cleared by a reset. GPIO Interrupt Both Edges (GPIOIBE) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 GPIO Port H base: 0x4002.7000 Offset 0x408 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 IBE RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPIO Interrupt Both Edges The IBE values are defined as follows: Value Description 0 1 Interrupt generation is controlled by the GPIO Interrupt Event (GPIOIEV) register (see page 144). Both edges on the corresponding pin trigger an interrupt. Note: Single edge is determined by the corresponding bit in GPIOIEV. 7:0 IBE R/W 0x00 November 30, 2007 Preliminary 143 General-Purpose Input/Outputs (GPIOs) Register 5: GPIO Interrupt Event (GPIOIEV), offset 0x40C The GPIOIEV register is the interrupt event register. Bits set to High in GPIOIEV configure the corresponding pin to detect rising edges or high levels, depending on the corresponding bit value in the GPIO Interrupt Sense (GPIOIS) register (see page 142). Clearing a bit configures the pin to detect falling edges or low levels, depending on the corresponding bit value in GPIOIS. All bits are cleared by a reset. GPIO Interrupt Event (GPIOIEV) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 GPIO Port H base: 0x4002.7000 Offset 0x40C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 IEV RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPIO Interrupt Event The IEV values are defined as follows: Value Description 0 1 Falling edge or Low levels on corresponding pins trigger interrupts. Rising edge or High levels on corresponding pins trigger interrupts. 7:0 IEV R/W 0x00 144 Preliminary November 30, 2007 LM3S2016 Microcontroller Register 6: GPIO Interrupt Mask (GPIOIM), offset 0x410 The GPIOIM register is the interrupt mask register. Bits set to High in GPIOIM allow the corresponding pins to trigger their individual interrupts and the combined GPIOINTR line. Clearing a bit disables interrupt triggering on that pin. All bits are cleared by a reset. GPIO Interrupt Mask (GPIOIM) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 GPIO Port H base: 0x4002.7000 Offset 0x410 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 IME RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPIO Interrupt Mask Enable The IME values are defined as follows: Value Description 0 1 Corresponding pin interrupt is masked. Corresponding pin interrupt is not masked. 7:0 IME R/W 0x00 November 30, 2007 Preliminary 145 General-Purpose Input/Outputs (GPIOs) Register 7: GPIO Raw Interrupt Status (GPIORIS), offset 0x414 The GPIORIS register is the raw interrupt status register. Bits read High in GPIORIS reflect the status of interrupt trigger conditions detected (raw, prior to masking), indicating that all the requirements have been met, before they are finally allowed to trigger by the GPIO Interrupt Mask (GPIOIM) register (see page 145). Bits read as zero indicate that corresponding input pins have not initiated an interrupt. All bits are cleared by a reset. GPIO Raw Interrupt Status (GPIORIS) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 GPIO Port H base: 0x4002.7000 Offset 0x414 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RIS RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPIO Interrupt Raw Status Reflects the status of interrupt trigger condition detection on pins (raw, prior to masking). The RIS values are defined as follows: Value Description 0 1 Corresponding pin interrupt requirements not met. Corresponding pin interrupt has met requirements. 7:0 RIS RO 0x00 146 Preliminary November 30, 2007 LM3S2016 Microcontroller Register 8: GPIO Masked Interrupt Status (GPIOMIS), offset 0x418 The GPIOMIS register is the masked interrupt status register. Bits read High in GPIOMIS reflect the status of input lines triggering an interrupt. Bits read as Low indicate that either no interrupt has been generated, or the interrupt is masked. In addition to providing GPIO functionality, PB4 can also be used as an external trigger for the ADC. If PB4 is configured as a non-masked interrupt pin (GPIOIM is set to 1), not only is an interrupt for PortB generated, but an external trigger signal is sent to the ADC. If the ADC Event Multiplexer Select (ADCEMUX) register is configured to use the external trigger, an ADC conversion is initiated. If no other PortB pins are being used to generate interrupts, the ARM Integrated Nested Vectored Interrupt Controller (NVIC) Interrupt Set Enable (SETNA) register can disable the PortB interrupts and the ADC interrupt can be used to read back the converted data. Otherwise, the PortB interrupt handler needs to ignore and clear interrupts on B4, and wait for the ADC interrupt or the ADC interrupt needs to be disabled in the SETNA register and the PortB interrupt handler polls the ADC registers until the conversion is completed. GPIOMIS is the state of the interrupt after masking. GPIO Masked Interrupt Status (GPIOMIS) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 GPIO Port H base: 0x4002.7000 Offset 0x418 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 MIS RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPIO Masked Interrupt Status Masked value of interrupt due to corresponding pin. The MIS values are defined as follows: Value Description 0 1 Corresponding GPIO line interrupt not active. Corresponding GPIO line asserting interrupt. 7:0 MIS RO 0x00 November 30, 2007 Preliminary 147 General-Purpose Input/Outputs (GPIOs) Register 9: GPIO Interrupt Clear (GPIOICR), offset 0x41C The GPIOICR register is the interrupt clear register. Writing a 1 to a bit in this register clears the corresponding interrupt edge detection logic register. Writing a 0 has no effect. GPIO Interrupt Clear (GPIOICR) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 GPIO Port H base: 0x4002.7000 Offset 0x41C Type W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 IC RO 0 RO 0 RO 0 W1C 0 W1C 0 W1C 0 W1C 0 W1C 0 W1C 0 W1C 0 W1C 0 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPIO Interrupt Clear The IC values are defined as follows: Value Description 0 1 Corresponding interrupt is unaffected. Corresponding interrupt is cleared. 7:0 IC W1C 0x00 148 Preliminary November 30, 2007 LM3S2016 Microcontroller Register 10: GPIO Alternate Function Select (GPIOAFSEL), offset 0x420 The GPIOAFSEL register is the mode control select register. Writing a 1 to any bit in this register selects the hardware control for the corresponding GPIO line. All bits are cleared by a reset, therefore no GPIO line is set to hardware control by default. The commit control registers provide a layer of protection against accidental programming of critical hardware peripherals. Writes to protected bits of the GPIO Alternate Function Select (GPIOAFSEL) register (see page 149) are not committed to storage unless the GPIO Lock (GPIOLOCK) register (see page 159) has been unlocked and the appropriate bits of the GPIO Commit (GPIOCR) register (see page 160) have been set to 1. Important: All GPIO pins are tri-stated by default (GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0, and GPIOPUR=0), with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]). The JTAG/SWD pins default to their JTAG/SWD functionality (GPIOAFSEL=1, GPIODEN=1 and GPIOPUR=1). A Power-On-Reset (POR) or asserting RST puts both groups of pins back to their default state. Caution – If the JTAG pins are used as GPIOs in a design, PB7 and PC2 cannot have external pull-down resistors connected to both of them at the same time. If both pins are pulled Low during reset, the controller has unpredictable behavior. If this happens, remove one or both of the pull-down resistors, and apply RST or power-cycle the part. In addition, it is possible to create a software sequence that prevents the debugger from connecting to the Stellaris® microcontroller. If the program code loaded into flash immediately changes the JTAG pins to their GPIO functionality, the debugger may not have enough time to connect and halt the controller before the JTAG pin functionality switches. This may lock the debugger out of the part. This can be avoided with a software routine that restores JTAG functionality based on an external or software trigger. GPIO Alternate Function Select (GPIOAFSEL) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 GPIO Port H base: 0x4002.7000 Offset 0x420 Type R/W, reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 AFSEL RO 0 RO 0 RO 0 R/W R/W R/W R/W R/W R/W R/W R/W RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. November 30, 2007 Preliminary 149 General-Purpose Input/Outputs (GPIOs) Bit/Field 7:0 Name AFSEL Type R/W Reset - Description GPIO Alternate Function Select The AFSEL values are defined as follows: Value Description 0 1 Software control of corresponding GPIO line (GPIO mode). Hardware control of corresponding GPIO line (alternate hardware function). Note: The default reset value for the GPIOAFSEL, GPIOPUR, and GPIODEN registers are 0x0000.0000 for all GPIO pins, with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]). These five pins default to JTAG/SWD functionality. Because of this, the default reset value of these registers for GPIO Port B is 0x0000.0080 while the default reset value for Port C is 0x0000.000F. 150 Preliminary November 30, 2007 LM3S2016 Microcontroller Register 11: GPIO 2-mA Drive Select (GPIODR2R), offset 0x500 The GPIODR2R register is the 2-mA drive control register. It allows for each GPIO signal in the port to be individually configured without affecting the other pads. When writing a DRV2 bit for a GPIO signal, the corresponding DRV4 bit in the GPIODR4R register and the DRV8 bit in the GPIODR8R register are automatically cleared by hardware. GPIO 2-mA Drive Select (GPIODR2R) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 GPIO Port H base: 0x4002.7000 Offset 0x500 Type R/W, reset 0x0000.00FF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 DRV2 RO 0 RO 0 RO 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Output Pad 2-mA Drive Enable A write of 1 to either GPIODR4[n] or GPIODR8[n] clears the corresponding 2-mA enable bit. The change is effective on the second clock cycle after the write. 7:0 DRV2 R/W 0xFF November 30, 2007 Preliminary 151 General-Purpose Input/Outputs (GPIOs) Register 12: GPIO 4-mA Drive Select (GPIODR4R), offset 0x504 The GPIODR4R register is the 4-mA drive control register. It allows for each GPIO signal in the port to be individually configured without affecting the other pads. When writing the DRV4 bit for a GPIO signal, the corresponding DRV2 bit in the GPIODR2R register and the DRV8 bit in the GPIODR8R register are automatically cleared by hardware. GPIO 4-mA Drive Select (GPIODR4R) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 GPIO Port H base: 0x4002.7000 Offset 0x504 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 DRV4 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Output Pad 4-mA Drive Enable A write of 1 to either GPIODR2[n] or GPIODR8[n] clears the corresponding 4-mA enable bit. The change is effective on the second clock cycle after the write. 7:0 DRV4 R/W 0x00 152 Preliminary November 30, 2007 LM3S2016 Microcontroller Register 13: GPIO 8-mA Drive Select (GPIODR8R), offset 0x508 The GPIODR8R register is the 8-mA drive control register. It allows for each GPIO signal in the port to be individually configured without affecting the other pads. When writing the DRV8 bit for a GPIO signal, the corresponding DRV2 bit in the GPIODR2R register and the DRV4 bit in the GPIODR4R register are automatically cleared by hardware. GPIO 8-mA Drive Select (GPIODR8R) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 GPIO Port H base: 0x4002.7000 Offset 0x508 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 DRV8 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Output Pad 8-mA Drive Enable A write of 1 to either GPIODR2[n] or GPIODR4[n] clears the corresponding 8-mA enable bit. The change is effective on the second clock cycle after the write. 7:0 DRV8 R/W 0x00 November 30, 2007 Preliminary 153 General-Purpose Input/Outputs (GPIOs) Register 14: GPIO Open Drain Select (GPIOODR), offset 0x50C The GPIOODR register is the open drain control register. Setting a bit in this register enables the open drain configuration of the corresponding GPIO pad. When open drain mode is enabled, the corresponding bit should also be set in the GPIO Digital Input Enable (GPIODEN) register (see page 158). Corresponding bits in the drive strength registers (GPIODR2R, GPIODR4R, GPIODR8R, and GPIOSLR ) can be set to achieve the desired rise and fall times. The GPIO acts as an open drain input if the corresponding bit in the GPIODIR register is set to 0; and as an open drain output when set to 1. When using the I2C module, the GPIO Alternate Function Select (GPIOAFSEL) register bit for PB2 and PB3 should be set to 1 (see examples in “Initialization and Configuration” on page 136). GPIO Open Drain Select (GPIOODR) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 GPIO Port H base: 0x4002.7000 Offset 0x50C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 ODE RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Output Pad Open Drain Enable The ODE values are defined as follows: Value Description 0 1 Open drain configuration is disabled. Open drain configuration is enabled. 7:0 ODE R/W 0x00 154 Preliminary November 30, 2007 LM3S2016 Microcontroller Register 15: GPIO Pull-Up Select (GPIOPUR), offset 0x510 The GPIOPUR register is the pull-up control register. When a bit is set to 1, it enables a weak pull-up resistor on the corresponding GPIO signal. Setting a bit in GPIOPUR automatically clears the corresponding bit in the GPIO Pull-Down Select (GPIOPDR) register (see page 156). GPIO Pull-Up Select (GPIOPUR) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 GPIO Port H base: 0x4002.7000 Offset 0x510 Type R/W, reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 PUE RO 0 RO 0 RO 0 R/W R/W R/W R/W R/W R/W R/W R/W RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Pad Weak Pull-Up Enable A write of 1 to GPIOPDR[n] clears the corresponding GPIOPUR[n] enables. The change is effective on the second clock cycle after the write. Note: The default reset value for the GPIOAFSEL, GPIOPUR, and GPIODEN registers are 0x0000.0000 for all GPIO pins, with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]). These five pins default to JTAG/SWD functionality. Because of this, the default reset value of these registers for GPIO Port B is 0x0000.0080 while the default reset value for Port C is 0x0000.000F. 7:0 PUE R/W - November 30, 2007 Preliminary 155 General-Purpose Input/Outputs (GPIOs) Register 16: GPIO Pull-Down Select (GPIOPDR), offset 0x514 The GPIOPDR register is the pull-down control register. When a bit is set to 1, it enables a weak pull-down resistor on the corresponding GPIO signal. Setting a bit in GPIOPDR automatically clears the corresponding bit in the GPIO Pull-Up Select (GPIOPUR) register (see page 155). GPIO Pull-Down Select (GPIOPDR) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 GPIO Port H base: 0x4002.7000 Offset 0x514 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 PDE RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Pad Weak Pull-Down Enable A write of 1 to GPIOPUR[n] clears the corresponding GPIOPDR[n] enables. The change is effective on the second clock cycle after the write. 7:0 PDE R/W 0x00 156 Preliminary November 30, 2007 LM3S2016 Microcontroller Register 17: GPIO Slew Rate Control Select (GPIOSLR), offset 0x518 The GPIOSLR register is the slew rate control register. Slew rate control is only available when using the 8-mA drive strength option via the GPIO 8-mA Drive Select (GPIODR8R) register (see page 153). GPIO Slew Rate Control Select (GPIOSLR) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 GPIO Port H base: 0x4002.7000 Offset 0x518 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 SRL RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Slew Rate Limit Enable (8-mA drive only) The SRL values are defined as follows: Value Description 0 1 Slew rate control disabled. Slew rate control enabled. 7:0 SRL R/W 0x00 November 30, 2007 Preliminary 157 General-Purpose Input/Outputs (GPIOs) Register 18: GPIO Digital Enable (GPIODEN), offset 0x51C The GPIODEN register is the digital enable register. By default, with the exception of the GPIO signals used for JTAG/SWD function, all other GPIO signals are configured out of reset to be undriven (tristate). Their digital function is disabled; they do not drive a logic value on the pin and they do not allow the pin voltage into the GPIO receiver. To use the pin in a digital function (either GPIO or alternate function), the corresponding GPIODEN bit must be set. GPIO Digital Enable (GPIODEN) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 GPIO Port H base: 0x4002.7000 Offset 0x51C Type R/W, reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 DEN RO 0 RO 0 RO 0 R/W R/W R/W R/W R/W R/W R/W R/W RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Digital Enable The DEN values are defined as follows: Value Description 0 1 Digital functions disabled. Digital functions enabled. Note: The default reset value for the GPIOAFSEL, GPIOPUR, and GPIODEN registers are 0x0000.0000 for all GPIO pins, with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]). These five pins default to JTAG/SWD functionality. Because of this, the default reset value of these registers for GPIO Port B is 0x0000.0080 while the default reset value for Port C is 0x0000.000F. 7:0 DEN R/W - 158 Preliminary November 30, 2007 LM3S2016 Microcontroller Register 19: GPIO Lock (GPIOLOCK), offset 0x520 The GPIOLOCK register enables write access to the GPIOCR register (see page 160). Writing 0x1ACCE551 to the GPIOLOCK register will unlock the GPIOCR register. Writing any other value to the GPIOLOCK register re-enables the locked state. Reading the GPIOLOCK register returns the lock status rather than the 32-bit value that was previously written. Therefore, when write accesses are disabled, or locked, reading the GPIOLOCK register returns 0x00000001. When write accesses are enabled, or unlocked, reading the GPIOLOCK register returns 0x00000000. GPIO Lock (GPIOLOCK) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 GPIO Port H base: 0x4002.7000 Offset 0x520 Type R/W, reset 0x0000.0001 31 30 29 28 27 26 25 24 LOCK Type Reset R/W 0 15 R/W 0 14 R/W 0 13 R/W 0 12 R/W 0 11 R/W 0 10 R/W 0 9 R/W 0 8 LOCK Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 1 R/W 0 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 23 22 21 20 19 18 17 16 Bit/Field 31:0 Name LOCK Type R/W Reset Description 0x0000.0001 GPIO Lock A write of the value 0x1ACCE551 unlocks the GPIO Commit (GPIOCR) register for write access. A write of any other value reapplies the lock, preventing any register updates. A read of this register returns the following values: Value Description 0x0000.0001 locked 0x0000.0000 unlocked November 30, 2007 Preliminary 159 General-Purpose Input/Outputs (GPIOs) Register 20: GPIO Commit (GPIOCR), offset 0x524 The GPIOCR register is the commit register. The value of the GPIOCR register determines which bits of the GPIOAFSEL register will be committed when a write to the GPIOAFSEL register is performed. If a bit in the GPIOCR register is a zero, the data being written to the corresponding bit in the GPIOAFSEL register will not be committed and will retain its previous value. If a bit in the GPIOCR register is a one, the data being written to the corresponding bit of the GPIOAFSEL register will be committed to the register and will reflect the new value. The contents of the GPIOCR register can only be modified if the GPIOLOCK register is unlocked. Writes to the GPIOCR register will be ignored if the GPIOLOCK register is locked. Important: This register is designed to prevent accidental programming of the GPIOAFSEL registers that control connectivity to the JTAG/SWD debug hardware. By initializing the bits of the GPIOCR register to 0 for PB7 and PC[3:0], the JTAG/SWD debug port can only be converted to GPIOs through a deliberate set of writes to the GPIOLOCK, GPIOCR, and GPIOAFSEL registers. Because this protection is currently only implemented on the JTAG/SWD pins on PB7 and PC[3:0], all of the other bits in the GPIOCR registers cannot be written with 0x0. These bits are hardwired to 0x1, ensuring that it is always possible to commit new values to the GPIOAFSEL register bits of these other pins. GPIO Commit (GPIOCR) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 GPIO Port H base: 0x4002.7000 Offset 0x524 Type -, reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 CR RO 0 RO 0 RO 0 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 160 Preliminary November 30, 2007 LM3S2016 Microcontroller Bit/Field 7:0 Name CR Type - Reset - Description GPIO Commit On a bit-wise basis, any bit set allows the corresponding GPIOAFSEL bit to be set to its alternate function. Note: The default register type for the GPIOCR register is RO for all GPIO pins, with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]). These five pins are currently the only GPIOs that are protected by the GPIOCR register. Because of this, the register type for GPIO Port B7 and GPIO Port C[3:0] is R/W. The default reset value for the GPIOCR register is 0x0000.00FF for all GPIO pins, with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]). To ensure that the JTAG port is not accidentally programmed as a GPIO, these five pins default to non-commitable. Because of this, the default reset value of GPIOCR for GPIO Port B is 0x0000.007F while the default reset value of GPIOCR for Port C is 0x0000.00F0. November 30, 2007 Preliminary 161 General-Purpose Input/Outputs (GPIOs) Register 21: GPIO Peripheral Identification 4 (GPIOPeriphID4), offset 0xFD0 The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, and GPIOPeriphID7 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 4 (GPIOPeriphID4) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 GPIO Port H base: 0x4002.7000 Offset 0xFD0 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 PID4 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPIO Peripheral ID Register[7:0] 7:0 PID4 RO 0x00 162 Preliminary November 30, 2007 LM3S2016 Microcontroller Register 22: GPIO Peripheral Identification 5 (GPIOPeriphID5), offset 0xFD4 The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, and GPIOPeriphID7 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 5 (GPIOPeriphID5) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 GPIO Port H base: 0x4002.7000 Offset 0xFD4 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 PID5 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPIO Peripheral ID Register[15:8] 7:0 PID5 RO 0x00 November 30, 2007 Preliminary 163 General-Purpose Input/Outputs (GPIOs) Register 23: GPIO Peripheral Identification 6 (GPIOPeriphID6), offset 0xFD8 The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, and GPIOPeriphID7 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 6 (GPIOPeriphID6) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 GPIO Port H base: 0x4002.7000 Offset 0xFD8 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 PID6 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPIO Peripheral ID Register[23:16] 7:0 PID6 RO 0x00 164 Preliminary November 30, 2007 LM3S2016 Microcontroller Register 24: GPIO Peripheral Identification 7 (GPIOPeriphID7), offset 0xFDC The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, and GPIOPeriphID7 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 7 (GPIOPeriphID7) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 GPIO Port H base: 0x4002.7000 Offset 0xFDC Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 PID7 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPIO Peripheral ID Register[31:24] 7:0 PID7 RO 0x00 November 30, 2007 Preliminary 165 General-Purpose Input/Outputs (GPIOs) Register 25: GPIO Peripheral Identification 0 (GPIOPeriphID0), offset 0xFE0 The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, and GPIOPeriphID3 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 0 (GPIOPeriphID0) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 GPIO Port H base: 0x4002.7000 Offset 0xFE0 Type RO, reset 0x0000.0061 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 PID0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 1 RO 0 RO 0 RO 0 RO 0 RO 1 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPIO Peripheral ID Register[7:0] Can be used by software to identify the presence of this peripheral. 7:0 PID0 RO 0x61 166 Preliminary November 30, 2007 LM3S2016 Microcontroller Register 26: GPIO Peripheral Identification 1 (GPIOPeriphID1), offset 0xFE4 The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, and GPIOPeriphID3 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 1 (GPIOPeriphID1) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 GPIO Port H base: 0x4002.7000 Offset 0xFE4 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 PID1 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPIO Peripheral ID Register[15:8] Can be used by software to identify the presence of this peripheral. 7:0 PID1 RO 0x00 November 30, 2007 Preliminary 167 General-Purpose Input/Outputs (GPIOs) Register 27: GPIO Peripheral Identification 2 (GPIOPeriphID2), offset 0xFE8 The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, and GPIOPeriphID3 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 2 (GPIOPeriphID2) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 GPIO Port H base: 0x4002.7000 Offset 0xFE8 Type RO, reset 0x0000.0018 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 PID2 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 1 RO 0 RO 0 RO 0 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPIO Peripheral ID Register[23:16] Can be used by software to identify the presence of this peripheral. 7:0 PID2 RO 0x18 168 Preliminary November 30, 2007 LM3S2016 Microcontroller Register 28: GPIO Peripheral Identification 3 (GPIOPeriphID3), offset 0xFEC The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, and GPIOPeriphID3 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 3 (GPIOPeriphID3) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 GPIO Port H base: 0x4002.7000 Offset 0xFEC Type RO, reset 0x0000.0001 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 PID3 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPIO Peripheral ID Register[31:24] Can be used by software to identify the presence of this peripheral. 7:0 PID3 RO 0x01 November 30, 2007 Preliminary 169 General-Purpose Input/Outputs (GPIOs) Register 29: GPIO PrimeCell Identification 0 (GPIOPCellID0), offset 0xFF0 The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide registers, that can conceptually be treated as one 32-bit register. The register is used as a standard cross-peripheral identification system. GPIO PrimeCell Identification 0 (GPIOPCellID0) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 GPIO Port H base: 0x4002.7000 Offset 0xFF0 Type RO, reset 0x0000.000D 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 CID0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 1 RO 0 RO 1 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPIO PrimeCell ID Register[7:0] Provides software a standard cross-peripheral identification system. 7:0 CID0 RO 0x0D 170 Preliminary November 30, 2007 LM3S2016 Microcontroller Register 30: GPIO PrimeCell Identification 1 (GPIOPCellID1), offset 0xFF4 The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide registers, that can conceptually be treated as one 32-bit register. The register is used as a standard cross-peripheral identification system. GPIO PrimeCell Identification 1 (GPIOPCellID1) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 GPIO Port H base: 0x4002.7000 Offset 0xFF4 Type RO, reset 0x0000.00F0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 CID1 RO 0 RO 0 RO 0 RO 1 RO 1 RO 1 RO 1 RO 0 RO 0 RO 0 RO 0 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPIO PrimeCell ID Register[15:8] Provides software a standard cross-peripheral identification system. 7:0 CID1 RO 0xF0 November 30, 2007 Preliminary 171 General-Purpose Input/Outputs (GPIOs) Register 31: GPIO PrimeCell Identification 2 (GPIOPCellID2), offset 0xFF8 The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide registers, that can conceptually be treated as one 32-bit register. The register is used as a standard cross-peripheral identification system. GPIO PrimeCell Identification 2 (GPIOPCellID2) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 GPIO Port H base: 0x4002.7000 Offset 0xFF8 Type RO, reset 0x0000.0005 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 CID2 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 0 RO 1 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPIO PrimeCell ID Register[23:16] Provides software a standard cross-peripheral identification system. 7:0 CID2 RO 0x05 172 Preliminary November 30, 2007 LM3S2016 Microcontroller Register 32: GPIO PrimeCell Identification 3 (GPIOPCellID3), offset 0xFFC The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide registers, that can conceptually be treated as one 32-bit register. The register is used as a standard cross-peripheral identification system. GPIO PrimeCell Identification 3 (GPIOPCellID3) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 GPIO Port H base: 0x4002.7000 Offset 0xFFC Type RO, reset 0x0000.00B1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 CID3 RO 0 RO 0 RO 0 RO 1 RO 0 RO 1 RO 1 RO 0 RO 0 RO 0 RO 1 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPIO PrimeCell ID Register[31:24] Provides software a standard cross-peripheral identification system. 7:0 CID3 RO 0xB1 November 30, 2007 Preliminary 173 General-Purpose Timers 9 General-Purpose Timers Programmable timers can be used to count or time external events that drive the Timer input pins. ® The Stellaris General-Purpose Timer Module (GPTM) contains two GPTM blocks (Timer0 and Timer1). Each GPTM block provides two 16-bit timers/counters (referred to as TimerA and TimerB) that can be configured to operate independently as timers or event counters, or configured to operate as one 32-bit timer or one 32-bit Real-Time Clock (RTC). Timers can also be used to trigger analog-to-digital (ADC) conversions. The trigger signals from all of the general-purpose timers are ORed together before reaching the ADC module, so only one timer should be used to trigger ADC events. The General-Purpose Timer Module is one timing resource available on the Stellaris microcontrollers. Other timer resources include the System Timer (SysTick) (see “System Timer (SysTick)” on page 36). The following modes are supported: ■ 32-bit Timer modes – Programmable one-shot timer – Programmable periodic timer – Real-Time Clock using 32.768-KHz input clock – Software-controlled event stalling (excluding RTC mode) ■ 16-bit Timer modes – General-purpose timer function with an 8-bit prescaler (for one-shot and periodic modes only) – Programmable one-shot timer – Programmable periodic timer – Software-controlled event stalling ■ 16-bit Input Capture modes – Input edge count capture – Input edge time capture ■ 16-bit PWM mode – Simple PWM mode with software-programmable output inversion of the PWM signal ® 9.1 Block Diagram Note: In Figure 9-1 on page 175, the specific CCP pins available depend on the Stellaris device. See Table 9-1 on page 175 for the available CCPs. ® 174 Preliminary November 30, 2007 LM3S2016 Microcontroller Figure 9-1. GPTM Module Block Diagram 0x0000 (Down Counter Modes) TimerA Control GPTMTAPMR GPTMTAPR GPTMTAMATCHR Interrupt / Config TimerA Interrupt GPTMCFG GPTMCTL GPTMIMR TimerB Interrupt GPTMRIS GPTMMIS GPTMICR GPTMTBPMR GPTMTBPR GPTMTBMATCHR GPTMTBILR GPTMTBMR TB Comparator TimerB Control GPTMTBR En Clock / Edge Detect Odd CCP Pin RTC Divider GPTMTAILR GPTMTAMR GPTMAR En Clock / Edge Detect TA Comparator 32 KHz or Even CCP Pin 0x0000 (Down Counter Modes) System Clock Table 9-1. Available CCP Pins Timer 16-Bit Up/Down Counter Even CCP Pin Odd CCP Pin CCP0 CCP2 CCP1 CCP3 Timer 0 TimerA TimerB Timer 1 TimerA TimerB 9.2 Functional Description The main components of each GPTM block are two free-running 16-bit up/down counters (referred to as TimerA and TimerB), two 16-bit match registers, two prescaler match registers, and two 16-bit load/initialization registers and their associated control functions. The exact functionality of each GPTM is controlled by software and configured through the register interface. Software configures the GPTM using the GPTM Configuration (GPTMCFG) register (see page 186), the GPTM TimerA Mode (GPTMTAMR) register (see page 187), and the GPTM TimerB Mode (GPTMTBMR) register (see page 189). When in one of the 32-bit modes, the timer can only act as a 32-bit timer. However, when configured in 16-bit mode, the GPTM can have its two 16-bit timers configured in any combination of the 16-bit modes. 9.2.1 GPTM Reset Conditions After reset has been applied to the GPTM module, the module is in an inactive state, and all control registers are cleared and in their default states. Counters TimerA and TimerB are initialized to 0xFFFF, along with their corresponding load registers: the GPTM TimerA Interval Load (GPTMTAILR) register (see page 200) and the GPTM TimerB Interval Load (GPTMTBILR) register (see page 201). The prescale counters are initialized to 0x00: the GPTM TimerA Prescale November 30, 2007 Preliminary 175 General-Purpose Timers (GPTMTAPR) register (see page 204) and the GPTM TimerB Prescale (GPTMTBPR) register (see page 205). 9.2.2 32-Bit Timer Operating Modes This section describes the three GPTM 32-bit timer modes (One-Shot, Periodic, and RTC) and their configuration. The GPTM is placed into 32-bit mode by writing a 0 (One-Shot/Periodic 32-bit timer mode) or a 1 (RTC mode) to the GPTM Configuration (GPTMCFG) register. In both configurations, certain GPTM registers are concatenated to form pseudo 32-bit registers. These registers include: ■ GPTM TimerA Interval Load (GPTMTAILR) register [15:0], see page 200 ■ GPTM TimerB Interval Load (GPTMTBILR) register [15:0], see page 201 ■ GPTM TimerA (GPTMTAR) register [15:0], see page 208 ■ GPTM TimerB (GPTMTBR) register [15:0], see page 209 In the 32-bit modes, the GPTM translates a 32-bit write access to GPTMTAILR into a write access to both GPTMTAILR and GPTMTBILR. The resulting word ordering for such a write operation is: GPTMTBILR[15:0]:GPTMTAILR[15:0] Likewise, a read access to GPTMTAR returns the value: GPTMTBR[15:0]:GPTMTAR[15:0] 9.2.2.1 32-Bit One-Shot/Periodic Timer Mode In 32-bit one-shot and periodic timer modes, the concatenated versions of the TimerA and TimerB registers are configured as a 32-bit down-counter. The selection of one-shot or periodic mode is determined by the value written to the TAMR field of the GPTM TimerA Mode (GPTMTAMR) register (see page 187), and there is no need to write to the GPTM TimerB Mode (GPTMTBMR) register. When software writes the TAEN bit in the GPTM Control (GPTMCTL) register (see page 191), the timer begins counting down from its preloaded value. Once the 0x0000.0000 state is reached, the timer reloads its start value from the concatenated GPTMTAILR on the next cycle. If configured to be a one-shot timer, the timer stops counting and clears the TAEN bit in the GPTMCTL register. If configured as a periodic timer, it continues counting. In addition to reloading the count value, the GPTM generates interrupts and output triggers when it reaches the 0x0000000 state. The GPTM sets the TATORIS bit in the GPTM Raw Interrupt Status (GPTMRIS) register (see page 196), and holds it until it is cleared by writing the GPTM Interrupt Clear (GPTMICR) register (see page 198). If the time-out interrupt is enabled in the GPTM Interrupt Mask (GPTIMR) register (see page 194), the GPTM also sets the TATOMIS bit in the GPTM Masked Interrupt Status (GPTMMIS) register (see page 197). The output trigger is a one-clock-cycle pulse that is asserted when the counter hits the 0x0000.0000 state, and deasserted on the following clock cycle. It is enabled by setting the TAOTE bit in GPTMCTL, and can trigger SoC-level events such as ADC conversions. If software reloads the GPTMTAILR register while the counter is running, the counter loads the new value on the next clock cycle and continues counting from the new value. If the TASTALL bit in the GPTMCTL register is asserted, the timer freezes counting until the signal is deasserted. 176 Preliminary November 30, 2007 LM3S2016 Microcontroller 9.2.2.2 32-Bit Real-Time Clock Timer Mode In Real-Time Clock (RTC) mode, the concatenated versions of the TimerA and TimerB registers are configured as a 32-bit up-counter. When RTC mode is selected for the first time, the counter is loaded with a value of 0x0000.0001. All subsequent load values must be written to the GPTM TimerA Match (GPTMTAMATCHR) register (see page 202) by the controller. The input clock on the CCP0, CCP2, or CCP4 pins is required to be 32.768 KHz in RTC mode. The clock signal is then divided down to a 1 Hz rate and is passed along to the input of the 32-bit counter. When software writes the TAEN bit inthe GPTMCTL register, the counter starts counting up from its preloaded value of 0x0000.0001. When the current count value matches the preloaded value in the GPTMTAMATCHR register, it rolls over to a value of 0x0000.0000 and continues counting until either a hardware reset, or it is disabled by software (clearing the TAEN bit). When a match occurs, the GPTM asserts the RTCRIS bit in GPTMRIS. If the RTC interrupt is enabled in GPTIMR, the GPTM also sets the RTCMIS bit in GPTMISR and generates a controller interrupt. The status flags are cleared by writing the RTCCINT bit in GPTMICR. If the TASTALL and/or TBSTALL bits in the GPTMCTL register are set, the timer does not freeze if the RTCEN bit is set in GPTMCTL. 9.2.3 16-Bit Timer Operating Modes The GPTM is placed into global 16-bit mode by writing a value of 0x4 to the GPTM Configuration (GPTMCFG) register (see page 186). This section describes each of the GPTM 16-bit modes of operation. TimerA and TimerB have identical modes, so a single description is given using an n to reference both. 9.2.3.1 16-Bit One-Shot/Periodic Timer Mode In 16-bit one-shot and periodic timer modes, the timer is configured as a 16-bit down-counter with an optional 8-bit prescaler that effectively extends the counting range of the timer to 24 bits. The selection of one-shot or periodic mode is determined by the value written to the TnMR field of the GPTMTnMR register. The optional prescaler is loaded into the GPTM Timern Prescale (GPTMTnPR) register. When software writes the TnEN bit in the GPTMCTL register, the timer begins counting down from its preloaded value. Once the 0x0000 state is reached, the timer reloads its start value from GPTMTnILR and GPTMTnPR on the next cycle. If configured to be a one-shot timer, the timer stops counting and clears the TnEN bit in the GPTMCTL register. If configured as a periodic timer, it continues counting. In addition to reloading the count value, the timer generates interrupts and output triggers when it reaches the 0x0000 state. The GPTM sets the TnTORIS bit in the GPTMRIS register, and holds it until it is cleared by writing the GPTMICR register. If the time-out interrupt is enabled in GPTIMR, the GPTM also sets the TnTOMIS bit in GPTMISR and generates a controller interrupt. The output trigger is a one-clock-cycle pulse that is asserted when the counter hits the 0x0000 state, and deasserted on the following clock cycle. It is enabled by setting the TnOTE bit in the GPTMCTL register, and can trigger SoC-level events such as ADC conversions. If software reloads the GPTMTAILR register while the counter is running, the counter loads the new value on the next clock cycle and continues counting from the new value. If the TnSTALL bit in the GPTMCTL register is enabled, the timer freezes counting until the signal is deasserted. November 30, 2007 Preliminary 177 General-Purpose Timers The following example shows a variety of configurations for a 16-bit free running timer while using the prescaler. All values assume a 50-MHz clock with Tc=20 ns (clock period). Table 9-2. 16-Bit Timer With Prescaler Configurations Prescale #Clock (T c) Max Time Units 00000000 00000001 00000010 -----------11111100 11111110 11111111 1 2 3 -254 255 256 1.3107 2.6214 3.9321 -332.9229 334.2336 335.5443 mS mS mS -mS mS mS a a. Tc is the clock period. 9.2.3.2 16-Bit Input Edge Count Mode In Edge Count mode, the timer is configured as a down-counter capable of capturing three types of events: rising edge, falling edge, or both. To place the timer in Edge Count mode, the TnCMR bit of the GPTMTnMR register must be set to 0. The type of edge that the timer counts is determined by the TnEVENT fields of the GPTMCTL register. During initialization, the GPTM Timern Match (GPTMTnMATCHR) register is configured so that the difference between the value in the GPTMTnILR register and the GPTMTnMATCHR register equals the number of edge events that must be counted. When software writes the TnEN bit in the GPTM Control (GPTMCTL) register, the timer is enabled for event capture. Each input event on the CCP pin decrements the counter by 1 until the event count matches GPTMTnMATCHR. When the counts match, the GPTM asserts the CnMRIS bit in the GPTMRIS register (and the CnMMIS bit, if the interrupt is not masked). The counter is then reloaded using the value in GPTMTnILR, and stopped since the GPTM automatically clears the TnEN bit in the GPTMCTL register. Once the event count has been reached, all further events are ignored until TnEN is re-enabled by software. Figure 9-2 on page 179 shows how input edge count mode works. In this case, the timer start value is set to GPTMnILR =0x000A and the match value is set to GPTMnMATCHR =0x0006 so that four edge events are counted. The counter is configured to detect both edges of the input signal. Note that the last two edges are not counted since the timer automatically clears the TnEN bit after the current count matches the value in the GPTMnMR register. 178 Preliminary November 30, 2007 LM3S2016 Microcontroller Figure 9-2. 16-Bit Input Edge Count Mode Example Timer reload on next cycle Ignored Ignored Count 0x000A 0x0009 0x0008 0x0007 0x0006 Timer stops, flags asserted Input Signal 9.2.3.3 16-Bit Input Edge Time Mode Note: The prescaler is not available in 16-Bit Input Edge Time mode. In Edge Time mode, the timer is configured as a free-running down-counter initialized to the value loaded in the GPTMTnILR register (or 0xFFFF at reset). This mode allows for event capture of both rising and falling edges. The timer is placed into Edge Time mode by setting the TnCMR bit in the GPTMTnMR register, and the type of event that the timer captures is determined by the TnEVENT fields of the GPTMCnTL register. When software writes the TnEN bit in the GPTMCTL register, the timer is enabled for event capture. When the selected input event is detected, the current Tn counter value is captured in the GPTMTnR register and is available to be read by the controller. The GPTM then asserts the CnERIS bit (and the CnEMIS bit, if the interrupt is not masked). After an event has been captured, the timer does not stop counting. It continues to count until the TnEN bit is cleared. When the timer reaches the 0x0000 state, it is reloaded with the value from the GPTMnILR register. Figure 9-3 on page 180 shows how input edge timing mode works. In the diagram, it is assumed that the start value of the timer is the default value of 0xFFFF, and the timer is configured to capture rising edge events. Each time a rising edge event is detected, the current count value is loaded into the GPTMTnR register, and is held there until another rising edge is detected (at which point the new count value is loaded into GPTMTnR). November 30, 2007 Preliminary 179 General-Purpose Timers Figure 9-3. 16-Bit Input Edge Time Mode Example Count 0xFFFF GPTMTnR=X GPTMTnR=Y GPTMTnR=Z Z X Y Time Input Signal 9.2.3.4 16-Bit PWM Mode The GPTM supports a simple PWM generation mode. In PWM mode, the timer is configured as a down-counter with a start value (and thus period) defined by GPTMTnILR. PWM mode is enabled with the GPTMTnMR register by setting the TnAMS bit to 0x1, the TnCMR bit to 0x0, and the TnMR field to 0x2. When software writes the TnEN bit in the GPTMCTL register, the counter begins counting down until it reaches the 0x0000 state. On the next counter cycle, the counter reloads its start value from GPTMTnILR (and GPTMTnPR if using a prescaler) and continues counting until disabled by software clearing the TnEN bit in the GPTMCTL register. No interrupts or status bits are asserted in PWM mode. The output PWM signal asserts when the counter is at the value of the GPTMTnILR register (its start state), and is deasserted when the counter value equals the value in the GPTM Timern Match Register (GPTMnMATCHR). Software has the capability of inverting the output PWM signal by setting the TnPWML bit in the GPTMCTL register. Figure 9-4 on page 181 shows how to generate an output PWM with a 1-ms period and a 66% duty cycle assuming a 50-MHz input clock and TnPWML =0 (duty cycle would be 33% for the TnPWML =1 configuration). For this example, the start value is GPTMnIRL=0xC350 and the match value is GPTMnMR=0x411A. 180 Preliminary November 30, 2007 LM3S2016 Microcontroller Figure 9-4. 16-Bit PWM Mode Example Count 0xC350 GPTMTnR=GPTMnMR GPTMTnR=GPTMnMR 0x411A Time TnEN set TnPWML = 0 Output Signal TnPWML = 1 9.3 Initialization and Configuration To use the general-purpose timers, the peripheral clock must be enabled by setting the TIMER0 and TIMER1 bits in the RCGC1 register. This section shows module initialization and configuration examples for each of the supported timer modes. 9.3.1 32-Bit One-Shot/Periodic Timer Mode The GPTM is configured for 32-bit One-Shot and Periodic modes by the following sequence: 1. Ensure the timer is disabled (the TAEN bit in the GPTMCTL register is cleared) before making any changes. 2. Write the GPTM Configuration Register (GPTMCFG) with a value of 0x0. 3. Set the TAMR field in the GPTM TimerA Mode Register (GPTMTAMR): a. Write a value of 0x1 for One-Shot mode. b. Write a value of 0x2 for Periodic mode. 4. Load the start value into the GPTM TimerA Interval Load Register (GPTMTAILR). 5. If interrupts are required, set the TATOIM bit in the GPTM Interrupt Mask Register (GPTMIMR). 6. Set the TAEN bit in the GPTMCTL register to enable the timer and start counting. November 30, 2007 Preliminary 181 General-Purpose Timers 7. Poll the TATORIS bit in the GPTMRIS register or wait for the interrupt to be generated (if enabled). In both cases, the status flags are cleared by writing a 1 to the TATOCINT bit of the GPTM Interrupt Clear Register (GPTMICR). In One-Shot mode, the timer stops counting after step 7 on page 182. To re-enable the timer, repeat the sequence. A timer configured in Periodic mode does not stop counting after it times out. 9.3.2 32-Bit Real-Time Clock (RTC) Mode To use the RTC mode, the timer must have a 32.768-KHz input signal on its CCP0, CCP2, or CCP4 pins. To enable the RTC feature, follow these steps: 1. Ensure the timer is disabled (the TAEN bit is cleared) before making any changes. 2. Write the GPTM Configuration Register (GPTMCFG) with a value of 0x1. 3. Write the desired match value to the GPTM TimerA Match Register (GPTMTAMATCHR). 4. Set/clear the RTCEN bit in the GPTM Control Register (GPTMCTL) as desired. 5. If interrupts are required, set the RTCIM bit in the GPTM Interrupt Mask Register (GPTMIMR). 6. Set the TAEN bit in the GPTMCTL register to enable the timer and start counting. When the timer count equals the value in the GPTMTAMATCHR register, the counter is re-loaded with 0x0000.0000 and begins counting. If an interrupt is enabled, it does not have to be cleared. 9.3.3 16-Bit One-Shot/Periodic Timer Mode A timer is configured for 16-bit One-Shot and Periodic modes by the following sequence: 1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes. 2. Write the GPTM Configuration Register (GPTMCFG) with a value of 0x4. 3. Set the TnMR field in the GPTM Timer Mode (GPTMTnMR) register: a. Write a value of 0x1 for One-Shot mode. b. Write a value of 0x2 for Periodic mode. 4. If a prescaler is to be used, write the prescale value to the GPTM Timern Prescale Register (GPTMTnPR). 5. Load the start value into the GPTM Timer Interval Load Register (GPTMTnILR). 6. If interrupts are required, set the TnTOIM bit in the GPTM Interrupt Mask Register (GPTMIMR). 7. Set the TnEN bit in the GPTM Control Register (GPTMCTL) to enable the timer and start counting. 8. Poll the TnTORIS bit in the GPTMRIS register or wait for the interrupt to be generated (if enabled). In both cases, the status flags are cleared by writing a 1 to the TnTOCINT bit of the GPTM Interrupt Clear Register (GPTMICR). 182 Preliminary November 30, 2007 LM3S2016 Microcontroller In One-Shot mode, the timer stops counting after step 8 on page 182. To re-enable the timer, repeat the sequence. A timer configured in Periodic mode does not stop counting after it times out. 9.3.4 16-Bit Input Edge Count Mode A timer is configured to Input Edge Count mode by the following sequence: 1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes. 2. Write the GPTM Configuration (GPTMCFG) register with a value of 0x4. 3. In the GPTM Timer Mode (GPTMTnMR) register, write the TnCMR field to 0x0 and the TnMR field to 0x3. 4. Configure the type of event(s) that the timer captures by writing the TnEVENT field of the GPTM Control (GPTMCTL) register. 5. Load the timer start value into the GPTM Timern Interval Load (GPTMTnILR) register. 6. Load the desired event count into the GPTM Timern Match (GPTMTnMATCHR) register. 7. If interrupts are required, set the CnMIM bit in the GPTM Interrupt Mask (GPTMIMR) register. 8. Set the TnEN bit in the GPTMCTL register to enable the timer and begin waiting for edge events. 9. Poll the CnMRIS bit in the GPTMRIS register or wait for the interrupt to be generated (if enabled). In both cases, the status flags are cleared by writing a 1 to the CnMCINT bit of the GPTM Interrupt Clear (GPTMICR) register. In Input Edge Count Mode, the timer stops after the desired number of edge events has been detected. To re-enable the timer, ensure that the TnEN bit is cleared and repeat step 4 on page 183 through step 9 on page 183. 9.3.5 16-Bit Input Edge Timing Mode A timer is configured to Input Edge Timing mode by the following sequence: 1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes. 2. Write the GPTM Configuration (GPTMCFG) register with a value of 0x4. 3. In the GPTM Timer Mode (GPTMTnMR) register, write the TnCMR field to 0x1 and the TnMR field to 0x3. 4. Configure the type of event that the timer captures by writing the TnEVENT field of the GPTM Control (GPTMCTL) register. 5. Load the timer start value into the GPTM Timern Interval Load (GPTMTnILR) register. 6. If interrupts are required, set the CnEIM bit in the GPTM Interrupt Mask (GPTMIMR) register. 7. Set the TnEN bit in the GPTM Control (GPTMCTL) register to enable the timer and start counting. 8. Poll the CnERIS bit in the GPTMRIS register or wait for the interrupt to be generated (if enabled). In both cases, the status flags are cleared by writing a 1 to the CnECINT bit of the GPTM November 30, 2007 Preliminary 183 General-Purpose Timers Interrupt Clear (GPTMICR) register. The time at which the event happened can be obtained by reading the GPTM Timern (GPTMTnR) register. In Input Edge Timing mode, the timer continues running after an edge event has been detected, but the timer interval can be changed at any time by writing the GPTMTnILR register. The change takes effect at the next cycle after the write. 9.3.6 16-Bit PWM Mode A timer is configured to PWM mode using the following sequence: 1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes. 2. Write the GPTM Configuration (GPTMCFG) register with a value of 0x4. 3. In the GPTM Timer Mode (GPTMTnMR) register, set the TnAMS bit to 0x1, the TnCMR bit to 0x0, and the TnMR field to 0x2. 4. Configure the output state of the PWM signal (whether or not it is inverted) in the TnEVENT field of the GPTM Control (GPTMCTL) register. 5. Load the timer start value into the GPTM Timern Interval Load (GPTMTnILR) register. 6. Load the GPTM Timern Match (GPTMTnMATCHR) register with the desired value. 7. If a prescaler is going to be used, configure the GPTM Timern Prescale (GPTMTnPR) register and the GPTM Timern Prescale Match (GPTMTnPMR) register. 8. Set the TnEN bit in the GPTM Control (GPTMCTL) register to enable the timer and begin generation of the output PWM signal. In PWM Timing mode, the timer continues running after the PWM signal has been generated. The PWM period can be adjusted at any time by writing the GPTMTnILR register, and the change takes effect at the next cycle after the write. 9.4 Register Map Table 9-3 on page 184 lists the GPTM registers. The offset listed is a hexadecimal increment to the register ’s address, relative to that timer ’s base address: ■ Timer0: 0x4003.0000 ■ Timer1: 0x4003.1000 Table 9-3. Timers Register Map Offset 0x000 0x004 0x008 0x00C 0x018 Name GPTMCFG GPTMTAMR GPTMTBMR GPTMCTL GPTMIMR Type R/W R/W R/W R/W R/W Reset 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 Description GPTM Configuration GPTM TimerA Mode GPTM TimerB Mode GPTM Control GPTM Interrupt Mask See page 186 187 189 191 194 184 Preliminary November 30, 2007 LM3S2016 Microcontroller Offset 0x01C 0x020 0x024 Name GPTMRIS GPTMMIS GPTMICR Type RO RO W1C Reset 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.FFFF (16-bit mode) 0xFFFF.FFFF (32-bit mode) 0x0000.FFFF 0x0000.FFFF (16-bit mode) 0xFFFF.FFFF (32-bit mode) 0x0000.FFFF 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.FFFF (16-bit mode) 0xFFFF.FFFF (32-bit mode) 0x0000.FFFF Description GPTM Raw Interrupt Status GPTM Masked Interrupt Status GPTM Interrupt Clear See page 196 197 198 0x028 GPTMTAILR R/W GPTM TimerA Interval Load 200 0x02C GPTMTBILR R/W GPTM TimerB Interval Load 201 0x030 GPTMTAMATCHR R/W GPTM TimerA Match 202 0x034 0x038 0x03C 0x040 0x044 GPTMTBMATCHR GPTMTAPR GPTMTBPR GPTMTAPMR GPTMTBPMR R/W R/W R/W R/W R/W GPTM TimerB Match GPTM TimerA Prescale GPTM TimerB Prescale GPTM TimerA Prescale Match GPTM TimerB Prescale Match 203 204 205 206 207 0x048 GPTMTAR RO GPTM TimerA 208 0x04C GPTMTBR RO GPTM TimerB 209 9.5 Register Descriptions The remainder of this section lists and describes the GPTM registers, in numerical order by address offset. November 30, 2007 Preliminary 185 General-Purpose Timers Register 1: GPTM Configuration (GPTMCFG), offset 0x000 This register configures the global operation of the GPTM module. The value written to this register determines whether the GPTM is in 32- or 16-bit mode. GPTM Configuration (GPTMCFG) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Offset 0x000 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 GPTMCFG R/W 0 R/W 0 RO 0 0 Bit/Field 31:3 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPTM Configuration The GPTMCFG values are defined as follows: Value 0x0 0x1 0x2 0x3 Description 32-bit timer configuration. 32-bit real-time clock (RTC) counter configuration. Reserved. Reserved. 2:0 GPTMCFG R/W 0x0 0x4-0x7 16-bit timer configuration, function is controlled by bits 1:0 of GPTMTAMR and GPTMTBMR. 186 Preliminary November 30, 2007 LM3S2016 Microcontroller Register 2: GPTM TimerA Mode (GPTMTAMR), offset 0x004 This register configures the GPTM based on the configuration selected in the GPTMCFG register. When in 16-bit PWM mode, set the TAAMS bit to 0x1, the TACMR bit to 0x0, and the TAMR field to 0x2. GPTM TimerA Mode (GPTMTAMR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Offset 0x004 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 TAAMS R/W 0 RO 0 2 TACMR R/W 0 R/W 0 RO 0 1 TAMR R/W 0 RO 0 0 Bit/Field 31:4 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPTM TimerA Alternate Mode Select The TAAMS values are defined as follows: Value Description 0 1 Capture mode is enabled. PWM mode is enabled. Note: To enable PWM mode, you must also clear the TACMR bit and set the TAMR field to 0x2. 3 TAAMS R/W 0 2 TACMR R/W 0 GPTM TimerA Capture Mode The TACMR values are defined as follows: Value Description 0 1 Edge-Count mode. Edge-Time mode. November 30, 2007 Preliminary 187 General-Purpose Timers Bit/Field 1:0 Name TAMR Type R/W Reset 0x0 Description GPTM TimerA Mode The TAMR values are defined as follows: Value Description 0x0 Reserved. 0x1 One-Shot Timer mode. 0x2 Periodic Timer mode. 0x3 Capture mode. The Timer mode is based on the timer configuration defined by bits 2:0 in the GPTMCFG register (16-or 32-bit). In 16-bit timer configuration, TAMR controls the 16-bit timer modes for TimerA. In 32-bit timer configuration, this register controls the mode and the contents of GPTMTBMR are ignored. 188 Preliminary November 30, 2007 LM3S2016 Microcontroller Register 3: GPTM TimerB Mode (GPTMTBMR), offset 0x008 This register configures the GPTM based on the configuration selected in the GPTMCFG register. When in 16-bit PWM mode, set the TBAMS bit to 0x1, the TBCMR bit to 0x0, and the TBMR field to 0x2. GPTM TimerB Mode (GPTMTBMR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Offset 0x008 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 TBAMS R/W 0 RO 0 2 TBCMR R/W 0 RO 0 1 TBMR R/W 0 R/W 0 RO 0 0 Bit/Field 31:4 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPTM TimerB Alternate Mode Select The TBAMS values are defined as follows: Value Description 0 1 Capture mode is enabled. PWM mode is enabled. Note: To enable PWM mode, you must also clear the TBCMR bit and set the TBMR field to 0x2. 3 TBAMS R/W 0 2 TBCMR R/W 0 GPTM TimerB Capture Mode The TBCMR values are defined as follows: Value Description 0 1 Edge-Count mode. Edge-Time mode. November 30, 2007 Preliminary 189 General-Purpose Timers Bit/Field 1:0 Name TBMR Type R/W Reset 0x0 Description GPTM TimerB Mode The TBMR values are defined as follows: Value Description 0x0 Reserved. 0x1 One-Shot Timer mode. 0x2 Periodic Timer mode. 0x3 Capture mode. The timer mode is based on the timer configuration defined by bits 2:0 in the GPTMCFG register. In 16-bit timer configuration, these bits control the 16-bit timer modes for TimerB. In 32-bit timer configuration, this register ’s contents are ignored and GPTMTAMR is used. 190 Preliminary November 30, 2007 LM3S2016 Microcontroller Register 4: GPTM Control (GPTMCTL), offset 0x00C This register is used alongside the GPTMCFG and GMTMTnMR registers to fine-tune the timer configuration, and to enable other features such as timer stall and the output trigger. The output trigger can be used to initiate transfers on the ADC module. GPTM Control (GPTMCTL) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Offset 0x00C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 reserved RO 0 RO 0 11 RO 0 10 RO 0 9 TBSTALL R/W 0 RO 0 8 TBEN R/W 0 RO 0 7 RO 0 6 RO 0 5 TAOTE R/W 0 RO 0 4 RTCEN R/W 0 RO 0 3 RO 0 2 RO 0 1 TASTALL R/W 0 RO 0 0 TAEN R/W 0 reserved TBPWML TBOTE Type Reset RO 0 R/W 0 R/W 0 TBEVENT R/W 0 R/W 0 reserved TAPWML RO 0 R/W 0 TAEVENT R/W 0 R/W 0 Bit/Field 31:15 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPTM TimerB PWM Output Level The TBPWML values are defined as follows: Value Description 0 1 Output is unaffected. Output is inverted. 14 TBPWML R/W 0 13 TBOTE R/W 0 GPTM TimerB Output Trigger Enable The TBOTE values are defined as follows: Value Description 0 1 The output TimerB trigger is disabled. The output TimerB trigger is enabled. 12 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPTM TimerB Event Mode The TBEVENT values are defined as follows: Value Description 0x0 Positive edge. 0x1 Negative edge. 0x2 Reserved 0x3 Both edges. 11:10 TBEVENT R/W 0x0 November 30, 2007 Preliminary 191 General-Purpose Timers Bit/Field 9 Name TBSTALL Type R/W Reset 0 Description GPTM TimerB Stall Enable The TBSTALL values are defined as follows: Value Description 0 1 TimerB stalling is disabled. TimerB stalling is enabled. 8 TBEN R/W 0 GPTM TimerB Enable The TBEN values are defined as follows: Value Description 0 1 TimerB is disabled. TimerB is enabled and begins counting or the capture logic is enabled based on the GPTMCFG register. 7 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPTM TimerA PWM Output Level The TAPWML values are defined as follows: Value Description 0 1 Output is unaffected. Output is inverted. 6 TAPWML R/W 0 5 TAOTE R/W 0 GPTM TimerA Output Trigger Enable The TAOTE values are defined as follows: Value Description 0 1 The output TimerA trigger is disabled. The output TimerA trigger is enabled. 4 RTCEN R/W 0 GPTM RTC Enable The RTCEN values are defined as follows: Value Description 0 1 RTC counting is disabled. RTC counting is enabled. 192 Preliminary November 30, 2007 LM3S2016 Microcontroller Bit/Field 3:2 Name TAEVENT Type R/W Reset 0x0 Description GPTM TimerA Event Mode The TAEVENT values are defined as follows: Value Description 0x0 Positive edge. 0x1 Negative edge. 0x2 Reserved 0x3 Both edges. 1 TASTALL R/W 0 GPTM TimerA Stall Enable The TASTALL values are defined as follows: Value Description 0 1 TimerA stalling is disabled. TimerA stalling is enabled. 0 TAEN R/W 0 GPTM TimerA Enable The TAEN values are defined as follows: Value Description 0 1 TimerA is disabled. TimerA is enabled and begins counting or the capture logic is enabled based on the GPTMCFG register. November 30, 2007 Preliminary 193 General-Purpose Timers Register 5: GPTM Interrupt Mask (GPTMIMR), offset 0x018 This register allows software to enable/disable GPTM controller-level interrupts. Writing a 1 enables the interrupt, while writing a 0 disables it. GPTM Interrupt Mask (GPTMIMR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Offset 0x018 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 12 RO 0 11 RO 0 10 CBEIM R/W 0 RO 0 9 CBMIM R/W 0 RO 0 8 TBTOIM R/W 0 RO 0 RO 0 7 RO 0 6 reserved RO 0 RO 0 RO 0 RO 0 5 RO 0 4 RO 0 3 RTCIM R/W 0 RO 0 2 CAEIM R/W 0 RO 0 1 CAMIM R/W 0 RO 0 0 TATOIM R/W 0 Bit/Field 31:11 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPTM CaptureB Event Interrupt Mask The CBEIM values are defined as follows: Value Description 0 1 Interrupt is disabled. Interrupt is enabled. 10 CBEIM R/W 0 9 CBMIM R/W 0 GPTM CaptureB Match Interrupt Mask The CBMIM values are defined as follows: Value Description 0 1 Interrupt is disabled. Interrupt is enabled. 8 TBTOIM R/W 0 GPTM TimerB Time-Out Interrupt Mask The TBTOIM values are defined as follows: Value Description 0 1 Interrupt is disabled. Interrupt is enabled. 7:4 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 194 Preliminary November 30, 2007 LM3S2016 Microcontroller Bit/Field 3 Name RTCIM Type R/W Reset 0 Description GPTM RTC Interrupt Mask The RTCIM values are defined as follows: Value Description 0 1 Interrupt is disabled. Interrupt is enabled. 2 CAEIM R/W 0 GPTM CaptureA Event Interrupt Mask The CAEIM values are defined as follows: Value Description 0 1 Interrupt is disabled. Interrupt is enabled. 1 CAMIM R/W 0 GPTM CaptureA Match Interrupt Mask The CAMIM values are defined as follows: Value Description 0 1 Interrupt is disabled. Interrupt is enabled. 0 TATOIM R/W 0 GPTM TimerA Time-Out Interrupt Mask The TATOIM values are defined as follows: Value Description 0 1 Interrupt is disabled. Interrupt is enabled. November 30, 2007 Preliminary 195 General-Purpose Timers Register 6: GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C This register shows the state of the GPTM's internal interrupt signal. These bits are set whether or not the interrupt is masked in the GPTMIMR register. Each bit can be cleared by writing a 1 to its corresponding bit in GPTMICR. GPTM Raw Interrupt Status (GPTMRIS) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Offset 0x01C Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 reserved RO 0 RO 0 RO 0 RO 0 RO 0 5 RO 0 4 RO 0 3 RTCRIS RO 0 RO 0 2 RO 0 1 RO 0 0 CBERIS CBMRIS TBTORIS RO 0 RO 0 RO 0 CAERIS CAMRIS TATORIS RO 0 RO 0 RO 0 Bit/Field 31:11 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPTM CaptureB Event Raw Interrupt This is the CaptureB Event interrupt status prior to masking. 10 CBERIS RO 0 9 CBMRIS RO 0 GPTM CaptureB Match Raw Interrupt This is the CaptureB Match interrupt status prior to masking. 8 TBTORIS RO 0 GPTM TimerB Time-Out Raw Interrupt This is the TimerB time-out interrupt status prior to masking. 7:4 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPTM RTC Raw Interrupt This is the RTC Event interrupt status prior to masking. 3 RTCRIS RO 0 2 CAERIS RO 0 GPTM CaptureA Event Raw Interrupt This is the CaptureA Event interrupt status prior to masking. 1 CAMRIS RO 0 GPTM CaptureA Match Raw Interrupt This is the CaptureA Match interrupt status prior to masking. 0 TATORIS RO 0 GPTM TimerA Time-Out Raw Interrupt This the TimerA time-out interrupt status prior to masking. 196 Preliminary November 30, 2007 LM3S2016 Microcontroller Register 7: GPTM Masked Interrupt Status (GPTMMIS), offset 0x020 This register show the state of the GPTM's controller-level interrupt. If an interrupt is unmasked in GPTMIMR, and there is an event that causes the interrupt to be asserted, the corresponding bit is set in this register. All bits are cleared by writing a 1 to the corresponding bit in GPTMICR. GPTM Masked Interrupt Status (GPTMMIS) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Offset 0x020 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 reserved RO 0 RO 0 RO 0 RO 0 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 CBEMIS CBMMIS TBTOMIS RO 0 RO 0 RO 0 RTCMIS CAEMIS CAMMIS TATOMIS RO 0 RO 0 RO 0 RO 0 Bit/Field 31:11 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPTM CaptureB Event Masked Interrupt This is the CaptureB event interrupt status after masking. 10 CBEMIS RO 0 9 CBMMIS RO 0 GPTM CaptureB Match Masked Interrupt This is the CaptureB match interrupt status after masking. 8 TBTOMIS RO 0 GPTM TimerB Time-Out Masked Interrupt This is the TimerB time-out interrupt status after masking. 7:4 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPTM RTC Masked Interrupt This is the RTC event interrupt status after masking. 3 RTCMIS RO 0 2 CAEMIS RO 0 GPTM CaptureA Event Masked Interrupt This is the CaptureA event interrupt status after masking. 1 CAMMIS RO 0 GPTM CaptureA Match Masked Interrupt This is the CaptureA match interrupt status after masking. 0 TATOMIS RO 0 GPTM TimerA Time-Out Masked Interrupt This is the TimerA time-out interrupt status after masking. November 30, 2007 Preliminary 197 General-Purpose Timers Register 8: GPTM Interrupt Clear (GPTMICR), offset 0x024 This register is used to clear the status bits in the GPTMRIS and GPTMMIS registers. Writing a 1 to a bit clears the corresponding bit in the GPTMRIS and GPTMMIS registers. GPTM Interrupt Clear (GPTMICR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Offset 0x024 Type W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 reserved RO 0 RO 0 RO 0 RO 0 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 CBECINT CBMCINT TBTOCINT W1C 0 W1C 0 W1C 0 RTCCINT CAECINT CAMCINT TATOCINT W1C 0 W1C 0 W1C 0 W1C 0 Bit/Field 31:11 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPTM CaptureB Event Interrupt Clear The CBECINT values are defined as follows: Value Description 0 1 The interrupt is unaffected. The interrupt is cleared. 10 CBECINT W1C 0 9 CBMCINT W1C 0 GPTM CaptureB Match Interrupt Clear The CBMCINT values are defined as follows: Value Description 0 1 The interrupt is unaffected. The interrupt is cleared. 8 TBTOCINT W1C 0 GPTM TimerB Time-Out Interrupt Clear The TBTOCINT values are defined as follows: Value Description 0 1 The interrupt is unaffected. The interrupt is cleared. 7:4 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 198 Preliminary November 30, 2007 LM3S2016 Microcontroller Bit/Field 3 Name RTCCINT Type W1C Reset 0 Description GPTM RTC Interrupt Clear The RTCCINT values are defined as follows: Value Description 0 1 The interrupt is unaffected. The interrupt is cleared. 2 CAECINT W1C 0 GPTM CaptureA Event Interrupt Clear The CAECINT values are defined as follows: Value Description 0 1 The interrupt is unaffected. The interrupt is cleared. 1 CAMCINT W1C 0 GPTM CaptureA Match Raw Interrupt This is the CaptureA match interrupt status after masking. 0 TATOCINT W1C 0 GPTM TimerA Time-Out Raw Interrupt The TATOCINT values are defined as follows: Value Description 0 1 The interrupt is unaffected. The interrupt is cleared. November 30, 2007 Preliminary 199 General-Purpose Timers Register 9: GPTM TimerA Interval Load (GPTMTAILR), offset 0x028 This register is used to load the starting count value into the timer. When GPTM is configured to one of the 32-bit modes, GPTMTAILR appears as a 32-bit register (the upper 16-bits correspond to the contents of the GPTM TimerB Interval Load (GPTMTBILR) register). In 16-bit mode, the upper 16 bits of this register read as 0s and have no effect on the state of GPTMTBILR. GPTM TimerA Interval Load (GPTMTAILR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Offset 0x028 Type R/W, reset 0x0000.FFFF (16-bit mode) and 0xFFFF.FFFF (32-bit mode) 31 30 29 28 27 26 25 24 TAILRH Type Reset R/W 0 15 R/W 1 14 R/W 1 13 R/W 0 12 R/W 1 11 R/W 0 10 R/W 1 9 R/W 1 8 TAILRL Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 7 R/W 1 6 R/W 0 5 R/W 1 4 R/W 1 3 R/W 1 2 R/W 1 1 R/W 0 0 23 22 21 20 19 18 17 16 Bit/Field 31:16 Name TAILRH Type R/W Reset Description 0xFFFF GPTM TimerA Interval Load Register High (32-bit mode) 0x0000 (16-bit When configured for 32-bit mode via the GPTMCFG register, the GPTM TimerB Interval Load (GPTMTBILR) register loads this value on a mode) write. A read returns the current value of GPTMTBILR. In 16-bit mode, this field reads as 0 and does not have an effect on the state of GPTMTBILR. 15:0 TAILRL R/W 0xFFFF GPTM TimerA Interval Load Register Low For both 16- and 32-bit modes, writing this field loads the counter for TimerA. A read returns the current value of GPTMTAILR. 200 Preliminary November 30, 2007 LM3S2016 Microcontroller Register 10: GPTM TimerB Interval Load (GPTMTBILR), offset 0x02C This register is used to load the starting count value into TimerB. When the GPTM is configured to a 32-bit mode, GPTMTBILR returns the current value of TimerB and ignores writes. GPTM TimerB Interval Load (GPTMTBILR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Offset 0x02C Type R/W, reset 0x0000.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 TBILRL Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 Bit/Field 31:16 Name reserved Type RO Reset 0x0000 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPTM TimerB Interval Load Register When the GPTM is not configured as a 32-bit timer, a write to this field updates GPTMTBILR. In 32-bit mode, writes are ignored, and reads return the current value of GPTMTBILR. 15:0 TBILRL R/W 0xFFFF November 30, 2007 Preliminary 201 General-Purpose Timers Register 11: GPTM TimerA Match (GPTMTAMATCHR), offset 0x030 This register is used in 32-bit Real-Time Clock mode and 16-bit PWM and Input Edge Count modes. GPTM TimerA Match (GPTMTAMATCHR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Offset 0x030 Type R/W, reset 0x0000.FFFF (16-bit mode) and 0xFFFF.FFFF (32-bit mode) 31 30 29 28 27 26 25 24 TAMRH Type Reset R/W 0 15 R/W 1 14 R/W 1 13 R/W 0 12 R/W 1 11 R/W 0 10 R/W 1 9 R/W 1 8 TAMRL Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 7 R/W 1 6 R/W 0 5 R/W 1 4 R/W 1 3 R/W 1 2 R/W 1 1 R/W 0 0 23 22 21 20 19 18 17 16 Bit/Field 31:16 Name TAMRH Type R/W Reset Description 0xFFFF GPTM TimerA Match Register High (32-bit mode) 0x0000 (16-bit When configured for 32-bit Real-Time Clock (RTC) mode via the GPTMCFG register, this value is compared to the upper half of mode) GPTMTAR, to determine match events. In 16-bit mode, this field reads as 0 and does not have an effect on the state of GPTMTBMATCHR. 15:0 TAMRL R/W 0xFFFF GPTM TimerA Match Register Low When configured for 32-bit Real-Time Clock (RTC) mode via the GPTMCFG register, this value is compared to the lower half of GPTMTAR, to determine match events. When configured for PWM mode, this value along with GPTMTAILR, determines the duty cycle of the output PWM signal. When configured for Edge Count mode, this value along with GPTMTAILR, determines how many edge events are counted. The total number of edge events counted is equal to the value in GPTMTAILR minus this value. 202 Preliminary November 30, 2007 LM3S2016 Microcontroller Register 12: GPTM TimerB Match (GPTMTBMATCHR), offset 0x034 This register is used in 32-bit Real-Time Clock mode and 16-bit PWM and Input Edge Count modes. GPTM TimerB Match (GPTMTBMATCHR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Offset 0x034 Type R/W, reset 0x0000.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 TBMRL Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 Bit/Field 31:16 Name reserved Type RO Reset 0x0000 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPTM TimerB Match Register Low When configured for PWM mode, this value along with GPTMTBILR, determines the duty cycle of the output PWM signal. When configured for Edge Count mode, this value along with GPTMTBILR, determines how many edge events are counted. The total number of edge events counted is equal to the value in GPTMTBILR minus this value. 15:0 TBMRL R/W 0xFFFF November 30, 2007 Preliminary 203 General-Purpose Timers Register 13: GPTM TimerA Prescale (GPTMTAPR), offset 0x038 This register allows software to extend the range of the 16-bit timers when operating in one-shot or periodic mode. GPTM TimerA Prescale (GPTMTAPR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Offset 0x038 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 TAPSR RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPTM TimerA Prescale The register loads this value on a write. A read returns the current value of the register. Refer to Table 9-2 on page 178 for more details and an example. 7:0 TAPSR R/W 0x00 204 Preliminary November 30, 2007 LM3S2016 Microcontroller Register 14: GPTM TimerB Prescale (GPTMTBPR), offset 0x03C This register allows software to extend the range of the 16-bit timers when operating in one-shot or periodic mode. GPTM TimerB Prescale (GPTMTBPR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Offset 0x03C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 TBPSR RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPTM TimerB Prescale The register loads this value on a write. A read returns the current value of this register. Refer to Table 9-2 on page 178 for more details and an example. 7:0 TBPSR R/W 0x00 November 30, 2007 Preliminary 205 General-Purpose Timers Register 15: GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040 This register effectively extends the range of GPTMTAMATCHR to 24 bits when operating in 16-bit one-shot or periodic mode. GPTM TimerA Prescale Match (GPTMTAPMR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Offset 0x040 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 TAPSMR RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPTM TimerA Prescale Match This value is used alongside GPTMTAMATCHR to detect timer match events while using a prescaler. 7:0 TAPSMR R/W 0x00 206 Preliminary November 30, 2007 LM3S2016 Microcontroller Register 16: GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044 This register effectively extends the range of GPTMTBMATCHR to 24 bits when operating in 16-bit one-shot or periodic mode. GPTM TimerB Prescale Match (GPTMTBPMR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Offset 0x044 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 TBPSMR RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPTM TimerB Prescale Match This value is used alongside GPTMTBMATCHR to detect timer match events while using a prescaler. 7:0 TBPSMR R/W 0x00 November 30, 2007 Preliminary 207 General-Purpose Timers Register 17: GPTM TimerA (GPTMTAR), offset 0x048 This register shows the current value of the TimerA counter in all cases except for Input Edge Count mode. When in this mode, this register contains the time at which the last edge event took place. GPTM TimerA (GPTMTAR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Offset 0x048 Type RO, reset 0x0000.FFFF (16-bit mode) and 0xFFFF.FFFF (32-bit mode) 31 30 29 28 27 26 25 24 TARH Type Reset RO 0 15 RO 1 14 RO 1 13 RO 0 12 RO 1 11 RO 0 10 RO 1 9 RO 1 8 TARL Type Reset RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 7 RO 1 6 RO 0 5 RO 1 4 RO 1 3 RO 1 2 RO 1 1 RO 0 0 23 22 21 20 19 18 17 16 Bit/Field 31:16 Name TARH Type RO Reset Description 0xFFFF GPTM TimerA Register High (32-bit mode) 0x0000 (16-bit If the GPTMCFG is in a 32-bit mode, TimerB value is read. If the GPTMCFG is in a 16-bit mode, this is read as zero. mode) 0xFFFF GPTM TimerA Register Low A read returns the current value of the GPTM TimerA Count Register, except in Input Edge Count mode, when it returns the timestamp from the last edge event. 15:0 TARL RO 208 Preliminary November 30, 2007 LM3S2016 Microcontroller Register 18: GPTM TimerB (GPTMTBR), offset 0x04C This register shows the current value of the TimerB counter in all cases except for Input Edge Count mode. When in this mode, this register contains the time at which the last edge event took place. GPTM TimerB (GPTMTBR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Offset 0x04C Type RO, reset 0x0000.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 TBRL Type Reset RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 Bit/Field 31:16 Name reserved Type RO Reset 0x0000 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPTM TimerB A read returns the current value of the GPTM TimerB Count Register, except in Input Edge Count mode, when it returns the timestamp from the last edge event. 15:0 TBRL RO 0xFFFF November 30, 2007 Preliminary 209 Watchdog Timer 10 Watchdog Timer A watchdog timer can generate nonmaskable interrupts (NMIs) or a reset when a time-out value is reached. The watchdog timer is used to regain control when a system has failed due to a software error or due to the failure of an external device to respond in the expected way. The Stellaris Watchdog Timer module consists of a 32-bit down counter, a programmable load register, interrupt generation logic, a locking register, and user-enabled stalling. The Watchdog Timer can be configured to generate an interrupt to the controller on its first time-out, and to generate a reset signal on its second time-out. Once the Watchdog Timer has been configured, the lock register can be written to prevent the timer configuration from being inadvertently altered. ® 10.1 Block Diagram Figure 10-1. WDT Module Block Diagram Control / Clock / Interrupt Generation WDTCTL WDTICR Interrupt WDTRIS WDTMIS WDTLOCK System Clock WDTTEST Comparator WDTVALUE 32-Bit Down Counter 0x00000000 WDTLOAD Identification Registers WDTPCellID0 WDTPCellID1 WDTPCellID2 WDTPCellID3 WDTPeriphID0 WDTPeriphID1 WDTPeriphID2 WDTPeriphID3 WDTPeriphID4 WDTPeriphID5 WDTPeriphID6 WDTPeriphID7 10.2 Functional Description The Watchdog Timer module generates the first time-out signal when the 32-bit counter reaches the zero state after being enabled; enabling the counter also enables the watchdog timer interrupt. After the first time-out event, the 32-bit counter is re-loaded with the value of the Watchdog Timer Load (WDTLOAD) register, and the timer resumes counting down from that value. Once the 210 Preliminary November 30, 2007 LM3S2016 Microcontroller Watchdog Timer has been configured, the Watchdog Timer Lock (WDTLOCK) register is written, which prevents the timer configuration from being inadvertently altered by software. If the timer counts down to its zero state again before the first time-out interrupt is cleared, and the reset signal has been enabled (via the WatchdogResetEnable function), the Watchdog timer asserts its reset signal to the system. If the interrupt is cleared before the 32-bit counter reaches its second time-out, the 32-bit counter is loaded with the value in the WDTLOAD register, and counting resumes from that value. If WDTLOAD is written with a new value while the Watchdog Timer counter is counting, then the counter is loaded with the new value and continues counting. Writing to WDTLOAD does not clear an active interrupt. An interrupt must be specifically cleared by writing to the Watchdog Interrupt Clear (WDTICR) register. The Watchdog module interrupt and reset generation can be enabled or disabled as required. When the interrupt is re-enabled, the 32-bit counter is preloaded with the load register value and not its last state. 10.3 Initialization and Configuration To use the WDT, its peripheral clock must be enabled by setting the WDT bit in the RCGC0 register. The Watchdog Timer is configured using the following sequence: 1. Load the WDTLOAD register with the desired timer load value. 2. If the Watchdog is configured to trigger system resets, set the RESEN bit in the WDTCTL register. 3. Set the INTEN bit in the WDTCTL register to enable the Watchdog and lock the control register. If software requires that all of the watchdog registers are locked, the Watchdog Timer module can be fully locked by writing any value to the WDTLOCK register. To unlock the Watchdog Timer, write a value of 0x1ACC.E551. 10.4 Register Map Table 10-1 on page 211 lists the Watchdog registers. The offset listed is a hexadecimal increment to the register ’s address, relative to the Watchdog Timer base address of 0x4000.0000. Table 10-1. Watchdog Timer Register Map Offset 0x000 0x004 0x008 0x00C 0x010 0x014 0x418 0xC00 Name WDTLOAD WDTVALUE WDTCTL WDTICR WDTRIS WDTMIS WDTTEST WDTLOCK Type R/W RO R/W WO RO RO R/W R/W Reset 0xFFFF.FFFF 0xFFFF.FFFF 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 Description Watchdog Load Watchdog Value Watchdog Control Watchdog Interrupt Clear Watchdog Raw Interrupt Status Watchdog Masked Interrupt Status Watchdog Test Watchdog Lock See page 213 214 215 216 217 218 219 220 November 30, 2007 Preliminary 211 Watchdog Timer Offset 0xFD0 0xFD4 0xFD8 0xFDC 0xFE0 0xFE4 0xFE8 0xFEC 0xFF0 0xFF4 0xFF8 0xFFC Name WDTPeriphID4 WDTPeriphID5 WDTPeriphID6 WDTPeriphID7 WDTPeriphID0 WDTPeriphID1 WDTPeriphID2 WDTPeriphID3 WDTPCellID0 WDTPCellID1 WDTPCellID2 WDTPCellID3 Type RO RO RO RO RO RO RO RO RO RO RO RO Reset 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0005 0x0000.0018 0x0000.0018 0x0000.0001 0x0000.000D 0x0000.00F0 0x0000.0005 0x0000.00B1 Description Watchdog Peripheral Identification 4 Watchdog Peripheral Identification 5 Watchdog Peripheral Identification 6 Watchdog Peripheral Identification 7 Watchdog Peripheral Identification 0 Watchdog Peripheral Identification 1 Watchdog Peripheral Identification 2 Watchdog Peripheral Identification 3 Watchdog PrimeCell Identification 0 Watchdog PrimeCell Identification 1 Watchdog PrimeCell Identification 2 Watchdog PrimeCell Identification 3 See page 221 222 223 224 225 226 227 228 229 230 231 232 10.5 Register Descriptions The remainder of this section lists and describes the WDT registers, in numerical order by address offset. 212 Preliminary November 30, 2007 LM3S2016 Microcontroller Register 1: Watchdog Load (WDTLOAD), offset 0x000 This register is the 32-bit interval value used by the 32-bit counter. When this register is written, the value is immediately loaded and the counter restarts counting down from the new value. If the WDTLOAD register is loaded with 0x0000.0000, an interrupt is immediately generated. Watchdog Load (WDTLOAD) Base 0x4000.0000 Offset 0x000 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 WDTLoad Type Reset R/W 1 15 R/W 1 14 R/W 1 13 R/W 1 12 R/W 1 11 R/W 1 10 R/W 1 9 R/W 1 8 R/W 1 7 R/W 1 6 R/W 1 5 R/W 1 4 R/W 1 3 R/W 1 2 R/W 1 1 R/W 1 0 WDTLoad Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 Bit/Field 31:0 Name WDTLoad Type R/W Reset Description 0xFFFF.FFFF Watchdog Load Value November 30, 2007 Preliminary 213 Watchdog Timer Register 2: Watchdog Value (WDTVALUE), offset 0x004 This register contains the current count value of the timer. Watchdog Value (WDTVALUE) Base 0x4000.0000 Offset 0x004 Type RO, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 WDTValue Type Reset RO 1 15 RO 1 14 RO 1 13 RO 1 12 RO 1 11 RO 1 10 RO 1 9 RO 1 8 RO 1 7 RO 1 6 RO 1 5 RO 1 4 RO 1 3 RO 1 2 RO 1 1 RO 1 0 WDTValue Type Reset RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 Bit/Field 31:0 Name WDTValue Type RO Reset Description 0xFFFF.FFFF Watchdog Value Current value of the 32-bit down counter. 214 Preliminary November 30, 2007 LM3S2016 Microcontroller Register 3: Watchdog Control (WDTCTL), offset 0x008 This register is the watchdog control register. The watchdog timer can be configured to generate a reset signal (on second time-out) or an interrupt on time-out. When the watchdog interrupt has been enabled, all subsequent writes to the control register are ignored. The only mechanism that can re-enable writes is a hardware reset. Watchdog Control (WDTCTL) Base 0x4000.0000 Offset 0x008 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RESEN R/W 0 RO 0 0 INTEN R/W 0 Bit/Field 31:2 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Watchdog Reset Enable The RESEN values are defined as follows: Value Description 0 1 Disabled. Enable the Watchdog module reset output. 1 RESEN R/W 0 0 INTEN R/W 0 Watchdog Interrupt Enable The INTEN values are defined as follows: Value Description 0 1 Interrupt event disabled (once this bit is set, it can only be cleared by a hardware reset). Interrupt event enabled. Once enabled, all writes are ignored. November 30, 2007 Preliminary 215 Watchdog Timer Register 4: Watchdog Interrupt Clear (WDTICR), offset 0x00C This register is the interrupt clear register. A write of any value to this register clears the Watchdog interrupt and reloads the 32-bit counter from the WDTLOAD register. Value for a read or reset is indeterminate. Watchdog Interrupt Clear (WDTICR) Base 0x4000.0000 Offset 0x00C Type WO, reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 WDTIntClr Type Reset WO 15 WO 14 WO 13 WO 12 WO 11 WO 10 WO 9 WO 8 WO 7 WO 6 WO 5 WO 4 WO 3 WO 2 WO 1 WO 0 WDTIntClr Type Reset WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO - Bit/Field 31:0 Name WDTIntClr Type WO Reset - Description Watchdog Interrupt Clear 216 Preliminary November 30, 2007 LM3S2016 Microcontroller Register 5: Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 This register is the raw interrupt status register. Watchdog interrupt events can be monitored via this register if the controller interrupt is masked. Watchdog Raw Interrupt Status (WDTRIS) Base 0x4000.0000 Offset 0x010 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 WDTRIS RO 0 Bit/Field 31:1 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Watchdog Raw Interrupt Status Gives the raw interrupt state (prior to masking) of WDTINTR. 0 WDTRIS RO 0 November 30, 2007 Preliminary 217 Watchdog Timer Register 6: Watchdog Masked Interrupt Status (WDTMIS), offset 0x014 This register is the masked interrupt status register. The value of this register is the logical AND of the raw interrupt bit and the Watchdog interrupt enable bit. Watchdog Masked Interrupt Status (WDTMIS) Base 0x4000.0000 Offset 0x014 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 WDTMIS RO 0 Bit/Field 31:1 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Watchdog Masked Interrupt Status Gives the masked interrupt state (after masking) of the WDTINTR interrupt. 0 WDTMIS RO 0 218 Preliminary November 30, 2007 LM3S2016 Microcontroller Register 7: Watchdog Test (WDTTEST), offset 0x418 This register provides user-enabled stalling when the microcontroller asserts the CPU halt flag during debug. Watchdog Test (WDTTEST) Base 0x4000.0000 Offset 0x418 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 11 RO 0 10 RO 0 9 RO 0 8 STALL R/W 0 RO 0 RO 0 RO 0 RO 0 7 RO 0 6 RO 0 5 RO 0 4 reserved RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 3 RO 0 2 RO 0 1 RO 0 0 Bit/Field 31:9 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Watchdog Stall Enable When set to 1, if the Stellaris microcontroller is stopped with a debugger, the watchdog timer stops counting. Once the microcontroller is restarted, the watchdog timer resumes counting. ® 8 STALL R/W 0 7:0 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. November 30, 2007 Preliminary 219 Watchdog Timer Register 8: Watchdog Lock (WDTLOCK), offset 0xC00 Writing 0x1ACC.E551 to the WDTLOCK register enables write access to all other registers. Writing any other value to the WDTLOCK register re-enables the locked state for register writes to all the other registers. Reading the WDTLOCK register returns the lock status rather than the 32-bit value written. Therefore, when write accesses are disabled, reading the WDTLOCK register returns 0x0000.0001 (when locked; otherwise, the returned value is 0x0000.0000 (unlocked)). Watchdog Lock (WDTLOCK) Base 0x4000.0000 Offset 0xC00 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 WDTLock Type Reset R/W 0 15 R/W 0 14 R/W 0 13 R/W 0 12 R/W 0 11 R/W 0 10 R/W 0 9 R/W 0 8 R/W 0 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 WDTLock Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field 31:0 Name WDTLock Type R/W Reset 0x0000 Description Watchdog Lock A write of the value 0x1ACC.E551 unlocks the watchdog registers for write access. A write of any other value reapplies the lock, preventing any register updates. A read of this register returns the following values: Value Description 0x0000.0001 Locked 0x0000.0000 Unlocked 220 Preliminary November 30, 2007 LM3S2016 Microcontroller Register 9: Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0 The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 4 (WDTPeriphID4) Base 0x4000.0000 Offset 0xFD0 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 PID4 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. WDT Peripheral ID Register[7:0] 7:0 PID4 RO 0x00 November 30, 2007 Preliminary 221 Watchdog Timer Register 10: Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4 The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 5 (WDTPeriphID5) Base 0x4000.0000 Offset 0xFD4 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 PID5 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. WDT Peripheral ID Register[15:8] 7:0 PID5 RO 0x00 222 Preliminary November 30, 2007 LM3S2016 Microcontroller Register 11: Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8 The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 6 (WDTPeriphID6) Base 0x4000.0000 Offset 0xFD8 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 PID6 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. WDT Peripheral ID Register[23:16] 7:0 PID6 RO 0x00 November 30, 2007 Preliminary 223 Watchdog Timer Register 12: Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 7 (WDTPeriphID7) Base 0x4000.0000 Offset 0xFDC Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 PID7 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. WDT Peripheral ID Register[31:24] 7:0 PID7 RO 0x00 224 Preliminary November 30, 2007 LM3S2016 Microcontroller Register 13: Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 0 (WDTPeriphID0) Base 0x4000.0000 Offset 0xFE0 Type RO, reset 0x0000.0005 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 PID0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 0 RO 1 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Watchdog Peripheral ID Register[7:0] 7:0 PID0 RO 0x05 November 30, 2007 Preliminary 225 Watchdog Timer Register 14: Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 1 (WDTPeriphID1) Base 0x4000.0000 Offset 0xFE4 Type RO, reset 0x0000.0018 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 PID1 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 1 RO 0 RO 0 RO 0 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Watchdog Peripheral ID Register[15:8] 7:0 PID1 RO 0x18 226 Preliminary November 30, 2007 LM3S2016 Microcontroller Register 15: Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 2 (WDTPeriphID2) Base 0x4000.0000 Offset 0xFE8 Type RO, reset 0x0000.0018 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 PID2 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 1 RO 0 RO 0 RO 0 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Watchdog Peripheral ID Register[23:16] 7:0 PID2 RO 0x18 November 30, 2007 Preliminary 227 Watchdog Timer Register 16: Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 3 (WDTPeriphID3) Base 0x4000.0000 Offset 0xFEC Type RO, reset 0x0000.0001 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 PID3 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Watchdog Peripheral ID Register[31:24] 7:0 PID3 RO 0x01 228 Preliminary November 30, 2007 LM3S2016 Microcontroller Register 17: Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0 The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog PrimeCell Identification 0 (WDTPCellID0) Base 0x4000.0000 Offset 0xFF0 Type RO, reset 0x0000.000D 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 CID0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 1 RO 0 RO 1 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Watchdog PrimeCell ID Register[7:0] 7:0 CID0 RO 0x0D November 30, 2007 Preliminary 229 Watchdog Timer Register 18: Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4 The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog PrimeCell Identification 1 (WDTPCellID1) Base 0x4000.0000 Offset 0xFF4 Type RO, reset 0x0000.00F0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 CID1 RO 0 RO 0 RO 0 RO 1 RO 1 RO 1 RO 1 RO 0 RO 0 RO 0 RO 0 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Watchdog PrimeCell ID Register[15:8] 7:0 CID1 RO 0xF0 230 Preliminary November 30, 2007 LM3S2016 Microcontroller Register 19: Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8 The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog PrimeCell Identification 2 (WDTPCellID2) Base 0x4000.0000 Offset 0xFF8 Type RO, reset 0x0000.0005 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 CID2 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 0 RO 1 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Watchdog PrimeCell ID Register[23:16] 7:0 CID2 RO 0x05 November 30, 2007 Preliminary 231 Watchdog Timer Register 20: Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog PrimeCell Identification 3 (WDTPCellID3) Base 0x4000.0000 Offset 0xFFC Type RO, reset 0x0000.00B1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 CID3 RO 0 RO 0 RO 0 RO 1 RO 0 RO 1 RO 1 RO 0 RO 0 RO 0 RO 1 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Watchdog PrimeCell ID Register[31:24] 7:0 CID3 RO 0xB1 232 Preliminary November 30, 2007 LM3S2016 Microcontroller 11 Analog-to-Digital Converter (ADC) An analog-to-digital converter (ADC) is a peripheral that converts a continuous analog voltage to a discrete digital number. The Stellaris ADC module features 10-bit conversion resolution and supports four input channels. The ADC module contains a programmable sequencer which allows for the sampling of multiple analog input sources without controller intervention. Each sample sequence provides flexible programming with fully configurable input source, trigger events, interrupt generation, and sequence priority. The Stellaris ADC provides the following features: ■ Four analog input channels ■ Single-ended and differential-input configurations ■ Sample rate of 500 thousand samples/second ■ Four programmable sample conversion sequences from one to eight entries long, with corresponding conversion result FIFOs ■ Flexible trigger control – Controller (software) – Timers – GPIO ■ Hardware averaging of up to 64 samples for improved accuracy ® ® November 30, 2007 Preliminary 233 Analog-to-Digital Converter (ADC) 11.1 Block Diagram Figure 11-1. ADC Module Block Diagram Trigger Events Comparator GPIO (PB4) Timer PWM Comparator GPIO (PB4) Timer PWM Comparator GPIO (PB4) Timer PWM Comparator GPIO (PB4) Timer PWM Control/Status SS3 ADCACTSS ADCOSTAT ADCUSTAT ADCSSPRI SS2 Sample Sequencer 1 ADCSSMUX1 ADCSSCTL1 SS1 ADCSSFSTAT1 Hardware Averager ADCSAC Sample Sequencer 0 ADCSSMUX0 ADCSSCTL0 ADCSSFSTAT0 Analog-to-Digital Converter Analog Inputs Sample Sequencer 2 SS0 ADCSSMUX2 ADCSSCTL2 ADCSSFSTAT2 ADCEMUX ADCPSSI Interrupt Control ADCIM ADCRIS ADCISC Sample Sequencer 3 ADCSSMUX3 ADCSSCTL3 ADCSSFSTAT3 FIFO Block ADCSSFIFO0 ADCSSFIFO1 ADCSSFIFO2 ADCSSFIFO3 SS0 Interrupt SS1 Interrupt SS2 Interrupt SS3 Interrupt 11.2 Functional Description The Stellaris ADC collects sample data by using a programmable sequence-based approach instead of the traditional single or double-sampling approach found on many ADC modules. Each sample sequence is a fully programmed series of consecutive (back-to-back) samples, allowing the ADC to collect data from multiple input sources without having to be re-configured or serviced by the controller. The programming of each sample in the sample sequence includes parameters such as the input source and mode (differential versus single-ended input), interrupt generation on sample completion, and the indicator for the last sample in the sequence. ® 11.2.1 Sample Sequencers The sampling control and data capture is handled by the Sample Sequencers. All of the sequencers are identical in implementation except for the number of samples that can be captured and the depth of the FIFO. Table 11-1 on page 234 shows the maximum number of samples that each Sequencer can capture and its corresponding FIFO depth. In this implementation, each FIFO entry is a 32-bit word, with the lower 10 bits containing the conversion result. Table 11-1. Samples and FIFO Depth of Sequencers Sequencer Number of Samples Depth of FIFO SS3 SS2 SS1 SS0 1 4 4 8 1 4 4 8 234 Preliminary November 30, 2007 LM3S2016 Microcontroller For a given sample sequence, each sample is defined by two 4-bit nibbles in the ADC Sample Sequence Input Multiplexer Select (ADCSSMUXn) and ADC Sample Sequence Control (ADCSSCTLn) registers, where "n" corresponds to the sequence number. The ADCSSMUXn nibbles select the input pin, while the ADCSSCTLn nibbles contain the sample control bits corresponding to parameters such as interrupt enable, end of sequence, and differential input mode. Sample Sequencers are enabled by setting the respective ASENn bit in the ADC Active Sample Sequencer (ADCACTSS) register, but can be configured before being enabled. When configuring a sample sequence, multiple uses of the same input pin within the same sequence is allowed. In the ADCSSCTLn register, the Interrupt Enable (IE) bits can be set for any combination of samples, allowing interrupts to be generated after every sample in the sequence if necessary. Also, the END bit can be set at any point within a sample sequence. For example, if Sequencer 0 is used, the END bit can be set in the nibble associated with the fifth sample, allowing Sequencer 0 to complete execution of the sample sequence after the fifth sample. After a sample sequence completes execution, the result data can be retrieved from the ADC Sample Sequence Result FIFO (ADCSSFIFOn) registers. The FIFOs are simple circular buffers that read a single address to "pop" result data. For software debug purposes, the positions of the FIFO head and tail pointers are visible in the ADC Sample Sequence FIFO Status (ADCSSFSTATn) registers along with FULL and EMPTY status flags. Overflow and underflow conditions are monitored using the ADCOSTAT and ADCUSTAT registers. 11.2.2 Module Control Outside of the Sample Sequencers, the remainder of the control logic is responsible for tasks such as interrupt generation, sequence prioritization, and trigger configuration. Most of the ADC control logic runs at the ADC clock rate of 14-18 MHz. The internal ADC divider is configured automatically by hardware when the system XTAL is selected. The automatic clock ® divider configuration targets 16.667 MHz operation for all Stellaris devices. 11.2.2.1 Interrupts The Sample Sequencers dictate the events that cause interrupts, but they don't have control over whether the interrupt is actually sent to the interrupt controller. The ADC module's interrupt signal is controlled by the state of the MASK bits in the ADC Interrupt Mask (ADCIM) register. Interrupt status can be viewed at two locations: the ADC Raw Interrupt Status (ADCRIS) register, which shows the raw status of a Sample Sequencer's interrupt signal, and the ADC Interrupt Status and Clear (ADCISC) register, which shows the logical AND of the ADCRIS register ’s INR bit and the ADCIM register ’s MASK bits. Interrupts are cleared by writing a 1 to the corresponding IN bit in ADCISC. 11.2.2.2 Prioritization When sampling events (triggers) happen concurrently, they are prioritized for processing by the values in the ADC Sample Sequencer Priority (ADCSSPRI) register. Valid priority values are in the range of 0-3, with 0 being the highest priority and 3 being the lowest. Multiple active Sample Sequencer units with the same priority do not provide consistent results, so software must ensure that all active Sample Sequencer units have a unique priority value. 11.2.2.3 Sampling Events Sample triggering for each Sample Sequencer is defined in the ADC Event Multiplexer Select ® (ADCEMUX) register. The external peripheral triggering sources vary by Stellaris family member, but all devices share the "Controller" and "Always" triggers. Software can initiate sampling by setting the CH bits in the ADC Processor Sample Sequence Initiate (ADCPSSI) register. November 30, 2007 Preliminary 235 Analog-to-Digital Converter (ADC) When using the "Always" trigger, care must be taken. If a sequence's priority is too high, it is possible to starve other lower priority sequences. 11.2.3 Hardware Sample Averaging Circuit Higher precision results can be generated using the hardware averaging circuit, however, the improved results are at the cost of throughput. Up to 64 samples can be accumulated and averaged to form a single data entry in the sequencer FIFO. Throughput is decreased proportionally to the number of samples in the averaging calculation. For example, if the averaging circuit is configured to average 16 samples, the throughput is decreased by a factor of 16. By default the averaging circuit is off and all data from the converter passes through to the sequencer FIFO. The averaging hardware is controlled by the ADC Sample Averaging Control (ADCSAC) register (see page 250). There is a single averaging circuit and all input channels receive the same amount of averaging whether they are single-ended or differential. 11.2.4 Analog-to-Digital Converter The converter itself generates a 10-bit output value for selected analog input. Special analog pads are used to minimize the distortion on the input. 11.2.5 Test Modes There is a user-available test mode that allows for loopback operation within the digital portion of the ADC module. This can be useful for debugging software without having to provide actual analog stimulus. This mode is available through the ADC Test Mode Loopback (ADCTMLB) register (see page 263). 11.3 Initialization and Configuration In order for the ADC module to be used, the PLL must be enabled and using a supported crystal frequency (see the RCC register). Using unsupported frequencies can cause faulty operation in the ADC module. 11.3.1 Module Initialization Initialization of the ADC module is a simple process with very few steps. The main steps include enabling the clock to the ADC and reconfiguring the Sample Sequencer priorities (if needed). The initialization sequence for the ADC is as follows: 1. Enable the ADC clock by writing a value of 0x0001.0000 to the RCGC1 register (see page 94). 2. If required by the application, reconfigure the Sample Sequencer priorities in the ADCSSPRI register. The default configuration has Sample Sequencer 0 with the highest priority, and Sample Sequencer 3 as the lowest priority. 11.3.2 Sample Sequencer Configuration Configuration of the Sample Sequencers is slightly more complex than the module initialization since each sample sequence is completely programmable. The configuration for each Sample Sequencer should be as follows: 1. Ensure that the Sample Sequencer is disabled by writing a 0 to the corresponding ASEN bit in the ADCACTSS register. Programming of the Sample Sequencers is allowed without having 236 Preliminary November 30, 2007 LM3S2016 Microcontroller them enabled. Disabling the Sequencer during programming prevents erroneous execution if a trigger event were to occur during the configuration process. 2. Configure the trigger event for the Sample Sequencer in the ADCEMUX register. 3. For each sample in the sample sequence, configure the corresponding input source in the ADCSSMUXn register. 4. For each sample in the sample sequence, configure the sample control bits in the corresponding nibble in the ADCSSCTLn register. When programming the last nibble, ensure that the END bit is set. Failure to set the END bit causes unpredictable behavior. 5. If interrupts are to be used, write a 1 to the corresponding MASK bit in the ADCIM register. 6. Enable the Sample Sequencer logic by writing a 1 to the corresponding ASEN bit in the ADCACTSS register. 11.4 Register Map Table 11-2 on page 237 lists the ADC registers. The offset listed is a hexadecimal increment to the register ’s address, relative to the ADC base address of 0x4003.8000. Table 11-2. ADC Register Map Offset 0x000 0x004 0x008 0x00C 0x010 0x014 0x018 0x020 0x028 0x030 0x040 0x044 0x048 0x04C 0x060 0x064 0x068 0x06C Name ADCACTSS ADCRIS ADCIM ADCISC ADCOSTAT ADCEMUX ADCUSTAT ADCSSPRI ADCPSSI ADCSAC ADCSSMUX0 ADCSSCTL0 ADCSSFIFO0 ADCSSFSTAT0 ADCSSMUX1 ADCSSCTL1 ADCSSFIFO1 ADCSSFSTAT1 Type R/W RO R/W R/W1C R/W1C R/W R/W1C R/W WO R/W R/W R/W RO RO R/W R/W RO RO Reset 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.3210 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0100 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0100 Description ADC Active Sample Sequencer ADC Raw Interrupt Status ADC Interrupt Mask ADC Interrupt Status and Clear ADC Overflow Status ADC Event Multiplexer Select ADC Underflow Status ADC Sample Sequencer Priority ADC Processor Sample Sequence Initiate ADC Sample Averaging Control ADC Sample Sequence Input Multiplexer Select 0 ADC Sample Sequence Control 0 ADC Sample Sequence Result FIFO 0 ADC Sample Sequence FIFO 0 Status ADC Sample Sequence Input Multiplexer Select 1 ADC Sample Sequence Control 1 ADC Sample Sequence Result FIFO 1 ADC Sample Sequence FIFO 1 Status See page 239 240 241 242 243 244 247 248 249 250 251 253 256 257 258 259 256 257 November 30, 2007 Preliminary 237 Analog-to-Digital Converter (ADC) Offset 0x080 0x084 0x088 0x08C 0x0A0 0x0A4 0x0A8 0x0AC 0x100 Name ADCSSMUX2 ADCSSCTL2 ADCSSFIFO2 ADCSSFSTAT2 ADCSSMUX3 ADCSSCTL3 ADCSSFIFO3 ADCSSFSTAT3 ADCTMLB Type R/W R/W RO RO R/W R/W RO RO R/W Reset 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0100 0x0000.0000 0x0000.0002 0x0000.0000 0x0000.0100 0x0000.0000 Description ADC Sample Sequence Input Multiplexer Select 2 ADC Sample Sequence Control 2 ADC Sample Sequence Result FIFO 2 ADC Sample Sequence FIFO 2 Status ADC Sample Sequence Input Multiplexer Select 3 ADC Sample Sequence Control 3 ADC Sample Sequence Result FIFO 3 ADC Sample Sequence FIFO 3 Status ADC Test Mode Loopback See page 258 259 256 257 261 262 256 257 263 11.5 Register Descriptions The remainder of this section lists and describes the ADC registers, in numerical order by address offset. 238 Preliminary November 30, 2007 LM3S2016 Microcontroller Register 1: ADC Active Sample Sequencer (ADCACTSS), offset 0x000 This register controls the activation of the Sample Sequencers. Each Sample Sequencer can be enabled/disabled independently. ADC Active Sample Sequencer (ADCACTSS) Base 0x4003.8000 Offset 0x000 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 ASEN3 R/W 0 RO 0 2 ASEN2 R/W 0 RO 0 1 ASEN1 R/W 0 RO 0 0 ASEN0 R/W 0 Bit/Field 31:4 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. ADC SS3 Enable Specifies whether Sample Sequencer 3 is enabled. If set, the sample sequence logic for Sequencer 3 is active. Otherwise, the Sequencer is inactive. 3 ASEN3 R/W 0 2 ASEN2 R/W 0 ADC SS2 Enable Specifies whether Sample Sequencer 2 is enabled. If set, the sample sequence logic for Sequencer 2 is active. Otherwise, the Sequencer is inactive. 1 ASEN1 R/W 0 ADC SS1 Enable Specifies whether Sample Sequencer 1 is enabled. If set, the sample sequence logic for Sequencer 1 is active. Otherwise, the Sequencer is inactive. 0 ASEN0 R/W 0 ADC SS0 Enable Specifies whether Sample Sequencer 0 is enabled. If set, the sample sequence logic for Sequencer 0 is active. Otherwise, the Sequencer is inactive. November 30, 2007 Preliminary 239 Analog-to-Digital Converter (ADC) Register 2: ADC Raw Interrupt Status (ADCRIS), offset 0x004 This register shows the status of the raw interrupt signal of each Sample Sequencer. These bits may be polled by software to look for interrupt conditions without having to generate controller interrupts. ADC Raw Interrupt Status (ADCRIS) Base 0x4003.8000 Offset 0x004 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 INR3 RO 0 RO 0 2 INR2 RO 0 RO 0 1 INR1 RO 0 RO 0 0 INR0 RO 0 Bit/Field 31:4 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SS3 Raw Interrupt Status Set by hardware when a sample with its respective ADCSSCTL3 IE bit has completed conversion. This bit is cleared by writing a 1 to the ADCISC IN3 bit. 3 INR3 RO 0 2 INR2 RO 0 SS2 Raw Interrupt Status Set by hardware when a sample with its respective ADCSSCTL2 IE bit has completed conversion. This bit is cleared by writing a 1 to the ADCISC IN2 bit. 1 INR1 RO 0 SS1 Raw Interrupt Status Set by hardware when a sample with its respective ADCSSCTL1 IE bit has completed conversion. This bit is cleared by writing a 1 to the ADCISC IN1 bit. 0 INR0 RO 0 SS0 Raw Interrupt Status Set by hardware when a sample with its respective ADCSSCTL0 IE bit has completed conversion. This bit is cleared by writing a 1 to the ADCISC IN0 bit. 240 Preliminary November 30, 2007 LM3S2016 Microcontroller Register 3: ADC Interrupt Mask (ADCIM), offset 0x008 This register controls whether the Sample Sequencer raw interrupt signals are promoted to controller interrupts. The raw interrupt signal for each Sample Sequencer can be masked independently. ADC Interrupt Mask (ADCIM) Base 0x4003.8000 Offset 0x008 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 MASK3 R/W 0 RO 0 2 MASK2 R/W 0 RO 0 1 MASK1 R/W 0 RO 0 0 MASK0 R/W 0 Bit/Field 31:4 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SS3 Interrupt Mask Specifies whether the raw interrupt signal from Sample Sequencer 3 (ADCRIS register INR3 bit) is promoted to a controller interrupt. If set, the raw interrupt signal is promoted to a controller interrupt. Otherwise, it is not. 3 MASK3 R/W 0 2 MASK2 R/W 0 SS2 Interrupt Mask Specifies whether the raw interrupt signal from Sample Sequencer 2 (ADCRIS register INR2 bit) is promoted to a controller interrupt. If set, the raw interrupt signal is promoted to a controller interrupt. Otherwise, it is not. 1 MASK1 R/W 0 SS1 Interrupt Mask Specifies whether the raw interrupt signal from Sample Sequencer 1 (ADCRIS register INR1 bit) is promoted to a controller interrupt. If set, the raw interrupt signal is promoted to a controller interrupt. Otherwise, it is not. 0 MASK0 R/W 0 SS0 Interrupt Mask Specifies whether the raw interrupt signal from Sample Sequencer 0 (ADCRIS register INR0 bit) is promoted to a controller interrupt. If set, the raw interrupt signal is promoted to a controller interrupt. Otherwise, it is not. November 30, 2007 Preliminary 241 Analog-to-Digital Converter (ADC) Register 4: ADC Interrupt Status and Clear (ADCISC), offset 0x00C This register provides the mechanism for clearing interrupt conditions, and shows the status of controller interrupts generated by the Sample Sequencers. When read, each bit field is the logical AND of the respective INR and MASK bits. Interrupts are cleared by writing a 1 to the corresponding bit position. If software is polling the ADCRIS instead of generating interrupts, the INR bits are still cleared via the ADCISC register, even if the IN bit is not set. ADC Interrupt Status and Clear (ADCISC) Base 0x4003.8000 Offset 0x00C Type R/W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 IN3 R/W1C 0 RO 0 2 IN2 R/W1C 0 RO 0 1 IN1 R/W1C 0 RO 0 0 IN0 R/W1C 0 Bit/Field 31:4 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SS3 Interrupt Status and Clear This bit is set by hardware when the MASK3 and INR3 bits are both 1, providing a level-based interrupt to the controller. It is cleared by writing a 1, and also clears the INR3 bit. 3 IN3 R/W1C 0 2 IN2 R/W1C 0 SS2 Interrupt Status and Clear This bit is set by hardware when the MASK2 and INR2 bits are both 1, providing a level based interrupt to the controller. It is cleared by writing a 1, and also clears the INR2 bit. 1 IN1 R/W1C 0 SS1 Interrupt Status and Clear This bit is set by hardware when the MASK1 and INR1 bits are both 1, providing a level based interrupt to the controller. It is cleared by writing a 1, and also clears the INR1 bit. 0 IN0 R/W1C 0 SS0 Interrupt Status and Clear This bit is set by hardware when the MASK0 and INR0 bits are both 1, providing a level based interrupt to the controller. It is cleared by writing a 1, and also clears the INR0 bit. 242 Preliminary November 30, 2007 LM3S2016 Microcontroller Register 5: ADC Overflow Status (ADCOSTAT), offset 0x010 This register indicates overflow conditions in the Sample Sequencer FIFOs. Once the overflow condition has been handled by software, the condition can be cleared by writing a 1 to the corresponding bit position. ADC Overflow Status (ADCOSTAT) Base 0x4003.8000 Offset 0x010 Type R/W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 OV3 R/W1C 0 RO 0 2 OV2 R/W1C 0 RO 0 1 OV1 R/W1C 0 RO 0 0 OV0 R/W1C 0 Bit/Field 31:4 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SS3 FIFO Overflow This bit specifies that the FIFO for Sample Sequencer 3 has hit an overflow condition where the FIFO is full and a write was requested. When an overflow is detected, the most recent write is dropped and this bit is set by hardware to indicate the occurrence of dropped data. This bit is cleared by writing a 1. 3 OV3 R/W1C 0 2 OV2 R/W1C 0 SS2 FIFO Overflow This bit specifies that the FIFO for Sample Sequencer 2 has hit an overflow condition where the FIFO is full and a write was requested. When an overflow is detected, the most recent write is dropped and this bit is set by hardware to indicate the occurrence of dropped data. This bit is cleared by writing a 1. 1 OV1 R/W1C 0 SS1 FIFO Overflow This bit specifies that the FIFO for Sample Sequencer 1 has hit an overflow condition where the FIFO is full and a write was requested. When an overflow is detected, the most recent write is dropped and this bit is set by hardware to indicate the occurrence of dropped data. This bit is cleared by writing a 1. 0 OV0 R/W1C 0 SS0 FIFO Overflow This bit specifies that the FIFO for Sample Sequencer 0 has hit an overflow condition where the FIFO is full and a write was requested. When an overflow is detected, the most recent write is dropped and this bit is set by hardware to indicate the occurrence of dropped data. This bit is cleared by writing a 1. November 30, 2007 Preliminary 243 Analog-to-Digital Converter (ADC) Register 6: ADC Event Multiplexer Select (ADCEMUX), offset 0x014 The ADCEMUX selects the event (trigger) that initiates sampling for each Sample Sequencer. Each Sample Sequencer can be configured with a unique trigger source. ADC Event Multiplexer Select (ADCEMUX) Base 0x4003.8000 Offset 0x014 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 EM3 Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 RO 0 13 RO 0 12 RO 0 11 RO 0 10 EM2 R/W 0 R/W 0 R/W 0 R/W 0 RO 0 9 RO 0 8 RO 0 7 RO 0 6 EM1 R/W 0 R/W 0 R/W 0 R/W 0 RO 0 5 RO 0 4 RO 0 3 RO 0 2 EM0 R/W 0 R/W 0 RO 0 1 RO 0 0 Bit/Field 31:16 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SS3 Trigger Select This field selects the trigger source for Sample Sequencer 3. The valid configurations for this field are: Value 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 Event Controller (default) Reserved Reserved Reserved External (GPIO PB4) Timer Reserved Reserved Reserved 15:12 EM3 R/W 0x00 0x9-0xE reserved 0xF Always (continuously sample) 244 Preliminary November 30, 2007 LM3S2016 Microcontroller Bit/Field 11:8 Name EM2 Type R/W Reset 0x00 Description SS2 Trigger Select This field selects the trigger source for Sample Sequencer 2. The valid configurations for this field are: Value 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 Event Controller (default) Reserved Reserved Reserved External (GPIO PB4) Timer Reserved Reserved Reserved 0x9-0xE reserved 0xF Always (continuously sample) 7:4 EM1 R/W 0x00 SS1 Trigger Select This field selects the trigger source for Sample Sequencer 1. The valid configurations for this field are: Value 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 Event Controller (default) Reserved Reserved Reserved External (GPIO PB4) Timer Reserved Reserved Reserved 0x9-0xE reserved 0xF Always (continuously sample) November 30, 2007 Preliminary 245 Analog-to-Digital Converter (ADC) Bit/Field 3:0 Name EM0 Type R/W Reset 0x00 Description SS0 Trigger Select This field selects the trigger source for Sample Sequencer 0. The valid configurations for this field are: Value 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 Event Controller (default) Reserved Reserved Reserved External (GPIO PB4) Timer Reserved Reserved Reserved 0x9-0xE reserved 0xF Always (continuously sample) 246 Preliminary November 30, 2007 LM3S2016 Microcontroller Register 7: ADC Underflow Status (ADCUSTAT), offset 0x018 This register indicates underflow conditions in the Sample Sequencer FIFOs. The corresponding underflow condition can be cleared by writing a 1 to the relevant bit position. ADC Underflow Status (ADCUSTAT) Base 0x4003.8000 Offset 0x018 Type R/W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 UV3 R/W1C 0 RO 0 2 UV2 R/W1C 0 RO 0 1 UV1 R/W1C 0 RO 0 0 UV0 R/W1C 0 Bit/Field 31:4 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SS3 FIFO Underflow This bit specifies that the FIFO for Sample Sequencer 3 has hit an underflow condition where the FIFO is empty and a read was requested. The problematic read does not move the FIFO pointers, and 0s are returned. This bit is cleared by writing a 1. 3 UV3 R/W1C 0 2 UV2 R/W1C 0 SS2 FIFO Underflow This bit specifies that the FIFO for Sample Sequencer 2 has hit an underflow condition where the FIFO is empty and a read was requested. The problematic read does not move the FIFO pointers, and 0s are returned. This bit is cleared by writing a 1. 1 UV1 R/W1C 0 SS1 FIFO Underflow This bit specifies that the FIFO for Sample Sequencer 1 has hit an underflow condition where the FIFO is empty and a read was requested. The problematic read does not move the FIFO pointers, and 0s are returned. This bit is cleared by writing a 1. 0 UV0 R/W1C 0 SS0 FIFO Underflow This bit specifies that the FIFO for Sample Sequencer 0 has hit an underflow condition where the FIFO is empty and a read was requested. The problematic read does not move the FIFO pointers, and 0s are returned. This bit is cleared by writing a 1. November 30, 2007 Preliminary 247 Analog-to-Digital Converter (ADC) Register 8: ADC Sample Sequencer Priority (ADCSSPRI), offset 0x020 This register sets the priority for each of the Sample Sequencers. Out of reset, Sequencer 0 has the highest priority, and sample sequence 3 has the lowest priority. When reconfiguring sequence priorities, each sequence must have a unique priority or the ADC behavior is inconsistent. ADC Sample Sequencer Priority (ADCSSPRI) Base 0x4003.8000 Offset 0x020 Type R/W, reset 0x0000.3210 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 SS3 R/W 1 R/W 1 RO 0 12 RO 0 11 RO 0 10 RO 0 9 SS2 R/W 1 R/W 0 RO 0 8 RO 0 7 reserved RO 0 RO 0 R/W 0 RO 0 6 RO 0 5 SS1 R/W 1 RO 0 4 RO 0 3 reserved RO 0 RO 0 R/W 0 RO 0 2 RO 0 1 SS0 R/W 0 RO 0 0 reserved Type Reset RO 0 RO 0 reserved RO 0 RO 0 Bit/Field 31:14 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SS3 Priority The SS3 field contains a binary-encoded value that specifies the priority encoding of Sample Sequencer 3. A priority encoding of 0 is highest and 3 is lowest. The priorities assigned to the Sequencers must be uniquely mapped. ADC behavior is not consistent if two or more fields are equal. 13:12 SS3 R/W 0x3 11:10 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SS2 Priority The SS2 field contains a binary-encoded value that specifies the priority encoding of Sample Sequencer 2. 9:8 SS2 R/W 0x2 7:6 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SS1 Priority The SS1 field contains a binary-encoded value that specifies the priority encoding of Sample Sequencer 1. 5:4 SS1 R/W 0x1 3:2 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SS0 Priority The SS0 field contains a binary-encoded value that specifies the priority encoding of Sample Sequencer 0. 1:0 SS0 R/W 0x0 248 Preliminary November 30, 2007 LM3S2016 Microcontroller Register 9: ADC Processor Sample Sequence Initiate (ADCPSSI), offset 0x028 This register provides a mechanism for application software to initiate sampling in the Sample Sequencers. Sample sequences can be initiated individually or in any combination. When multiple sequences are triggered simultaneously, the priority encodings in ADCSSPRI dictate execution order. ADC Processor Sample Sequence Initiate (ADCPSSI) Base 0x4003.8000 Offset 0x028 Type WO, reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset WO 15 WO 14 WO 13 WO 12 WO 11 WO 10 reserved Type Reset WO WO WO WO WO WO WO WO WO WO WO WO WO 9 WO 8 WO 7 WO 6 WO 5 WO 4 WO 3 SS3 WO WO 2 SS2 WO WO 1 SS1 WO WO 0 SS0 WO - Bit/Field 31:4 Name reserved Type WO Reset - Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SS3 Initiate Only a write by software is valid; a read of the register returns no meaningful data. When set by software, sampling is triggered on Sample Sequencer 3, assuming the Sequencer is enabled in the ADCACTSS register. 3 SS3 WO - 2 SS2 WO - SS2 Initiate Only a write by software is valid; a read of the register returns no meaningful data. When set by software, sampling is triggered on Sample Sequencer 2, assuming the Sequencer is enabled in the ADCACTSS register. 1 SS1 WO - SS1 Initiate Only a write by software is valid; a read of the register returns no meaningful data. When set by software, sampling is triggered on Sample Sequencer 1, assuming the Sequencer is enabled in the ADCACTSS register. 0 SS0 WO - SS0 Initiate Only a write by software is valid; a read of the register returns no meaningful data. When set by software, sampling is triggered on Sample Sequencer 0, assuming the Sequencer is enabled in the ADCACTSS register. November 30, 2007 Preliminary 249 Analog-to-Digital Converter (ADC) Register 10: ADC Sample Averaging Control (ADCSAC), offset 0x030 This register controls the amount of hardware averaging applied to conversion results. The final conversion result stored in the FIFO is averaged from 2 AVG consecutive ADC samples at the specified ADC speed. If AVG is 0, the sample is passed directly through without any averaging. If AVG=6, then 64 consecutive ADC samples are averaged to generate one result in the sequencer FIFO. An AVG = 7 provides unpredictable results. ADC Sample Averaging Control (ADCSAC) Base 0x4003.8000 Offset 0x030 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 AVG R/W 0 R/W 0 RO 0 0 Bit/Field 31:3 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Hardware Averaging Control Specifies the amount of hardware averaging that will be applied to ADC samples. The AVG field can be any value between 0 and 6. Entering a value of 7 creates unpredictable results. Value Description 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 No hardware oversampling 2x hardware oversampling 4x hardware oversampling 8x hardware oversampling 16x hardware oversampling 32x hardware oversampling 64x hardware oversampling Reserved 2:0 AVG R/W 0x0 250 Preliminary November 30, 2007 LM3S2016 Microcontroller Register 11: ADC Sample Sequence Input Multiplexer Select 0 (ADCSSMUX0), offset 0x040 This register defines the analog input configuration for each sample in a sequence executed with Sample Sequencer 0. This register is 32-bits wide and contains information for eight possible samples. ADC Sample Sequence Input Multiplexer Select 0 (ADCSSMUX0) Base 0x4003.8000 Offset 0x040 Type R/W, reset 0x0000.0000 31 30 29 MUX7 R/W 0 13 MUX3 R/W 0 R/W 0 R/W 0 12 28 27 26 25 MUX6 R/W 0 9 MUX2 R/W 0 R/W 0 R/W 0 8 24 23 22 21 MUX5 R/W 0 5 MUX1 R/W 0 R/W 0 R/W 0 4 20 19 18 17 MUX4 R/W 0 1 MUX0 R/W 0 R/W 0 R/W 0 0 16 reserved Type Reset RO 0 15 RO 0 14 reserved RO 0 11 RO 0 10 reserved RO 0 7 reserved RO 0 RO 0 RO 0 6 reserved RO 0 3 reserved RO 0 RO 0 RO 0 2 reserved Type Reset RO 0 RO 0 reserved RO 0 RO 0 Bit/Field 31:30 Name reserved Type RO Reset 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 8th Sample Input Select The MUX7 field is used during the eighth sample of a sequence executed with the Sample Sequencer. It specifies which of the analog inputs is sampled for the analog-to-digital conversion. The value set here indicates the corresponding pin, for example, a value of 1 indicates the input is ADC1. 29:28 MUX7 R/W 0 27:26 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7th Sample Input Select The MUX6 field is used during the seventh sample of a sequence executed with the Sample Sequencer and specifies which of the analog inputs is sampled for the analog-to-digital conversion. 25:24 MUX6 R/W 0 23:22 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 6th Sample Input Select The MUX5 field is used during the sixth sample of a sequence executed with the Sample Sequencer and specifies which of the analog inputs is sampled for the analog-to-digital conversion. 21:20 MUX5 R/W 0 19:18 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. November 30, 2007 Preliminary 251 Analog-to-Digital Converter (ADC) Bit/Field 17:16 Name MUX4 Type R/W Reset 0 Description 5th Sample Input Select The MUX4 field is used during the fifth sample of a sequence executed with the Sample Sequencer and specifies which of the analog inputs is sampled for the analog-to-digital conversion. 15:14 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 4th Sample Input Select The MUX3 field is used during the fourth sample of a sequence executed with the Sample Sequencer and specifies which of the analog inputs is sampled for the analog-to-digital conversion. 13:12 MUX3 R/W 0 11:10 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3rd Sample Input Select The MUX2 field is used during the third sample of a sequence executed with the Sample Sequencer and specifies which of the analog inputs is sampled for the analog-to-digital conversion. 9:8 MUX2 R/W 0 7:6 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 2nd Sample Input Select The MUX1 field is used during the second sample of a sequence executed with the Sample Sequencer and specifies which of the analog inputs is sampled for the analog-to-digital conversion. 5:4 MUX1 R/W 0 3:2 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 1st Sample Input Select The MUX0 field is used during the first sample of a sequence executed with the Sample Sequencer and specifies which of the analog inputs is sampled for the analog-to-digital conversion. 1:0 MUX0 R/W 0 252 Preliminary November 30, 2007 LM3S2016 Microcontroller Register 12: ADC Sample Sequence Control 0 (ADCSSCTL0), offset 0x044 This register contains the configuration information for each sample for a sequence executed with Sample Sequencer 0. When configuring a sample sequence, the END bit must be set at some point, whether it be after the first sample, last sample, or any sample in between. This register is 32-bits wide and contains information for eight possible samples. ADC Sample Sequence Control 0 (ADCSSCTL0) Base 0x4003.8000 Offset 0x044 Type R/W, reset 0x0000.0000 31 reserved Type Reset RO 0 15 reserved Type Reset RO 0 30 IE7 R/W 0 14 IE3 R/W 0 29 END7 R/W 0 13 END3 R/W 0 28 D7 R/W 0 12 D3 R/W 0 27 reserved RO 0 11 reserved RO 0 26 IE6 R/W 0 10 IE2 R/W 0 25 END6 R/W 0 9 END2 R/W 0 24 D6 R/W 0 8 D2 R/W 0 23 reserved RO 0 7 reserved RO 0 22 IE5 R/W 0 6 IE1 R/W 0 21 END5 R/W 0 5 END1 R/W 0 20 D5 R/W 0 4 D1 R/W 0 19 reserved RO 0 3 reserved RO 0 18 IE4 R/W 0 2 IE0 R/W 0 17 END4 R/W 0 1 END0 R/W 0 16 D4 R/W 0 0 D0 R/W 0 Bit/Field 31 Name reserved Type RO Reset 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 8th Sample Interrupt Enable The IE7 bit is used during the eighth sample of the sample sequence and specifies whether the raw interrupt signal (INR0 bit) is asserted at the end of the sample's conversion. If the MASK0 bit in the ADCIM register is set, the interrupt is promoted to a controller-level interrupt. When this bit is set, the raw interrupt is asserted, otherwise it is not. It is legal to have multiple samples within a sequence generate interrupts. 30 IE7 R/W 0 29 END7 R/W 0 8th Sample is End of Sequence The END7 bit indicates that this is the last sample of the sequence. It is possible to end the sequence on any sample position. Samples defined after the sample containing a set END are not requested for conversion even though the fields may be non-zero. It is required that software write the END bit somewhere within the sequence. (Sample Sequencer 3, which only has a single sample in the sequence, is hardwired to have the END0 bit set.) Setting this bit indicates that this sample is the last in the sequence. 28 D7 R/W 0 8th Sample Diff Input Select The D7 bit indicates that the analog input is to be differentially sampled. The corresponding ADCSSMUXx nibble must be set to the pair number "i", where the paired inputs are "2i and 2i+1". When set, the analog inputs are differentially sampled. 27 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. November 30, 2007 Preliminary 253 Analog-to-Digital Converter (ADC) Bit/Field 26 Name IE6 Type R/W Reset 0 Description 7th Sample Interrupt Enable Same definition as IE7 but used during the seventh sample. 25 END6 R/W 0 7th Sample is End of Sequence Same definition as END7 but used during the seventh sample. 24 D6 R/W 0 7th Sample Diff Input Select Same definition as D7 but used during the seventh sample. 23 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 6th Sample Interrupt Enable Same definition as IE7 but used during the sixth sample. 22 IE5 R/W 0 21 END5 R/W 0 6th Sample is End of Sequence Same definition as END7 but used during the sixth sample. 20 D5 R/W 0 6th Sample Diff Input Select Same definition as D7 but used during the sixth sample. 19 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 5th Sample Interrupt Enable Same definition as IE7 but used during the fifth sample. 18 IE4 R/W 0 17 END4 R/W 0 5th Sample is End of Sequence Same definition as END7 but used during the fifth sample. 16 D4 R/W 0 5th Sample Diff Input Select Same definition as D7 but used during the fifth sample. 15 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 4th Sample Interrupt Enable Same definition as IE7 but used during the fourth sample. 14 IE3 R/W 0 13 END3 R/W 0 4th Sample is End of Sequence Same definition as END7 but used during the fourth sample. 12 D3 R/W 0 4th Sample Diff Input Select Same definition as D7 but used during the fourth sample. 11 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 254 Preliminary November 30, 2007 LM3S2016 Microcontroller Bit/Field 10 Name IE2 Type R/W Reset 0 Description 3rd Sample Interrupt Enable Same definition as IE7 but used during the third sample. 9 END2 R/W 0 3rd Sample is End of Sequence Same definition as END7 but used during the third sample. 8 D2 R/W 0 3rd Sample Diff Input Select Same definition as D7 but used during the third sample. 7 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 2nd Sample Interrupt Enable Same definition as IE7 but used during the second sample. 6 IE1 R/W 0 5 END1 R/W 0 2nd Sample is End of Sequence Same definition as END7 but used during the second sample. 4 D1 R/W 0 2nd Sample Diff Input Select Same definition as D7 but used during the second sample. 3 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 1st Sample Interrupt Enable Same definition as IE7 but used during the first sample. 2 IE0 R/W 0 1 END0 R/W 0 1st Sample is End of Sequence Same definition as END7 but used during the first sample. Since this sequencer has only one entry, this bit must be set. 0 D0 R/W 0 1st Sample Diff Input Select Same definition as D7 but used during the first sample. November 30, 2007 Preliminary 255 Analog-to-Digital Converter (ADC) Register 13: ADC Sample Sequence Result FIFO 0 (ADCSSFIFO0), offset 0x048 Register 14: ADC Sample Sequence Result FIFO 1 (ADCSSFIFO1), offset 0x068 Register 15: ADC Sample Sequence Result FIFO 2 (ADCSSFIFO2), offset 0x088 Register 16: ADC Sample Sequence Result FIFO 3 (ADCSSFIFO3), offset 0x0A8 This register contains the conversion results for samples collected with the Sample Sequencer (the ADCSSFIFO0 register is used for Sample Sequencer 0, ADCSSFIFO1 for Sequencer 1, ADCSSFIFO2 for Sequencer 2, and ADCSSFIFO3 for Sequencer 3). Reads of this register return conversion result data in the order sample 0, sample 1, and so on, until the FIFO is empty. If the FIFO is not properly handled by software, overflow and underflow conditions are registered in the ADCOSTAT and ADCUSTAT registers. ADC Sample Sequence Result FIFO 0 (ADCSSFIFO0) Base 0x4003.8000 Offset 0x048 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 DATA RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 Bit/Field 31:10 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Conversion Result Data 9:0 DATA RO 0x00 256 Preliminary November 30, 2007 LM3S2016 Microcontroller Register 17: ADC Sample Sequence FIFO 0 Status (ADCSSFSTAT0), offset 0x04C Register 18: ADC Sample Sequence FIFO 1 Status (ADCSSFSTAT1), offset 0x06C Register 19: ADC Sample Sequence FIFO 2 Status (ADCSSFSTAT2), offset 0x08C Register 20: ADC Sample Sequence FIFO 3 Status (ADCSSFSTAT3), offset 0x0AC This register provides a window into the Sample Sequencer, providing full/empty status information as well as the positions of the head and tail pointers. The reset value of 0x100 indicates an empty FIFO. The ADCSSFSTAT0 register provides status on FIF0, ADCSSFSTAT1 on FIFO1, ADCSSFSTAT2 on FIFO2, and ADCSSFSTAT3 on FIFO3. ADC Sample Sequence FIFO 0 Status (ADCSSFSTAT0) Base 0x4003.8000 Offset 0x04C Type RO, reset 0x0000.0100 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 reserved Type Reset RO 0 RO 0 RO 0 RO 0 13 RO 0 12 FULL RO 0 RO 0 RO 0 11 RO 0 10 reserved RO 0 RO 0 RO 0 9 RO 0 8 EMPTY RO 1 RO 0 RO 0 RO 0 7 RO 0 6 HPTR RO 0 RO 0 RO 0 RO 0 RO 0 5 RO 0 4 RO 0 3 RO 0 2 TPTR RO 0 RO 0 RO 0 1 RO 0 0 Bit/Field 31:13 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. FIFO Full When set, indicates that the FIFO is currently full. 12 FULL RO 0 11:9 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. FIFO Empty When set, indicates that the FIFO is currently empty. 8 EMPTY RO 1 7:4 HPTR RO 0x00 FIFO Head Pointer This field contains the current "head" pointer index for the FIFO, that is, the next entry to be written. 3:0 TPTR RO 0x00 FIFO Tail Pointer This field contains the current "tail" pointer index for the FIFO, that is, the next entry to be read. November 30, 2007 Preliminary 257 Analog-to-Digital Converter (ADC) Register 21: ADC Sample Sequence Input Multiplexer Select 1 (ADCSSMUX1), offset 0x060 Register 22: ADC Sample Sequence Input Multiplexer Select 2 (ADCSSMUX2), offset 0x080 This register defines the analog input configuration for each sample in a sequence executed with Sample Sequencer 1 or 2. These registers are 16-bits wide and contain information for four possible samples. See the ADCSSMUX0 register on page 251 for detailed bit descriptions. ADC Sample Sequence Input Multiplexer Select 1 (ADCSSMUX1) Base 0x4003.8000 Offset 0x060 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 MUX3 R/W 0 R/W 0 RO 0 12 RO 0 11 RO 0 10 RO 0 9 MUX2 R/W 0 R/W 0 RO 0 8 RO 0 7 reserved RO 0 RO 0 R/W 0 RO 0 6 RO 0 5 MUX1 R/W 0 RO 0 4 RO 0 3 reserved RO 0 RO 0 R/W 0 RO 0 2 RO 0 1 MUX0 R/W 0 RO 0 0 reserved Type Reset RO 0 RO 0 reserved RO 0 RO 0 Bit/Field 31:14 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 4th Sample Input Select Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3rd Sample Input Select Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 2nd Sample Input Select Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 1st Sample Input Select 13:12 11:10 MUX3 reserved R/W RO 0 0 9:8 7:6 MUX2 reserved R/W RO 0 0 5:4 3:2 MUX1 reserved R/W RO 0 0 1:0 MUX0 R/W 0 258 Preliminary November 30, 2007 LM3S2016 Microcontroller Register 23: ADC Sample Sequence Control 1 (ADCSSCTL1), offset 0x064 Register 24: ADC Sample Sequence Control 2 (ADCSSCTL2), offset 0x084 These registers contain the configuration information for each sample for a sequence executed with Sample Sequencer 1 or 2. When configuring a sample sequence, the END bit must be set at some point, whether it be after the first sample, last sample, or any sample in between. This register is 16-bits wide and contains information for four possible samples. See the ADCSSCTL0 register on page 253 for detailed bit descriptions. ADC Sample Sequence Control 1 (ADCSSCTL1) Base 0x4003.8000 Offset 0x064 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 reserved Type Reset RO 0 RO 0 14 IE3 R/W 0 RO 0 13 END3 R/W 0 RO 0 12 D3 R/W 0 RO 0 11 reserved RO 0 RO 0 10 IE2 R/W 0 RO 0 9 END2 R/W 0 RO 0 8 D2 R/W 0 RO 0 7 reserved RO 0 RO 0 6 IE1 R/W 0 RO 0 5 END1 R/W 0 RO 0 4 D1 R/W 0 RO 0 3 reserved RO 0 RO 0 2 IE0 R/W 0 RO 0 1 END0 R/W 0 RO 0 0 D0 R/W 0 Bit/Field 31:15 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 4th Sample Interrupt Enable Same definition as IE7 but used during the fourth sample. 14 IE3 R/W 0 13 END3 R/W 0 4th Sample is End of Sequence Same definition as END7 but used during the fourth sample. 12 D3 R/W 0 4th Sample Diff Input Select Same definition as D7 but used during the fourth sample. 11 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3rd Sample Interrupt Enable Same definition as IE7 but used during the third sample. 10 IE2 R/W 0 9 END2 R/W 0 3rd Sample is End of Sequence Same definition as END7 but used during the third sample. 8 D2 R/W 0 3rd Sample Diff Input Select Same definition as D7 but used during the third sample. 7 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. November 30, 2007 Preliminary 259 Analog-to-Digital Converter (ADC) Bit/Field 6 Name IE1 Type R/W Reset 0 Description 2nd Sample Interrupt Enable Same definition as IE7 but used during the second sample. 5 END1 R/W 0 2nd Sample is End of Sequence Same definition as END7 but used during the second sample. 4 D1 R/W 0 2nd Sample Diff Input Select Same definition as D7 but used during the second sample. 3 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 1st Sample Interrupt Enable Same definition as IE7 but used during the first sample. 2 IE0 R/W 0 1 END0 R/W 0 1st Sample is End of Sequence Same definition as END7 but used during the first sample. Since this sequencer has only one entry, this bit must be set. 0 D0 R/W 0 1st Sample Diff Input Select Same definition as D7 but used during the first sample. 260 Preliminary November 30, 2007 LM3S2016 Microcontroller Register 25: ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3), offset 0x0A0 This register defines the analog input configuration for each sample in a sequence executed with Sample Sequencer 3. This register is 4-bits wide and contains information for one possible sample. See the ADCSSMUX0 register on page 251 for detailed bit descriptions. ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3) Base 0x4003.8000 Offset 0x0A0 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 MUX0 R/W 0 RO 0 0 Bit/Field 31:2 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 1st Sample Input Select 1:0 MUX0 R/W 0 November 30, 2007 Preliminary 261 Analog-to-Digital Converter (ADC) Register 26: ADC Sample Sequence Control 3 (ADCSSCTL3), offset 0x0A4 This register contains the configuration information for each sample for a sequence executed with Sample Sequencer 3. The END bit is always set since there is only one sample in this sequencer. This register is 4-bits wide and contains information for one possible sample. See the ADCSSCTL0 register on page 253 for detailed bit descriptions. ADC Sample Sequence Control 3 (ADCSSCTL3) Base 0x4003.8000 Offset 0x0A4 Type R/W, reset 0x0000.0002 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 IE0 R/W 0 RO 0 1 END0 R/W 1 RO 0 0 D0 R/W 0 Bit/Field 31:3 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 1st Sample Interrupt Enable Same definition as IE7 but used during the first sample. 2 IE0 R/W 0 1 END0 R/W 1 1st Sample is End of Sequence Same definition as END7 but used during the first sample. Since this sequencer has only one entry, this bit must be set. 0 D0 R/W 0 1st Sample Diff Input Select Same definition as D7 but used during the first sample. 262 Preliminary November 30, 2007 LM3S2016 Microcontroller Register 27: ADC Test Mode Loopback (ADCTMLB), offset 0x100 This register provides loopback operation within the digital logic of the ADC, which can be useful in debugging software without having to provide actual analog stimulus. This test mode is entered by writing a value of 0x0000.0001 to this register. When data is read from the FIFO in loopback mode, the read-only portion of this register is returned. Read-Only Register ADC Test Mode Loopback (ADCTMLB) Base 0x4003.8000 Offset 0x100 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 CNT RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 RO 0 6 RO 0 5 CONT RO 0 RO 0 4 DIFF RO 0 RO 0 3 reserved RO 0 RO 0 RO 0 2 RO 0 1 MUX RO 0 RO 0 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 Bit/Field 31:10 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Continuous Sample Counter Continuous sample counter that is initialized to 0 and counts each sample as it processed. This helps provide a unique value for the data received. 9:6 CNT RO 0x0 5 CONT RO 0 Continuation Sample Indicator When set, indicates that this is a continuation sample. For example, if two sequencers were to run back-to-back, this indicates that the controller kept continuously sampling at full rate. 4 DIFF RO 0 Differential Sample Indicator When set, indicates that this is a differential sample. 3 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Analog Input Indicator Indicates which analog input is to be sampled. 2:0 MUX RO 0x0 November 30, 2007 Preliminary 263 Analog-to-Digital Converter (ADC) Write-Only Register ADC Test Mode Loopback (ADCTMLB) Base 0x4003.8000 Offset 0x100 Type WO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 LB WO 0 Bit/Field 31:1 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Loopback Mode Enable When set, forces a loopback within the digital block to provide information on input and unique numbering. The 10-bit loopback data is defined as shown in the read for bits 9:0 above. 0 LB WO 0 264 Preliminary November 30, 2007 LM3S2016 Microcontroller 12 Universal Asynchronous Receivers/Transmitters (UARTs) The Stellaris Universal Asynchronous Receiver/Transmitter (UART) provides fully programmable, 16C550-type serial interface characteristics. The LM3S2016 controller is equipped with two UART modules. Each UART has the following features: ■ Separate transmit and receive FIFOs ■ Programmable FIFO length, including 1-byte deep operation providing conventional double-buffered interface ■ FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8 ■ Programmable baud-rate generator allowing rates up to 3.125 Mbps ■ Standard asynchronous communication bits for start, stop, and parity ■ False start bit detection ■ Line-break generation and detection ■ Fully programmable serial interface characteristics: – 5, 6, 7, or 8 data bits – Even, odd, stick, or no-parity bit generation/detection – 1 or 2 stop bit generation ■ IrDA serial-IR (SIR) encoder/decoder providing: – Programmable use of IrDA Serial InfraRed (SIR) or UART input/output – Support of IrDA SIR encoder/decoder functions for data rates up to 115.2 Kbps half-duplex – Support of normal 3/16 and low-power (1.41-2.23 μs) bit durations – Programmable internal clock generator enabling division of reference clock by 1 to 256 for low-power mode bit duration ® November 30, 2007 Preliminary 265 Universal Asynchronous Receivers/Transmitters (UARTs) 12.1 Block Diagram Figure 12-1. UART Module Block Diagram System Clock Interrupt Interrupt Control UARTIFLS UARTIM UARTMIS TXFIFO 16x8 . . . Transmitter Baud Rate Generator UARTIBRD UARTFBRD Receiver UnRx UnTx Identification Registers UARTPCellID0 UARTPCellID1 UARTPCellID2 UARTPCellID3 UARTPeriphID0 UARTPeriphID1 UARTPeriphID2 UARTPeriphID3 UART PeriphID4 UARTRIS UARTICR UARTDR Control / Status UARTRSR/ECR RXFIFO 16x8 UARTPeriphID5 UARTFR UARTPeriphID6 UARTLCRH UARTPeriphID7 UARTCTL UARTILPR . . . 12.2 Functional Description Each Stellaris UART performs the functions of parallel-to-serial and serial-to-parallel conversions. It is similar in functionality to a 16C550 UART, but is not register compatible. The UART is configured for transmit and/or receive via the TXE and RXE bits of the UART Control (UARTCTL) register (see page 284). Transmit and receive are both enabled out of reset. Before any control registers are programmed, the UART must be disabled by clearing the UARTEN bit in UARTCTL. If the UART is disabled during a TX or RX operation, the current transaction is completed prior to the UART stopping. The UART peripheral also includes a serial IR (SIR) encoder/decoder block that can be connected to an infrared transceiver to implement an IrDA SIR physical layer. The SIR function is programmed using the UARTCTL register. ® 12.2.1 Transmit/Receive Logic The transmit logic performs parallel-to-serial conversion on the data read from the transmit FIFO. The control logic outputs the serial bit stream beginning with a start bit, and followed by the data 266 Preliminary November 30, 2007 LM3S2016 Microcontroller bits (LSB first), parity bit, and the stop bits according to the programmed configuration in the control registers. See Figure 12-2 on page 267 for details. The receive logic performs serial-to-parallel conversion on the received bit stream after a valid start pulse has been detected. Overrun, parity, frame error checking, and line-break detection are also performed, and their status accompanies the data that is written to the receive FIFO. Figure 12-2. UART Character Frame UnTX 1 0 n Star t LSB 5-8 data bits Parity bit if enabled MSB 1-2 stop bits 12.2.2 Baud-Rate Generation The baud-rate divisor is a 22-bit number consisting of a 16-bit integer and a 6-bit fractional part. The number formed by these two values is used by the baud-rate generator to determine the bit period. Having a fractional baud-rate divider allows the UART to generate all the standard baud rates. The 16-bit integer is loaded through the UART Integer Baud-Rate Divisor (UARTIBRD) register (see page 280) and the 6-bit fractional part is loaded with the UART Fractional Baud-Rate Divisor (UARTFBRD) register (see page 281). The baud-rate divisor (BRD) has the following relationship to the system clock (where BRDI is the integer part of the BRD and BRDF is the fractional part, separated by a decimal place.): BRD = BRDI + BRDF = SysClk / (16 * Baud Rate) The 6-bit fractional number (that is to be loaded into the DIVFRAC bit field in the UARTFBRD register) can be calculated by taking the fractional part of the baud-rate divisor, multiplying it by 64, and adding 0.5 to account for rounding errors: UARTFBRD[DIVFRAC] = integer(BRDF * 64 + 0.5) The UART generates an internal baud-rate reference clock at 16x the baud-rate (referred to as Baud16). This reference clock is divided by 16 to generate the transmit clock, and is used for error detection during receive operations. Along with the UART Line Control, High Byte (UARTLCRH) register (see page 282), the UARTIBRD and UARTFBRD registers form an internal 30-bit register. This internal register is only updated when a write operation to UARTLCRH is performed, so any changes to the baud-rate divisor must be followed by a write to the UARTLCRH register for the changes to take effect. To update the baud-rate registers, there are four possible sequences: ■ UARTIBRD write, UARTFBRD write, and UARTLCRH write ■ UARTFBRD write, UARTIBRD write, and UARTLCRH write ■ UARTIBRD write and UARTLCRH write ■ UARTFBRD write and UARTLCRH write November 30, 2007 Preliminary 267 Universal Asynchronous Receivers/Transmitters (UARTs) 12.2.3 Data Transmission Data received or transmitted is stored in two 16-byte FIFOs, though the receive FIFO has an extra four bits per character for status information. For transmission, data is written into the transmit FIFO. If the UART is enabled, it causes a data frame to start transmitting with the parameters indicated in the UARTLCRH register. Data continues to be transmitted until there is no data left in the transmit FIFO. The BUSY bit in the UART Flag (UARTFR) register (see page 277) is asserted as soon as data is written to the transmit FIFO (that is, if the FIFO is non-empty) and remains asserted while data is being transmitted. The BUSY bit is negated only when the transmit FIFO is empty, and the last character has been transmitted from the shift register, including the stop bits. The UART can indicate that it is busy even though the UART may no longer be enabled. When the receiver is idle (the UnRx is continuously 1) and the data input goes Low (a start bit has been received), the receive counter begins running and data is sampled on the eighth cycle of Baud16 (described in “Transmit/Receive Logic” on page 266). The start bit is valid if UnRx is still low on the eighth cycle of Baud16, otherwise a false start bit is detected and it is ignored. Start bit errors can be viewed in the UART Receive Status (UARTRSR) register (see page 275). If the start bit was valid, successive data bits are sampled on every 16th cycle of Baud16 (that is, one bit period later) according to the programmed length of the data characters. The parity bit is then checked if parity mode was enabled. Data length and parity are defined in the UARTLCRH register. Lastly, a valid stop bit is confirmed if UnRx is High, otherwise a framing error has occurred. When a full word is received, the data is stored in the receive FIFO, with any error bits associated with that word. 12.2.4 Serial IR (SIR) The UART peripheral includes an IrDA serial-IR (SIR) encoder/decoder block. The IrDA SIR block provides functionality that converts between an asynchronous UART data stream, and half-duplex serial SIR interface. No analog processing is performed on-chip. The role of the SIR block is to provide a digital encoded output, and decoded input to the UART. The UART signal pins can be connected to an infrared transceiver to implement an IrDA SIR physical layer link. The SIR block has two modes of operation: ■ In normal IrDA mode, a zero logic level is transmitted as high pulse of 3/16th duration of the selected baud rate bit period on the output pin, while logic one levels are transmitted as a static LOW signal. These levels control the driver of an infrared transmitter, sending a pulse of light for each zero. On the reception side, the incoming light pulses energize the photo transistor base of the receiver, pulling its output LOW. This drives the UART input pin LOW. ■ In low-power IrDA mode, the width of the transmitted infrared pulse is set to three times the period of the internally generated IrLPBaud16 signal (1.63 µs, assuming a nominal 1.8432 MHz frequency) by changing the appropriate bit in the UARTCR register. Figure 12-3 on page 269 shows the UART transmit and receive signals, with and without IrDA modulation. 268 Preliminary November 30, 2007 LM3S2016 Microcontroller Figure 12-3. IrDA Data Modulation Start bit Data bits 0 Stop bit 0 1 1 0 1 UnTx UnTx with IrDA 0 1 0 1 Bit period 3 16 Bit period UnRx with IrDA UnRx 0 Start 1 0 1 0 Data bits 0 1 1 0 1 Stop In both normal and low-power IrDA modes: ■ During transmission, the UART data bit is used as the base for encoding ■ During reception, the decoded bits are transferred to the UART receive logic The IrDA SIR physical layer specifies a half-duplex communication link, with a minimum 10 ms delay between transmission and reception. This delay must be generated by software because it is not automatically supported by the UART. The delay is required because the infrared receiver electronics might become biased, or even saturated from the optical power coupled from the adjacent transmitter LED. This delay is known as latency, or receiver setup time. 12.2.5 FIFO Operation The UART has two 16-entry FIFOs; one for transmit and one for receive. Both FIFOs are accessed via the UART Data (UARTDR) register (see page 273). Read operations of the UARTDR register return a 12-bit value consisting of 8 data bits and 4 error flags while write operations place 8-bit data in the transmit FIFO. Out of reset, both FIFOs are disabled and act as 1-byte-deep holding registers. The FIFOs are enabled by setting the FEN bit in UARTLCRH (page 282). FIFO status can be monitored via the UART Flag (UARTFR) register (see page 277) and the UART Receive Status (UARTRSR) register. Hardware monitors empty, full and overrun conditions. The UARTFR register contains empty and full flags (TXFE, TXFF, RXFE, and RXFF bits) and the UARTRSR register shows overrun status via the OE bit. The trigger points at which the FIFOs generate interrupts is controlled via the UART Interrupt FIFO Level Select (UARTIFLS) register (see page 286). Both FIFOs can be individually configured to trigger interrupts at different levels. Available configurations include 1/8, ¼, ½, ¾, and 7/8. For example, if the ¼ option is selected for the receive FIFO, the UART generates a receive interrupt after 4 data bytes are received. Out of reset, both FIFOs are configured to trigger an interrupt at the ½ mark. 12.2.6 Interrupts The UART can generate interrupts when the following conditions are observed: ■ Overrun Error ■ Break Error November 30, 2007 Preliminary 269 Universal Asynchronous Receivers/Transmitters (UARTs) ■ Parity Error ■ Framing Error ■ Receive Timeout ■ Transmit (when condition defined in the TXIFLSEL bit in the UARTIFLS register is met) ■ Receive (when condition defined in the RXIFLSEL bit in the UARTIFLS register is met) All of the interrupt events are ORed together before being sent to the interrupt controller, so the UART can only generate a single interrupt request to the controller at any given time. Software can service multiple interrupt events in a single interrupt service routine by reading the UART Masked Interrupt Status (UARTMIS) register (see page 291). The interrupt events that can trigger a controller-level interrupt are defined in the UART Interrupt Mask (UARTIM ) register (see page 288) by setting the corresponding IM bit to 1. If interrupts are not used, the raw interrupt status is always visible via the UART Raw Interrupt Status (UARTRIS) register (see page 290). Interrupts are always cleared (for both the UARTMIS and UARTRIS registers) by setting the corresponding bit in the UART Interrupt Clear (UARTICR) register (see page 292). The receive timeout interrupt is asserted when the receive FIFO is not empty, and no further data is received over a 32-bit period. The receive timeout interrupt is cleared either when the FIFO becomes empty through reading all the data (or by reading the holding register), or when a 1 is written to the corresponding bit in the UARTICR register. 12.2.7 Loopback Operation The UART can be placed into an internal loopback mode for diagnostic or debug work. This is accomplished by setting the LBE bit in the UARTCTL register (see page 284). In loopback mode, data transmitted on UnTx is received on the UnRx input. 12.2.8 IrDA SIR block The IrDA SIR block contains an IrDA serial IR (SIR) protocol encoder/decoder. When enabled, the SIR block uses the UnTx and UnRx pins for the SIR protocol, which should be connected to an IR transceiver. The SIR block can receive and transmit, but it is only half-duplex so it cannot do both at the same time. Transmission must be stopped before data can be received. The IrDA SIR physical layer specifies a minimum 10-ms delay between transmission and reception. 12.3 Initialization and Configuration To use the UARTs, the peripheral clock must be enabled by setting the UART0 or UART1 bits in the RCGC1 register. This section discusses the steps that are required for using a UART module. For this example, the system clock is assumed to be 20 MHz and the desired UART configuration is: ■ 115200 baud rate ■ Data length of 8 bits ■ One stop bit 270 Preliminary November 30, 2007 LM3S2016 Microcontroller ■ No parity ■ FIFOs disabled ■ No interrupts The first thing to consider when programming the UART is the baud-rate divisor (BRD), since the UARTIBRD and UARTFBRD registers must be written before the UARTLCRH register. Using the equation described in “Baud-Rate Generation” on page 267, the BRD can be calculated: BRD = 20,000,000 / (16 * 115,200) = 10.8507 which means that the DIVINT field of the UARTIBRD register (see page 280) should be set to 10. The value to be loaded into the UARTFBRD register (see page 281) is calculated by the equation: UARTFBRD[DIVFRAC] = integer(0.8507 * 64 + 0.5) = 54 With the BRD values in hand, the UART configuration is written to the module in the following order: 1. Disable the UART by clearing the UARTEN bit in the UARTCTL register. 2. Write the integer portion of the BRD to the UARTIBRD register. 3. Write the fractional portion of the BRD to the UARTFBRD register. 4. Write the desired serial parameters to the UARTLCRH register (in this case, a value of 0x0000.0060). 5. Enable the UART by setting the UARTEN bit in the UARTCTL register. 12.4 Register Map Table 12-1 on page 271 lists the UART registers. The offset listed is a hexadecimal increment to the register ’s address, relative to that UART’s base address: ■ UART0: 0x4000.C000 ■ UART1: 0x4000.D000 Note: The UART must be disabled (see the UARTEN bit in the UARTCTL register on page 284) before any of the control registers are reprogrammed. When the UART is disabled during a TX or RX operation, the current transaction is completed prior to the UART stopping. Table 12-1. UART Register Map Offset 0x000 0x004 0x018 0x020 0x024 Name UARTDR UARTRSR/UARTECR UARTFR UARTILPR UARTIBRD Type R/W R/W RO R/W R/W Reset 0x0000.0000 0x0000.0000 0x0000.0090 0x0000.0000 0x0000.0000 Description UART Data UART Receive Status/Error Clear UART Flag UART IrDA Low-Power Register UART Integer Baud-Rate Divisor See page 273 275 277 279 280 November 30, 2007 Preliminary 271 Universal Asynchronous Receivers/Transmitters (UARTs) Offset 0x028 0x02C 0x030 0x034 0x038 0x03C 0x040 0x044 0xFD0 0xFD4 0xFD8 0xFDC 0xFE0 0xFE4 0xFE8 0xFEC 0xFF0 0xFF4 0xFF8 0xFFC Name UARTFBRD UARTLCRH UARTCTL UARTIFLS UARTIM UARTRIS UARTMIS UARTICR UARTPeriphID4 UARTPeriphID5 UARTPeriphID6 UARTPeriphID7 UARTPeriphID0 UARTPeriphID1 UARTPeriphID2 UARTPeriphID3 UARTPCellID0 UARTPCellID1 UARTPCellID2 UARTPCellID3 Type R/W R/W R/W R/W R/W RO RO W1C RO RO RO RO RO RO RO RO RO RO RO RO Reset 0x0000.0000 0x0000.0000 0x0000.0300 0x0000.0012 0x0000.0000 0x0000.000F 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0011 0x0000.0000 0x0000.0018 0x0000.0001 0x0000.000D 0x0000.00F0 0x0000.0005 0x0000.00B1 Description UART Fractional Baud-Rate Divisor UART Line Control UART Control UART Interrupt FIFO Level Select UART Interrupt Mask UART Raw Interrupt Status UART Masked Interrupt Status UART Interrupt Clear UART Peripheral Identification 4 UART Peripheral Identification 5 UART Peripheral Identification 6 UART Peripheral Identification 7 UART Peripheral Identification 0 UART Peripheral Identification 1 UART Peripheral Identification 2 UART Peripheral Identification 3 UART PrimeCell Identification 0 UART PrimeCell Identification 1 UART PrimeCell Identification 2 UART PrimeCell Identification 3 See page 281 282 284 286 288 290 291 292 294 295 296 297 298 299 300 301 302 303 304 305 12.5 Register Descriptions The remainder of this section lists and describes the UART registers, in numerical order by address offset. 272 Preliminary November 30, 2007 LM3S2016 Microcontroller Register 1: UART Data (UARTDR), offset 0x000 This register is the data register (the interface to the FIFOs). When FIFOs are enabled, data written to this location is pushed onto the transmit FIFO. If FIFOs are disabled, data is stored in the transmitter holding register (the bottom word of the transmit FIFO). A write to this register initiates a transmission from the UART. For received data, if the FIFO is enabled, the data byte and the 4-bit status (break, frame, parity, and overrun) is pushed onto the 12-bit wide receive FIFO. If FIFOs are disabled, the data byte and status are stored in the receiving holding register (the bottom word of the receive FIFO). The received data can be retrieved by reading this register. UART Data (UARTDR) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 Offset 0x000 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 OE RO 0 RO 0 RO 0 10 BE RO 0 RO 0 9 PE RO 0 RO 0 8 FE RO 0 R/W 0 R/W 0 R/W 0 R/W 0 RO 0 7 RO 0 6 RO 0 5 RO 0 4 DATA R/W 0 R/W 0 R/W 0 R/W 0 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 Bit/Field 31:12 Name reserved Type RO Reset 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. UART Overrun Error The OE values are defined as follows: Value Description 0 1 There has been no data loss due to a FIFO overrun. New data was received when the FIFO was full, resulting in data loss. 11 OE RO 0 10 BE RO 0 UART Break Error This bit is set to 1 when a break condition is detected, indicating that the receive data input was held Low for longer than a full-word transmission time (defined as start, data, parity, and stop bits). In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the received data input goes to a 1 (marking state) and the next valid start bit is received. November 30, 2007 Preliminary 273 Universal Asynchronous Receivers/Transmitters (UARTs) Bit/Field 9 Name PE Type RO Reset 0 Description UART Parity Error This bit is set to 1 when the parity of the received data character does not match the parity defined by bits 2 and 7 of the UARTLCRH register. In FIFO mode, this error is associated with the character at the top of the FIFO. 8 FE RO 0 UART Framing Error This bit is set to 1 when the received character does not have a valid stop bit (a valid stop bit is 1). 7:0 DATA R/W 0 Data Transmitted or Received When written, the data that is to be transmitted via the UART. When read, the data that was received by the UART. 274 Preliminary November 30, 2007 LM3S2016 Microcontroller Register 2: UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 The UARTRSR/UARTECR register is the receive status register/error clear register. In addition to the UARTDR register, receive status can also be read from the UARTRSR register. If the status is read from this register, then the status information corresponds to the entry read from UARTDR prior to reading UARTRSR. The status information for overrun is set immediately when an overrun condition occurs. The UARTRSR register cannot be written. A write of any value to the UARTECR register clears the framing, parity, break, and overrun errors. All the bits are cleared to 0 on reset. Read-Only Receive Status (UARTRSR) Register UART Receive Status/Error Clear (UARTRSR/UARTECR) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 Offset 0x004 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 OE RO 0 RO 0 2 BE RO 0 RO 0 1 PE RO 0 RO 0 0 FE RO 0 Bit/Field 31:4 Name reserved Type RO Reset 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. UART Overrun Error When this bit is set to 1, data is received and the FIFO is already full. This bit is cleared to 0 by a write to UARTECR. The FIFO contents remain valid since no further data is written when the FIFO is full, only the contents of the shift register are overwritten. The CPU must now read the data in order to empty the FIFO. 3 OE RO 0 2 BE RO 0 UART Break Error This bit is set to 1 when a break condition is detected, indicating that the received data input was held Low for longer than a full-word transmission time (defined as start, data, parity, and stop bits). This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state) and the next valid start bit is received. November 30, 2007 Preliminary 275 Universal Asynchronous Receivers/Transmitters (UARTs) Bit/Field 1 Name PE Type RO Reset 0 Description UART Parity Error This bit is set to 1 when the parity of the received data character does not match the parity defined by bits 2 and 7 of the UARTLCRH register. This bit is cleared to 0 by a write to UARTECR. 0 FE RO 0 UART Framing Error This bit is set to 1 when the received character does not have a valid stop bit (a valid stop bit is 1). This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. Write-Only Error Clear (UARTECR) Register UART Receive Status/Error Clear (UARTRSR/UARTECR) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 Offset 0x004 Type WO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset WO 0 15 WO 0 14 WO 0 13 WO 0 12 WO 0 11 WO 0 10 WO 0 9 WO 0 8 WO 0 7 WO 0 6 WO 0 5 WO 0 4 DATA WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 3 WO 0 2 WO 0 1 WO 0 0 reserved Type Reset WO 0 WO 0 WO 0 WO 0 WO 0 Bit/Field 31:8 Name reserved Type WO Reset 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Error Clear A write to this register of any data clears the framing, parity, break, and overrun flags. 7:0 DATA WO 0 276 Preliminary November 30, 2007 LM3S2016 Microcontroller Register 3: UART Flag (UARTFR), offset 0x018 The UARTFR register is the flag register. After reset, the TXFF, RXFF, and BUSY bits are 0, and TXFE and RXFE bits are 1. UART Flag (UARTFR) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 Offset 0x018 Type RO, reset 0x0000.0090 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 TXFE RO 0 RO 0 RO 0 RO 1 RO 0 6 RXFF RO 0 RO 0 5 TXFF RO 0 RO 0 4 RXFE RO 1 RO 0 3 BUSY RO 0 RO 0 RO 0 2 RO 0 1 reserved RO 0 RO 0 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. UART Transmit FIFO Empty The meaning of this bit depends on the state of the FEN bit in the UARTLCRH register. If the FIFO is disabled (FEN is 0), this bit is set when the transmit holding register is empty. If the FIFO is enabled (FEN is 1), this bit is set when the transmit FIFO is empty. 7 TXFE RO 1 6 RXFF RO 0 UART Receive FIFO Full The meaning of this bit depends on the state of the FEN bit in the UARTLCRH register. If the FIFO is disabled, this bit is set when the receive holding register is full. If the FIFO is enabled, this bit is set when the receive FIFO is full. 5 TXFF RO 0 UART Transmit FIFO Full The meaning of this bit depends on the state of the FEN bit in the UARTLCRH register. If the FIFO is disabled, this bit is set when the transmit holding register is full. If the FIFO is enabled, this bit is set when the transmit FIFO is full. November 30, 2007 Preliminary 277 Universal Asynchronous Receivers/Transmitters (UARTs) Bit/Field 4 Name RXFE Type RO Reset 1 Description UART Receive FIFO Empty The meaning of this bit depends on the state of the FEN bit in the UARTLCRH register. If the FIFO is disabled, this bit is set when the receive holding register is empty. If the FIFO is enabled, this bit is set when the receive FIFO is empty. 3 BUSY RO 0 UART Busy When this bit is 1, the UART is busy transmitting data. This bit remains set until the complete byte, including all stop bits, has been sent from the shift register. This bit is set as soon as the transmit FIFO becomes non-empty (regardless of whether UART is enabled). 2:0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 278 Preliminary November 30, 2007 LM3S2016 Microcontroller Register 4: UART IrDA Low-Power Register (UARTILPR), offset 0x020 The UARTILPR register is an 8-bit read/write register that stores the low-power counter divisor value used to generate the IrLPBaud16 signal by dividing down the system clock (SysClk). All the bits are cleared to 0 when reset. The IrLPBaud16 internal signal is generated by dividing down the UARTCLK signal according to the low-power divisor value written to UARTILPR. The low-power divisor value is calculated as follows: ILPDVSR = SysClk / FIrLPBaud16 where FIrLPBaud16 is nominally 1.8432 MHz. IrLPBaud16 is an internal signal used for SIR pulse generation when low-power mode is used. You must choose the divisor so that 1.42 MHz < FIrLPBaud16 < 2.12 MHz, which results in a low-power pulse duration of 1.41–2.11 μs (three times the period of IrLPBaud16). The minimum frequency of IrLPBaud16 ensures that pulses less than one period of IrLPBaud16 are rejected, but that pulses greater than 1.4 μs are accepted as valid pulses. Note: Zero is an illegal value. Programming a zero value results in no IrLPBaud16 pulses being generated. UART IrDA Low-Power Register (UARTILPR) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 Offset 0x020 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 ILPDVSR R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field 31:8 Name reserved Type RO Reset 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. IrDA Low-Power Divisor This is an 8-bit low-power divisor value. 7:0 ILPDVSR R/W 0x00 November 30, 2007 Preliminary 279 Universal Asynchronous Receivers/Transmitters (UARTs) Register 5: UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 The UARTIBRD register is the integer part of the baud-rate divisor value. All the bits are cleared on reset. The minimum possible divide ratio is 1 (when UARTIBRD=0), in which case the UARTFBRD register is ignored. When changing the UARTIBRD register, the new value does not take effect until transmission/reception of the current character is complete. Any changes to the baud-rate divisor must be followed by a write to the UARTLCRH register. See “Baud-Rate Generation” on page 267 for configuration details. UART Integer Baud-Rate Divisor (UARTIBRD) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 Offset 0x024 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 DIVINT Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 Bit/Field 31:16 Name reserved Type RO Reset 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Integer Baud-Rate Divisor 15:0 DIVINT R/W 0x0000 280 Preliminary November 30, 2007 LM3S2016 Microcontroller Register 6: UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 The UARTFBRD register is the fractional part of the baud-rate divisor value. All the bits are cleared on reset. When changing the UARTFBRD register, the new value does not take effect until transmission/reception of the current character is complete. Any changes to the baud-rate divisor must be followed by a write to the UARTLCRH register. See “Baud-Rate Generation” on page 267 for configuration details. UART Fractional Baud-Rate Divisor (UARTFBRD) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 Offset 0x028 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 DIVFRAC R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field 31:6 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Fractional Baud-Rate Divisor 5:0 DIVFRAC R/W 0x000 November 30, 2007 Preliminary 281 Universal Asynchronous Receivers/Transmitters (UARTs) Register 7: UART Line Control (UARTLCRH), offset 0x02C The UARTLCRH register is the line control register. Serial parameters such as data length, parity, and stop bit selection are implemented in this register. When updating the baud-rate divisor (UARTIBRD and/or UARTIFRD), the UARTLCRH register must also be written. The write strobe for the baud-rate divisor registers is tied to the UARTLCRH register. UART Line Control (UARTLCRH) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 Offset 0x02C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 SPS RO 0 RO 0 RO 0 R/W 0 RO 0 6 WLEN R/W 0 R/W 0 RO 0 5 RO 0 4 FEN R/W 0 RO 0 3 STP2 R/W 0 RO 0 2 EPS R/W 0 RO 0 1 PEN R/W 0 RO 0 0 BRK R/W 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. UART Stick Parity Select When bits 1, 2, and 7 of UARTLCRH are set, the parity bit is transmitted and checked as a 0. When bits 1 and 7 are set and 2 is cleared, the parity bit is transmitted and checked as a 1. When this bit is cleared, stick parity is disabled. 7 SPS R/W 0 6:5 WLEN R/W 0 UART Word Length The bits indicate the number of data bits transmitted or received in a frame as follows: Value Description 0x3 8 bits 0x2 7 bits 0x1 6 bits 0x0 5 bits (default) 4 FEN R/W 0 UART Enable FIFOs If this bit is set to 1, transmit and receive FIFO buffers are enabled (FIFO mode). When cleared to 0, FIFOs are disabled (Character mode). The FIFOs become 1-byte-deep holding registers. 282 Preliminary November 30, 2007 LM3S2016 Microcontroller Bit/Field 3 Name STP2 Type R/W Reset 0 Description UART Two Stop Bits Select If this bit is set to 1, two stop bits are transmitted at the end of a frame. The receive logic does not check for two stop bits being received. 2 EPS R/W 0 UART Even Parity Select If this bit is set to 1, even parity generation and checking is performed during transmission and reception, which checks for an even number of 1s in data and parity bits. When cleared to 0, then odd parity is performed, which checks for an odd number of 1s. This bit has no effect when parity is disabled by the PEN bit. 1 PEN R/W 0 UART Parity Enable If this bit is set to 1, parity checking and generation is enabled; otherwise, parity is disabled and no parity bit is added to the data frame. 0 BRK R/W 0 UART Send Break If this bit is set to 1, a Low level is continually output on the UnTX output, after completing transmission of the current character. For the proper execution of the break command, the software must set this bit for at least two frames (character periods). For normal use, this bit must be cleared to 0. November 30, 2007 Preliminary 283 Universal Asynchronous Receivers/Transmitters (UARTs) Register 8: UART Control (UARTCTL), offset 0x030 The UARTCTL register is the control register. All the bits are cleared on reset except for the Transmit Enable (TXE) and Receive Enable (RXE) bits, which are set to 1. To enable the UART module, the UARTEN bit must be set to 1. If software requires a configuration change in the module, the UARTEN bit must be cleared before the configuration changes are written. If the UART is disabled during a transmit or receive operation, the current transaction is completed prior to the UART stopping. UART Control (UARTCTL) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 Offset 0x030 Type R/W, reset 0x0000.0300 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RXE RO 0 RO 0 R/W 1 RO 0 8 TXE R/W 1 RO 0 7 LBE R/W 0 RO 0 RO 0 6 RO 0 5 reserved RO 0 RO 0 RO 0 RO 0 4 RO 0 3 RO 0 2 SIRLP R/W 0 RO 0 1 SIREN R/W 0 RO 0 0 UARTEN R/W 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 Bit/Field 31:10 Name reserved Type RO Reset 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. UART Receive Enable If this bit is set to 1, the receive section of the UART is enabled. When the UART is disabled in the middle of a receive, it completes the current character before stopping. Note: To enable reception, the UARTEN bit must also be set. 9 RXE R/W 1 8 TXE R/W 1 UART Transmit Enable If this bit is set to 1, the transmit section of the UART is enabled. When the UART is disabled in the middle of a transmission, it completes the current character before stopping. Note: To enable transmission, the UARTEN bit must also be set. 7 LBE R/W 0 UART Loop Back Enable If this bit is set to 1, the UnTX path is fed through the UnRX path. 6:3 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 284 Preliminary November 30, 2007 LM3S2016 Microcontroller Bit/Field 2 Name SIRLP Type R/W Reset 0 Description UART SIR Low Power Mode This bit selects the IrDA encoding mode. If this bit is cleared to 0, low-level bits are transmitted as an active High pulse with a width of 3/16th of the bit period. If this bit is set to 1, low-level bits are transmitted with a pulse width which is 3 times the period of the IrLPBaud16 input signal, regardless of the selected bit rate. Setting this bit uses less power, but might reduce transmission distances. See page 279 for more information. 1 SIREN R/W 0 UART SIR Enable If this bit is set to 1, the IrDA SIR block is enabled, and the UART will transmit and receive data using SIR protocol. 0 UARTEN R/W 0 UART Enable If this bit is set to 1, the UART is enabled. When the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. November 30, 2007 Preliminary 285 Universal Asynchronous Receivers/Transmitters (UARTs) Register 9: UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 The UARTIFLS register is the interrupt FIFO level select register. You can use this register to define the FIFO level at which the TXRIS and RXRIS bits in the UARTRIS register are triggered. The interrupts are generated based on a transition through a level rather than being based on the level. That is, the interrupts are generated when the fill level progresses through the trigger level. For example, if the receive trigger level is set to the half-way mark, the interrupt is triggered as the module is receiving the 9th character. Out of reset, the TXIFLSEL and RXIFLSEL bits are configured so that the FIFOs trigger an interrupt at the half-way mark. UART Interrupt FIFO Level Select (UARTIFLS) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 Offset 0x034 Type R/W, reset 0x0000.0012 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RXIFLSEL RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 1 R/W 0 R/W 0 RO 0 3 RO 0 2 RO 0 1 TXIFLSEL R/W 1 R/W 0 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:6 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. UART Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows: Value 0x0 0x1 0x2 0x3 0x4 Description RX FIFO ≥ 1/8 full RX FIFO ≥ ¼ full RX FIFO ≥ ½ full (default) RX FIFO ≥ ¾ full RX FIFO ≥ 7/8 full 5:3 RXIFLSEL R/W 0x2 0x5-0x7 Reserved 286 Preliminary November 30, 2007 LM3S2016 Microcontroller Bit/Field 2:0 Name TXIFLSEL Type R/W Reset 0x2 Description UART Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows: Value 0x0 0x1 0x2 0x3 0x4 Description TX FIFO ≤ 1/8 full TX FIFO ≤ ¼ full TX FIFO ≤ ½ full (default) TX FIFO ≤ ¾ full TX FIFO ≤ 7/8 full 0x5-0x7 Reserved November 30, 2007 Preliminary 287 Universal Asynchronous Receivers/Transmitters (UARTs) Register 10: UART Interrupt Mask (UARTIM), offset 0x038 The UARTIM register is the interrupt mask set/clear register. On a read, this register gives the current value of the mask on the relevant interrupt. Writing a 1 to a bit allows the corresponding raw interrupt signal to be routed to the interrupt controller. Writing a 0 prevents the raw interrupt signal from being sent to the interrupt controller. UART Interrupt Mask (UARTIM) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 Offset 0x038 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 12 RO 0 11 RO 0 10 OEIM R/W 0 RO 0 9 BEIM R/W 0 RO 0 8 PEIM R/W 0 RO 0 7 FEIM R/W 0 RO 0 6 RTIM R/W 0 RO 0 5 TXIM R/W 0 RO 0 4 RXIM R/W 0 RO 0 RO 0 3 RO 0 2 reserved RO 0 RO 0 RO 0 RO 0 1 RO 0 0 Bit/Field 31:11 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. UART Overrun Error Interrupt Mask On a read, the current mask for the OEIM interrupt is returned. Setting this bit to 1 promotes the OEIM interrupt to the interrupt controller. 10 OEIM R/W 0 9 BEIM R/W 0 UART Break Error Interrupt Mask On a read, the current mask for the BEIM interrupt is returned. Setting this bit to 1 promotes the BEIM interrupt to the interrupt controller. 8 PEIM R/W 0 UART Parity Error Interrupt Mask On a read, the current mask for the PEIM interrupt is returned. Setting this bit to 1 promotes the PEIM interrupt to the interrupt controller. 7 FEIM R/W 0 UART Framing Error Interrupt Mask On a read, the current mask for the FEIM interrupt is returned. Setting this bit to 1 promotes the FEIM interrupt to the interrupt controller. 6 RTIM R/W 0 UART Receive Time-Out Interrupt Mask On a read, the current mask for the RTIM interrupt is returned. Setting this bit to 1 promotes the RTIM interrupt to the interrupt controller. 5 TXIM R/W 0 UART Transmit Interrupt Mask On a read, the current mask for the TXIM interrupt is returned. Setting this bit to 1 promotes the TXIM interrupt to the interrupt controller. 288 Preliminary November 30, 2007 LM3S2016 Microcontroller Bit/Field 4 Name RXIM Type R/W Reset 0 Description UART Receive Interrupt Mask On a read, the current mask for the RXIM interrupt is returned. Setting this bit to 1 promotes the RXIM interrupt to the interrupt controller. 3:0 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. November 30, 2007 Preliminary 289 Universal Asynchronous Receivers/Transmitters (UARTs) Register 11: UART Raw Interrupt Status (UARTRIS), offset 0x03C The UARTRIS register is the raw interrupt status register. On a read, this register gives the current raw status value of the corresponding interrupt. A write has no effect. UART Raw Interrupt Status (UARTRIS) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 Offset 0x03C Type RO, reset 0x0000.000F 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 12 RO 0 11 RO 0 10 OERIS RO 0 RO 0 9 BERIS RO 0 RO 0 8 PERIS RO 0 RO 0 7 FERIS RO 0 RO 0 6 RTRIS RO 0 RO 0 5 TXRIS RO 0 RO 0 4 RXRIS RO 0 RO 1 RO 0 3 RO 0 2 reserved RO 1 RO 1 RO 1 RO 0 1 RO 0 0 Bit/Field 31:11 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. UART Overrun Error Raw Interrupt Status Gives the raw interrupt state (prior to masking) of this interrupt. 10 OERIS RO 0 9 BERIS RO 0 UART Break Error Raw Interrupt Status Gives the raw interrupt state (prior to masking) of this interrupt. 8 PERIS RO 0 UART Parity Error Raw Interrupt Status Gives the raw interrupt state (prior to masking) of this interrupt. 7 FERIS RO 0 UART Framing Error Raw Interrupt Status Gives the raw interrupt state (prior to masking) of this interrupt. 6 RTRIS RO 0 UART Receive Time-Out Raw Interrupt Status Gives the raw interrupt state (prior to masking) of this interrupt. 5 TXRIS RO 0 UART Transmit Raw Interrupt Status Gives the raw interrupt state (prior to masking) of this interrupt. 4 RXRIS RO 0 UART Receive Raw Interrupt Status Gives the raw interrupt state (prior to masking) of this interrupt. 3:0 reserved RO 0xF Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 290 Preliminary November 30, 2007 LM3S2016 Microcontroller Register 12: UART Masked Interrupt Status (UARTMIS), offset 0x040 The UARTMIS register is the masked interrupt status register. On a read, this register gives the current masked status value of the corresponding interrupt. A write has no effect. UART Masked Interrupt Status (UARTMIS) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 Offset 0x040 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 12 RO 0 11 RO 0 10 OEMIS RO 0 RO 0 9 BEMIS RO 0 RO 0 8 PEMIS RO 0 RO 0 7 FEMIS RO 0 RO 0 6 RTMIS RO 0 RO 0 5 TXMIS RO 0 RO 0 4 RXMIS RO 0 RO 0 RO 0 3 RO 0 2 reserved RO 0 RO 0 RO 0 RO 0 1 RO 0 0 Bit/Field 31:11 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. UART Overrun Error Masked Interrupt Status Gives the masked interrupt state of this interrupt. 10 OEMIS RO 0 9 BEMIS RO 0 UART Break Error Masked Interrupt Status Gives the masked interrupt state of this interrupt. 8 PEMIS RO 0 UART Parity Error Masked Interrupt Status Gives the masked interrupt state of this interrupt. 7 FEMIS RO 0 UART Framing Error Masked Interrupt Status Gives the masked interrupt state of this interrupt. 6 RTMIS RO 0 UART Receive Time-Out Masked Interrupt Status Gives the masked interrupt state of this interrupt. 5 TXMIS RO 0 UART Transmit Masked Interrupt Status Gives the masked interrupt state of this interrupt. 4 RXMIS RO 0 UART Receive Masked Interrupt Status Gives the masked interrupt state of this interrupt. 3:0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. November 30, 2007 Preliminary 291 Universal Asynchronous Receivers/Transmitters (UARTs) Register 13: UART Interrupt Clear (UARTICR), offset 0x044 The UARTICR register is the interrupt clear register. On a write of 1, the corresponding interrupt (both raw interrupt and masked interrupt, if enabled) is cleared. A write of 0 has no effect. UART Interrupt Clear (UARTICR) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 Offset 0x044 Type W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 12 RO 0 11 RO 0 10 OEIC W1C 0 RO 0 9 BEIC W1C 0 RO 0 8 PEIC W1C 0 RO 0 7 FEIC W1C 0 RO 0 6 RTIC W1C 0 RO 0 5 TXIC W1C 0 RO 0 4 RXIC W1C 0 RO 0 RO 0 3 RO 0 2 reserved RO 0 RO 0 RO 0 RO 0 1 RO 0 0 Bit/Field 31:11 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Overrun Error Interrupt Clear The OEIC values are defined as follows: Value Description 0 1 No effect on the interrupt. Clears interrupt. 10 OEIC W1C 0 9 BEIC W1C 0 Break Error Interrupt Clear The BEIC values are defined as follows: Value Description 0 1 No effect on the interrupt. Clears interrupt. 8 PEIC W1C 0 Parity Error Interrupt Clear The PEIC values are defined as follows: Value Description 0 1 No effect on the interrupt. Clears interrupt. 292 Preliminary November 30, 2007 LM3S2016 Microcontroller Bit/Field 7 Name FEIC Type W1C Reset 0 Description Framing Error Interrupt Clear The FEIC values are defined as follows: Value Description 0 1 No effect on the interrupt. Clears interrupt. 6 RTIC W1C 0 Receive Time-Out Interrupt Clear The RTIC values are defined as follows: Value Description 0 1 No effect on the interrupt. Clears interrupt. 5 TXIC W1C 0 Transmit Interrupt Clear The TXIC values are defined as follows: Value Description 0 1 No effect on the interrupt. Clears interrupt. 4 RXIC W1C 0 Receive Interrupt Clear The RXIC values are defined as follows: Value Description 0 1 No effect on the interrupt. Clears interrupt. 3:0 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. November 30, 2007 Preliminary 293 Universal Asynchronous Receivers/Transmitters (UARTs) Register 14: UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the reset values. UART Peripheral Identification 4 (UARTPeriphID4) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 Offset 0xFD0 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 PID4 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. UART Peripheral ID Register[7:0] Can be used by software to identify the presence of this peripheral. 7:0 PID4 RO 0x0000 294 Preliminary November 30, 2007 LM3S2016 Microcontroller Register 15: UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the reset values. UART Peripheral Identification 5 (UARTPeriphID5) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 Offset 0xFD4 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 PID5 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. UART Peripheral ID Register[15:8] Can be used by software to identify the presence of this peripheral. 7:0 PID5 RO 0x0000 November 30, 2007 Preliminary 295 Universal Asynchronous Receivers/Transmitters (UARTs) Register 16: UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the reset values. UART Peripheral Identification 6 (UARTPeriphID6) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 Offset 0xFD8 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 PID6 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. UART Peripheral ID Register[23:16] Can be used by software to identify the presence of this peripheral. 7:0 PID6 RO 0x0000 296 Preliminary November 30, 2007 LM3S2016 Microcontroller Register 17: UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the reset values. UART Peripheral Identification 7 (UARTPeriphID7) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 Offset 0xFDC Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 PID7 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. UART Peripheral ID Register[31:24] Can be used by software to identify the presence of this peripheral. 7:0 PID7 RO 0x0000 November 30, 2007 Preliminary 297 Universal Asynchronous Receivers/Transmitters (UARTs) Register 18: UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the reset values. UART Peripheral Identification 0 (UARTPeriphID0) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 Offset 0xFE0 Type RO, reset 0x0000.0011 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 PID0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 0 RO 0 RO 0 RO 1 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. UART Peripheral ID Register[7:0] Can be used by software to identify the presence of this peripheral. 7:0 PID0 RO 0x11 298 Preliminary November 30, 2007 LM3S2016 Microcontroller Register 19: UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the reset values. UART Peripheral Identification 1 (UARTPeriphID1) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 Offset 0xFE4 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 PID1 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. UART Peripheral ID Register[15:8] Can be used by software to identify the presence of this peripheral. 7:0 PID1 RO 0x00 November 30, 2007 Preliminary 299 Universal Asynchronous Receivers/Transmitters (UARTs) Register 20: UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the reset values. UART Peripheral Identification 2 (UARTPeriphID2) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 Offset 0xFE8 Type RO, reset 0x0000.0018 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 PID2 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 1 RO 0 RO 0 RO 0 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. UART Peripheral ID Register[23:16] Can be used by software to identify the presence of this peripheral. 7:0 PID2 RO 0x18 300 Preliminary November 30, 2007 LM3S2016 Microcontroller Register 21: UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the reset values. UART Peripheral Identification 3 (UARTPeriphID3) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 Offset 0xFEC Type RO, reset 0x0000.0001 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 PID3 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. UART Peripheral ID Register[31:24] Can be used by software to identify the presence of this peripheral. 7:0 PID3 RO 0x01 November 30, 2007 Preliminary 301 Universal Asynchronous Receivers/Transmitters (UARTs) Register 22: UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 The UARTPCellIDn registers are hard-coded and the fields within the registers determine the reset values. UART PrimeCell Identification 0 (UARTPCellID0) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 Offset 0xFF0 Type RO, reset 0x0000.000D 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 CID0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 1 RO 0 RO 1 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. UART PrimeCell ID Register[7:0] Provides software a standard cross-peripheral identification system. 7:0 CID0 RO 0x0D 302 Preliminary November 30, 2007 LM3S2016 Microcontroller Register 23: UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 The UARTPCellIDn registers are hard-coded and the fields within the registers determine the reset values. UART PrimeCell Identification 1 (UARTPCellID1) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 Offset 0xFF4 Type RO, reset 0x0000.00F0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 CID1 RO 0 RO 0 RO 0 RO 1 RO 1 RO 1 RO 1 RO 0 RO 0 RO 0 RO 0 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. UART PrimeCell ID Register[15:8] Provides software a standard cross-peripheral identification system. 7:0 CID1 RO 0xF0 November 30, 2007 Preliminary 303 Universal Asynchronous Receivers/Transmitters (UARTs) Register 24: UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 The UARTPCellIDn registers are hard-coded and the fields within the registers determine the reset values. UART PrimeCell Identification 2 (UARTPCellID2) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 Offset 0xFF8 Type RO, reset 0x0000.0005 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 CID2 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 0 RO 1 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. UART PrimeCell ID Register[23:16] Provides software a standard cross-peripheral identification system. 7:0 CID2 RO 0x05 304 Preliminary November 30, 2007 LM3S2016 Microcontroller Register 25: UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC The UARTPCellIDn registers are hard-coded and the fields within the registers determine the reset values. UART PrimeCell Identification 3 (UARTPCellID3) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 Offset 0xFFC Type RO, reset 0x0000.00B1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 CID3 RO 0 RO 0 RO 0 RO 1 RO 0 RO 1 RO 1 RO 0 RO 0 RO 0 RO 1 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. UART PrimeCell ID Register[31:24] Provides software a standard cross-peripheral identification system. 7:0 CID3 RO 0xB1 November 30, 2007 Preliminary 305 Synchronous Serial Interface (SSI) 13 Synchronous Serial Interface (SSI) The Stellaris Synchronous Serial Interface (SSI) is a master or slave interface for synchronous serial communication with peripheral devices that have either Freescale SPI, MICROWIRE, or Texas Instruments synchronous serial interfaces. The Stellaris SSI module has the following features: ■ Master or slave operation ■ Programmable clock bit rate and prescale ■ Separate transmit and receive FIFOs, 16 bits wide, 8 locations deep ■ Programmable interface operation for Freescale SPI, MICROWIRE, or Texas Instruments synchronous serial interfaces ■ Programmable data frame size from 4 to 16 bits ■ Internal loopback test mode for diagnostic/debug testing ® ® 13.1 Block Diagram Figure 13-1. SSI Module Block Diagram Interrupt Interrupt Control SSIIM SSIMIS Control / Status SSICR0 SSICR1 SSISR SSIDR RxFIFO 8 x 16 System Clock Clock Prescaler Identification Registers SSIPCellID0 SSIPCellID1 SSIPCellID2 SSIPCellID3 SSIPeriphID0 SSIPeriphID1 SSIPeriphID2 SSIPeriphID3 SSIPeriphID4 SSIPeriphID5 SSIPeriphID6 SSIPeriphID7 SSICPSR Transmit / Receive Logic SSIRIS SSIICR TxFIFO 8 x 16 . . . SSITx SSIRx SSIClk SSIFss . . . 13.2 Functional Description The SSI performs serial-to-parallel conversion on data received from a peripheral device. The CPU accesses data, control, and status information. The transmit and receive paths are buffered with 306 Preliminary November 30, 2007 LM3S2016 Microcontroller internal FIFO memories allowing up to eight 16-bit values to be stored independently in both transmit and receive modes. 13.2.1 Bit Rate Generation The SSI includes a programmable bit rate clock divider and prescaler to generate the serial output clock. Bit rates are supported to 2 MHz and higher, although maximum bit rate is determined by peripheral devices. The serial bit rate is derived by dividing down the 50-MHz input clock. The clock is first divided by an even prescale value CPSDVSR from 2 to 254, which is programmed in the SSI Clock Prescale (SSICPSR) register (see page 325). The clock is further divided by a value from 1 to 256, which is 1 + SCR, where SCR is the value programmed in the SSI Control0 (SSICR0) register (see page 318). The frequency of the output clock SSIClk is defined by: FSSIClk = FSysClk / (CPSDVSR * (1 + SCR)) Note that although the SSIClk transmit clock can theoretically be 25 MHz, the module may not be able to operate at that speed. For master mode, the system clock must be at least two times faster than the SSIClk. For slave mode, the system clock must be at least 12 times faster than the SSIClk. See “Synchronous Serial Interface (SSI)” on page 438 to view SSI timing parameters. 13.2.2 FIFO Operation 13.2.2.1 Transmit FIFO The common transmit FIFO is a 16-bit wide, 8-locations deep, first-in, first-out memory buffer. The CPU writes data to the FIFO by writing the SSI Data (SSIDR) register (see page 322), and data is stored in the FIFO until it is read out by the transmission logic. When configured as a master or a slave, parallel data is written into the transmit FIFO prior to serial conversion and transmission to the attached slave or master, respectively, through the SSITx pin. 13.2.2.2 Receive FIFO The common receive FIFO is a 16-bit wide, 8-locations deep, first-in, first-out memory buffer. Received data from the serial interface is stored in the buffer until read out by the CPU, which accesses the read FIFO by reading the SSIDR register. When configured as a master or slave, serial data received through the SSIRx pin is registered prior to parallel loading into the attached slave or master receive FIFO, respectively. 13.2.3 Interrupts The SSI can generate interrupts when the following conditions are observed: ■ Transmit FIFO service ■ Receive FIFO service ■ Receive FIFO time-out ■ Receive FIFO overrun All of the interrupt events are ORed together before being sent to the interrupt controller, so the SSI can only generate a single interrupt request to the controller at any given time. You can mask each November 30, 2007 Preliminary 307 Synchronous Serial Interface (SSI) of the four individual maskable interrupts by setting the appropriate bits in the SSI Interrupt Mask (SSIIM) register (see page 326). Setting the appropriate mask bit to 1 enables the interrupt. Provision of the individual outputs, as well as a combined interrupt output, allows use of either a global interrupt service routine, or modular device drivers to handle interrupts. The transmit and receive dynamic dataflow interrupts have been separated from the status interrupts so that data can be read or written in response to the FIFO trigger levels. The status of the individual interrupt sources can be read from the SSI Raw Interrupt Status (SSIRIS) and SSI Masked Interrupt Status (SSIMIS) registers (see page 328 and page 329, respectively). 13.2.4 Frame Formats Each data frame is between 4 and 16 bits long, depending on the size of data programmed, and is transmitted starting with the MSB. There are three basic frame types that can be selected: ■ Texas Instruments synchronous serial ■ Freescale SPI ■ MICROWIRE For all three formats, the serial clock (SSIClk) is held inactive while the SSI is idle, and SSIClk transitions at the programmed frequency only during active transmission or reception of data. The idle state of SSIClk is utilized to provide a receive timeout indication that occurs when the receive FIFO still contains data after a timeout period. For Freescale SPI and MICROWIRE frame formats, the serial frame (SSIFss ) pin is active Low, and is asserted (pulled down) during the entire transmission of the frame. For Texas Instruments synchronous serial frame format, the SSIFss pin is pulsed for one serial clock period starting at its rising edge, prior to the transmission of each frame. For this frame format, both the SSI and the off-chip slave device drive their output data on the rising edge of SSIClk, and latch data from the other device on the falling edge. Unlike the full-duplex transmission of the other two frame formats, the MICROWIRE format uses a special master-slave messaging technique, which operates at half-duplex. In this mode, when a frame begins, an 8-bit control message is transmitted to the off-chip slave. During this transmit, no incoming data is received by the SSI. After the message has been sent, the off-chip slave decodes it and, after waiting one serial clock after the last bit of the 8-bit control message has been sent, responds with the requested data. The returned data can be 4 to 16 bits in length, making the total frame length anywhere from 13 to 25 bits. 13.2.4.1 Texas Instruments Synchronous Serial Frame Format Figure 13-2 on page 308 shows the Texas Instruments synchronous serial frame format for a single transmitted frame. Figure 13-2. TI Synchronous Serial Frame Format (Single Transfer) SSIClk SSIFss SSITx/SSIRx MSB 4 to 16 bits LSB 308 Preliminary November 30, 2007 LM3S2016 Microcontroller In this mode, SSIClk and SSIFss are forced Low, and the transmit data line SSITx is tristated whenever the SSI is idle. Once the bottom entry of the transmit FIFO contains data, SSIFss is pulsed High for one SSIClk period. The value to be transmitted is also transferred from the transmit FIFO to the serial shift register of the transmit logic. On the next rising edge of SSIClk, the MSB of the 4 to 16-bit data frame is shifted out on the SSITx pin. Likewise, the MSB of the received data is shifted onto the SSIRx pin by the off-chip serial slave device. Both the SSI and the off-chip serial slave device then clock each data bit into their serial shifter on the falling edge of each SSIClk. The received data is transferred from the serial shifter to the receive FIFO on the first rising edge of SSIClk after the LSB has been latched. Figure 13-3 on page 309 shows the Texas Instruments synchronous serial frame format when back-to-back frames are transmitted. Figure 13-3. TI Synchronous Serial Frame Format (Continuous Transfer) SSIClk SSIFss SSITx/SSIRx MSB 4 to 16 bits LSB 13.2.4.2 Freescale SPI Frame Format The Freescale SPI interface is a four-wire interface where the SSIFss signal behaves as a slave select. The main feature of the Freescale SPI format is that the inactive state and phase of the SSIClk signal are programmable through the SPO and SPH bits within the SSISCR0 control register. SPO Clock Polarity Bit When the SPO clock polarity control bit is Low, it produces a steady state Low value on the SSIClk pin. If the SPO bit is High, a steady state High value is placed on the SSIClk pin when data is not being transferred. SPH Phase Control Bit The SPH phase control bit selects the clock edge that captures data and allows it to change state. It has the most impact on the first bit transmitted by either allowing or not allowing a clock transition before the first data capture edge. When the SPH phase control bit is Low, data is captured on the first clock edge transition. If the SPH bit is High, data is captured on the second clock edge transition. 13.2.4.3 Freescale SPI Frame Format with SPO=0 and SPH=0 Single and continuous transmission signal sequences for Freescale SPI format with SPO=0 and SPH=0 are shown in Figure 13-4 on page 310 and Figure 13-5 on page 310. November 30, 2007 Preliminary 309 Synchronous Serial Interface (SSI) Figure 13-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 SSIClk SSIFss SSIRx MSB 4 to 16 bits SSITx MSB LSB LSB Q Note: Q is undefined. Figure 13-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 SSIClk SSIFss SSIRx LSB MSB 4 to 16 bits SSITx LSB MSB LSB MSB LSB MSB In this configuration, during idle periods: ■ SSIClk is forced Low ■ SSIFss is forced High ■ The transmit data line SSITx is arbitrarily forced Low ■ When the SSI is configured as a master, it enables the SSIClk pad ■ When the SSI is configured as a slave, it disables the SSIClk pad If the SSI is enabled and there is valid data within the transmit FIFO, the start of transmission is signified by the SSIFss master signal being driven Low. This causes slave data to be enabled onto the SSIRx input line of the master. The master SSITx output pad is enabled. One half SSIClk period later, valid master data is transferred to the SSITx pin. Now that both the master and slave data have been set, the SSIClk master clock pin goes High after one further half SSIClk period. The data is now captured on the rising and propagated on the falling edges of the SSIClk signal. In the case of a single word transmission, after all bits of the data word have been transferred, the SSIFss line is returned to its idle High state one SSIClk period after the last bit has been captured. However, in the case of continuous back-to-back transmissions, the SSIFss signal must be pulsed High between each data word transfer. This is because the slave select pin freezes the data in its serial peripheral register and does not allow it to be altered if the SPH bit is logic zero. Therefore, the master device must raise the SSIFss pin of the slave device between each data transfer to enable the serial peripheral data write. On completion of the continuous transfer, the SSIFss pin is returned to its idle state one SSIClk period after the last bit has been captured. 310 Preliminary November 30, 2007 LM3S2016 Microcontroller 13.2.4.4 Freescale SPI Frame Format with SPO=0 and SPH=1 The transfer signal sequence for Freescale SPI format with SPO=0 and SPH=1 is shown in Figure 13-6 on page 311, which covers both single and continuous transfers. Figure 13-6. Freescale SPI Frame Format with SPO=0 and SPH=1 SSIClk SSIFss SSIRx Q MSB 4 to 16 bits SSITx MSB LSB LSB Q Note: Q is undefined. In this configuration, during idle periods: ■ SSIClk is forced Low ■ SSIFss is forced High ■ The transmit data line SSITx is arbitrarily forced Low ■ When the SSI is configured as a master, it enables the SSIClk pad ■ When the SSI is configured as a slave, it disables the SSIClk pad If the SSI is enabled and there is valid data within the transmit FIFO, the start of transmission is signified by the SSIFss master signal being driven Low. The master SSITx output is enabled. After a further one half SSIClk period, both master and slave valid data is enabled onto their respective transmission lines. At the same time, the SSIClk is enabled with a rising edge transition. Data is then captured on the falling edges and propagated on the rising edges of the SSIClk signal. In the case of a single word transfer, after all bits have been transferred, the SSIFss line is returned to its idle High state one SSIClk period after the last bit has been captured. For continuous back-to-back transfers, the SSIFss pin is held Low between successive data words and termination is the same as that of the single word transfer. 13.2.4.5 Freescale SPI Frame Format with SPO=1 and SPH=0 Single and continuous transmission signal sequences for Freescale SPI format with SPO=1 and SPH=0 are shown in Figure 13-7 on page 312 and Figure 13-8 on page 312. November 30, 2007 Preliminary 311 Synchronous Serial Interface (SSI) Figure 13-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 SSIClk SSIFss SSIRx MSB 4 to 16 bits SSITx MSB LSB LSB Q Note: Q is undefined. Figure 13-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 SSIClk SSIFss SSITx/SSIRxLSB MSB 4 to 16 bits LSB MSB In this configuration, during idle periods: ■ SSIClk is forced High ■ SSIFss is forced High ■ The transmit data line SSITx is arbitrarily forced Low ■ When the SSI is configured as a master, it enables the SSIClk pad ■ When the SSI is configured as a slave, it disables the SSIClk pad If the SSI is enabled and there is valid data within the transmit FIFO, the start of transmission is signified by the SSIFss master signal being driven Low, which causes slave data to be immediately transferred onto the SSIRx line of the master. The master SSITx output pad is enabled. One half period later, valid master data is transferred to the SSITx line. Now that both the master and slave data have been set, the SSIClk master clock pin becomes Low after one further half SSIClk period. This means that data is captured on the falling edges and propagated on the rising edges of the SSIClk signal. In the case of a single word transmission, after all bits of the data word are transferred, the SSIFss line is returned to its idle High state one SSIClk period after the last bit has been captured. However, in the case of continuous back-to-back transmissions, the SSIFss signal must be pulsed High between each data word transfer. This is because the slave select pin freezes the data in its serial peripheral register and does not allow it to be altered if the SPH bit is logic zero. Therefore, the master device must raise the SSIFss pin of the slave device between each data transfer to enable the serial peripheral data write. On completion of the continuous transfer, the SSIFss pin is returned to its idle state one SSIClk period after the last bit has been captured. 312 Preliminary November 30, 2007 LM3S2016 Microcontroller 13.2.4.6 Freescale SPI Frame Format with SPO=1 and SPH=1 The transfer signal sequence for Freescale SPI format with SPO=1 and SPH=1 is shown in Figure 13-9 on page 313, which covers both single and continuous transfers. Figure 13-9. Freescale SPI Frame Format with SPO=1 and SPH=1 SSIClk SSIFss SSIRx Q MSB 4 to 16 bits SSITx MSB LSB LSB Q Note: Q is undefined. In this configuration, during idle periods: ■ SSIClk is forced High ■ SSIFss is forced High ■ The transmit data line SSITx is arbitrarily forced Low ■ When the SSI is configured as a master, it enables the SSIClk pad ■ When the SSI is configured as a slave, it disables the SSIClk pad If the SSI is enabled and there is valid data within the transmit FIFO, the start of transmission is signified by the SSIFss master signal being driven Low. The master SSITx output pad is enabled. After a further one-half SSIClk period, both master and slave data are enabled onto their respective transmission lines. At the same time, SSIClk is enabled with a falling edge transition. Data is then captured on the rising edges and propagated on the falling edges of the SSIClk signal. After all bits have been transferred, in the case of a single word transmission, the SSIFss line is returned to its idle high state one SSIClk period after the last bit has been captured. For continuous back-to-back transmissions, the SSIFss pin remains in its active Low state, until the final bit of the last word has been captured, and then returns to its idle state as described above. For continuous back-to-back transfers, the SSIFss pin is held Low between successive data words and termination is the same as that of the single word transfer. 13.2.4.7 MICROWIRE Frame Format Figure 13-10 on page 314 shows the MICROWIRE frame format, again for a single frame. Figure 13-11 on page 315 shows the same format when back-to-back frames are transmitted. November 30, 2007 Preliminary 313 Synchronous Serial Interface (SSI) Figure 13-10. MICROWIRE Frame Format (Single Frame) SSIClk SSIFss SSITx SSIRx MSB LSB 8-bit control 0 MSB LSB 4 to 16 bits output data MICROWIRE format is very similar to SPI format, except that transmission is half-duplex instead of full-duplex, using a master-slave message passing technique. Each serial transmission begins with an 8-bit control word that is transmitted from the SSI to the off-chip slave device. During this transmission, no incoming data is received by the SSI. After the message has been sent, the off-chip slave decodes it and, after waiting one serial clock after the last bit of the 8-bit control message has been sent, responds with the required data. The returned data is 4 to 16 bits in length, making the total frame length anywhere from 13 to 25 bits. In this configuration, during idle periods: ■ SSIClk is forced Low ■ SSIFss is forced High ■ The transmit data line SSITx is arbitrarily forced Low A transmission is triggered by writing a control byte to the transmit FIFO. The falling edge of SSIFss causes the value contained in the bottom entry of the transmit FIFO to be transferred to the serial shift register of the transmit logic, and the MSB of the 8-bit control frame to be shifted out onto the SSITx pin. SSIFss remains Low for the duration of the frame transmission. The SSIRx pin remains tristated during this transmission. The off-chip serial slave device latches each control bit into its serial shifter on the rising edge of each SSIClk. After the last bit is latched by the slave device, the control byte is decoded during a one clock wait-state, and the slave responds by transmitting data back to the SSI. Each bit is driven onto the SSIRx line on the falling edge of SSIClk. The SSI in turn latches each bit on the rising edge of SSIClk. At the end of the frame, for single transfers, the SSIFss signal is pulled High one clock period after the last bit has been latched in the receive serial shifter, which causes the data to be transferred to the receive FIFO. Note: The off-chip slave device can tristate the receive line either on the falling edge of SSIClk after the LSB has been latched by the receive shifter, or when the SSIFss pin goes High. For continuous transfers, data transmission begins and ends in the same manner as a single transfer. However, the SSIFss line is continuously asserted (held Low) and transmission of data occurs back-to-back. The control byte of the next frame follows directly after the LSB of the received data from the current frame. Each of the received values is transferred from the receive shifter on the falling edge of SSIClk, after the LSB of the frame has been latched into the SSI. 314 Preliminary November 30, 2007 LM3S2016 Microcontroller Figure 13-11. MICROWIRE Frame Format (Continuous Transfer) SSIClk SSIFss SSITx LSB MSB LSB 8-bit control SSIRx 0 MSB LSB MSB 4 to 16 bits output data In the MICROWIRE mode, the SSI slave samples the first bit of receive data on the rising edge of SSIClk after SSIFss has gone Low. Masters that drive a free-running SSIClk must ensure that the SSIFss signal has sufficient setup and hold margins with respect to the rising edge of SSIClk. Figure 13-12 on page 315 illustrates these setup and hold time requirements. With respect to the SSIClk rising edge on which the first bit of receive data is to be sampled by the SSI slave, SSIFss must have a setup of at least two times the period of SSIClk on which the SSI operates. With respect to the SSIClk rising edge previous to this edge, SSIFss must have a hold of at least one SSIClk period. Figure 13-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements tSetup=(2*tSSIClk ) tHold=tSSIClk SSIClk SSIFss SSIRx First RX data to be sampled by SSI slave 13.3 Initialization and Configuration To use the SSI, its peripheral clock must be enabled by setting the SSI bit in the RCGC1 register. For each of the frame formats, the SSI is configured using the following steps: 1. Ensure that the SSE bit in the SSICR1 register is disabled before making any configuration changes. 2. Select whether the SSI is a master or slave: a. For master operations, set the SSICR1 register to 0x0000.0000. b. For slave mode (output enabled), set the SSICR1 register to 0x0000.0004. c. For slave mode (output disabled), set the SSICR1 register to 0x0000.000C. 3. Configure the clock prescale divisor by writing the SSICPSR register. November 30, 2007 Preliminary 315 Synchronous Serial Interface (SSI) 4. Write the SSICR0 register with the following configuration: ■ Serial clock rate (SCR) ■ Desired clock phase/polarity, if using Freescale SPI mode (SPH and SPO) ■ The protocol mode: Freescale SPI, TI SSF, MICROWIRE (FRF) ■ The data size (DSS) 5. Enable the SSI by setting the SSE bit in the SSICR1 register. As an example, assume the SSI must be configured to operate with the following parameters: ■ Master operation ■ Freescale SPI mode (SPO=1, SPH=1) ■ 1 Mbps bit rate ■ 8 data bits Assuming the system clock is 20 MHz, the bit rate calculation would be: FSSIClk = FSysClk / (CPSDVSR * (1 + SCR)) 1x106 = 20x106 / (CPSDVSR * (1 + SCR)) In this case, if CPSDVSR=2, SCR must be 9. The configuration sequence would be as follows: 1. Ensure that the SSE bit in the SSICR1 register is disabled. 2. Write the SSICR1 register with a value of 0x0000.0000. 3. Write the SSICPSR register with a value of 0x0000.0002. 4. Write the SSICR0 register with a value of 0x0000.09C7. 5. The SSI is then enabled by setting the SSE bit in the SSICR1 register to 1. 13.4 Register Map Table 13-1 on page 316 lists the SSI registers. The offset listed is a hexadecimal increment to the register ’s address, relative to that SSI module’s base address: ■ SSI0: 0x4000.8000 Note: The SSI must be disabled (see the SSE bit in the SSICR1 register) before any of the control registers are reprogrammed. Table 13-1. SSI Register Map Offset 0x000 Name SSICR0 Type R/W Reset 0x0000.0000 Description SSI Control 0 See page 318 316 Preliminary November 30, 2007 LM3S2016 Microcontroller Offset 0x004 0x008 0x00C 0x010 0x014 0x018 0x01C 0x020 0xFD0 0xFD4 0xFD8 0xFDC 0xFE0 0xFE4 0xFE8 0xFEC 0xFF0 0xFF4 0xFF8 0xFFC Name SSICR1 SSIDR SSISR SSICPSR SSIIM SSIRIS SSIMIS SSIICR SSIPeriphID4 SSIPeriphID5 SSIPeriphID6 SSIPeriphID7 SSIPeriphID0 SSIPeriphID1 SSIPeriphID2 SSIPeriphID3 SSIPCellID0 SSIPCellID1 SSIPCellID2 SSIPCellID3 Type R/W R/W RO R/W R/W RO RO W1C RO RO RO RO RO RO RO RO RO RO RO RO Reset 0x0000.0000 0x0000.0000 0x0000.0003 0x0000.0000 0x0000.0000 0x0000.0008 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0022 0x0000.0000 0x0000.0018 0x0000.0001 0x0000.000D 0x0000.00F0 0x0000.0005 0x0000.00B1 Description SSI Control 1 SSI Data SSI Status SSI Clock Prescale SSI Interrupt Mask SSI Raw Interrupt Status SSI Masked Interrupt Status SSI Interrupt Clear SSI Peripheral Identification 4 SSI Peripheral Identification 5 SSI Peripheral Identification 6 SSI Peripheral Identification 7 SSI Peripheral Identification 0 SSI Peripheral Identification 1 SSI Peripheral Identification 2 SSI Peripheral Identification 3 SSI PrimeCell Identification 0 SSI PrimeCell Identification 1 SSI PrimeCell Identification 2 SSI PrimeCell Identification 3 See page 320 322 323 325 326 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 13.5 Register Descriptions The remainder of this section lists and describes the SSI registers, in numerical order by address offset. November 30, 2007 Preliminary 317 Synchronous Serial Interface (SSI) Register 1: SSI Control 0 (SSICR0), offset 0x000 SSICR0 is control register 0 and contains bit fields that control various functions within the SSI module. Functionality such as protocol mode, clock rate, and data size are configured in this register. SSI Control 0 (SSICR0) SSI0 base: 0x4000.8000 Offset 0x000 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 SCR Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 SPH R/W 0 RO 0 6 SPO R/W 0 R/W 0 RO 0 5 FRF R/W 0 R/W 0 R/W 0 RO 0 4 RO 0 3 RO 0 2 DSS R/W 0 R/W 0 RO 0 1 RO 0 0 Bit/Field 31:16 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SSI Serial Clock Rate The value SCR is used to generate the transmit and receive bit rate of the SSI. The bit rate is: BR=FSSIClk/(CPSDVSR * (1 + SCR)) where CPSDVSR is an even value from 2-254 programmed in the SSICPSR register, and SCR is a value from 0-255. 15:8 SCR R/W 0x0000 7 SPH R/W 0 SSI Serial Clock Phase This bit is only applicable to the Freescale SPI Format. The SPH control bit selects the clock edge that captures data and allows it to change state. It has the most impact on the first bit transmitted by either allowing or not allowing a clock transition before the first data capture edge. When the SPH bit is 0, data is captured on the first clock edge transition. If SPH is 1, data is captured on the second clock edge transition. 6 SPO R/W 0 SSI Serial Clock Polarity This bit is only applicable to the Freescale SPI Format. When the SPO bit is 0, it produces a steady state Low value on the SSIClk pin. If SPO is 1, a steady state High value is placed on the SSIClk pin when data is not being transferred. 318 Preliminary November 30, 2007 LM3S2016 Microcontroller Bit/Field 5:4 Name FRF Type R/W Reset 0x0 Description SSI Frame Format Select The FRF values are defined as follows: Value Frame Format 0x0 Freescale SPI Frame Format 0x1 Texas Intruments Synchronous Serial Frame Format 0x2 MICROWIRE Frame Format 0x3 Reserved 3:0 DSS R/W 0x00 SSI Data Size Select The DSS values are defined as follows: Value Data Size 0x0-0x2 Reserved 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF 4-bit data 5-bit data 6-bit data 7-bit data 8-bit data 9-bit data 10-bit data 11-bit data 12-bit data 13-bit data 14-bit data 15-bit data 16-bit data November 30, 2007 Preliminary 319 Synchronous Serial Interface (SSI) Register 2: SSI Control 1 (SSICR1), offset 0x004 SSICR1 is control register 1 and contains bit fields that control various functions within the SSI module. Master and slave mode functionality is controlled by this register. SSI Control 1 (SSICR1) SSI0 base: 0x4000.8000 Offset 0x004 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 SOD R/W 0 RO 0 2 MS R/W 0 RO 0 1 SSE R/W 0 RO 0 0 LBM R/W 0 Bit/Field 31:4 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SSI Slave Mode Output Disable This bit is relevant only in the Slave mode (MS=1). In multiple-slave systems, it is possible for the SSI master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto the serial output line. In such systems, the TXD lines from multiple slaves could be tied together. To operate in such a system, the SOD bit can be configured so that the SSI slave does not drive the SSITx pin. The SOD values are defined as follows: Value Description 0 1 SSI can drive SSITx output in Slave Output mode. SSI must not drive the SSITx output in Slave mode. 3 SOD R/W 0 2 MS R/W 0 SSI Master/Slave Select This bit selects Master or Slave mode and can be modified only when SSI is disabled (SSE=0). The MS values are defined as follows: Value Description 0 1 Device configured as a master. Device configured as a slave. 320 Preliminary November 30, 2007 LM3S2016 Microcontroller Bit/Field 1 Name SSE Type R/W Reset 0 Description SSI Synchronous Serial Port Enable Setting this bit enables SSI operation. The SSE values are defined as follows: Value Description 0 1 SSI operation disabled. SSI operation enabled. Note: This bit must be set to 0 before any control registers are reprogrammed. 0 LBM R/W 0 SSI Loopback Mode Setting this bit enables Loopback Test mode. The LBM values are defined as follows: Value Description 0 1 Normal serial port operation enabled. Output of the transmit serial shift register is connected internally to the input of the receive serial shift register. November 30, 2007 Preliminary 321 Synchronous Serial Interface (SSI) Register 3: SSI Data (SSIDR), offset 0x008 SSIDR is the data register and is 16-bits wide. When SSIDR is read, the entry in the receive FIFO (pointed to by the current FIFO read pointer) is accessed. As data values are removed by the SSI receive logic from the incoming data frame, they are placed into the entry in the receive FIFO (pointed to by the current FIFO write pointer). When SSIDR is written to, the entry in the transmit FIFO (pointed to by the write pointer) is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSITx pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer. When the SSI is programmed for MICROWIRE frame format, the default size for transmit data is eight bits (the most significant byte is ignored). The receive data size is controlled by the programmer. The transmit FIFO and the receive FIFO are not cleared even when the SSE bit in the SSICR1 register is set to zero. This allows the software to fill the transmit FIFO before enabling the SSI. SSI Data (SSIDR) SSI0 base: 0x4000.8000 Offset 0x008 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 DATA Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 Bit/Field 31:16 Name reserved Type RO Reset 0x0000 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SSI Receive/Transmit Data A read operation reads the receive FIFO. A write operation writes the transmit FIFO. Software must right-justify data when the SSI is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by the transmit logic. The receive logic automatically right-justifies the data. 15:0 DATA R/W 0x0000 322 Preliminary November 30, 2007 LM3S2016 Microcontroller Register 4: SSI Status (SSISR), offset 0x00C SSISR is a status register that contains bits that indicate the FIFO fill status and the SSI busy status. SSI Status (SSISR) SSI0 base: 0x4000.8000 Offset 0x00C Type RO, reset 0x0000.0003 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 BSY RO 0 RO 0 3 RFF RO 0 RO 0 2 RNE RO 0 RO 0 1 TNF RO 1 RO 0 0 TFE R0 1 Bit/Field 31:5 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SSI Busy Bit The BSY values are defined as follows: Value Description 0 1 SSI is idle. SSI is currently transmitting and/or receiving a frame, or the transmit FIFO is not empty. 4 BSY RO 0 3 RFF RO 0 SSI Receive FIFO Full The RFF values are defined as follows: Value Description 0 1 Receive FIFO is not full. Receive FIFO is full. 2 RNE RO 0 SSI Receive FIFO Not Empty The RNE values are defined as follows: Value Description 0 1 Receive FIFO is empty. Receive FIFO is not empty. 1 TNF RO 1 SSI Transmit FIFO Not Full The TNF values are defined as follows: Value Description 0 1 Transmit FIFO is full. Transmit FIFO is not full. November 30, 2007 Preliminary 323 Synchronous Serial Interface (SSI) Bit/Field 0 Name TFE Type R0 Reset 1 Description SSI Transmit FIFO Empty The TFE values are defined as follows: Value Description 0 1 Transmit FIFO is not empty. Transmit FIFO is empty. 324 Preliminary November 30, 2007 LM3S2016 Microcontroller Register 5: SSI Clock Prescale (SSICPSR), offset 0x010 SSICPSR is the clock prescale register and specifies the division factor by which the system clock must be internally divided before further use. The value programmed into this register must be an even number between 2 and 254. The least-significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least-significant bit as zero. SSI Clock Prescale (SSICPSR) SSI0 base: 0x4000.8000 Offset 0x010 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 CPSDVSR R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SSI Clock Prescale Divisor This value must be an even number from 2 to 254, depending on the frequency of SSIClk. The LSB always returns 0 on reads. 7:0 CPSDVSR R/W 0x00 November 30, 2007 Preliminary 325 Synchronous Serial Interface (SSI) Register 6: SSI Interrupt Mask (SSIIM), offset 0x014 The SSIIM register is the interrupt mask set or clear register. It is a read/write register and all bits are cleared to 0 on reset. On a read, this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. SSI Interrupt Mask (SSIIM) SSI0 base: 0x4000.8000 Offset 0x014 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 TXIM R/W 0 RO 0 2 RXIM R/W 0 RO 0 1 RTIM R/W 0 RO 0 0 RORIM R/W 0 Bit/Field 31:4 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SSI Transmit FIFO Interrupt Mask The TXIM values are defined as follows: Value Description 0 1 TX FIFO half-full or less condition interrupt is masked. TX FIFO half-full or less condition interrupt is not masked. 3 TXIM R/W 0 2 RXIM R/W 0 SSI Receive FIFO Interrupt Mask The RXIM values are defined as follows: Value Description 0 1 RX FIFO half-full or more condition interrupt is masked. RX FIFO half-full or more condition interrupt is not masked. 1 RTIM R/W 0 SSI Receive Time-Out Interrupt Mask The RTIM values are defined as follows: Value Description 0 1 RX FIFO time-out interrupt is masked. RX FIFO time-out interrupt is not masked. 326 Preliminary November 30, 2007 LM3S2016 Microcontroller Bit/Field 0 Name RORIM Type R/W Reset 0 Description SSI Receive Overrun Interrupt Mask The RORIM values are defined as follows: Value Description 0 1 RX FIFO overrun interrupt is masked. RX FIFO overrun interrupt is not masked. November 30, 2007 Preliminary 327 Synchronous Serial Interface (SSI) Register 7: SSI Raw Interrupt Status (SSIRIS), offset 0x018 The SSIRIS register is the raw interrupt status register. On a read, this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect. SSI Raw Interrupt Status (SSIRIS) SSI0 base: 0x4000.8000 Offset 0x018 Type RO, reset 0x0000.0008 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 TXRIS RO 1 RO 0 2 RXRIS RO 0 RO 0 1 RTRIS RO 0 RO 0 0 RORRIS RO 0 Bit/Field 31:4 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SSI Transmit FIFO Raw Interrupt Status Indicates that the transmit FIFO is half full or less, when set. 3 TXRIS RO 1 2 RXRIS RO 0 SSI Receive FIFO Raw Interrupt Status Indicates that the receive FIFO is half full or more, when set. 1 RTRIS RO 0 SSI Receive Time-Out Raw Interrupt Status Indicates that the receive time-out has occurred, when set. 0 RORRIS RO 0 SSI Receive Overrun Raw Interrupt Status Indicates that the receive FIFO has overflowed, when set. 328 Preliminary November 30, 2007 LM3S2016 Microcontroller Register 8: SSI Masked Interrupt Status (SSIMIS), offset 0x01C The SSIMIS register is the masked interrupt status register. On a read, this register gives the current masked status value of the corresponding interrupt. A write has no effect. SSI Masked Interrupt Status (SSIMIS) SSI0 base: 0x4000.8000 Offset 0x01C Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 TXMIS RO 0 RO 0 2 RXMIS RO 0 RO 0 1 RTMIS RO 0 RO 0 0 RORMIS RO 0 Bit/Field 31:4 Name reserved Type RO Reset 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SSI Transmit FIFO Masked Interrupt Status Indicates that the transmit FIFO is half full or less, when set. 3 TXMIS RO 0 2 RXMIS RO 0 SSI Receive FIFO Masked Interrupt Status Indicates that the receive FIFO is half full or more, when set. 1 RTMIS RO 0 SSI Receive Time-Out Masked Interrupt Status Indicates that the receive time-out has occurred, when set. 0 RORMIS RO 0 SSI Receive Overrun Masked Interrupt Status Indicates that the receive FIFO has overflowed, when set. November 30, 2007 Preliminary 329 Synchronous Serial Interface (SSI) Register 9: SSI Interrupt Clear (SSIICR), offset 0x020 The SSIICR register is the interrupt clear register. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect. SSI Interrupt Clear (SSIICR) SSI0 base: 0x4000.8000 Offset 0x020 Type W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RTIC W1C 0 RO 0 0 RORIC W1C 0 Bit/Field 31:2 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SSI Receive Time-Out Interrupt Clear The RTIC values are defined as follows: Value Description 0 1 No effect on interrupt. Clears interrupt. 1 RTIC W1C 0 0 RORIC W1C 0 SSI Receive Overrun Interrupt Clear The RORIC values are defined as follows: Value Description 0 1 No effect on interrupt. Clears interrupt. 330 Preliminary November 30, 2007 LM3S2016 Microcontroller Register 10: SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset value. SSI Peripheral Identification 4 (SSIPeriphID4) SSI0 base: 0x4000.8000 Offset 0xFD0 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 PID4 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SSI Peripheral ID Register[7:0] Can be used by software to identify the presence of this peripheral. 7:0 PID4 RO 0x00 November 30, 2007 Preliminary 331 Synchronous Serial Interface (SSI) Register 11: SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset value. SSI Peripheral Identification 5 (SSIPeriphID5) SSI0 base: 0x4000.8000 Offset 0xFD4 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 PID5 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SSI Peripheral ID Register[15:8] Can be used by software to identify the presence of this peripheral. 7:0 PID5 RO 0x00 332 Preliminary November 30, 2007 LM3S2016 Microcontroller Register 12: SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset value. SSI Peripheral Identification 6 (SSIPeriphID6) SSI0 base: 0x4000.8000 Offset 0xFD8 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 PID6 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SSI Peripheral ID Register[23:16] Can be used by software to identify the presence of this peripheral. 7:0 PID6 RO 0x00 November 30, 2007 Preliminary 333 Synchronous Serial Interface (SSI) Register 13: SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset value. SSI Peripheral Identification 7 (SSIPeriphID7) SSI0 base: 0x4000.8000 Offset 0xFDC Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 PID7 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SSI Peripheral ID Register[31:24] Can be used by software to identify the presence of this peripheral. 7:0 PID7 RO 0x00 334 Preliminary November 30, 2007 LM3S2016 Microcontroller Register 14: SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset value. SSI Peripheral Identification 0 (SSIPeriphID0) SSI0 base: 0x4000.8000 Offset 0xFE0 Type RO, reset 0x0000.0022 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 PID0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 0 RO 0 RO 0 RO 1 RO 0 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SSI Peripheral ID Register[7:0] Can be used by software to identify the presence of this peripheral. 7:0 PID0 RO 0x22 November 30, 2007 Preliminary 335 Synchronous Serial Interface (SSI) Register 15: SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset value. SSI Peripheral Identification 1 (SSIPeriphID1) SSI0 base: 0x4000.8000 Offset 0xFE4 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 PID1 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SSI Peripheral ID Register [15:8] Can be used by software to identify the presence of this peripheral. 7:0 PID1 RO 0x00 336 Preliminary November 30, 2007 LM3S2016 Microcontroller Register 16: SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset value. SSI Peripheral Identification 2 (SSIPeriphID2) SSI0 base: 0x4000.8000 Offset 0xFE8 Type RO, reset 0x0000.0018 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 PID2 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 1 RO 0 RO 0 RO 0 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SSI Peripheral ID Register [23:16] Can be used by software to identify the presence of this peripheral. 7:0 PID2 RO 0x18 November 30, 2007 Preliminary 337 Synchronous Serial Interface (SSI) Register 17: SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset value. SSI Peripheral Identification 3 (SSIPeriphID3) SSI0 base: 0x4000.8000 Offset 0xFEC Type RO, reset 0x0000.0001 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 PID3 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SSI Peripheral ID Register [31:24] Can be used by software to identify the presence of this peripheral. 7:0 PID3 RO 0x01 338 Preliminary November 30, 2007 LM3S2016 Microcontroller Register 18: SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 The SSIPCellIDn registers are hard-coded and the fields within the register determine the reset value. SSI PrimeCell Identification 0 (SSIPCellID0) SSI0 base: 0x4000.8000 Offset 0xFF0 Type RO, reset 0x0000.000D 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 CID0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 1 RO 0 RO 1 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SSI PrimeCell ID Register [7:0] Provides software a standard cross-peripheral identification system. 7:0 CID0 RO 0x0D November 30, 2007 Preliminary 339 Synchronous Serial Interface (SSI) Register 19: SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 The SSIPCellIDn registers are hard-coded and the fields within the register determine the reset value. SSI PrimeCell Identification 1 (SSIPCellID1) SSI0 base: 0x4000.8000 Offset 0xFF4 Type RO, reset 0x0000.00F0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 CID1 RO 0 RO 0 RO 0 RO 1 RO 1 RO 1 RO 1 RO 0 RO 0 RO 0 RO 0 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SSI PrimeCell ID Register [15:8] Provides software a standard cross-peripheral identification system. 7:0 CID1 RO 0xF0 340 Preliminary November 30, 2007 LM3S2016 Microcontroller Register 20: SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 The SSIPCellIDn registers are hard-coded and the fields within the register determine the reset value. SSI PrimeCell Identification 2 (SSIPCellID2) SSI0 base: 0x4000.8000 Offset 0xFF8 Type RO, reset 0x0000.0005 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 CID2 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 0 RO 1 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SSI PrimeCell ID Register [23:16] Provides software a standard cross-peripheral identification system. 7:0 CID2 RO 0x05 November 30, 2007 Preliminary 341 Synchronous Serial Interface (SSI) Register 21: SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC The SSIPCellIDn registers are hard-coded and the fields within the register determine the reset value. SSI PrimeCell Identification 3 (SSIPCellID3) SSI0 base: 0x4000.8000 Offset 0xFFC Type RO, reset 0x0000.00B1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 CID3 RO 0 RO 0 RO 0 RO 1 RO 0 RO 1 RO 1 RO 0 RO 0 RO 0 RO 1 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SSI PrimeCell ID Register [31:24] Provides software a standard cross-peripheral identification system. 7:0 CID3 RO 0xB1 342 Preliminary November 30, 2007 LM3S2016 Microcontroller 14 Inter-Integrated Circuit (I2C) Interface The Inter-Integrated Circuit (I2C) bus provides bi-directional data transfer through a two-wire design (a serial data line SDA and a serial clock line SCL), and interfaces to external I2C devices such as serial memory (RAMs and ROMs), networking devices, LCDs, tone generators, and so on. The I2C bus may also be used for system testing and diagnostic purposes in product development and manufacture. The LM3S2016 microcontroller includes one I2C module, providing the ability to interact (both send and receive) with other I2C devices on the bus. Devices on the I2C bus can be designated as either a master or a slave. The Stellaris I2C module supports both sending and receiving data as either a master or a slave, and also supports the simultaneous operation as both a master and a slave. There are a total of four I2C modes: Master ® Transmit, Master Receive, Slave Transmit, and Slave Receive. The Stellaris I2C module can operate at two speeds: Standard (100 Kbps) and Fast (400 Kbps). Both the I2C master and slave can generate interrupts; the I2C master generates interrupts when a transmit or receive operation completes (or aborts due to an error) and the I2C slave generates interrupts when data has been sent or requested by a master. ® 14.1 Block Diagram Figure 14-1. I2C Block Diagram I2C Control I2CMSA I2CMCS I2CMDR Interrupt I2CMTPR I2CMIMR I2CMRIS I2CMMIS I2CMICR I2CMCR I2CSOAR I2CSCSR I2CSDR I2CSIM I2CSRIS I2CSMIS I2CSICR I2C Slave Core I C Master Core 2 I2CSCL I2CSDA I2CSCL I C I/O Select I2CSDA I2CSCL 2 I2CSDA 14.2 Functional Description The I2C module is comprised of both master and slave functions which are implemented as separate peripherals. For proper operation, the SDA and SCL pins must be connected to bi-directional open-drain pads. A typical I2C bus configuration is shown in Figure 14-2 on page 344. See “I2C” on page 437 for I2C timing diagrams. November 30, 2007 Preliminary 343 Inter-Integrated Circuit (I2C) Interface Figure 14-2. I2C Bus Configuration SCL SDA I2CSCL I2CSDA RPUP RPUP I2C Bus SCL SDA SCL SDA StellarisTM 3rd Par ty Device with I2C Interface 3rd Par ty Device with I2C Interface 14.2.1 I2C Bus Functional Overview The I2C bus uses only two signals: SDA and SCL, named I2CSDA and I2CSCL on Stellaris microcontrollers. SDA is the bi-directional serial data line and SCL is the bi-directional serial clock line. The bus is considered idle when both lines are high. Every transaction on the I2C bus is nine bits long, consisting of eight data bits and a single acknowledge bit. The number of bytes per transfer (defined as the time between a valid START and STOP condition, described in “START and STOP Conditions” on page 344) is unrestricted, but each byte has to be followed by an acknowledge bit, and data must be transferred MSB first. When a receiver cannot receive another complete byte, it can hold the clock line SCL Low and force the transmitter into a wait state. The data transfer continues when the receiver releases the clock SCL. ® 14.2.1.1 START and STOP Conditions The protocol of the I2C bus defines two states to begin and end a transaction: START and STOP. A high-to-low transition on the SDA line while the SCL is high is defined as a START condition, and a low-to-high transition on the SDA line while SCL is high is defined as a STOP condition. The bus is considered busy after a START condition and free after a STOP condition. See Figure 14-3 on page 344. Figure 14-3. START and STOP Conditions SDA SCL START condition STOP condition SDA SCL 14.2.1.2 Data Format with 7-Bit Address Data transfers follow the format shown in Figure 14-4 on page 345. After the START condition, a slave address is sent. This address is 7-bits long followed by an eighth bit, which is a data direction bit (R/S bit in the I2CMSA register). A zero indicates a transmit operation (send), and a one indicates a request for data (receive). A data transfer is always terminated by a STOP condition generated by the master, however, a master can initiate communications with another device on the bus by generating a repeated START condition and addressing another slave without first generating a STOP condition. Various combinations of receive/send formats are then possible within a single transfer. 344 Preliminary November 30, 2007 LM3S2016 Microcontroller Figure 14-4. Complete Data Transfer with a 7-Bit Address SDA MSB LSB R/S ACK MSB LSB ACK SCL 1 2 Slave add ress 7 8 9 1 2 Data 7 8 9 The first seven bits of the first byte make up the slave address (see Figure 14-5 on page 345). The eighth bit determines the direction of the message. A zero in the R/S position of the first byte means that the master will write (send) data to the selected slave, and a one in this position means that the master will receive data from the slave. Figure 14-5. R/S Bit in First Byte MSB LSB R/S Slave address 14.2.1.3 Data Validity The data on the SDA line must be stable during the high period of the clock, and the data line can only change when SCL is low (see Figure 14-6 on page 345). Figure 14-6. Data Validity During Bit Transfer on the I2C Bus SDA SCL g Data line Chan e stable of data allowed 14.2.1.4 Acknowledge All bus transactions have a required acknowledge clock cycle that is generated by the master. During the acknowledge cycle, the transmitter (which can be the master or slave) releases the SDA line. To acknowledge the transaction, the receiver must pull down SDA during the acknowledge clock cycle. The data sent out by the receiver during the acknowledge cycle must comply with the data validity requirements described in “Data Validity” on page 345. When a slave receiver does not acknowledge the slave address, SDA must be left high by the slave so that the master can generate a STOP condition and abort the current transfer. If the master device is acting as a receiver during a transfer, it is responsible for acknowledging each transfer made by the slave. Since the master controls the number of bytes in the transfer, it signals the end of data to the slave transmitter by not generating an acknowledge on the last data byte. The slave transmitter must then release SDA to allow the master to generate the STOP or a repeated START condition. November 30, 2007 Preliminary 345 Inter-Integrated Circuit (I2C) Interface 14.2.1.5 Arbitration A master may start a transfer only if the bus is idle. It's possible for two or more masters to generate a START condition within minimum hold time of the START condition. In these situations, an arbitration scheme takes place on the SDA line, while SCL is high. During arbitration, the first of the competing master devices to place a '1' (high) on SDA while another master transmits a '0' (low) will switch off its data output stage and retire until the bus is idle again. Arbitration can take place over several bits. Its first stage is a comparison of address bits, and if both masters are trying to address the same device, arbitration continues on to the comparison of data bits. 14.2.2 Available Speed Modes The I2C clock rate is determined by the parameters: CLK_PRD, TIMER_PRD, SCL_LP, and SCL_HP. where: CLK_PRD is the system clock period SCL_LP is the low phase of SCL (fixed at 6) SCL_HP is the high phase of SCL (fixed at 4) TIMER_PRD is the programmed value in the I2C Master Timer Period (I2CMTPR) register (see page 363). The I2C clock period is calculated as follows: SCL_PERIOD = 2*(1 + TIMER_PRD)*(SCL_LP + SCL_HP)*CLK_PRD For example: CLK_PRD = 50 ns TIMER_PRD = 2 SCL_LP=6 SCL_HP=4 yields a SCL frequency of: 1/T = 333 Khz Table 14-1 on page 346 gives examples of timer period, system clock, and speed mode (Standard or Fast). Table 14-1. Examples of I2C Master Timer Period versus Speed Mode System Clock Timer Period Standard Mode Timer Period Fast Mode 4 Mhz 6 Mhz 12.5 Mhz 16.7 Mhz 20 Mhz 25 Mhz 33Mhz 40Mhz 0x01 0x02 0x06 0x08 0x09 0x0C 0x10 0x13 100 Kbps 100 Kbps 89 Kbps 93 Kbps 100 Kbps 96.2 Kbps 97.1 Kbps 100 Kbps 0x01 0x02 0x02 0x03 0x04 0x04 312 Kbps 278 Kbps 333 Kbps 312 Kbps 330 Kbps 400 Kbps 346 Preliminary November 30, 2007 LM3S2016 Microcontroller System Clock Timer Period Standard Mode Timer Period Fast Mode 50Mhz 0x18 100 Kbps 0x06 357 Kbps 14.2.3 Interrupts The I2C can generate interrupts when the following conditions are observed: ■ Master transaction completed ■ Master transaction error ■ Slave transaction received ■ Slave transaction requested There is a separate interrupt signal for the I2C master and I2C modules. While both modules can generate interrupts for multiple conditions, only a single interrupt signal is sent to the interrupt controller. 14.2.3.1 I2C Master Interrupts The I2C master module generates an interrupt when a transaction completes (either transmit or receive), or when an error occurs during a transaction. To enable the I2C master interrupt, software must write a '1' to the I2C Master Interrupt Mask (I2CMIMR) register. When an interrupt condition is met, software must check the ERROR bit in the I2C Master Control/Status (I2CMCS) register to verify that an error didn't occur during the last transaction. An error condition is asserted if the last transaction wasn't acknowledge by the slave or if the master was forced to give up ownership of the bus due to a lost arbitration round with another master. If an error is not detected, the application can proceed with the transfer. The interrupt is cleared by writing a '1' to the I2C Master Interrupt Clear (I2CMICR) register. If the application doesn't require the use of interrupts, the raw interrupt status is always visible via the I2C Master Raw Interrupt Status (I2CMRIS) register. 14.2.3.2 I2C Slave Interrupts The slave module generates interrupts as it receives requests from an I2C master. To enable the I2C slave interrupt, write a '1' to the I2C Slave Interrupt Mask (I2CSIMR) register. Software determines whether the module should write (transmit) or read (receive) data from the I2C Slave Data (I2CSDR) register, by checking the RREQ and TREQ bits of the I2C Slave Control/Status (I2CSCSR) register. If the slave module is in receive mode and the first byte of a transfer is received, the FBR bit is set along with the RREQ bit. The interrupt is cleared by writing a '1' to the I2C Slave Interrupt Clear (I2CSICR) register. If the application doesn't require the use of interrupts, the raw interrupt status is always visible via the I2C Slave Raw Interrupt Status (I2CSRIS) register. 14.2.4 Loopback Operation The I2C modules can be placed into an internal loopback mode for diagnostic or debug work. This is accomplished by setting the LPBK bit in the I2C Master Configuration (I2CMCR) register. In loopback mode, the SDA and SCL signals from the master and slave modules are tied together. November 30, 2007 Preliminary 347 Inter-Integrated Circuit (I2C) Interface 14.2.5 Command Sequence Flow Charts This section details the steps required to perform the various I2C transfer types in both master and slave mode. 14.2.5.1 I2C Master Command Sequences The figures that follow show the command sequences available for the I2C master. Figure 14-7. Master Single SEND Idle Write Slave Address to I2CMSA Sequence may be omitted in a Single Master system Write data to I2CMDR Read I2CMCS NO BUSBSY bit=0? YES Write ---0-111 to I2CMCS Read I2CMCS NO BUSY bit=0? YES Error Service NO ERROR bit=0? YES Idle 348 Preliminary November 30, 2007 LM3S2016 Microcontroller Figure 14-8. Master Single RECEIVE Idle Write Slave Address to I2CMSA Sequence may be omitted in a Single Master system Read I2CMCS NO BUSBSY bit=0? YES Write ---00111 to I2CMCS Read I2CMCS NO BUSY bit=0? YES Error Service NO ERROR bit=0? YES Read data from I2CMDR Idle November 30, 2007 Preliminary 349 Inter-Integrated Circuit (I2C) Interface Figure 14-9. Master Burst SEND Idle Write Slave Address to I2CMSA Sequence may be omitted in a Single Master system Read I2CMCS Write data to I2CMDR BUSY bit=0? NO Read I2CMCS YES ERROR bit=0? NO NO BUSBSY bit=0? YES YES Write data to I2CMDR NO ARBLST bit=1? Write ---0-011 to I2CMCS Write ---0-001 to I2CMCS NO YES Index=n? Write ---0-100 to I2CMCS YES Error Service Write ---0-101 to I2CMCS Idle Read I2CMCS NO BUSY bit=0? YES Error Service NO ERROR bit=0? YES Idle 350 Preliminary November 30, 2007 LM3S2016 Microcontroller Figure 14-10. Master Burst RECEIVE Idle Sequence may be omitted in a Single Master system Write Slave Address to I2CMSA Read I2CMCS Read I2CMCS BUSY bit=0? NO YES NO BUSBSY bit=0? ERROR bit=0? YES NO Write ---01011 to I2CMCS Read data from I2CMDR NO ARBLST bit=1? YES Write ---01001 to I2CMCS NO Write ---0-100 to I2CMCS Index=m-1? Error Service YES Write ---00101 to I2CMCS Idle Read I2CMCS BUSY bit=0? NO YES NO ERROR bit=0? YES Error Service Read data from I2CMDR Idle November 30, 2007 Preliminary 351 Inter-Integrated Circuit (I2C) Interface Figure 14-11. Master Burst RECEIVE after Burst SEND Idle Master operates in Master Transmit mode STOP condition is not generated Write Slave Address to I2CMSA Write ---01011 to I2CMCS Repeated START condition is generated with changing data direction Master operates in Master Receive mode Idle 352 Preliminary November 30, 2007 LM3S2016 Microcontroller Figure 14-12. Master Burst SEND after Burst RECEIVE Idle Master operates in Master Receive mode STOP condition is not generated Write Slave Address to I2CMSA Write ---0-011 to I2CMCS Repeated START condition is generated with changing data direction Master operates in Master Transmit mode Idle 14.2.5.2 I2C Slave Command Sequences Figure 14-13 on page 354 presents the command sequence available for the I2C slave. November 30, 2007 Preliminary 353 Inter-Integrated Circuit (I2C) Interface Figure 14-13. Slave Command Sequence Idle Write OWN Slave Address to I2CSOAR Write -------1 to I2CSCSR Read I2CSCSR NO TREQ bit=1? NO RREQ bit=1? YES FBR is also valid YES Write data to I2CSDR Read data from I2CSDR 14.3 Initialization and Configuration The following example shows how to configure the I2C module to send a single byte as a master. This assumes the system clock is 20 MHz. 1. Enable the I2C clock by writing a value of 0x0000.1000 to the RCGC1 register in the System Control module. 2. Enable the clock to the appropriate GPIO module via the RCGC2 register in the System Control module. 3. In the GPIO module, enable the appropriate pins for their alternate function using the GPIOAFSEL register. Also, be sure to enable the same pins for Open Drain operation. 4. Initialize the I2C Master by writing the I2CMCR register with a value of 0x0000.0020. 5. Set the desired SCL clock speed of 100 Kbps by writing the I2CMTPR register with the correct value. The value written to the I2CMTPR register represents the number of system clock periods in one SCL clock period. The TPR value is determined by the following equation: 354 Preliminary November 30, 2007 LM3S2016 Microcontroller TPR = (System Clock / (2 * (SCL_LP + SCL_HP) * SCL_CLK)) - 1; TPR = (20MHz / (2 * (6 + 4) * 100000)) - 1; TPR = 9 Write the I2CMTPR register with the value of 0x0000.0009. 6. Specify the slave address of the master and that the next operation will be a Send by writing the I2CMSA register with a value of 0x0000.0076. This sets the slave address to 0x3B. 7. Place data (byte) to be sent in the data register by writing the I2CMDR register with the desired data. 8. Initiate a single byte send of the data from Master to Slave by writing the I2CMCS register with a value of 0x0000.0007 (STOP, START, RUN). 9. Wait until the transmission completes by polling the I2CMCS register ’s BUSBSY bit until it has been cleared. 14.4 I2C Register Map Table 14-2 on page 355 lists the I2C registers. All addresses given are relative to the I2C base addresses for the master and slave: ■ I2C Master 0: 0x4002.0000 ■ I2C Slave 0: 0x4002.0800 Table 14-2. Inter-Integrated Circuit (I2C) Interface Register Map Offset I2C Master 0x000 0x004 0x008 0x00C 0x010 0x014 0x018 0x01C 0x020 I2C Slave 0x000 0x004 0x008 0x00C I2CSOAR I2CSCSR I2CSDR I2CSIMR R/W RO R/W R/W 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 I2C Slave Own Address I2C Slave Control/Status I2C Slave Data I2C Slave Interrupt Mask 370 371 373 374 I2CMSA I2CMCS I2CMDR I2CMTPR I2CMIMR I2CMRIS I2CMMIS I2CMICR I2CMCR R/W R/W R/W R/W R/W RO RO WO R/W 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0001 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 I2C Master Slave Address I2C Master Control/Status I2C Master Data I2C Master Timer Period I2C Master Interrupt Mask I2C Master Raw Interrupt Status I2C Master Masked Interrupt Status I2C Master Interrupt Clear I2C Master Configuration 357 358 362 363 364 365 366 367 368 Name Type Reset Description See page November 30, 2007 Preliminary 355 Inter-Integrated Circuit (I2C) Interface Offset 0x010 0x014 0x018 Name I2CSRIS I2CSMIS I2CSICR Type RO RO WO Reset 0x0000.0000 0x0000.0000 0x0000.0000 Description I2C Slave Raw Interrupt Status I2C Slave Masked Interrupt Status I2C Slave Interrupt Clear See page 375 376 377 14.5 Register Descriptions (I2C Master) The remainder of this section lists and describes the I2C master registers, in numerical order by address offset. See also “Register Descriptions (I2C Slave)” on page 369. 356 Preliminary November 30, 2007 LM3S2016 Microcontroller Register 1: I2C Master Slave Address (I2CMSA), offset 0x000 This register consists of eight bits: seven address bits (A6-A0), and a Receive/Send bit, which determines if the next operation is a Receive (High), or Send (Low). I2C Master Slave Address (I2CMSA) I2C Master 0 base: 0x4002.0000 Offset 0x000 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 SA RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 RO 0 3 RO 0 2 RO 0 1 RO 0 0 R/S R/W 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. I2C Slave Address This field specifies bits A6 through A0 of the slave address. 7:1 SA R/W 0 0 R/S R/W 0 Receive/Send The R/S bit specifies if the next operation is a Receive (High) or Send (Low). Value Description 0 1 Send. Receive. November 30, 2007 Preliminary 357 Inter-Integrated Circuit (I2C) Interface Register 2: I2C Master Control/Status (I2CMCS), offset 0x004 This register accesses four control bits when written, and accesses seven status bits when read. The status register consists of seven bits, which when read determine the state of the I2C bus controller. The control register consists of four bits: the RUN, START, STOP, and ACK bits. The START bit causes the generation of the START, or REPEATED START condition. The STOP bit determines if the cycle stops at the end of the data cycle, or continues on to a burst. To generate a single send cycle, the I2C Master Slave Address (I2CMSA) register is written with the desired address, the R/S bit is set to 0, and the Control register is written with ACK=X (0 or 1), STOP=1, START=1, and RUN=1 to perform the operation and stop. When the operation is completed (or aborted due an error), the interrupt pin becomes active and the data may be read from the I2CMDR register. When the I2C module operates in Master receiver mode, the ACK bit must be set normally to logic 1. This causes the I2C bus controller to send an acknowledge automatically after each byte. This bit must be reset when the I2C bus controller requires no further data to be sent from the slave transmitter. Read-Only Status Register I2C Master Control/Status (I2CMCS) I2C Master 0 base: 0x4002.0000 Offset 0x004 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 BUSBSY RO 0 RO 0 5 IDLE RO 0 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 BUSY RO 0 ARBLST DATACK ADRACK ERROR RO 0 RO 0 RO 0 RO 0 Bit/Field 31:7 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Bus Busy This bit specifies the state of the I2C bus. If set, the bus is busy; otherwise, the bus is idle. The bit changes based on the START and STOP conditions. 6 BUSBSY RO 0 5 IDLE RO 0 I2C Idle This bit specifies the I2C controller state. If set, the controller is idle; otherwise the controller is not idle. 4 ARBLST RO 0 Arbitration Lost This bit specifies the result of bus arbitration. If set, the controller lost arbitration; otherwise, the controller won arbitration. 358 Preliminary November 30, 2007 LM3S2016 Microcontroller Bit/Field 3 Name DATACK Type RO Reset 0 Description Acknowledge Data This bit specifies the result of the last data operation. If set, the transmitted data was not acknowledged; otherwise, the data was acknowledged. 2 ADRACK RO 0 Acknowledge Address This bit specifies the result of the last address operation. If set, the transmitted address was not acknowledged; otherwise, the address was acknowledged. 1 ERROR RO 0 Error This bit specifies the result of the last bus operation. If set, an error occurred on the last operation; otherwise, no error was detected. The error can be from the slave address not being acknowledged, the transmit data not being acknowledged, or because the controller lost arbitration. 0 BUSY RO 0 I2C Busy This bit specifies the state of the controller. If set, the controller is busy; otherwise, the controller is idle. When the BUSY bit is set, the other status bits are not valid. Write-Only Control Register I2C Master Control/Status (I2CMCS) I2C Master 0 base: 0x4002.0000 Offset 0x004 Type WO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset WO 0 15 WO 0 14 WO 0 13 WO 0 12 WO 0 11 WO 0 10 reserved Type Reset WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 9 WO 0 8 WO 0 7 WO 0 6 WO 0 5 WO 0 4 WO 0 3 ACK WO 0 WO 0 2 STOP WO 0 WO 0 1 START WO 0 WO 0 0 RUN WO 0 Bit/Field 31:4 Name reserved Type WO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Data Acknowledge Enable When set, causes received data byte to be acknowledged automatically by the master. See field decoding in Table 14-3 on page 360. 3 ACK WO 0 2 STOP WO 0 Generate STOP When set, causes the generation of the STOP condition. See field decoding in Table 14-3 on page 360. November 30, 2007 Preliminary 359 Inter-Integrated Circuit (I2C) Interface Bit/Field 1 Name START Type WO Reset 0 Description Generate START When set, causes the generation of a START or repeated START condition. See field decoding in Table 14-3 on page 360. 0 RUN WO 0 I2C Master Enable When set, allows the master to send or receive data. See field decoding in Table 14-3 on page 360. Table 14-3. Write Field Decoding for I2CMCS[3:0] Field (Sheet 1 of 3) Current I2CMSA[0] State R/S Idle 0 0 1 1 1 1 I2CMCS[3:0] ACK X a Description RUN 1 1 1 1 1 1 START condition followed by SEND (master goes to the Master Transmit state). START condition followed by a SEND and STOP condition (master remains in Idle state). START condition followed by RECEIVE operation with negative ACK (master goes to the Master Receive state). START condition followed by RECEIVE and STOP condition (master remains in Idle state). START condition followed by RECEIVE (master goes to the Master Receive state). Illegal. STOP 0 1 0 1 0 1 START 1 1 1 1 1 1 X 0 0 1 1 All other combinations not listed are non-operations. NOP. Master Transmit X X X 0 0 1 X X X X X 0 0 1 1 0 1 0 0 0 0 1 1 1 1 0 1 1 1 1 SEND operation (master remains in Master Transmit state). STOP condition (master goes to Idle state). SEND followed by STOP condition (master goes to Idle state). Repeated START condition followed by a SEND (master remains in Master Transmit state). Repeated START condition followed by SEND and STOP condition (master goes to Idle state). Repeated START condition followed by a RECEIVE operation with a negative ACK (master goes to Master Receive state). Repeated START condition followed by a SEND and STOP condition (master goes to Idle state). Repeated START condition followed by RECEIVE (master goes to Master Receive state). Illegal. 1 1 1 0 1 1 1 0 1 1 1 1 1 1 1 All other combinations not listed are non-operations. NOP. 360 Preliminary November 30, 2007 LM3S2016 Microcontroller Current I2CMSA[0] State R/S Master Receive X X X X X 1 I2CMCS[3:0] ACK 0 X 0 1 1 0 STOP 0 1 1 0 1 0 START 0 0 0 0 0 1 RUN 1 0 1 1 1 1 Description RECEIVE operation with negative ACK (master remains in Master Receive state). STOP condition (master goes to Idle state). b RECEIVE followed by STOP condition (master goes to Idle state). RECEIVE operation (master remains in Master Receive state). Illegal. Repeated START condition followed by RECEIVE operation with a negative ACK (master remains in Master Receive state). Repeated START condition followed by RECEIVE and STOP condition (master goes to Idle state). Repeated START condition followed by RECEIVE (master remains in Master Receive state). Repeated START condition followed by SEND (master goes to Master Transmit state). Repeated START condition followed by SEND and STOP condition (master goes to Idle state). 1 1 0 0 0 1 X X 1 0 0 1 1 1 1 1 1 1 1 1 All other combinations not listed are non-operations. NOP. a. An X in a table cell indicates the bit can be 0 or 1. b. In Master Receive mode, a STOP condition should be generated only after a Data Negative Acknowledge executed by the master or an Address Negative Acknowledge executed by the slave. November 30, 2007 Preliminary 361 Inter-Integrated Circuit (I2C) Interface Register 3: I2C Master Data (I2CMDR), offset 0x008 This register contains the data to be transmitted when in the Master Transmit state, and the data received when in the Master Receive state. I2C Master Data (I2CMDR) I2C Master 0 base: 0x4002.0000 Offset 0x008 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 DATA RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Data Transferred Data transferred during transaction. 7:0 DATA R/W 0x00 362 Preliminary November 30, 2007 LM3S2016 Microcontroller Register 4: I2C Master Timer Period (I2CMTPR), offset 0x00C This register specifies the period of the SCL clock. I2C Master Timer Period (I2CMTPR) I2C Master 0 base: 0x4002.0000 Offset 0x00C Type R/W, reset 0x0000.0001 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 TPR RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 1 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SCL Clock Period This field specifies the period of the SCL clock. SCL_PRD = 2*(1 + TPR)*(SCL_LP + SCL_HP)*CLK_PRD where: SCL_PRD is the SCL line period (I2C clock). TPR is the Timer Period register value (range of 1 to 255). SCL_LP is the SCL Low period (fixed at 6). SCL_HP is the SCL High period (fixed at 4). 7:0 TPR R/W 0x1 November 30, 2007 Preliminary 363 Inter-Integrated Circuit (I2C) Interface Register 5: I2C Master Interrupt Mask (I2CMIMR), offset 0x010 This register controls whether a raw interrupt is promoted to a controller interrupt. I2C Master Interrupt Mask (I2CMIMR) I2C Master 0 base: 0x4002.0000 Offset 0x010 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 IM R/W 0 Bit/Field 31:1 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Interrupt Mask This bit controls whether a raw interrupt is promoted to a controller interrupt. If set, the interrupt is not masked and the interrupt is promoted; otherwise, the interrupt is masked. 0 IM R/W 0 364 Preliminary November 30, 2007 LM3S2016 Microcontroller Register 6: I2C Master Raw Interrupt Status (I2CMRIS), offset 0x014 This register specifies whether an interrupt is pending. I2C Master Raw Interrupt Status (I2CMRIS) I2C Master 0 base: 0x4002.0000 Offset 0x014 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 RIS RO 0 Bit/Field 31:1 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Raw Interrupt Status This bit specifies the raw interrupt state (prior to masking) of the I2C master block. If set, an interrupt is pending; otherwise, an interrupt is not pending. 0 RIS RO 0 November 30, 2007 Preliminary 365 Inter-Integrated Circuit (I2C) Interface Register 7: I2C Master Masked Interrupt Status (I2CMMIS), offset 0x018 This register specifies whether an interrupt was signaled. I2C Master Masked Interrupt Status (I2CMMIS) I2C Master 0 base: 0x4002.0000 Offset 0x018 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 MIS RO 0 Bit/Field 31:1 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Masked Interrupt Status This bit specifies the raw interrupt state (after masking) of the I2C master block. If set, an interrupt was signaled; otherwise, an interrupt has not been generated since the bit was last cleared. 0 MIS RO 0 366 Preliminary November 30, 2007 LM3S2016 Microcontroller Register 8: I2C Master Interrupt Clear (I2CMICR), offset 0x01C This register clears the raw interrupt. I2C Master Interrupt Clear (I2CMICR) I2C Master 0 base: 0x4002.0000 Offset 0x01C Type WO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 IC WO 0 Bit/Field 31:1 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Interrupt Clear This bit controls the clearing of the raw interrupt. A write of 1 clears the interrupt; otherwise, a write of 0 has no affect on the interrupt state. A read of this register returns no meaningful data. 0 IC WO 0 November 30, 2007 Preliminary 367 Inter-Integrated Circuit (I2C) Interface Register 9: I2C Master Configuration (I2CMCR), offset 0x020 This register configures the mode (Master or Slave) and sets the interface for test mode loopback. I2C Master Configuration (I2CMCR) I2C Master 0 base: 0x4002.0000 Offset 0x020 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 SFE RO 0 RO 0 RO 0 RO 0 R/W 0 RO 0 4 MFE R/W 0 RO 0 RO 0 3 RO 0 2 reserved RO 0 RO 0 RO 0 1 RO 0 0 LPBK R/W 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:6 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. I2C Slave Function Enable This bit specifies whether the interface may operate in Slave mode. If set, Slave mode is enabled; otherwise, Slave mode is disabled. 5 SFE R/W 0 4 MFE R/W 0 I2C Master Function Enable This bit specifies whether the interface may operate in Master mode. If set, Master mode is enabled; otherwise, Master mode is disabled and the interface clock is disabled. 3:1 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. I2C Loopback This bit specifies whether the interface is operating normally or in Loopback mode. If set, the device is put in a test mode loopback configuration; otherwise, the device operates normally. 0 LPBK R/W 0 368 Preliminary November 30, 2007 LM3S2016 Microcontroller 14.6 Register Descriptions (I2C Slave) The remainder of this section lists and describes the I2C slave registers, in numerical order by address offset. See also “Register Descriptions (I2C Master)” on page 356. November 30, 2007 Preliminary 369 Inter-Integrated Circuit (I2C) Interface Register 10: I2C Slave Own Address (I2CSOAR), offset 0x000 This register consists of seven address bits that identify the Stellaris I2C device on the I2C bus. I2C Slave Own Address (I2CSOAR) I2C Slave 0 base: 0x4002.0800 Offset 0x000 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ® reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 OAR R/W 0 R/W 0 R/W 0 R/W 0 RO 0 2 RO 0 1 RO 0 0 Bit/Field 31:7 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. I2C Slave Own Address This field specifies bits A6 through A0 of the slave address. 6:0 OAR R/W 0x00 370 Preliminary November 30, 2007 LM3S2016 Microcontroller Register 11: I2C Slave Control/Status (I2CSCSR), offset 0x004 This register accesses one control bit when written, and three status bits when read. The read-only Status register consists of three bits: the FBR, RREQ, and TREQ bits. The First ® Byte Received (FBR) bit is set only after the Stellaris device detects its own slave address and receives the first data byte from the I2C master. The Receive Request (RREQ) bit indicates ® that the Stellaris I2C device has received a data byte from an I2C master. Read one data byte from the I2C Slave Data (I2CSDR) register to clear the RREQ bit. The Transmit Request (TREQ) bit ® indicates that the Stellaris I2C device is addressed as a Slave Transmitter. Write one data byte 2C Slave Data (I2CSDR) register to clear the TREQ bit. into the I The write-only Control register consists of one bit: the DA bit. The DA bit enables and disables the ® Stellaris I2C slave operation. Read-Only Status Register I2C Slave Control/Status (I2CSCSR) I2C Slave 0 base: 0x4002.0800 Offset 0x004 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 FBR RO 0 RO 0 1 TREQ RO 0 RO 0 0 RREQ RO 0 Bit/Field 31:3 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. First Byte Received Indicates that the first byte following the slave’s own address is received. This bit is only valid when the RREQ bit is set, and is automatically cleared when data has been read from the I2CSDR register. Note: This bit is not used for slave transmit operations. 2 FBR RO 0 1 TREQ RO 0 Transmit Request This bit specifies the state of the I2C slave with regards to outstanding transmit requests. If set, the I2C unit has been addressed as a slave transmitter and uses clock stretching to delay the master until data has been written to the I2CSDR register. Otherwise, there is no outstanding transmit request. 0 RREQ RO 0 Receive Request This bit specifies the status of the I2C slave with regards to outstanding receive requests. If set, the I2C unit has outstanding receive data from the I2C master and uses clock stretching to delay the master until the data has been read from the I2CSDR register. Otherwise, no receive data is outstanding. November 30, 2007 Preliminary 371 Inter-Integrated Circuit (I2C) Interface Write-Only Control Register I2C Slave Control/Status (I2CSCSR) I2C Slave 0 base: 0x4002.0800 Offset 0x004 Type WO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 DA WO 0 Bit/Field 31:1 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Device Active Value Description 0 1 Disables the I2C slave operation. Enables the I2C slave operation. 0 DA WO 0 372 Preliminary November 30, 2007 LM3S2016 Microcontroller Register 12: I2C Slave Data (I2CSDR), offset 0x008 This register contains the data to be transmitted when in the Slave Transmit state, and the data received when in the Slave Receive state. I2C Slave Data (I2CSDR) I2C Slave 0 base: 0x4002.0800 Offset 0x008 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 DATA RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Data for Transfer This field contains the data for transfer during a slave receive or transmit operation. 7:0 DATA R/W 0x0 November 30, 2007 Preliminary 373 Inter-Integrated Circuit (I2C) Interface Register 13: I2C Slave Interrupt Mask (I2CSIMR), offset 0x00C This register controls whether a raw interrupt is promoted to a controller interrupt. I2C Slave Interrupt Mask (I2CSIMR) I2C Slave 0 base: 0x4002.0800 Offset 0x00C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 IM R/W 0 Bit/Field 31:1 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Interrupt Mask This bit controls whether a raw interrupt is promoted to a controller interrupt. If set, the interrupt is not masked and the interrupt is promoted; otherwise, the interrupt is masked. 0 IM R/W 0 374 Preliminary November 30, 2007 LM3S2016 Microcontroller Register 14: I2C Slave Raw Interrupt Status (I2CSRIS), offset 0x010 This register specifies whether an interrupt is pending. I2C Slave Raw Interrupt Status (I2CSRIS) I2C Slave 0 base: 0x4002.0800 Offset 0x010 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 RIS RO 0 Bit/Field 31:1 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Raw Interrupt Status This bit specifies the raw interrupt state (prior to masking) of the I2C slave block. If set, an interrupt is pending; otherwise, an interrupt is not pending. 0 RIS RO 0 November 30, 2007 Preliminary 375 Inter-Integrated Circuit (I2C) Interface Register 15: I2C Slave Masked Interrupt Status (I2CSMIS), offset 0x014 This register specifies whether an interrupt was signaled. I2C Slave Masked Interrupt Status (I2CSMIS) I2C Slave 0 base: 0x4002.0800 Offset 0x014 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 MIS RO 0 Bit/Field 31:1 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Masked Interrupt Status This bit specifies the raw interrupt state (after masking) of the I2C slave block. If set, an interrupt was signaled; otherwise, an interrupt has not been generated since the bit was last cleared. 0 MIS RO 0 376 Preliminary November 30, 2007 LM3S2016 Microcontroller Register 16: I2C Slave Interrupt Clear (I2CSICR), offset 0x018 This register clears the raw interrupt. I2C Slave Interrupt Clear (I2CSICR) I2C Slave 0 base: 0x4002.0800 Offset 0x018 Type WO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 IC WO 0 Bit/Field 31:1 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Clear Interrupt This bit controls the clearing of the raw interrupt. A write of 1 clears the interrupt; otherwise a write of 0 has no affect on the interrupt state. A read of this register returns no meaningful data. 0 IC WO 0 November 30, 2007 Preliminary 377 Controller Area Network (CAN) Module 15 15.1 Controller Area Network (CAN) Module Controller Area Network Overview Controller Area Network (CAN) is a multicast shared serial bus standard for connecting electronic control units (ECUs). CAN was specifically designed to be robust in electromagnetically noisy environments and can utilize a differential balanced line like RS-485 or a more robust twisted-pair wire. Originally created for automotive purposes, it is also used in many embedded control applications (such as industrial and medical). Bit rates up to 1 Mbps are possible at network lengths below 40 meters. Decreased bit rates allow longer network distances (for example, 125 Kbps at 500 m). 15.2 Controller Area Network Features The Stellaris CAN module supports the following features: ■ ■ ■ ■ ■ ■ ■ ■ ■ CAN protocol version 2.0 part A/B Bit rates up to 1 Mbps 32 message objects Each message object has its own identifier mask Maskable interrupt Disable Automatic Retransmission mode for Time Triggered CAN (TTCAN) applications Programmable Loopback mode for self-test operation Programmable FIFO mode Gluelessly attach to an external CAN PHY through the CAN0Tx and CAN0Rx pins ® 378 Preliminary November 30, 2007 LM3S2016 Microcontroller 15.3 Controller Area Network Block Diagram Figure 15-1. CAN Module Block Diagram CAN Control CANCTL CANSTS CANBIT CANINT CANTST CANBRPE CANIF1CRQ CANIF1CMSK CANIF1MSK1 CANIF1MSK2 CANIF1ARB1 APB Pins APB Interface CANIF1ARB2 CANIF1MCTL CANIF1DA1 CANIF1DA2 CANIF1DB1 CANIF1DB2 CAN Core CAN TX/RX CANIF2CRQ CANIF2CMSK CANIF2MSK1 CANIF2MSK2 CANIF2ARB1 CANIF2ARB2 CANIF2MCTL CANIF2DA1 CANIF2DA2 CANIF2DB1 CANIF2DB2 Message RAM 32 Message Objects November 30, 2007 Preliminary 379 Controller Area Network (CAN) Module 15.4 Controller Area Network Functional Description The CAN module conforms to the CAN protocol version 2.0 (parts A and B). Message transfers that include data, remote, error, and overload frames with an 11-bit identifier (standard) or a 29-bit identifier (extended) are supported. Transfer rates can be programmed up to 1 Mbps. The CAN module consists of three major parts: ■ CAN protocol controller and message handler ■ Message memory ■ CAN register interface The protocol controller transfers and receives the serial data from the CAN bus and passes the data on to the message handler. The message handler then loads this information into the appropriate message object based on the current filtering and identifiers in the message object memory. The message handler is also responsible for generating interrupts based on events on the CAN bus. The message object memory is a set of 32 identical memory blocks that hold the current configuration, status, and actual data for each message object. These are accessed via the CAN message object ® register interface. The message memory is not directly accessable in the Stellaris memory map, ® so the Stellaris CAN controller provides an interface to communicate with the message memory. The CAN message object register interface provides two register sets for communicating with the message objects. Since there is no direct access to the message object memory, these two interfaces must be used to read or write to each message object. The two message object interfaces allow parallel access to the CAN controller message objects when multiple objects may have new information that needs to be processed. 15.4.1 Initialization The software initialization is started by setting the INIT bit in the CAN Control (CANCTL) register, with software or by a hardware reset, or by going bus-off, which occurs when the transmitter's error counter exceeds a count of 255. While INIT is set, all message transfers to and from the CAN bus are stopped and the status of the CAN transmit output is recessive (High). Entering the initialization state does not change the configuration of the CAN controller, the message objects, or the error counters. However, some configuration registers are only accessible when in the initialization state. To initialize the CAN controller, set the CAN Bit Timing (CANBIT) register and configure each message object. If a message object is not needed, it is sufficient to set it as not valid by clearing the MsgVal bit in the CANIFnARB2 register. Otherwise, the whole message object has to be initialized, as the fields of the message object may not have valid information causing unexpected results. Access to the CAN Bit Timing (CANBIT) register and to the CAN Baud Rate Prescalar Extension (CANBRPE) register to configure the bit timing are enabled when both the INIT and CCE bits in the CANCTL register are set. To leave the initialization state, the INIT bit must be cleared. Afterwards, the internal Bit Stream Processor (BSP) synchronizes itself to the data transfer on the CAN bus by waiting for the occurrence of a sequence of 11 consecutive recessive bits (Bus Idle) before it takes part in bus activities and starts message transfers. The initialization of the message objects is independent of being in the initialization state and can be done on the fly, but message objects should all be configured to particular identifiers or set to not valid before the BSP starts the message transfer. To change the configuration of a message object during normal operation, set the MsgVal bit in the CANIFnARB2 register to 0 (not valid). When the configuration is completed, MsgVal is set to 1 again (valid). 380 Preliminary November 30, 2007 LM3S2016 Microcontroller 15.4.2 Operation Once the CAN module is initialized and the INIT bit in the CANCTL register is reset to 0, the CAN module synchronizes itself to the CAN bus and starts the message transfer. As messages are received, they are stored in their appropriate message objects if they pass the message handler's filtering. The whole message (including all arbitration bits, data-length code, and eight data bytes) is stored in the message object. If the Identifier Mask (the Msk bits in the CANIFnMSKn registers) is used, the arbitration bits which are masked to "don't care" may be overwritten in the message object. The CPU may read or write each message any time via the CAN Interface Registers (CANIFnCRQ, CANIFnCMSK, CANIFnMSKn, CANIFnARBn, CANIFnMCTL, CANIFnDAn, and CANIFnDBn). The message handler guarantees data consistency in case of concurrent accesses. The transmission of message objects are under the control of the software that is managing the CAN hardware. These can be message objects used for one-time data transfers, or permanent message objects used to respond in a more periodic manner. Permanent message objects have all arbitration and control set up, and only the data bytes are updated. To start the transmission, the TxRqst bit in the CANTXRQn register and the NewDat bit in the CANNWDAn register are set. If several transmit messages are assigned to the same message object (when the number of message objects is not sufficient), the whole message object has to be configured before the transmission of this message is requested. The transmission of any number of message objects may be requested at the same time; they are transmitted according to their internal priority, which is based on the message identifier for the message object. Messages may be updated or set to not valid any time, even when their requested transmission is still pending. The old data is discarded when a message is updated before its pending transmission has started. Depending on the configuration of the message object, the transmission of a message may be requested autonomously by the reception of a remote frame with a matching identifier. There are two sets of CAN Interface Registers (CANIF1x and CANIF2x), which are used to access the Message Objects in the Message RAM. The CAN controller coordinates transfers to and from the Message RAM to and from the registers. The function of the two sets are independent and identical and can be used to queue transactions. 15.4.3 Transmitting Message Objects If the internal transmit shift register of the CAN module is ready for loading, and if there is no data transfer between the CAN Interface Registers and message RAM, the valid message object with the highest priority and that has a pending transmission request is loaded into the transmit shift register by the message handler and the transmission is started. The message object's NewDat bit is reset and can be viewed in the CANNWDAn register. After a successful transmission, and if no new data was written to the message object since the start of the transmission, the TxRqst bit in the CANIFnCMSK register is reset. If the TxIE bit in the CANIFnMCTL register is set, the IntPnd bit in the CANIFnMCTL register is set after a successful transmission. If the CAN module has lost the arbitration or if an error occurred during the transmission, the message is re-transmitted as soon as the CAN bus is free again. If, meanwhile, the transmission of a message with higher priority has been requested, the messages are transmitted in the order of their priority. 15.4.4 Configuring a Transmit Message Object Table 15-1 on page 382 specifies the bit settings for a transmit message object. November 30, 2007 Preliminary 381 Controller Area Network (CAN) Module Table 15-1. Transmit Message Object Bit Settings Register CANIFnARB2 Bit Value MsgVal 1 CANIFnCMSK Arb Data Mask appl appl appl CANIFnMCTL CANIFnARB2 EoB 1 Dir 1 CANIFnMCTL NewDat MsgLst RxIE TxIE IntPnd RmtEn TxRqst 0 0 0 appl 0 appl 0 The Xtd and ID bit fields in the CANIFnARBn registers are set by an application. They define the identifier and type of the outgoing message. If an 11-bit Identifier (Standard Frame) is used, it is programmed to bits [28:18] of CANIFnARB1, as bits 17:0 of CANIFnARBn are not used by the CAN controller for 11-bit identifiers. If the TxIE bit is set, the IntPnd bit is set after a successful transmission of the message object. If the RmtEn bit is set, a matching received Remote Frame causes the TxRqst bit to be set and the Remote Frame is autonomously answered by a Data Frame with the data from the message object. The DLC bit in the CANIFnMCTL register is set by an application. TxRqst and RmtEn may not be set before the data is valid. The CAN mask registers (Msk bits in CANIFnMSKn, UMask bit in CANIFnMCTL register, and MXtd and MDir bits in CANIFnMSK2 register) may be used (UMask=1) to allow groups of Remote Frames with similar identifiers to set the TxRqst bit. The Dir bit should not be masked. 15.4.5 Updating a Transmit Message Object The CPU may update the data bytes of a Transmit Message Object any time via the CAN Interface Registers and neither the MsgVal nor the TxRqst bits have to be reset before the update. Even if only a part of the data bytes are to be updated, all four bytes of the corresponding CANIFnDAn or CANIFnDBn register have to be valid before the content of that register is transferred to the message object. Either the CPU has to write all four bytes into the CANIFnDAn or CANIFnDBn register or the message object is transferred to the CANIFnDAn or CANIFnDBn register before the CPU writes the new data bytes. In order to only update the data in a message object, the WR, NewDat, DataA, and DataB bits are written to the CAN IFn Command Mask (CANIFnMSKn) register, followed by writing the CAN IFn Data registers, and then the number of the message object is written to the CAN IFn Command Request (CANIFnCRQ) register, to update the data bytes and the TxRqst bit at the same time. To prevent the reset of TxRqst at the end of a transmission that may already be in progress while the data is updated, NewDat has to be set together with TxRqst. When NewDat is set together with TxRqst, NewDat is reset as soon as the new transmission has started. 15.4.6 Accepting Received Message Objects When the arbitration and control field (ID + Xtd + RmtEn + DLC) of an incoming message is completely shifted into the CAN module, the message handling capability of the module starts scanning the message RAM for a matching valid message object. To scan the message RAM for a matching message object, the Acceptance Filtering unit is loaded with the arbitration bits from the core. Then the arbitration and mask fields (including MsgVal, UMask, NewDat, and EoB) of message object 1 are loaded into the Acceptance Filtering unit and compared with the arbitration field from the shift register. This is repeated with each following message object until a matching message object is found or until the end of the message RAM is reached. If a match occurs, the scanning is stopped and the message handler proceeds depending on the type of frame received. 382 Preliminary November 30, 2007 LM3S2016 Microcontroller 15.4.7 Receiving a Data Frame The message handler stores the message from the CAN module receive shift register into the respective message object in the message RAM. It stores the data bytes, all arbitration bits, and the Data Length Code into the corresponding message object. This is implemented to keep the data bytes connected with the identifier even if arbitration mask registers are used. The CANIFnMCTL.NewDat bit is set to indicate that new data has been received. The CPU should reset CANIFnMCTL.NewDat when it reads the message object to indicate to the controller that the message has been received and the buffer is free to receive more messages. If the CAN controller receives a message and the CANIFnMCTL.NewDat bit was already set, the MsgLst bit is set to indicate that the previous data was lost. If the CANIFnMCTL.RxIE bit is set, the CANIFnMCTL.IntPnd bit is set, causing the CANINT interrupt register to point to the message object that just received a message. The CANIFnMCTL.TxRqst bit of this message object is reset to prevent the transmission of a Remote Frame, while the requested Data Frame has just been received. 15.4.8 Receiving a Remote Frame When a Remote Frame is received, three different configurations of the matching message object have to be considered: ■ Dir = 1 (direction = transmit), RmtEn = 1, UMask = 1 or 0 At the reception of a matching Remote Frame, the TxRqst bit of this message object is set. The rest of the message object remains unchanged. ■ Dir = 1 (direction = transmit), RmtEn = 0, UMask = 0 At the reception of a matching Remote Frame, the TxRqst bit of this message object remains unchanged; the Remote Frame is ignored. This remote frame is disabled and will not automatically respond or indicate that the remote frame ever happened. ■ Dir = 1 (direction = transmit), RmtEn = 0, UMask = 1 At the reception of a matching Remote Frame, the TxRqst bit of this message object is reset. The arbitration and control field (ID + Xtd + RmtEn + DLC) from the shift register is stored into the message object in the message RAM and the NewDat bit of this message object is set. The data field of the message object remains unchanged; the Remote Frame is treated similar to a received Data Frame. This is useful for a remote data request from another CAN device for which ® the Stellaris controller does not have readily available data. The software must fill the data and answer the frame manually. 15.4.9 Receive/Transmit Priority The receive/transmit priority for the message objects is controlled by the message number. Message object 1 has the highest priority, while message object 32 has the lowest priority. If more than one transmission request is pending, the message objects are transmitted in order based on the message object with the lowest message number. This should not be confused with the message identifier as that priority is enforced by the CAN bus. This means that if message object 1 and message object 2 both have valid messages that need to be transmitted, message object 1 will always be transmitted first regardless of the message identifier in the message object itself. 15.4.10 Configuring a Receive Message Object Table 15-2 on page 384 specifies the bit settings for a transmit message object. November 30, 2007 Preliminary 383 Controller Area Network (CAN) Module Table 15-2. Receive Message Object Bit Settings Register CANIFnARB2 Bit Value MsgVal 1 CANIFnCMSK Arb Data Mask appl appl appl CANIFnMCTL CANIFnARB2 EoB 1 Dir 0 CANIFnMCTL NewDat MsgLst RxIE TxIE IntPnd RmtEn TxRqst 0 0 appl 0 0 0 0 The Xtd and ID bit fields in the CANIFnARBn registers are set by an application. They define the identifier and type of accepted received messages. If an 11-bit Identifier (Standard Frame) is used, it is programmed to bits [28:18] of CANIFnARB1, and bits [17:0] are ignored by the CAN controller. When a Data Frame with an 11-bit Identifier is received, bits [17:0] are set to 0. If the RxIE bit is set, the IntPnd bit is set when a received Data Frame is accepted and stored in the message object. When the message handler stores a Data Frame in the message object, it stores the received Data Length Code and eight data bytes. If the Data Length Code is less than 8, the remaining bytes of the message object are overwritten by nonspecified values. The CAN mask registers (Msk bits in CANIFnMSKn, UMask bit in CANIFnMCTL register, and MXtd and MDir bits in CANIFnMSK2 register) may be used (UMask=1) to allow groups of Data Frames with similar identifiers to be accepted. The Dir bit should not be masked in typical applications. 15.4.11 Handling of Received Message Objects The CPU may read a received message any time via the CAN Interface registers because the data consistency is guaranteed by the message handler state machine. Typically, the CPU first writes 0x007F to the CAN IFn Command Mask (CANIFnCMSK) register and then writes the number of the message object to the CAN IFn Command Request (CANIFnCRQ) register. That combination transfers the whole received message from the message RAM into the Message Buffer registers (CANIFnMSKn, CANIFnARBn, and CANIFnMCTL). Additionally, the NewDat and IntPnd bits are cleared in the message RAM, acknowledging that the message has been read and clearing the pending interrupt being generated by this message object. If the message object uses masks for acceptance filtering, the arbitration bits show which of the matching messages has been received. The actual value of NewDat shows whether a new message has been received since the last time this message object was read. The actual value of MsgLst shows whether more than one message has been received since the last time this message object was read. MsgLst is not automatically reset. Using a Remote Frame, the CPU may request new data from another CAN node on the CAN bus. Setting the TxRqst bit of a receive object causes the transmission of a Remote Frame with the receive object's identifier. This Remote Frame triggers the other CAN node to start the transmission of the matching Data Frame. If the matching Data Frame is received before the Remote Frame could be transmitted, the TxRqst bit is automatically reset. This prevents the possible loss of data when the other device on the CAN bus has already transmitted the data, slightly earlier than expected. 15.4.12 Handling of Interrupts If several interrupts are pending, the CAN Interrupt (CANINT) register points to the pending interrupt with the highest priority, disregarding their chronological order. An interrupt remains pending until the CPU has cleared it. 384 Preliminary November 30, 2007 LM3S2016 Microcontroller The Status Interrupt has the highest priority. Among the message interrupts, the message object's interrupt priority decreases with increasing message number. A message interrupt is cleared by clearing the message object's IntPnd bit. The Status Interrupt is cleared by reading the CAN Status (CANSTS) register. The interrupt identifier IntId in the CANINT register indicates the cause of the interrupt. When no interrupt is pending, the register holds the value to 0. If the value of CANINT is different from 0, then there is an interrupt pending. If the IE bit is set in the CANCTL register, the interrupt line to the CPU is active. The interrupt line remains active until CANINT is 0, all interrupt sources have been cleared, (the cause of the interrupt is reset), or until IE is reset, which disables interrupts from the CAN controller. The value 0x8000 in the CANINT register indicates that an interrupt is pending because the CAN module has updated, but not necessarily changed, the CANSTS register (Error Interrupt or Status Interrupt). This indicates that there is either a new Error Interrupt or a new Status Interrupt. A write access can clear the RxOK, TxOK, and LEC flags in the CANSTS register, however, only a read access to the CANSTS register will clear the source of the status interrupt. IntId points to the pending message interrupt with the highest interrupt priority. The SIE bit in the CANCTL register controls whether a change of the status register may cause an interrupt. The EIE bit in the CANCTL register controls whether any interrupt from the CAN controller actually generates an interrupt to the microcontroller's interrupt controller. The CANINT interrupt register is updated even when the IE bit is set to zero. There are two possibilities when handling the source of a message interrupt. The first is to read the IntId bit in the CANINT interrupt register to determine the highest priority interrupt that is pending, and the second is to read the CAN Message Interrupt Pending (CANMSGnINT) register to see all of the message objects that have pending interrupts. An interrupt service routine reading the message that is the source of the interrupt may read the message and reset the message object's IntPnd at the same time by setting the ClrIntPnd bit in the CAN IFn Command Mask (CANIFnCMSK) register. When the IntPnd bit is cleared, the CANINT register will contain the message number for the next message object with a pending interrupt. 15.4.13 Bit Timing Configuration Error Considerations Even if minor errors in the configuration of the CAN bit timing do not result in immediate failure, the performance of a CAN network can be reduced significantly. In many cases, the CAN bit synchronization amends a faulty configuration of the CAN bit timing to such a degree that only occasionally an error frame is generated. In the case of arbitration, however, when two or more CAN nodes simultaneously try to transmit a frame, a misplaced sample point may cause one of the transmitters to become error passive. The analysis of such sporadic errors requires a detailed knowledge of the CAN bit synchronization inside a CAN node and of the CAN nodes' interaction on the CAN bus. 15.4.14 Bit Time and Bit Rate The CAN system supports bit rates in the range of lower than 1 Kbps up to 1000 Kbps. Each member of the CAN network has its own clock generator. The timing parameter of the bit time can be configured individually for each CAN node, creating a common bit rate even though the CAN nodes' oscillator periods may be different. Because of small variations in frequency caused by changes in temperature or voltage and by deteriorating components, these oscillators are not absolutely stable. As long as the variations November 30, 2007 Preliminary 385 Controller Area Network (CAN) Module remain inside a specific oscillator's tolerance range, the CAN nodes are able to compensate for the different bit rates by periodically resynchronizing to the bit stream. According to the CAN specification, the bit time is divided into four segments (see Figure 15-2 on page 386): the Synchronization Segment, the Propagation Time Segment, the Phase Buffer Segment 1, and the Phase Buffer Segment 2. Each segment consists of a specific, programmable number of time quanta (see Table 15-3 on page 386). The length of the time quantum (tq), which is the basic time unit of the bit time, is defined by the CAN controller's system clock (fsys) and the Baud Rate Prescaler (BRP): tq = BRP / fsys The CAN module's system clock fsys is the frequency of its CAN module clock (CAN_CLK) input. The Synchronization Segment Sync_Seg is that part of the bit time where edges of the CAN bus level are expected to occur; the distance between an edge that occurs outside of Sync_Seg and the Sync_Seg is called the phase error of that edge. The Propagation Time Segment Prop_Seg is intended to compensate for the physical delay times within the CAN network. The Phase Buffer Segments Phase_Seg1 and Phase_Seg2 surround the Sample Point. The (Re-)Synchronization Jump Width (SJW) defines how far a resynchronization may move the Sample Point inside the limits defined by the Phase Buffer Segments to compensate for edge phase errors. A given bit rate may be met by different bit-time configurations, but for the proper function of the CAN network, the physical delay times and the oscillator's tolerance range have to be considered. Figure 15-2. CAN Bit Time Table 15-3. CAN Protocol Ranges Parameter BRP Sync_Seg Prop_Seg Range Remark a [1 .. 32] Defines the length of the time quantum tq 1 tq Fixed length, synchronization of bus input to system clock [1 .. 8] tq Compensates for the physical delay times Phase_Seg1 [1 .. 8] tq May be lengthened temporarily by synchronization Phase_Seg2 [1 .. 8] tq May be shortened temporarily by synchronization 386 Preliminary November 30, 2007 LM3S2016 Microcontroller Parameter SJW Range Remark [1 .. 4] tq May not be longer than either Phase Buffer Segment a. This table describes the minimum programmable ranges required by the CAN protocol. The bit timing configuration is programmed in two register bytes in the CANBIT register. The sum of Prop_Seg and Phase_Seg1 (as TSEG1) is combined with Phase_Seg2 (as TSEG2) in one byte, and SJW and BRP are combined in the other byte. In these bit timing registers, the four components TSEG1, TSEG2, SJW, and BRP have to be programmed to a numerical value that is one less than its functional value; so instead of values in the range of [1..n], values in the range of [0..n-1] are programmed. That way, for example, SJW (functional range of [1..4]) is represented by only two bits. Therefore, the length of the bit time is (programmed values): [TSEG1 + TSEG2 + 3] tq or (functional values): [Sync_Seg + Prop_Seg + Phase_Seg1 + Phase_Seg2] tq The data in the bit timing registers are the configuration input of the CAN protocol controller. The Baud Rate Prescalar (configured by BRP) defines the length of the time quantum, the basic time unit of the bit time; the Bit Timing Logic (configured by TSEG1, TSEG2, and SJW) defines the number of time quanta in the bit time. The processing of the bit time, the calculation of the position of the Sample Point, and occasional synchronizations are controlled by the CAN controller and are evaluated once per time quantum. The CAN controller translates messages to and from frames. It generates and discards the enclosing fixed format bits, inserts and extracts stuff bits, calculates and checks the CRC code, performs the error management, and decides which type of synchronization is to be used. It is evaluated at the Sample Point and processes the sampled bus input bit. The time after the Sample Point that is needed to calculate the next bit to be sent (that is, the data bit, CRC bit, stuff bit, error flag, or idle) is called the Information Processing Time (IPT). The IPT is application-specific but may not be longer than 2 tq; the CAN's IPT is 0 tq. Its length is the lower limit of the programmed length of Phase_Seg2. In case of synchronization, Phase_Seg2 may be shortened to a value less than IPT, which does not affect bus timing. 15.4.15 Calculating the Bit Timing Parameters Usually, the calculation of the bit timing configuration starts with a desired bit rate or bit time. The resulting bit time (1/bit rate) must be an integer multiple of the system clock period. The bit time may consist of 4 to 25 time quanta. Several combinations may lead to the desired bit time, allowing iterations of the following steps. The first part of the bit time to be defined is the Prop_Seg. Its length depends on the delay times measured in the system. A maximum bus length as well as a maximum node delay has to be defined for expandable CAN bus systems. The resulting time for Prop_Seg is converted into time quanta (rounded up to the nearest integer multiple of tq). The Sync_Seg is 1 tq long (fixed), which leaves (bit time - Prop_Seg - 1) tq for the two Phase Buffer Segments. If the number of remaining tq is even, the Phase Buffer Segments have the same length, that is, Phase_Seg2 = Phase_Seg1, else Phase_Seg2 = Phase_Seg1 + 1. November 30, 2007 Preliminary 387 Controller Area Network (CAN) Module The minimum nominal length of Phase_Seg2 has to be regarded as well. Phase_Seg2 may not be shorter than the CAN controller's Information Processing Time, which is, depending on the actual implementation, in the range of [0..2] tq. The length of the Synchronization Jump Width is set to its maximum value, which is the minimum of 4 and Phase_Seg1. The oscillator tolerance range necessary for the resulting configuration is calculated by the formula given below: (1 -df) x fnom