LM3S6965-IRN20A2

P RE LIMIN A R Y LM3S6965 Microcontroller D ATA SHE E T D S -LM3S 6965 - 1 9 7 2 C o p yri g h t © 2 0 0 7 L u mi n a ry Mi cro, Inc. Legal Disclaimers and Trademark Information INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH LUMINARY MICRO PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN LUMINARY MICRO'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, LUMINARY MICRO ASSUMES NO LIABILITY WHATSOEVER, AND LUMINARY MICRO DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF LUMINARY MICRO'S PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. LUMINARY MICRO'S PRODUCTS ARE NOT INTENDED FOR USE IN MEDICAL, LIFE SAVING, OR LIFE-SUSTAINING APPLICATIONS. Luminary Micro may make changes to specifications and product descriptions at any time, without notice. Contact your local Luminary Micro sales office or your distributor to obtain the latest specifications before placing your product order. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Luminary Micro reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. Copyright © 2007 Luminary Micro, Inc. All rights reserved. Stellaris, Luminary Micro, and the Luminary Micro logo are registered trademarks of Luminary Micro, Inc. or its subsidiaries in the United States and other countries. ARM and Thumb are registered trademarks and Cortex is a trademark of ARM Limited. Other names and brands may be claimed as the property of others. Luminary Micro, Inc. 108 Wild Basin, Suite 350 Austin, TX 78746 Main: +1-512-279-8800 Fax: +1-512-279-8879 http://www.luminarymicro.com 2 Preliminary November 30, 2007 LM3S6965 Microcontroller Table of Contents About This Document .................................................................................................................... 20 Audience .............................................................................................................................................. About This Manual ................................................................................................................................ Related Documents ............................................................................................................................... Documentation Conventions .................................................................................................................. 20 20 20 20 22 28 29 30 30 30 31 32 33 34 35 35 38 38 38 39 39 39 39 39 1 1.1 1.2 1.3 1.4 1.4.1 1.4.2 1.4.3 1.4.4 1.4.5 1.4.6 1.4.7 1.4.8 Architectural Overview ...................................................................................................... 22 Product Features ...................................................................................................................... Target Applications .................................................................................................................... High-Level Block Diagram ......................................................................................................... Functional Overview .................................................................................................................. ARM Cortex™-M3 ..................................................................................................................... Motor Control Peripherals .......................................................................................................... Analog Peripherals .................................................................................................................... Serial Communications Peripherals ............................................................................................ System Peripherals ................................................................................................................... Memory Peripherals .................................................................................................................. Additional Features ................................................................................................................... Hardware Details ...................................................................................................................... Block Diagram .......................................................................................................................... Functional Description ............................................................................................................... Serial Wire and JTAG Debug ..................................................................................................... Embedded Trace Macrocell (ETM) ............................................................................................. Trace Port Interface Unit (TPIU) ................................................................................................. ROM Table ............................................................................................................................... Memory Protection Unit (MPU) ................................................................................................... Nested Vectored Interrupt Controller (NVIC) ................................................................................ 2 2.1 2.2 2.2.1 2.2.2 2.2.3 2.2.4 2.2.5 2.2.6 ARM Cortex-M3 Processor Core ...................................................................................... 37 3 4 5 5.1 5.2 5.2.1 5.2.2 5.2.3 5.2.4 5.3 5.4 5.4.1 5.4.2 Memory Map ....................................................................................................................... 43 Interrupts ............................................................................................................................ 45 JTAG Interface .................................................................................................................... 48 Block Diagram .......................................................................................................................... Functional Description ............................................................................................................... JTAG Interface Pins .................................................................................................................. JTAG TAP Controller ................................................................................................................. Shift Registers .......................................................................................................................... Operational Considerations ........................................................................................................ Initialization and Configuration ................................................................................................... Register Descriptions ................................................................................................................ Instruction Register (IR) ............................................................................................................. Data Registers .......................................................................................................................... 49 49 50 51 52 52 55 55 55 57 6 6.1 6.1.1 6.1.2 System Control ................................................................................................................... 59 Functional Description ............................................................................................................... 59 Device Identification .................................................................................................................. 59 Reset Control ............................................................................................................................ 59 November 30, 2007 Preliminary 3 Table of Contents 6.1.3 6.1.4 6.1.5 6.2 6.3 6.4 Power Control ........................................................................................................................... Clock Control ............................................................................................................................ System Control ......................................................................................................................... Initialization and Configuration ................................................................................................... Register Map ............................................................................................................................ Register Descriptions ................................................................................................................ Block Diagram ........................................................................................................................ Functional Description ............................................................................................................. Register Access Timing ........................................................................................................... Clock Source .......................................................................................................................... Battery Management ............................................................................................................... Real-Time Clock ...................................................................................................................... Non-Volatile Memory ............................................................................................................... Power Control ......................................................................................................................... Interrupts and Status ............................................................................................................... Initialization and Configuration ................................................................................................. Initialization ............................................................................................................................. RTC Match Functionality (No Hibernation) ................................................................................ RTC Match/Wake-Up from Hibernation ..................................................................................... External Wake-Up from Hibernation .......................................................................................... RTC/External Wake-Up from Hibernation .................................................................................. Register Map .......................................................................................................................... Register Descriptions .............................................................................................................. 62 62 64 65 65 66 7 7.1 7.2 7.2.1 7.2.2 7.2.3 7.2.4 7.2.5 7.2.6 7.2.7 7.3 7.3.1 7.3.2 7.3.3 7.3.4 7.3.5 7.4 7.5 Hibernation Module .......................................................................................................... 120 121 121 121 122 122 122 123 123 123 124 124 124 124 125 125 125 126 8 8.1 8.2 8.2.1 8.2.2 8.3 8.3.1 8.3.2 8.4 8.5 8.6 Internal Memory ............................................................................................................... 139 Block Diagram ........................................................................................................................ 139 Functional Description ............................................................................................................. 139 SRAM Memory ........................................................................................................................ 139 Flash Memory ......................................................................................................................... 140 Flash Memory Initialization and Configuration ........................................................................... 141 Flash Programming ................................................................................................................. 141 Nonvolatile Register Programming ........................................................................................... 142 Register Map .......................................................................................................................... 142 Flash Register Descriptions (Flash Control Offset) ..................................................................... 143 Flash Register Descriptions (System Control Offset) .................................................................. 150 9 9.1 9.1.1 9.1.2 9.1.3 9.1.4 9.1.5 9.1.6 9.2 9.3 9.4 General-Purpose Input/Outputs (GPIOs) ....................................................................... 163 Functional Description ............................................................................................................. 163 Data Control ........................................................................................................................... 164 Interrupt Control ...................................................................................................................... 165 Mode Control .......................................................................................................................... 166 Commit Control ....................................................................................................................... 166 Pad Control ............................................................................................................................. 166 Identification ........................................................................................................................... 166 Initialization and Configuration ................................................................................................. 166 Register Map .......................................................................................................................... 168 Register Descriptions .............................................................................................................. 169 4 Preliminary November 30, 2007 LM3S6965 Microcontroller 10 10.1 10.2 10.2.1 10.2.2 10.2.3 10.3 10.3.1 10.3.2 10.3.3 10.3.4 10.3.5 10.3.6 10.4 10.5 General-Purpose Timers ................................................................................................. 204 Block Diagram ........................................................................................................................ Functional Description ............................................................................................................. GPTM Reset Conditions .......................................................................................................... 32-Bit Timer Operating Modes .................................................................................................. 16-Bit Timer Operating Modes .................................................................................................. Initialization and Configuration ................................................................................................. 32-Bit One-Shot/Periodic Timer Mode ....................................................................................... 32-Bit Real-Time Clock (RTC) Mode ......................................................................................... 16-Bit One-Shot/Periodic Timer Mode ....................................................................................... 16-Bit Input Edge Count Mode ................................................................................................. 16-Bit Input Edge Timing Mode ................................................................................................ 16-Bit PWM Mode ................................................................................................................... Register Map .......................................................................................................................... Register Descriptions .............................................................................................................. Block Diagram ........................................................................................................................ Functional Description ............................................................................................................. Initialization and Configuration ................................................................................................. Register Map .......................................................................................................................... Register Descriptions .............................................................................................................. 204 205 206 206 207 211 211 212 212 213 213 214 214 215 240 240 241 241 242 11 11.1 11.2 11.3 11.4 11.5 Watchdog Timer ............................................................................................................... 240 12 12.1 12.2 12.2.1 12.2.2 12.2.3 12.2.4 12.2.5 12.2.6 12.3 12.3.1 12.3.2 12.4 12.5 Analog-to-Digital Converter (ADC) ................................................................................. 263 Block Diagram ........................................................................................................................ 264 Functional Description ............................................................................................................. 264 Sample Sequencers ................................................................................................................ 264 Module Control ........................................................................................................................ 265 Hardware Sample Averaging Circuit ......................................................................................... 266 Analog-to-Digital Converter ...................................................................................................... 266 Test Modes ............................................................................................................................. 266 Internal Temperature Sensor .................................................................................................... 266 Initialization and Configuration ................................................................................................. 267 Module Initialization ................................................................................................................. 267 Sample Sequencer Configuration ............................................................................................. 267 Register Map .......................................................................................................................... 268 Register Descriptions .............................................................................................................. 269 13 13.1 13.2 13.2.1 13.2.2 13.2.3 13.2.4 13.2.5 13.2.6 13.2.7 13.2.8 13.3 13.4 Universal Asynchronous Receivers/Transmitters (UARTs) ......................................... 296 Block Diagram ........................................................................................................................ Functional Description ............................................................................................................. Transmit/Receive Logic ........................................................................................................... Baud-Rate Generation ............................................................................................................. Data Transmission .................................................................................................................. Serial IR (SIR) ......................................................................................................................... FIFO Operation ....................................................................................................................... Interrupts ................................................................................................................................ Loopback Operation ................................................................................................................ IrDA SIR block ........................................................................................................................ Initialization and Configuration ................................................................................................. Register Map .......................................................................................................................... 297 297 297 298 299 299 300 300 301 301 301 302 November 30, 2007 Preliminary 5 Table of Contents 13.5 Register Descriptions .............................................................................................................. 303 14 14.1 14.2 14.2.1 14.2.2 14.2.3 14.2.4 14.3 14.4 14.5 Synchronous Serial Interface (SSI) ................................................................................ 337 Block Diagram ........................................................................................................................ Functional Description ............................................................................................................. Bit Rate Generation ................................................................................................................. FIFO Operation ....................................................................................................................... Interrupts ................................................................................................................................ Frame Formats ....................................................................................................................... Initialization and Configuration ................................................................................................. Register Map .......................................................................................................................... Register Descriptions .............................................................................................................. Block Diagram ........................................................................................................................ Functional Description ............................................................................................................. I2C Bus Functional Overview .................................................................................................... Available Speed Modes ........................................................................................................... Interrupts ................................................................................................................................ Loopback Operation ................................................................................................................ Command Sequence Flow Charts ............................................................................................ Initialization and Configuration ................................................................................................. I2C Register Map ..................................................................................................................... Register Descriptions (I2C Master) ........................................................................................... Register Descriptions (I2C Slave) ............................................................................................. 337 337 338 338 338 339 346 347 348 374 374 375 377 378 378 379 385 386 387 400 15 15.1 15.2 15.2.1 15.2.2 15.2.3 15.2.4 15.2.5 15.3 15.4 15.5 15.6 Inter-Integrated Circuit (I2C) Interface ............................................................................ 374 16 16.1 16.2 16.2.1 16.2.2 16.2.3 16.2.4 16.3 16.4 16.5 16.6 Ethernet Controller .......................................................................................................... 409 Block Diagram ........................................................................................................................ 410 Functional Description ............................................................................................................. 410 Internal MII Operation .............................................................................................................. 410 PHY Configuration/Operation ................................................................................................... 411 MAC Configuration/Operation .................................................................................................. 412 Interrupts ................................................................................................................................ 414 Initialization and Configuration ................................................................................................. 415 Ethernet Register Map ............................................................................................................. 415 Ethernet MAC Register Descriptions ......................................................................................... 417 MII Management Register Descriptions ..................................................................................... 434 17 17.1 17.2 17.2.1 17.3 17.4 17.5 Analog Comparators ....................................................................................................... 453 Block Diagram ........................................................................................................................ Functional Description ............................................................................................................. Internal Reference Programming .............................................................................................. Initialization and Configuration ................................................................................................. Register Map .......................................................................................................................... Register Descriptions .............................................................................................................. Block Diagram ........................................................................................................................ Functional Description ............................................................................................................. PWM Timer ............................................................................................................................. PWM Comparators .................................................................................................................. PWM Signal Generator ............................................................................................................ 453 454 455 456 456 457 465 465 465 466 467 18 18.1 18.2 18.2.1 18.2.2 18.2.3 Pulse Width Modulator (PWM) ........................................................................................ 465 6 Preliminary November 30, 2007 LM3S6965 Microcontroller 18.2.4 18.2.5 18.2.6 18.2.7 18.2.8 18.3 18.4 18.5 Dead-Band Generator ............................................................................................................. Interrupt/ADC-Trigger Selector ................................................................................................. Synchronization Methods ......................................................................................................... Fault Conditions ...................................................................................................................... Output Control Block ............................................................................................................... Initialization and Configuration ................................................................................................. Register Map .......................................................................................................................... Register Descriptions .............................................................................................................. Block Diagram ........................................................................................................................ Functional Description ............................................................................................................. Initialization and Configuration ................................................................................................. Register Map .......................................................................................................................... Register Descriptions .............................................................................................................. 468 468 468 469 469 469 470 472 501 502 504 505 505 19 19.1 19.2 19.3 19.4 19.5 Quadrature Encoder Interface (QEI) ............................................................................... 501 20 21 22 23 Pin Diagram ...................................................................................................................... 518 Signal Tables .................................................................................................................... 519 Operating Characteristics ............................................................................................... 534 Electrical Characteristics ................................................................................................ 535 23.1 DC Characteristics .................................................................................................................. 535 23.1.1 Maximum Ratings ................................................................................................................... 535 23.1.2 Recommended DC Operating Conditions .................................................................................. 535 23.1.3 On-Chip Low Drop-Out (LDO) Regulator Characteristics ............................................................ 536 23.1.4 Power Specifications ............................................................................................................... 536 23.1.5 Flash Memory Characteristics .................................................................................................. 538 23.2 AC Characteristics ................................................................................................................... 538 23.2.1 Load Conditions ...................................................................................................................... 538 23.2.2 Clocks .................................................................................................................................... 538 23.2.3 Analog-to-Digital Converter ...................................................................................................... 539 23.2.4 Analog Comparator ................................................................................................................. 540 23.2.5 I2C ......................................................................................................................................... 540 23.2.6 Ethernet Controller .................................................................................................................. 541 23.2.7 Hibernation Module ................................................................................................................. 544 23.2.8 Synchronous Serial Interface (SSI) ........................................................................................... 544 23.2.9 JTAG and Boundary Scan ........................................................................................................ 546 23.2.10 General-Purpose I/O ............................................................................................................... 547 23.2.11 Reset ..................................................................................................................................... 548 24 A A.1 A.2 A.2.1 A.2.2 A.3 A.3.1 A.3.2 A.3.3 Package Information ........................................................................................................ 550 Serial Flash Loader .......................................................................................................... 552 Serial Flash Loader ................................................................................................................. Interfaces ............................................................................................................................... UART ..................................................................................................................................... SSI ......................................................................................................................................... Packet Handling ...................................................................................................................... Packet Format ........................................................................................................................ Sending Packets ..................................................................................................................... Receiving Packets ................................................................................................................... 552 552 552 552 553 553 553 553 November 30, 2007 Preliminary 7 Table of Contents A.4 A.4.1 A.4.2 A.4.3 A.4.4 A.4.5 A.4.6 Commands ............................................................................................................................. COMMAND_PING (0X20) ........................................................................................................ COMMAND_GET_STATUS (0x23) ........................................................................................... COMMAND_DOWNLOAD (0x21) ............................................................................................. COMMAND_SEND_DATA (0x24) ............................................................................................. COMMAND_RUN (0x22) ......................................................................................................... COMMAND_RESET (0x25) ..................................................................................................... 554 554 554 554 555 555 555 B C C.1 C.2 C.3 C.4 Register Quick Reference ............................................................................................... 557 Ordering and Contact Information ................................................................................. 577 Ordering Information ................................................................................................................ Kits ......................................................................................................................................... Company Information .............................................................................................................. Support Information ................................................................................................................. 577 577 577 578 8 Preliminary November 30, 2007 LM3S6965 Microcontroller List of Figures Figure 1-1. Figure 2-1. Figure 2-2. Figure 5-1. Figure 5-2. Figure 5-3. Figure 5-4. Figure 5-5. Figure 6-1. Figure 7-1. Figure 8-1. Figure 9-1. Figure 9-2. Figure 9-3. Figure 10-1. Figure 10-2. Figure 10-3. Figure 10-4. Figure 11-1. Figure 12-1. Figure 12-2. Figure 13-1. Figure 13-2. Figure 13-3. Figure 14-1. Figure 14-2. Figure 14-3. Figure 14-4. Figure 14-5. Figure 14-6. Figure 14-7. Figure 14-8. Figure 14-9. Figure 14-10. Figure 14-11. Figure 14-12. Figure 15-1. Figure 15-2. Figure 15-3. Figure 15-4. Figure 15-5. Figure 15-6. Figure 15-7. Figure 15-8. Figure 15-9. Stellaris 6000 Series High-Level Block Diagram ............................................................... 29 CPU Block Diagram ......................................................................................................... 38 TPIU Block Diagram ........................................................................................................ 39 JTAG Module Block Diagram ............................................................................................ 49 Test Access Port State Machine ....................................................................................... 52 IDCODE Register Format ................................................................................................. 57 BYPASS Register Format ................................................................................................ 58 Boundary Scan Register Format ....................................................................................... 58 External Circuitry to Extend Reset .................................................................................... 60 Hibernation Module Block Diagram ................................................................................. 121 Flash Block Diagram ...................................................................................................... 139 GPIO Port Block Diagram ............................................................................................... 164 GPIODATA Write Example ............................................................................................. 165 GPIODATA Read Example ............................................................................................. 165 GPTM Module Block Diagram ........................................................................................ 205 16-Bit Input Edge Count Mode Example .......................................................................... 209 16-Bit Input Edge Time Mode Example ........................................................................... 210 16-Bit PWM Mode Example ............................................................................................ 211 WDT Module Block Diagram .......................................................................................... 240 ADC Module Block Diagram ........................................................................................... 264 Internal Temperature Sensor Characteristic ..................................................................... 267 UART Module Block Diagram ......................................................................................... 297 UART Character Frame ................................................................................................. 298 IrDA Data Modulation ..................................................................................................... 300 SSI Module Block Diagram ............................................................................................. 337 TI Synchronous Serial Frame Format (Single Transfer) .................................................... 339 TI Synchronous Serial Frame Format (Continuous Transfer) ............................................ 340 Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 ...................................... 341 Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .............................. 341 Freescale SPI Frame Format with SPO=0 and SPH=1 ..................................................... 342 Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ........................... 343 Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 .................... 343 Freescale SPI Frame Format with SPO=1 and SPH=1 ..................................................... 344 MICROWIRE Frame Format (Single Frame) .................................................................... 345 MICROWIRE Frame Format (Continuous Transfer) ......................................................... 346 MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ........................ 346 I2C Block Diagram ......................................................................................................... 374 I2C Bus Configuration .................................................................................................... 375 START and STOP Conditions ......................................................................................... 375 Complete Data Transfer with a 7-Bit Address ................................................................... 376 R/S Bit in First Byte ........................................................................................................ 376 Data Validity During Bit Transfer on the I2C Bus ............................................................... 376 Master Single SEND ...................................................................................................... 379 Master Single RECEIVE ................................................................................................. 380 Master Burst SEND ....................................................................................................... 381 ® November 30, 2007 Preliminary 9 Table of Contents Figure 15-10. Figure 15-11. Figure 15-12. Figure 15-13. Figure 16-1. Figure 16-2. Figure 16-3. Figure 17-1. Figure 17-2. Figure 17-3. Figure 18-1. Figure 18-2. Figure 18-3. Figure 18-4. Figure 18-5. Figure 19-1. Figure 19-2. Figure 20-1. Figure 23-1. Figure 23-2. Figure 23-3. Figure 23-4. Figure 23-5. Figure 23-6. Figure 23-7. Figure 23-8. Figure 23-9. Figure 23-10. Figure 23-11. Figure 23-12. Figure 23-13. Figure 23-14. Figure 23-15. Figure 24-1. Master Burst RECEIVE .................................................................................................. 382 Master Burst RECEIVE after Burst SEND ........................................................................ 383 Master Burst SEND after Burst RECEIVE ........................................................................ 384 Slave Command Sequence ............................................................................................ 385 Ethernet Controller Block Diagram .................................................................................. 410 Ethernet Controller ......................................................................................................... 410 Ethernet Frame ............................................................................................................. 412 Analog Comparator Module Block Diagram ..................................................................... 453 Structure of Comparator Unit .......................................................................................... 454 Comparator Internal Reference Structure ........................................................................ 455 PWM Module Block Diagram .......................................................................................... 465 PWM Count-Down Mode ................................................................................................ 466 PWM Count-Up/Down Mode .......................................................................................... 467 PWM Generation Example In Count-Up/Down Mode ....................................................... 467 PWM Dead-Band Generator ........................................................................................... 468 QEI Block Diagram ........................................................................................................ 502 Quadrature Encoder and Velocity Predivider Operation .................................................... 503 Pin Connection Diagram ................................................................................................ 518 Load Conditions ............................................................................................................ 538 I2C Timing ..................................................................................................................... 541 External XTLP Oscillator Characteristics ......................................................................... 543 Hibernation Module Timing ............................................................................................. 544 SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement .............. 545 SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ............................. 545 SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ................................................. 546 JTAG Test Clock Input Timing ......................................................................................... 547 JTAG Test Access Port (TAP) Timing .............................................................................. 547 JTAG TRST Timing ........................................................................................................ 547 External Reset Timing (RST) .......................................................................................... 548 Power-On Reset Timing ................................................................................................. 549 Brown-Out Reset Timing ................................................................................................ 549 Software Reset Timing ................................................................................................... 549 Watchdog Reset Timing ................................................................................................. 549 100-Pin LQFP Package .................................................................................................. 550 10 Preliminary November 30, 2007 LM3S6965 Microcontroller List of Tables Table 1. Table 3-1. Table 4-1. Table 4-2. Table 5-1. Table 5-2. Table 6-1. Table 7-1. Table 8-1. Table 8-2. Table 8-3. Table 9-1. Table 9-2. Table 9-3. Table 10-1. Table 10-2. Table 10-3. Table 11-1. Table 12-1. Table 12-2. Table 13-1. Table 14-1. Table 15-1. Table 15-2. Table 15-3. Table 16-1. Table 16-2. Table 17-1. Table 17-2. Table 17-3. Table 17-4. Table 18-1. Table 19-1. Table 21-1. Table 21-2. Table 21-3. Table 21-4. Table 22-1. Table 22-2. Table 23-1. Table 23-2. Table 23-3. Table 23-4. Table 23-5. Table 23-6. Table 23-7. Documentation Conventions ............................................................................................ 20 Memory Map ................................................................................................................... 43 Exception Types .............................................................................................................. 45 Interrupts ........................................................................................................................ 46 JTAG Port Pins Reset State ............................................................................................. 50 JTAG Instruction Register Commands ............................................................................... 55 System Control Register Map ........................................................................................... 65 Hibernation Module Register Map ................................................................................... 125 Flash Protection Policy Combinations ............................................................................. 141 Flash Resident Registers ............................................................................................... 142 Flash Register Map ........................................................................................................ 142 GPIO Pad Configuration Examples ................................................................................. 167 GPIO Interrupt Configuration Example ............................................................................ 167 GPIO Register Map ....................................................................................................... 168 Available CCP Pins ........................................................................................................ 205 16-Bit Timer With Prescaler Configurations ..................................................................... 208 Timers Register Map ...................................................................................................... 214 Watchdog Timer Register Map ........................................................................................ 241 Samples and FIFO Depth of Sequencers ........................................................................ 264 ADC Register Map ......................................................................................................... 268 UART Register Map ....................................................................................................... 302 SSI Register Map .......................................................................................................... 347 Examples of I2C Master Timer Period versus Speed Mode ............................................... 377 Inter-Integrated Circuit (I2C) Interface Register Map ......................................................... 386 Write Field Decoding for I2CMCS[3:0] Field (Sheet 1 of 3) ................................................ 391 TX & RX FIFO Organization ........................................................................................... 413 Ethernet Register Map ................................................................................................... 416 Comparator 0 Operating Modes ...................................................................................... 454 Comparator 1 Operating Modes ..................................................................................... 455 Internal Reference Voltage and ACREFCTL Field Values ................................................. 455 Analog Comparators Register Map ................................................................................. 457 PWM Register Map ........................................................................................................ 470 QEI Register Map .......................................................................................................... 505 Signals by Pin Number ................................................................................................... 519 Signals by Signal Name ................................................................................................. 523 Signals by Function, Except for GPIO ............................................................................. 528 GPIO Pins and Alternate Functions ................................................................................. 532 Temperature Characteristics ........................................................................................... 534 Thermal Characteristics ................................................................................................. 534 Maximum Ratings .......................................................................................................... 535 Recommended DC Operating Conditions ........................................................................ 535 LDO Regulator Characteristics ....................................................................................... 536 Detailed Power Specifications ........................................................................................ 537 Flash Memory Characteristics ........................................................................................ 538 Phase Locked Loop (PLL) Characteristics ....................................................................... 538 Clock Characteristics ..................................................................................................... 538 November 30, 2007 Preliminary 11 Table of Contents Table 23-8. Table 23-9. Table 23-10. Table 23-11. Table 23-12. Table 23-13. Table 23-14. Table 23-15. Table 23-16. Table 23-17. Table 23-18. Table 23-19. Table 23-20. Table 23-21. Table 23-22. Table 23-23. Table 23-24. Table 23-25. Table 23-26. Table C-1. Crystal Characteristics ................................................................................................... 539 ADC Characteristics ....................................................................................................... 539 Analog Comparator Characteristics ................................................................................. 540 Analog Comparator Voltage Reference Characteristics .................................................... 540 I2C Characteristics ......................................................................................................... 540 100BASE-TX Transmitter Characteristics ........................................................................ 541 100BASE-TX Transmitter Characteristics (informative) ..................................................... 541 100BASE-TX Receiver Characteristics ............................................................................ 541 10BASE-T Transmitter Characteristics ............................................................................ 541 10BASE-T Transmitter Characteristics (informative) ......................................................... 542 10BASE-T Receiver Characteristics ................................................................................ 542 Isolation Transformers ................................................................................................... 542 Ethernet Reference Crystal ............................................................................................ 543 External XTLP Oscillator Characteristics ......................................................................... 543 Hibernation Module Characteristics ................................................................................. 544 SSI Characteristics ........................................................................................................ 544 JTAG Characteristics ..................................................................................................... 546 GPIO Characteristics ..................................................................................................... 548 Reset Characteristics ..................................................................................................... 548 Part Ordering Information ............................................................................................... 577 12 Preliminary November 30, 2007 LM3S6965 Microcontroller List of Registers System Control .............................................................................................................................. 59 Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: Register 17: Register 18: Register 19: Register 20: Register 21: Register 22: Register 23: Register 24: Register 25: Register 26: Register 27: Register 28: Register 29: Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 1: Register 2: Device Identification 0 (DID0), offset 0x000 ....................................................................... 67 Brown-Out Reset Control (PBORCTL), offset 0x030 .......................................................... 69 LDO Power Control (LDOPCTL), offset 0x034 ................................................................... 70 Raw Interrupt Status (RIS), offset 0x050 ........................................................................... 71 Interrupt Mask Control (IMC), offset 0x054 ........................................................................ 72 Masked Interrupt Status and Clear (MISC), offset 0x058 .................................................... 73 Reset Cause (RESC), offset 0x05C .................................................................................. 74 Run-Mode Clock Configuration (RCC), offset 0x060 .......................................................... 75 XTAL to PLL Translation (PLLCFG), offset 0x064 .............................................................. 79 Run-Mode Clock Configuration 2 (RCC2), offset 0x070 ...................................................... 80 Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 .......................................... 82 Device Identification 1 (DID1), offset 0x004 ....................................................................... 83 Device Capabilities 0 (DC0), offset 0x008 ......................................................................... 85 Device Capabilities 1 (DC1), offset 0x010 ......................................................................... 86 Device Capabilities 2 (DC2), offset 0x014 ......................................................................... 88 Device Capabilities 3 (DC3), offset 0x018 ......................................................................... 90 Device Capabilities 4 (DC4), offset 0x01C ......................................................................... 92 Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100 .................................... 94 Sleep Mode Clock Gating Control Register 0 (SCGC0), offset 0x110 .................................. 96 Deep Sleep Mode Clock Gating Control Register 0 (DCGC0), offset 0x120 ......................... 98 Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104 ................................... 100 Sleep Mode Clock Gating Control Register 1 (SCGC1), offset 0x114 ................................. 103 Deep Sleep Mode Clock Gating Control Register 1 (DCGC1), offset 0x124 ....................... 106 Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108 ................................... 109 Sleep Mode Clock Gating Control Register 2 (SCGC2), offset 0x118 ................................. 111 Deep Sleep Mode Clock Gating Control Register 2 (DCGC2), offset 0x128 ....................... 113 Software Reset Control 0 (SRCR0), offset 0x040 ............................................................. 115 Software Reset Control 1 (SRCR1), offset 0x044 ............................................................. 116 Software Reset Control 2 (SRCR2), offset 0x048 ............................................................. 118 Hibernation RTC Counter (HIBRTCC), offset 0x000 ......................................................... Hibernation RTC Match 0 (HIBRTCM0), offset 0x004 ....................................................... Hibernation RTC Match 1 (HIBRTCM1), offset 0x008 ....................................................... Hibernation RTC Load (HIBRTCLD), offset 0x00C ........................................................... Hibernation Control (HIBCTL), offset 0x010 ..................................................................... Hibernation Interrupt Mask (HIBIM), offset 0x014 ............................................................. Hibernation Raw Interrupt Status (HIBRIS), offset 0x018 .................................................. Hibernation Masked Interrupt Status (HIBMIS), offset 0x01C ............................................ Hibernation Interrupt Clear (HIBIC), offset 0x020 ............................................................. Hibernation RTC Trim (HIBRTCT), offset 0x024 ............................................................... Hibernation Data (HIBDATA), offset 0x030-0x12C ............................................................ 127 128 129 130 131 133 134 135 136 137 138 Hibernation Module ..................................................................................................................... 120 Internal Memory ........................................................................................................................... 139 Flash Memory Address (FMA), offset 0x000 .................................................................... 144 Flash Memory Data (FMD), offset 0x004 ......................................................................... 145 November 30, 2007 Preliminary 13 Table of Contents Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: Register 17: Register 18: Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: Register 17: Register 18: Register 19: Register 20: Register 21: Register 22: Register 23: Register 24: Register 25: Register 26: Register 27: Register 28: Register 29: Register 30: Register 31: Flash Memory Control (FMC), offset 0x008 ..................................................................... Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C ............................................ Flash Controller Interrupt Mask (FCIM), offset 0x010 ........................................................ Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014 ..................... USec Reload (USECRL), offset 0x140 ............................................................................ Flash Memory Protection Read Enable 0 (FMPRE0), offset 0x130 and 0x200 ................... Flash Memory Protection Program Enable 0 (FMPPE0), offset 0x134 and 0x400 ............... User Debug (USER_DBG), offset 0x1D0 ......................................................................... User Register 0 (USER_REG0), offset 0x1E0 .................................................................. User Register 1 (USER_REG1), offset 0x1E4 .................................................................. Flash Memory Protection Read Enable 1 (FMPRE1), offset 0x204 .................................... Flash Memory Protection Read Enable 2 (FMPRE2), offset 0x208 .................................... Flash Memory Protection Read Enable 3 (FMPRE3), offset 0x20C ................................... Flash Memory Protection Program Enable 1 (FMPPE1), offset 0x404 ............................... Flash Memory Protection Program Enable 2 (FMPPE2), offset 0x408 ............................... Flash Memory Protection Program Enable 3 (FMPPE3), offset 0x40C ............................... 146 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 General-Purpose Input/Outputs (GPIOs) ................................................................................... 163 GPIO Data (GPIODATA), offset 0x000 ............................................................................ 170 GPIO Direction (GPIODIR), offset 0x400 ......................................................................... 171 GPIO Interrupt Sense (GPIOIS), offset 0x404 .................................................................. 172 GPIO Interrupt Both Edges (GPIOIBE), offset 0x408 ........................................................ 173 GPIO Interrupt Event (GPIOIEV), offset 0x40C ................................................................ 174 GPIO Interrupt Mask (GPIOIM), offset 0x410 ................................................................... 175 GPIO Raw Interrupt Status (GPIORIS), offset 0x414 ........................................................ 176 GPIO Masked Interrupt Status (GPIOMIS), offset 0x418 ................................................... 177 GPIO Interrupt Clear (GPIOICR), offset 0x41C ................................................................ 178 GPIO Alternate Function Select (GPIOAFSEL), offset 0x420 ............................................ 179 GPIO 2-mA Drive Select (GPIODR2R), offset 0x500 ........................................................ 181 GPIO 4-mA Drive Select (GPIODR4R), offset 0x504 ........................................................ 182 GPIO 8-mA Drive Select (GPIODR8R), offset 0x508 ........................................................ 183 GPIO Open Drain Select (GPIOODR), offset 0x50C ......................................................... 184 GPIO Pull-Up Select (GPIOPUR), offset 0x510 ................................................................ 185 GPIO Pull-Down Select (GPIOPDR), offset 0x514 ........................................................... 186 GPIO Slew Rate Control Select (GPIOSLR), offset 0x518 ................................................ 187 GPIO Digital Enable (GPIODEN), offset 0x51C ................................................................ 188 GPIO Lock (GPIOLOCK), offset 0x520 ............................................................................ 189 GPIO Commit (GPIOCR), offset 0x524 ............................................................................ 190 GPIO Peripheral Identification 4 (GPIOPeriphID4), offset 0xFD0 ....................................... 192 GPIO Peripheral Identification 5 (GPIOPeriphID5), offset 0xFD4 ....................................... 193 GPIO Peripheral Identification 6 (GPIOPeriphID6), offset 0xFD8 ....................................... 194 GPIO Peripheral Identification 7 (GPIOPeriphID7), offset 0xFDC ...................................... 195 GPIO Peripheral Identification 0 (GPIOPeriphID0), offset 0xFE0 ....................................... 196 GPIO Peripheral Identification 1 (GPIOPeriphID1), offset 0xFE4 ....................................... 197 GPIO Peripheral Identification 2 (GPIOPeriphID2), offset 0xFE8 ....................................... 198 GPIO Peripheral Identification 3 (GPIOPeriphID3), offset 0xFEC ...................................... 199 GPIO PrimeCell Identification 0 (GPIOPCellID0), offset 0xFF0 .......................................... 200 GPIO PrimeCell Identification 1 (GPIOPCellID1), offset 0xFF4 .......................................... 201 GPIO PrimeCell Identification 2 (GPIOPCellID2), offset 0xFF8 .......................................... 202 14 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 32: Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: Register 17: Register 18: Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: Register 17: Register 18: Register 19: Register 20: Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: GPIO PrimeCell Identification 3 (GPIOPCellID3), offset 0xFFC ......................................... 203 GPTM Configuration (GPTMCFG), offset 0x000 .............................................................. GPTM TimerA Mode (GPTMTAMR), offset 0x004 ............................................................ GPTM TimerB Mode (GPTMTBMR), offset 0x008 ............................................................ GPTM Control (GPTMCTL), offset 0x00C ........................................................................ GPTM Interrupt Mask (GPTMIMR), offset 0x018 .............................................................. GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C ..................................................... GPTM Masked Interrupt Status (GPTMMIS), offset 0x020 ................................................ GPTM Interrupt Clear (GPTMICR), offset 0x024 .............................................................. GPTM TimerA Interval Load (GPTMTAILR), offset 0x028 ................................................. GPTM TimerB Interval Load (GPTMTBILR), offset 0x02C ................................................ GPTM TimerA Match (GPTMTAMATCHR), offset 0x030 ................................................... GPTM TimerB Match (GPTMTBMATCHR), offset 0x034 .................................................. GPTM TimerA Prescale (GPTMTAPR), offset 0x038 ........................................................ GPTM TimerB Prescale (GPTMTBPR), offset 0x03C ....................................................... GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040 ........................................... GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044 ........................................... GPTM TimerA (GPTMTAR), offset 0x048 ........................................................................ GPTM TimerB (GPTMTBR), offset 0x04C ....................................................................... Watchdog Load (WDTLOAD), offset 0x000 ...................................................................... Watchdog Value (WDTVALUE), offset 0x004 ................................................................... Watchdog Control (WDTCTL), offset 0x008 ..................................................................... Watchdog Interrupt Clear (WDTICR), offset 0x00C .......................................................... Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 .................................................. Watchdog Masked Interrupt Status (WDTMIS), offset 0x014 ............................................. Watchdog Test (WDTTEST), offset 0x418 ....................................................................... Watchdog Lock (WDTLOCK), offset 0xC00 ..................................................................... Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0 ................................. Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4 ................................. Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8 ................................. Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC ................................ Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 ................................. Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 ................................. Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 ................................. Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC ................................. Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0 .................................... Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4 .................................... Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8 .................................... Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC .................................. 216 217 219 221 224 226 227 228 230 231 232 233 234 235 236 237 238 239 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 General-Purpose Timers ............................................................................................................. 204 Watchdog Timer ........................................................................................................................... 240 Analog-to-Digital Converter (ADC) ............................................................................................. 263 ADC Active Sample Sequencer (ADCACTSS), offset 0x000 ............................................. 270 ADC Raw Interrupt Status (ADCRIS), offset 0x004 ........................................................... 271 ADC Interrupt Mask (ADCIM), offset 0x008 ..................................................................... 272 ADC Interrupt Status and Clear (ADCISC), offset 0x00C .................................................. 273 ADC Overflow Status (ADCOSTAT), offset 0x010 ............................................................ 274 ADC Event Multiplexer Select (ADCEMUX), offset 0x014 ................................................. 275 November 30, 2007 Preliminary 15 Table of Contents Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: Register 17: Register 18: Register 19: Register 20: Register 21: Register 22: Register 23: Register 24: Register 25: Register 26: Register 27: Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: Register 17: Register 18: Register 19: Register 20: Register 21: Register 22: Register 23: Register 24: Register 25: ADC Underflow Status (ADCUSTAT), offset 0x018 ........................................................... ADC Sample Sequencer Priority (ADCSSPRI), offset 0x020 ............................................. ADC Processor Sample Sequence Initiate (ADCPSSI), offset 0x028 ................................. ADC Sample Averaging Control (ADCSAC), offset 0x030 ................................................. ADC Sample Sequence Input Multiplexer Select 0 (ADCSSMUX0), offset 0x040 ............... ADC Sample Sequence Control 0 (ADCSSCTL0), offset 0x044 ........................................ ADC Sample Sequence Result FIFO 0 (ADCSSFIFO0), offset 0x048 ................................ ADC Sample Sequence Result FIFO 1 (ADCSSFIFO1), offset 0x068 ................................ ADC Sample Sequence Result FIFO 2 (ADCSSFIFO2), offset 0x088 ................................ ADC Sample Sequence Result FIFO 3 (ADCSSFIFO3), offset 0x0A8 ............................... ADC Sample Sequence FIFO 0 Status (ADCSSFSTAT0), offset 0x04C ............................. ADC Sample Sequence FIFO 1 Status (ADCSSFSTAT1), offset 0x06C ............................. ADC Sample Sequence FIFO 2 Status (ADCSSFSTAT2), offset 0x08C ............................ ADC Sample Sequence FIFO 3 Status (ADCSSFSTAT3), offset 0x0AC ............................ ADC Sample Sequence Input Multiplexer Select 1 (ADCSSMUX1), offset 0x060 ............... ADC Sample Sequence Input Multiplexer Select 2 (ADCSSMUX2), offset 0x080 ............... ADC Sample Sequence Control 1 (ADCSSCTL1), offset 0x064 ........................................ ADC Sample Sequence Control 2 (ADCSSCTL2), offset 0x084 ........................................ ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3), offset 0x0A0 ............... ADC Sample Sequence Control 3 (ADCSSCTL3), offset 0x0A4 ........................................ ADC Test Mode Loopback (ADCTMLB), offset 0x100 ....................................................... UART Data (UARTDR), offset 0x000 ............................................................................... UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 ........................... UART Flag (UARTFR), offset 0x018 ................................................................................ UART IrDA Low-Power Register (UARTILPR), offset 0x020 ............................................. UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 ............................................ UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 ....................................... UART Line Control (UARTLCRH), offset 0x02C ............................................................... UART Control (UARTCTL), offset 0x030 ......................................................................... UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 ........................................... UART Interrupt Mask (UARTIM), offset 0x038 ................................................................. UART Raw Interrupt Status (UARTRIS), offset 0x03C ...................................................... UART Masked Interrupt Status (UARTMIS), offset 0x040 ................................................. UART Interrupt Clear (UARTICR), offset 0x044 ............................................................... UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 ..................................... UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 ..................................... UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 ..................................... UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC ..................................... UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 ...................................... UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 ...................................... UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 ...................................... UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC ..................................... UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 ........................................ UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 ........................................ UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 ........................................ UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ........................................ 278 279 280 281 282 284 287 287 287 287 288 288 288 288 289 289 290 290 292 293 294 304 306 308 310 311 312 313 315 317 319 321 322 323 325 326 327 328 329 330 331 332 333 334 335 336 Universal Asynchronous Receivers/Transmitters (UARTs) ..................................................... 296 16 Preliminary November 30, 2007 LM3S6965 Microcontroller Synchronous Serial Interface (SSI) ............................................................................................ 337 Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: Register 17: Register 18: Register 19: Register 20: Register 21: Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: SSI Control 0 (SSICR0), offset 0x000 .............................................................................. SSI Control 1 (SSICR1), offset 0x004 .............................................................................. SSI Data (SSIDR), offset 0x008 ...................................................................................... SSI Status (SSISR), offset 0x00C ................................................................................... SSI Clock Prescale (SSICPSR), offset 0x010 .................................................................. SSI Interrupt Mask (SSIIM), offset 0x014 ......................................................................... SSI Raw Interrupt Status (SSIRIS), offset 0x018 .............................................................. SSI Masked Interrupt Status (SSIMIS), offset 0x01C ........................................................ SSI Interrupt Clear (SSIICR), offset 0x020 ....................................................................... SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 ............................................. SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 ............................................. SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 ............................................. SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ............................................ SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 ............................................. SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 ............................................. SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 ............................................. SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ............................................ SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 ............................................... SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 ............................................... SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 ............................................... SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC ............................................... I2C Master Slave Address (I2CMSA), offset 0x000 ........................................................... I2C Master Control/Status (I2CMCS), offset 0x004 ........................................................... I2C Master Data (I2CMDR), offset 0x008 ......................................................................... I2C Master Timer Period (I2CMTPR), offset 0x00C ........................................................... I2C Master Interrupt Mask (I2CMIMR), offset 0x010 ......................................................... I2C Master Raw Interrupt Status (I2CMRIS), offset 0x014 ................................................. I2C Master Masked Interrupt Status (I2CMMIS), offset 0x018 ........................................... I2C Master Interrupt Clear (I2CMICR), offset 0x01C ......................................................... I2C Master Configuration (I2CMCR), offset 0x020 ............................................................ I2C Slave Own Address (I2CSOAR), offset 0x000 ............................................................ I2C Slave Control/Status (I2CSCSR), offset 0x004 ........................................................... I2C Slave Data (I2CSDR), offset 0x008 ........................................................................... I2C Slave Interrupt Mask (I2CSIMR), offset 0x00C ........................................................... I2C Slave Raw Interrupt Status (I2CSRIS), offset 0x010 ................................................... I2C Slave Masked Interrupt Status (I2CSMIS), offset 0x014 .............................................. I2C Slave Interrupt Clear (I2CSICR), offset 0x018 ............................................................ Ethernet MAC Raw Interrupt Status (MACRIS), offset 0x000 ............................................ Ethernet MAC Interrupt Acknowledge (MACIACK), offset 0x000 ....................................... Ethernet MAC Interrupt Mask (MACIM), offset 0x004 ....................................................... Ethernet MAC Receive Control (MACRCTL), offset 0x008 ................................................ Ethernet MAC Transmit Control (MACTCTL), offset 0x00C ............................................... Ethernet MAC Data (MACDATA), offset 0x010 ................................................................. Ethernet MAC Individual Address 0 (MACIA0), offset 0x014 ............................................. 349 351 353 354 356 357 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 388 389 393 394 395 396 397 398 399 401 402 404 405 406 407 408 418 420 421 422 423 424 426 Inter-Integrated Circuit (I2C) Interface ........................................................................................ 374 Ethernet Controller ...................................................................................................................... 409 November 30, 2007 Preliminary 17 Table of Contents Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: Register 17: Register 18: Register 19: Register 20: Register 21: Register 22: Register 23: Register 24: Register 25: Register 26: Register 27: Register 28: Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Ethernet MAC Individual Address 1 (MACIA1), offset 0x018 ............................................. Ethernet MAC Threshold (MACTHR), offset 0x01C .......................................................... Ethernet MAC Management Control (MACMCTL), offset 0x020 ........................................ Ethernet MAC Management Divider (MACMDV), offset 0x024 .......................................... Ethernet MAC Management Transmit Data (MACMTXD), offset 0x02C ............................. Ethernet MAC Management Receive Data (MACMRXD), offset 0x030 .............................. Ethernet MAC Number of Packets (MACNP), offset 0x034 ............................................... Ethernet MAC Transmission Request (MACTR), offset 0x038 ........................................... Ethernet PHY Management Register 0 – Control (MR0), address 0x00 ............................. Ethernet PHY Management Register 1 – Status (MR1), address 0x01 .............................. Ethernet PHY Management Register 2 – PHY Identifier 1 (MR2), address 0x02 ................. Ethernet PHY Management Register 3 – PHY Identifier 2 (MR3), address 0x03 ................. Ethernet PHY Management Register 4 – Auto-Negotiation Advertisement (MR4), address 0x04 ............................................................................................................................. Ethernet PHY Management Register 5 – Auto-Negotiation Link Partner Base Page Ability (MR5), address 0x05 ..................................................................................................... Ethernet PHY Management Register 6 – Auto-Negotiation Expansion (MR6), address 0x06 ............................................................................................................................. Ethernet PHY Management Register 16 – Vendor-Specific (MR16), address 0x10 ............. Ethernet PHY Management Register 17 – Interrupt Control/Status (MR17), address 0x11 .............................................................................................................................. Ethernet PHY Management Register 18 – Diagnostic (MR18), address 0x12 ..................... Ethernet PHY Management Register 19 – Transceiver Control (MR19), address 0x13 ....... Ethernet PHY Management Register 23 – LED Configuration (MR23), address 0x17 ......... Ethernet PHY Management Register 24 –MDI/MDIX Control (MR24), address 0x18 .......... Analog Comparator Masked Interrupt Status (ACMIS), offset 0x00 .................................... Analog Comparator Raw Interrupt Status (ACRIS), offset 0x04 ......................................... Analog Comparator Interrupt Enable (ACINTEN), offset 0x08 ........................................... Analog Comparator Reference Voltage Control (ACREFCTL), offset 0x10 ......................... Analog Comparator Status 0 (ACSTAT0), offset 0x20 ....................................................... Analog Comparator Status 1 (ACSTAT1), offset 0x40 ....................................................... Analog Comparator Control 0 (ACCTL0), offset 0x24 ....................................................... Analog Comparator Control 1 (ACCTL1), offset 0x44 ....................................................... 427 428 429 430 431 432 433 434 435 437 439 440 441 443 444 445 447 449 450 451 452 458 459 460 461 462 462 463 463 Analog Comparators ................................................................................................................... 453 Pulse Width Modulator (PWM) .................................................................................................... 465 PWM Master Control (PWMCTL), offset 0x000 ................................................................ 473 PWM Time Base Sync (PWMSYNC), offset 0x004 ........................................................... 474 PWM Output Enable (PWMENABLE), offset 0x008 .......................................................... 475 PWM Output Inversion (PWMINVERT), offset 0x00C ....................................................... 476 PWM Output Fault (PWMFAULT), offset 0x010 ................................................................ 477 PWM Interrupt Enable (PWMINTEN), offset 0x014 ........................................................... 478 PWM Raw Interrupt Status (PWMRIS), offset 0x018 ........................................................ 479 PWM Interrupt Status and Clear (PWMISC), offset 0x01C ................................................ 480 PWM Status (PWMSTATUS), offset 0x020 ...................................................................... 481 PWM0 Control (PWM0CTL), offset 0x040 ....................................................................... 482 PWM1 Control (PWM1CTL), offset 0x080 ....................................................................... 482 PWM2 Control (PWM2CTL), offset 0x0C0 ...................................................................... 482 PWM0 Interrupt and Trigger Enable (PWM0INTEN), offset 0x044 .................................... 484 18 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 14: Register 15: Register 16: Register 17: Register 18: Register 19: Register 20: Register 21: Register 22: Register 23: Register 24: Register 25: Register 26: Register 27: Register 28: Register 29: Register 30: Register 31: Register 32: Register 33: Register 34: Register 35: Register 36: Register 37: Register 38: Register 39: Register 40: Register 41: Register 42: Register 43: Register 44: Register 45: Register 46: Register 47: Register 48: Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: PWM1 Interrupt and Trigger Enable (PWM1INTEN), offset 0x084 .................................... 484 PWM2 Interrupt and Trigger Enable (PWM2INTEN), offset 0x0C4 .................................... 484 PWM0 Raw Interrupt Status (PWM0RIS), offset 0x048 .................................................... 486 PWM1 Raw Interrupt Status (PWM1RIS), offset 0x088 .................................................... 486 PWM2 Raw Interrupt Status (PWM2RIS), offset 0x0C8 ................................................... 486 PWM0 Interrupt Status and Clear (PWM0ISC), offset 0x04C ........................................... 487 PWM1 Interrupt Status and Clear (PWM1ISC), offset 0x08C ........................................... 487 PWM2 Interrupt Status and Clear (PWM2ISC), offset 0x0CC ........................................... 487 PWM0 Load (PWM0LOAD), offset 0x050 ....................................................................... 488 PWM1 Load (PWM1LOAD), offset 0x090 ....................................................................... 488 PWM2 Load (PWM2LOAD), offset 0x0D0 ....................................................................... 488 PWM0 Counter (PWM0COUNT), offset 0x054 ................................................................ 489 PWM1 Counter (PWM1COUNT), offset 0x094 ................................................................ 489 PWM2 Counter (PWM2COUNT), offset 0x0D4 ............................................................... 489 PWM0 Compare A (PWM0CMPA), offset 0x058 ............................................................. 490 PWM1 Compare A (PWM1CMPA), offset 0x098 ............................................................. 490 PWM2 Compare A (PWM2CMPA), offset 0x0D8 ............................................................. 490 PWM0 Compare B (PWM0CMPB), offset 0x05C ............................................................. 491 PWM1 Compare B (PWM1CMPB), offset 0x09C ............................................................. 491 PWM2 Compare B (PWM2CMPB), offset 0x0DC ............................................................ 491 PWM0 Generator A Control (PWM0GENA), offset 0x060 ................................................ 492 PWM1 Generator A Control (PWM1GENA), offset 0x0A0 ................................................ 492 PWM2 Generator A Control (PWM2GENA), offset 0x0E0 ................................................ 492 PWM0 Generator B Control (PWM0GENB), offset 0x064 ................................................ 495 PWM1 Generator B Control (PWM1GENB), offset 0x0A4 ................................................ 495 PWM2 Generator B Control (PWM2GENB), offset 0x0E4 ................................................ 495 PWM0 Dead-Band Control (PWM0DBCTL), offset 0x068 ................................................ 498 PWM1 Dead-Band Control (PWM1DBCTL), offset 0x0A8 ................................................. 498 PWM2 Dead-Band Control (PWM2DBCTL), offset 0x0E8 ................................................ 498 PWM0 Dead-Band Rising-Edge Delay (PWM0DBRISE), offset 0x06C ............................. 499 PWM1 Dead-Band Rising-Edge Delay (PWM1DBRISE), offset 0x0AC ............................. 499 PWM2 Dead-Band Rising-Edge Delay (PWM2DBRISE), offset 0x0EC ............................. 499 PWM0 Dead-Band Falling-Edge-Delay (PWM0DBFALL), offset 0x070 ............................. 500 PWM1 Dead-Band Falling-Edge-Delay (PWM1DBFALL), offset 0x0B0 ............................. 500 PWM2 Dead-Band Falling-Edge-Delay (PWM2DBFALL), offset 0x0F0 ............................. 500 QEI Control (QEICTL), offset 0x000 ................................................................................ QEI Status (QEISTAT), offset 0x004 ................................................................................ QEI Position (QEIPOS), offset 0x008 .............................................................................. QEI Maximum Position (QEIMAXPOS), offset 0x00C ....................................................... QEI Timer Load (QEILOAD), offset 0x010 ....................................................................... QEI Timer (QEITIME), offset 0x014 ................................................................................. QEI Velocity Counter (QEICOUNT), offset 0x018 ............................................................. QEI Velocity (QEISPEED), offset 0x01C .......................................................................... QEI Interrupt Enable (QEIINTEN), offset 0x020 ............................................................... QEI Raw Interrupt Status (QEIRIS), offset 0x024 ............................................................. QEI Interrupt Status and Clear (QEIISC), offset 0x028 ..................................................... 506 508 509 510 511 512 513 514 515 516 517 Quadrature Encoder Interface (QEI) .......................................................................................... 501 November 30, 2007 Preliminary 19 About This Document About This Document This data sheet provides reference information for the LM3S6965 microcontroller, describing the functional blocks of the system-on-chip (SoC) device designed around the ARM® Cortex™-M3 core. Audience This manual is intended for system software developers, hardware designers, and application developers. About This Manual This document is organized into sections that correspond to each major feature. Related Documents The following documents are referenced by the data sheet, and available on the documentation CD or from the Luminary Micro web site at www.luminarymicro.com: ■ ARM® Cortex™-M3 Technical Reference Manual ■ ARM® CoreSight Technical Reference Manual ■ ARM® v7-M Architecture Application Level Reference Manual The following related documents are also referenced: ■ IEEE Standard 1149.1-Test Access Port and Boundary-Scan Architecture This documentation list was current as of publication date. Please check the Luminary Micro web site for additional documentation, including application notes and white papers. Documentation Conventions This document uses the conventions shown in Table 1 on page 20. Table 1. Documentation Conventions Notation Meaning General Register Notation REGISTER APB registers are indicated in uppercase bold. For example, PBORCTL is the Power-On and Brown-Out Reset Control register. If a register name contains a lowercase n, it represents more than one register. For example, SRCRn represents any (or all) of the three Software Reset Control registers: SRCR0, SRCR1 , and SRCR2. A single bit in a register. Two or more consecutive and related bits. A hexadecimal increment to a register's address, relative to that module's base address as specified in “Memory Map” on page 43. Registers are numbered consecutively throughout the document to aid in referencing them. The register number has no meaning to software. bit bit field offset 0xnnn Register N 20 Preliminary November 30, 2007 LM3S6965 Microcontroller Notation reserved Meaning Register bits marked reserved are reserved for future use. In most cases, reserved bits are set to 0; however, user software should not rely on the value of a reserved bit. To provide software compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. The range of register bits inclusive from xx to yy. For example, 31:15 means bits 15 through 31 in that register. This value in the register bit diagram indicates whether software running on the controller can change the value of the bit field. Software can read this field. The bit or field is cleared by hardware after reading the bit/field. Software can read this field. Always write the chip reset value. Software can read or write this field. Software can read or write this field. A write of a 0 to a W1C bit does not affect the bit value in the register. A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged. This register type is primarily used for clearing interrupt status bits where the read operation provides the interrupt status and the write of the read value clears only the interrupts being reported at the time the register was read. yy:xx Register Bit/Field Types RC RO R/W R/W1C W1C Software can write this field. A write of a 0 to a W1C bit does not affect the bit value in the register. A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged. A read of the register returns no meaningful data. This register is typically used to clear the corresponding bit in an interrupt register. WO Register Bit/Field Reset Value 0 1 Pin/Signal Notation [] pin signal assert a signal Only a write by software is valid; a read of the register returns no meaningful data. This value in the register bit diagram shows the bit/field value after any reset, unless noted. Bit cleared to 0 on chip reset. Bit set to 1 on chip reset. Nondeterministic. Pin alternate function; a pin defaults to the signal without the brackets. Refers to the physical connection on the package. Refers to the electrical signal encoding of a pin. Change the value of the signal from the logically False state to the logically True state. For active High signals, the asserted signal value is 1 (High); for active Low signals, the asserted signal value is 0 (Low). The active polarity (High or Low) is defined by the signal name (see SIGNAL and SIGNAL below). Change the value of the signal from the logically True state to the logically False state. Signal names are in uppercase and in the Courier font. An overbar on a signal name indicates that it is active Low. To assert SIGNAL is to drive it Low; to deassert SIGNAL is to drive it High. Signal names are in uppercase and in the Courier font. An active High signal has no overbar. To assert SIGNAL is to drive it High; to deassert SIGNAL is to drive it Low. deassert a signal SIGNAL SIGNAL Numbers X An uppercase X indicates any of several values is allowed, where X can be any legal pattern. For example, a binary value of 0X00 can be either 0100 or 0000, a hex value of 0xX is 0x0 or 0x1, and so on. Hexadecimal numbers have a prefix of 0x. For example, 0x00FF is the hexadecimal number FF. All other numbers within register tables are assumed to be binary. Within conceptual information, binary numbers are indicated with a b suffix, for example, 1011b, and decimal numbers are written without a prefix or suffix. 0x November 30, 2007 Preliminary 21 Architectural Overview 1 Architectural Overview The Luminary Micro Stellaris family of microcontrollers—the first ARM® Cortex™-M3 based controllers—brings high-performance 32-bit computing to cost-sensitive embedded microcontroller applications. These pioneering parts deliver customers 32-bit performance at a cost equivalent to legacy 8- and 16-bit devices, all in a package with a small footprint. The Stellaris family offers efficient performance and extensive integration, favorably positioning the device into cost-conscious applications requiring significant control-processing and connectivity ® ® capabilities. The Stellaris LM3S1000 series extends the Stellaris family with larger on-chip ® memories, enhanced power management, and expanded I/O and control capabilities. The Stellaris LM3S2000 series, designed for Controller Area Network (CAN) applications, extends the Stellaris family with Bosch CAN networking technology, the golden standard in short-haul industrial networks. ® The Stellaris LM3S2000 series also marks the first integration of CAN capabilities with the ® revolutionary Cortex-M3 core. The Stellaris LM3S6000 series combines both a 10/100 Ethernet Media Access Control (MAC) and Physical (PHY) layer, marking the first time that integrated connectivity is available with an ARM Cortex-M3 MCU and the only integrated 10/100 Ethernet MAC ® and PHY available in an ARM architecture MCU. The Stellaris LM3S8000 series combines Bosch Controller Area Network technology with both a 10/100 Ethernet Media Access Control (MAC) and Physical (PHY) layer. The LM3S6965 microcontroller is targeted for industrial applications, including remote monitoring, electronic point-of-sale machines, test and measurement equipment, network appliances and switches, factory automation, HVAC and building control, gaming equipment, motion control, medical instrumentation, and fire and security. For applications requiring extreme conservation of power, the LM3S6965 microcontroller features a Battery-backed Hibernation module to efficiently power down the LM3S6965 to a low-power state during extended periods of inactivity. With a power-up/power-down sequencer, a continuous time counter (RTC), a pair of match registers, an APB interface to the system bus, and dedicated non-volatile memory, the Hibernation module positions the LM3S6965 microcontroller perfectly for battery applications. In addition, the LM3S6965 microcontroller offers the advantages of ARM's widely available development tools, System-on-Chip (SoC) infrastructure IP applications, and a large user community. Additionally, the microcontroller uses ARM's Thumb®-compatible Thumb-2 instruction set to reduce memory requirements and, thereby, cost. Finally, the LM3S6965 microcontroller is code-compatible ® to all members of the extensive Stellaris family; providing flexibility to fit our customers' precise needs. Luminary Micro offers a complete solution to get to market quickly, with evaluation and development boards, white papers and application notes, an easy-to-use peripheral driver library, and a strong support, sales, and distributor network. ® ® 1.1 Product Features The LM3S6965 microcontroller includes the following product features: ■ 32-Bit RISC Performance – 32-bit ARM® Cortex™-M3 v7M architecture optimized for small-footprint embedded applications 22 Preliminary November 30, 2007 LM3S6965 Microcontroller – System timer (SysTick), providing a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism – Thumb®-compatible Thumb-2-only instruction set processor core for high code density – 50-MHz operation – Hardware-division and single-cycle-multiplication – Integrated Nested Vectored Interrupt Controller (NVIC) providing deterministic interrupt handling – 38 interrupts with eight priority levels – Memory protection unit (MPU), providing a privileged mode for protected operating system functionality – Unaligned data access, enabling data to be efficiently packed into memory – Atomic bit manipulation (bit-banding), delivering maximum memory utilization and streamlined peripheral control ■ Internal Memory – 256 KB single-cycle flash • • • User-managed flash block protection on a 2-KB block basis User-managed flash data programming User-defined and managed flash-protection block – 64 KB single-cycle SRAM ■ General-Purpose Timers – Four General-Purpose Timer Modules (GPTM), each of which provides two 16-bit timers. Each GPTM can be configured to operate independently: • • • • As a single 32-bit timer As one 32-bit Real-Time Clock (RTC) to event capture For Pulse Width Modulation (PWM) To trigger analog-to-digital conversions – 32-bit Timer modes • • • Programmable one-shot timer Programmable periodic timer Real-Time Clock when using an external 32.768-KHz clock as the input November 30, 2007 Preliminary 23 Architectural Overview • • User-enabled stalling in periodic and one-shot mode when the controller asserts the CPU Halt flag during debug ADC event trigger – 16-bit Timer modes • • • • • General-purpose timer function with an 8-bit prescaler Programmable one-shot timer Programmable periodic timer User-enabled stalling when the controller asserts CPU Halt flag during debug ADC event trigger – 16-bit Input Capture modes • • Input edge count capture Input edge time capture – 16-bit PWM mode • Simple PWM mode with software-programmable output inversion of the PWM signal ■ ARM FiRM-compliant Watchdog Timer – 32-bit down counter with a programmable load register – Separate watchdog clock with an enable – Programmable interrupt generation logic with interrupt masking – Lock register protection from runaway software – Reset generation logic with an enable/disable – User-enabled stalling when the controller asserts the CPU Halt flag during debug ■ 10/100 Ethernet Controller – Conforms to the IEEE 802.3-2002 Specification – Full- and half-duplex for both 100 Mbps and 10 Mbps operation – Integrated 10/100 Mbps Transceiver (PHY) – Automatic MDI/MDI-X cross-over correction – Programmable MAC address – Power-saving and power-down modes ■ Synchronous Serial Interface (SSI) 24 Preliminary November 30, 2007 LM3S6965 Microcontroller – Master or slave operation – Programmable clock bit rate and prescale – Separate transmit and receive FIFOs, 16 bits wide, 8 locations deep – Programmable interface operation for Freescale SPI, MICROWIRE, or Texas Instruments synchronous serial interfaces – Programmable data frame size from 4 to 16 bits – Internal loopback test mode for diagnostic/debug testing ■ UART – Three fully programmable 16C550-type UARTs with IrDA support – Separate 16x8 transmit (TX) and 16x12 receive (RX) FIFOs to reduce CPU interrupt service loading – Programmable baud-rate generator with fractional divider – Programmable FIFO length, including 1-byte deep operation providing conventional double-buffered interface – FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8 – Standard asynchronous communication bits for start, stop, and parity – False-start-bit detection – Line-break generation and detection ■ ADC – Single- and differential-input configurations – Four 10-bit channels (inputs) when used as single-ended inputs – Sample rate of one million samples/second – Flexible, configurable analog-to-digital conversion – Four programmable sample conversion sequences from one to eight entries long, with corresponding conversion result FIFOs – Each sequence triggered by software or internal event (timers, analog comparators, PWM or GPIO) – On-chip temperature sensor ■ Analog Comparators – Two independent integrated analog comparators November 30, 2007 Preliminary 25 Architectural Overview – Configurable for output to: drive an output pin, generate an interrupt, or initiate an ADC sample sequence – Compare external pin input to external pin input or to internal programmable voltage reference ■ I2C – Two I C modules – Master and slave receive and transmit operation with transmission speed up to 100 Kbps in Standard mode and 400 Kbps in Fast mode – Interrupt generation – Master with arbitration and clock synchronization, multimaster support, and 7-bit addressing mode ■ PWM – Three PWM generator blocks, each with one 16-bit counter, two comparators, a PWM generator, and a dead-band generator – One 16-bit counter • • • • Runs in Down or Up/Down mode Output frequency controlled by a 16-bit load value Load value updates can be synchronized Produces output signals at zero and load value 2 – Two PWM comparators • • Comparator value updates can be synchronized Produces output signals on match – PWM generator • • Output PWM signal is constructed based on actions taken as a result of the counter and PWM comparator output signals Produces two independent PWM signals – Dead-band generator • • Produces two PWM signals with programmable dead-band delays suitable for driving a half-H bridge Can be bypassed, leaving input PWM signals unmodified – Flexible output control block with PWM output enable of each PWM signal • PWM output enable of each PWM signal 26 Preliminary November 30, 2007 LM3S6965 Microcontroller • • • • • Optional output inversion of each PWM signal (polarity control) Optional fault handling for each PWM signal Synchronization of timers in the PWM generator blocks Synchronization of timer/comparator updates across the PWM generator blocks Interrupt status summary of the PWM generator blocks – Can initiate an ADC sample sequence ■ QEI – Two QEI modules – Hardware position integrator tracks the encoder position – Velocity capture using built-in timer – Interrupt generation on index pulse, velocity-timer expiration, direction change, and quadrature error detection ■ GPIOs – 0-42 GPIOs, depending on configuration – 5-V-tolerant input/outputs – Programmable interrupt generation as either edge-triggered or level-sensitive – Bit masking in both read and write operations through address lines – Can initiate an ADC sample sequence – Programmable control for GPIO pad configuration: • • • • • ■ Power – On-chip Low Drop-Out (LDO) voltage regulator, with programmable output user-adjustable from 2.25 V to 2.75 V – Hibernation module handles the power-up/down 3.3 V sequencing and control for the core digital logic and analog circuits – Low-power options on controller: Sleep and Deep-sleep modes Weak pull-up or pull-down resistors 2-mA, 4-mA, and 8-mA pad drive Slew rate control for the 8-mA drive Open drain enables Digital input enables November 30, 2007 Preliminary 27 Architectural Overview – Low-power options for peripherals: software controls shutdown of individual peripherals – User-enabled LDO unregulated voltage detection and automatic reset – 3.3-V supply brown-out detection and reporting via interrupt or reset ■ Flexible Reset Sources – Power-on reset (POR) – Reset pin assertion – Brown-out (BOR) detector alerts to system power drops – Software reset – Watchdog timer reset – Internal low drop-out (LDO) regulator output goes unregulated ■ Additional Features – Six reset sources – Programmable clock source control – Clock gating to individual peripherals for power savings – IEEE 1149.1-1990 compliant Test Access Port (TAP) controller – Debug access via JTAG and Serial Wire interfaces – Full JTAG boundary scan ■ Industrial-range 100-pin RoHS-compliant LQFP package 1.2 Target Applications ■ Remote monitoring ■ Electronic point-of-sale (POS) machines ■ Test and measurement equipment ■ Network appliances and switches ■ Factory automation ■ HVAC and building control ■ Gaming equipment ■ Motion control ■ Medical instrumentation ■ Fire and security 28 Preliminary November 30, 2007 LM3S6965 Microcontroller ■ Power and energy ■ Transportation 1.3 High-Level Block Diagram Figure 1-1 on page 29 represents the full set of features in the Stellaris 6000 series of devices; not all features may be available on the LM3S6965 microcontroller. Figure 1-1. Stellaris 6000 Series High-Level Block Diagram ® ® November 30, 2007 Preliminary 29 Architectural Overview 1.4 Functional Overview The following sections provide an overview of the features of the LM3S6965 microcontroller. The page number in parenthesis indicates where that feature is discussed in detail. Ordering and support information can be found in “Ordering and Contact Information” on page 577. 1.4.1 1.4.1.1 ARM Cortex™-M3 Processor Core (see page 37) All members of the Stellaris product family, including the LM3S6965 microcontroller, are designed around an ARM Cortex™-M3 processor core. The ARM Cortex-M3 processor provides the core for a high-performance, low-cost platform that meets the needs of minimal memory implementation, reduced pin count, and low-power consumption, while delivering outstanding computational performance and exceptional system response to interrupts. “ARM Cortex-M3 Processor Core” on page 37 provides an overview of the ARM core; the core is detailed in the ARM® Cortex™-M3 Technical Reference Manual. ® 1.4.1.2 System Timer (SysTick) Cortex-M3 includes an integrated system timer, SysTick. SysTick provides a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter can be used in several different ways, for example: ■ An RTOS tick timer which fires at a programmable rate (for example, 100 Hz) and invokes a SysTick routine. ■ A high-speed alarm timer using the system clock. ■ A variable rate alarm or signal timer—the duration is range-dependent on the reference clock used and the dynamic range of the counter. ■ A simple counter. Software can use this to measure time to completion and time used. ■ An internal clock source control based on missing/meeting durations. The COUNTFLAG bit-field in the control and status register can be used to determine if an action completed within a set duration, as part of a dynamic clock management control loop. 1.4.1.3 Nested Vectored Interrupt Controller (NVIC) The LM3S6965 controller includes the ARM Nested Vectored Interrupt Controller (NVIC) on the ARM Cortex-M3 core. The NVIC and Cortex-M3 prioritize and handle all exceptions. All exceptions are handled in Handler Mode. The processor state is automatically stored to the stack on an exception, and automatically restored from the stack at the end of the Interrupt Service Routine (ISR). The vector is fetched in parallel to the state saving, which enables efficient interrupt entry. The processor supports tail-chaining, which enables back-to-back interrupts to be performed without the overhead of state saving and restoration. Software can set eight priority levels on 7 exceptions (system handlers) and 38 interrupts. “Interrupts” on page 45 provides an overview of the NVIC controller and the interrupt map. Exceptions and interrupts are detailed in the ARM® Cortex™-M3 Technical Reference Manual. 1.4.2 Motor Control Peripherals To enhance motor control, the LM3S6965 controller features Pulse Width Modulation (PWM) outputs and the Quadrature Encoder Interface (QEI). 30 Preliminary November 30, 2007 LM3S6965 Microcontroller 1.4.2.1 PWM Pulse width modulation (PWM) is a powerful technique for digitally encoding analog signal levels. High-resolution counters are used to generate a square wave, and the duty cycle of the square wave is modulated to encode an analog signal. Typical applications include switching power supplies and motor control. On the LM3S6965, PWM motion control functionality can be achieved through: ■ Dedicated, flexible motion control hardware using the PWM pins ■ The motion control features of the general-purpose timers using the CCP pins PWM Pins (see page 465) The LM3S6965 PWM module consists of three PWM generator blocks and a control block. Each PWM generator block contains one timer (16-bit down or up/down counter), two comparators, a PWM signal generator, a dead-band generator, and an interrupt/ADC-trigger selector. The control block determines the polarity of the PWM signals, and which signals are passed through to the pins. Each PWM generator block produces two PWM signals that can either be independent signals or a single pair of complementary signals with dead-band delays inserted. The output of the PWM generation blocks are managed by the output control block before being passed to the device pins. CCP Pins (see page 210) The General-Purpose Timer Module's CCP (Capture Compare PWM) pins are software programmable to support a simple PWM mode with a software-programmable output inversion of the PWM signal. 1.4.2.2 QEI (see page 501) A quadrature encoder, also known as a 2-channel incremental encoder, converts linear displacement into a pulse signal. By monitoring both the number of pulses and the relative phase of the two signals, you can track the position, direction of rotation, and speed. In addition, a third channel, or index signal, can be used to reset the position counter. The Stellaris quadrature encoder with index (QEI) module interprets the code produced by a quadrature encoder wheel to integrate position over time and determine direction of rotation. In addition, it can capture a running estimate of the velocity of the encoder wheel. The LM3S6965 microcontroller includes two QEI modules, which enables control of two motors at the same time. 1.4.3 Analog Peripherals To handle analog signals, the LM3S6965 microcontroller offers an Analog-to-Digital Converter (ADC). For support of analog signals, the LM3S6965 microcontroller offers two analog comparators. 1.4.3.1 ADC (see page 263) An analog-to-digital converter (ADC) is a peripheral that converts a continuous analog voltage to a discrete digital number. The LM3S6965 ADC module features 10-bit conversion resolution and supports four input channels, plus an internal temperature sensor. Four buffered sample sequences allow rapid sampling of up to eight analog input sources without controller intervention. Each sample sequence provides flexible programming with fully configurable input source, trigger events, interrupt generation, and sequence priority. November 30, 2007 Preliminary 31 Architectural Overview 1.4.3.2 Analog Comparators (see page 453) An analog comparator is a peripheral that compares two analog voltages, and provides a logical output that signals the comparison result. The LM3S6965 microcontroller provides two independent integrated analog comparators that can be configured to drive an output or generate an interrupt or ADC event. A comparator can compare a test voltage against any one of these voltages: ■ An individual external reference voltage ■ A shared single external reference voltage ■ A shared internal reference voltage The comparator can provide its output to a device pin, acting as a replacement for an analog comparator on the board, or it can be used to signal the application via interrupts or triggers to the ADC to cause it to start capturing a sample sequence. The interrupt generation and ADC triggering logic is separate. This means, for example, that an interrupt can be generated on a rising edge and the ADC triggered on a falling edge. 1.4.4 Serial Communications Peripherals The LM3S6965 controller supports both asynchronous and synchronous serial communications with: ■ Three fully programmable 16C550-type UARTs ■ One SSI module ■ Two I2C modules ■ Ethernet controller 1.4.4.1 UART (see page 296) A Universal Asynchronous Receiver/Transmitter (UART) is an integrated circuit used for RS-232C serial communications, containing a transmitter (parallel-to-serial converter) and a receiver (serial-to-parallel converter), each clocked separately. The LM3S6965 controller includes three fully programmable 16C550-type UARTs that support data transfer speeds up to 460.8 Kbps. (Although similar in functionality to a 16C550 UART, it is not register-compatible.) In addition, each UART is capable of supporting IrDA. Separate 16x8 transmit (TX) and 16x12 receive (RX) FIFOs reduce CPU interrupt service loading. The UART can generate individually masked interrupts from the RX, TX, modem status, and error conditions. The module provides a single combined interrupt when any of the interrupts are asserted and are unmasked. 1.4.4.2 SSI (see page 337) Synchronous Serial Interface (SSI) is a four-wire bi-directional communications interface. The LM3S6965 controller includes one SSI module that provides the functionality for synchronous serial communications with peripheral devices, and can be configured to use the Freescale SPI, MICROWIRE, or TI synchronous serial interface frame formats. The size of the data frame is also configurable, and can be set between 4 and 16 bits, inclusive. 32 Preliminary November 30, 2007 LM3S6965 Microcontroller The SSI module performs serial-to-parallel conversion on data received from a peripheral device, and parallel-to-serial conversion on data transmitted to a peripheral device. The TX and RX paths are buffered with internal FIFOs, allowing up to eight 16-bit values to be stored independently. The SSI module can be configured as either a master or slave device. As a slave device, the SSI module can also be configured to disable its output, which allows a master device to be coupled with multiple slave devices. The SSI module also includes a programmable bit rate clock divider and prescaler to generate the output serial clock derived from the SSI module's input clock. Bit rates are generated based on the input clock and the maximum bit rate is determined by the connected peripheral. 1.4.4.3 I2C (see page 374) The Inter-Integrated Circuit (I2C) bus provides bi-directional data transfer through a two-wire design (a serial data line SDA and a serial clock line SCL). The I2C bus interfaces to external I2C devices such as serial memory (RAMs and ROMs), networking devices, LCDs, tone generators, and so on. The I2C bus may also be used for system testing and diagnostic purposes in product development and manufacture. The LM3S6965 controller includes two I2C modules that provide the ability to communicate to other IC devices over an I2C bus. The I2C bus supports devices that can both transmit and receive (write and read) data. Devices on the I2C bus can be designated as either a master or a slave. Each I2C module supports both sending and receiving data as either a master or a slave, and also supports the simultaneous operation as both a master and a slave. The four I2C modes are: Master Transmit, Master Receive, Slave Transmit, and Slave Receive. A Stellaris I2C module can operate at two speeds: Standard (100 Kbps) and Fast (400 Kbps). Both the I2C master and slave can generate interrupts. The I2C master generates interrupts when a transmit or receive operation completes (or aborts due to an error). The I2C slave generates interrupts when data has been sent or requested by a master. ® 1.4.4.4 Ethernet Controller (see page 409) Ethernet is a frame-based computer networking technology for local area networks (LANs). Ethernet has been standardized as IEEE 802.3. It defines a number of wiring and signaling standards for the physical layer, two means of network access at the Media Access Control (MAC)/Data Link Layer, and a common addressing format. The Stellaris® Ethernet Controller consists of a fully integrated media access controller (MAC) and network physical (PHY) interface device. The Ethernet Controller conforms to IEEE 802.3 specifications and fully supports 10BASE-T and 100BASE-TX standards. In addition, the Ethernet Controller supports automatic MDI/MDI-X cross-over correction. 1.4.5 1.4.5.1 System Peripherals Programmable GPIOs (see page 163) General-purpose input/output (GPIO) pins offer flexibility for a variety of connections. The Stellaris GPIO module is composed of seven physical GPIO blocks, each corresponding to an individual GPIO port. The GPIO module is FiRM-compliant (compliant to the ARM Foundation IP for Real-Time Microcontrollers specification) and supports 0-42 programmable input/output pins. ® November 30, 2007 Preliminary 33 Architectural Overview The number of GPIOs available depends on the peripherals being used (see “Signal Tables” on page 519 for the signals available to each GPIO pin). The GPIO module features programmable interrupt generation as either edge-triggered or level-sensitive on all pins, programmable control for GPIO pad configuration, and bit masking in both read and write operations through address lines. 1.4.5.2 Four Programmable Timers (see page 204) Programmable timers can be used to count or time external events that drive the Timer input pins. The Stellaris General-Purpose Timer Module (GPTM) contains four GPTM blocks. Each GPTM block provides two 16-bit timers/counters that can be configured to operate independently as timers or event counters, or configured to operate as one 32-bit timer or one 32-bit Real-Time Clock (RTC). Timers can also be used to trigger analog-to-digital (ADC) conversions. When configured in 32-bit mode, a timer can run as a Real-Time Clock (RTC), one-shot timer or periodic timer. When in 16-bit mode, a timer can run as a one-shot timer or periodic timer, and can extend its precision by using an 8-bit prescaler. A 16-bit timer can also be configured for event capture or Pulse Width Modulation (PWM) generation. ® 1.4.5.3 Watchdog Timer (see page 240) A watchdog timer can generate nonmaskable interrupts (NMIs) or a reset when a time-out value is reached. The watchdog timer is used to regain control when a system has failed due to a software error or to the failure of an external device to respond in the expected way. The Stellaris Watchdog Timer module consists of a 32-bit down counter, a programmable load register, interrupt generation logic, and a locking register. The Watchdog Timer can be configured to generate an interrupt to the controller on its first time-out, and to generate a reset signal on its second time-out. Once the Watchdog Timer has been configured, the lock register can be written to prevent the timer configuration from being inadvertently altered. ® 1.4.6 1.4.6.1 Memory Peripherals The LM3S6965 controller offers both single-cycle SRAM and single-cycle Flash memory. SRAM (see page 139) The LM3S6965 static random access memory (SRAM) controller supports 64 KB SRAM. The internal ® SRAM of the Stellaris devices is located at offset 0x0000.0000 of the device memory map. To reduce the number of time-consuming read-modify-write (RMW) operations, ARM has introduced bit-banding technology in the new Cortex-M3 processor. With a bit-band-enabled processor, certain regions in the memory map (SRAM and peripheral space) can use address aliases to access individual bits in a single, atomic operation. 1.4.6.2 Flash (see page 140) The LM3S6965 Flash controller supports 256 KB of flash memory. The flash is organized as a set of 1-KB blocks that can be individually erased. Erasing a block causes the entire contents of the block to be reset to all 1s. These blocks are paired into a set of 2-KB blocks that can be individually protected. The blocks can be marked as read-only or execute-only, providing different levels of code protection. Read-only blocks cannot be erased or programmed, protecting the contents of those blocks from being modified. Execute-only blocks cannot be erased or programmed, and can only be read by the controller instruction fetch mechanism, protecting the contents of those blocks from being read by either the controller or by a debugger. 34 Preliminary November 30, 2007 LM3S6965 Microcontroller 1.4.7 1.4.7.1 Additional Features Memory Map (see page 43) A memory map lists the location of instructions and data in memory. The memory map for the LM3S6965 controller can be found in “Memory Map” on page 43. Register addresses are given as a hexadecimal increment, relative to the module's base address as shown in the memory map. The ARM® Cortex™-M3 Technical Reference Manual provides further information on the memory map. 1.4.7.2 JTAG TAP Controller (see page 48) The Joint Test Action Group (JTAG) port provides a standardized serial interface for controlling the Test Access Port (TAP) and associated test logic. The TAP, JTAG instruction register, and JTAG data registers can be used to test the interconnects of assembled printed circuit boards, obtain manufacturing information on the components, and observe and/or control the inputs and outputs of the controller during normal operation. The JTAG port provides a high degree of testability and chip-level access at a low cost. The JTAG port is comprised of the standard five pins: TRST, TCK, TMS, TDI, and TDO. Data is transmitted serially into the controller on TDI and out of the controller on TDO. The interpretation of this data is dependent on the current state of the TAP controller. For detailed information on the operation of the JTAG port and TAP controller, please refer to the IEEE Standard 1149.1-Test Access Port and Boundary-Scan Architecture. The Luminary Micro JTAG controller works with the ARM JTAG controller built into the Cortex-M3 core. This is implemented by multiplexing the TDO outputs from both JTAG controllers. ARM JTAG instructions select the ARM TDO output while Luminary Micro JTAG instructions select the Luminary Micro TDO outputs. The multiplexer is controlled by the Luminary Micro JTAG controller, which has comprehensive programming for the ARM, Luminary Micro, and unimplemented JTAG instructions. 1.4.7.3 System Control and Clocks (see page 59) System control determines the overall operation of the device. It provides information about the device, controls the clocking of the device and individual peripherals, and handles reset detection and reporting. 1.4.7.4 Hibernation Module (see page 120) The Hibernation module provides logic to switch power off to the main processor and peripherals, and to wake on external or time-based events. The Hibernation module includes power-sequencing logic, a real-time clock with a pair of match registers, low-battery detection circuitry, and interrupt signalling to the processor. It also includes 64 32-bit words of non-volatile memory that can be used for saving state during hibernation. 1.4.8 Hardware Details Details on the pins and package can be found in the following sections: ■ “Pin Diagram” on page 518 ■ “Signal Tables” on page 519 ■ “Operating Characteristics” on page 534 ■ “Electrical Characteristics” on page 535 November 30, 2007 Preliminary 35 Architectural Overview ■ “Package Information” on page 550 36 Preliminary November 30, 2007 LM3S6965 Microcontroller 2 ARM Cortex-M3 Processor Core The ARM Cortex-M3 processor provides the core for a high-performance, low-cost platform that meets the needs of minimal memory implementation, reduced pin count, and low power consumption, while delivering outstanding computational performance and exceptional system response to interrupts. Features include: ■ Compact core. ■ Thumb-2 instruction set, delivering the high-performance expected of an ARM core in the memory size usually associated with 8- and 16-bit devices; typically in the range of a few kilobytes of memory for microcontroller class applications. ■ Rapid application execution through Harvard architecture characterized by separate buses for instruction and data. ■ Exceptional interrupt handling, by implementing the register manipulations required for handling an interrupt in hardware. ■ Memory protection unit (MPU) to provide a privileged mode of operation for complex applications. ■ Migration from the ARM7™ processor family for better performance and power efficiency. ■ Full-featured debug solution with a: – Serial Wire JTAG Debug Port (SWJ-DP) – Flash Patch and Breakpoint (FPB) unit for implementing breakpoints – Data Watchpoint and Trigger (DWT) unit for implementing watchpoints, trigger resources, and system profiling – Instrumentation Trace Macrocell (ITM) for support of printf style debugging – Trace Port Interface Unit (TPIU) for bridging to a Trace Port Analyzer The Stellaris family of microcontrollers builds on this core to bring high-performance 32-bit computing to cost-sensitive embedded microcontroller applications, such as factory automation and control, industrial control power devices, building and home automation, and stepper motors. For more information on the ARM Cortex-M3 processor core, see the ARM® Cortex™-M3 Technical Reference Manual. For information on SWJ-DP, see the ARM® CoreSight Technical Reference Manual. ® November 30, 2007 Preliminary 37 ARM Cortex-M3 Processor Core 2.1 Block Diagram Figure 2-1. CPU Block Diagram Nested Vectored Interrupt Controller Interrupts Sleep Debug Instructions Memory Protection Unit Data Trace Port Interface Unit CM3 Core ARM Cortex-M3 Serial Wire Output Trace Port (SWO) Flash Patch and Breakpoint Instrumentation Data Watchpoint Trace Macrocell and Trace Private Peripheral Bus (external) ROM Table Private Peripheral Bus (internal) Bus Matrix Adv. Peripheral Bus I-code bus D-code bus System bus Serial Wire JTAG Debug Port Adv. HighPerf. Bus Access Port 2.2 Functional Description Important: The ARM® Cortex™-M3 Technical Reference Manual describes all the features of an ARM Cortex-M3 in detail. However, these features differ based on the implementation. ® This section describes the Stellaris implementation. Luminary Micro has implemented the ARM Cortex-M3 core as shown in Figure 2-1 on page 38. As noted in the ARM® Cortex™-M3 Technical Reference Manual, several Cortex-M3 components are flexible in their implementation: SW/JTAG-DP, ETM, TPIU, the ROM table, the MPU, and the Nested Vectored Interrupt Controller (NVIC). Each of these is addressed in the sections that follow. 2.2.1 Serial Wire and JTAG Debug Luminary Micro has replaced the ARM SW-DP and JTAG-DP with the ARM CoreSight™-compliant Serial Wire JTAG Debug Port (SWJ-DP) interface. This means Chapter 12, “Debug Port,” of the ® ARM® Cortex™-M3 Technical Reference Manual does not apply to Stellaris devices. The SWJ-DP interface combines the SWD and JTAG debug ports into one module. See the CoreSight™ Design Kit Technical Reference Manual for details on SWJ-DP. 38 Preliminary November 30, 2007 LM3S6965 Microcontroller 2.2.2 Embedded Trace Macrocell (ETM) ETM was not implemented in the Stellaris devices. This means Chapters 15 and 16 of the ARM® Cortex™-M3 Technical Reference Manual can be ignored. ® 2.2.3 Trace Port Interface Unit (TPIU) The TPIU acts as a bridge between the Cortex-M3 trace data from the ITM, and an off-chip Trace ® Port Analyzer. The Stellaris devices have implemented TPIU as shown in Figure 2-2 on page 39. This is similar to the non-ETM version described in the ARM® Cortex™-M3 Technical Reference Manual, however, SWJ-DP only provides SWV output for the TPIU. Figure 2-2. TPIU Block Diagram Debug ATB Slave Port ATB Interface Asynchronous FIFO Trace Out (serializer) Serial Wire Trace Port (SWO) APB Slave Port APB Interface 2.2.4 ROM Table The default ROM table was implemented as described in the ARM® Cortex™-M3 Technical Reference Manual. 2.2.5 Memory Protection Unit (MPU) The Memory Protection Unit (MPU) is included on the LM3S6965 controller and supports the standard ARMv7 Protected Memory System Architecture (PMSA) model. The MPU provides full support for protection regions, overlapping protection regions, access permissions, and exporting memory attributes to the system. 2.2.6 Nested Vectored Interrupt Controller (NVIC) The Nested Vectored Interrupt Controller (NVIC): ■ Facilitates low-latency exception and interrupt handling ■ Controls power management ■ Implements system control registers November 30, 2007 Preliminary 39 ARM Cortex-M3 Processor Core The NVIC supports up to 240 dynamically reprioritizable interrupts each with up to 256 levels of priority. The NVIC and the processor core interface are closely coupled, which enables low latency interrupt processing and efficient processing of late arriving interrupts. The NVIC maintains knowledge of the stacked (nested) interrupts to enable tail-chaining of interrupts. You can only fully access the NVIC from privileged mode, but you can pend interrupts in user-mode if you enable the Configuration Control Register (see the ARM® Cortex™-M3 Technical Reference Manual). Any other user-mode access causes a bus fault. All NVIC registers are accessible using byte, halfword, and word unless otherwise stated. All NVIC registers and system debug registers are little endian regardless of the endianness state of the processor. 2.2.6.1 Interrupts The ARM® Cortex™-M3 Technical Reference Manual describes the maximum number of interrupts and interrupt priorities. The LM3S6965 microcontroller supports 38 interrupts with eight priority levels. 2.2.6.2 System Timer (SysTick) Cortex-M3 includes an integrated system timer, SysTick. SysTick provides a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter can be used in several different ways, for example: ■ An RTOS tick timer which fires at a programmable rate (for example, 100 Hz) and invokes a SysTick routine. ■ A high-speed alarm timer using the system clock. ■ A variable rate alarm or signal timer—the duration is range-dependent on the reference clock used and the dynamic range of the counter. ■ A simple counter. Software can use this to measure time to completion and time used. ■ An internal clock source control based on missing/meeting durations. The COUNTFLAG bit-field in the control and status register can be used to determine if an action completed within a set duration, as part of a dynamic clock management control loop. Functional Description The timer consists of three registers: ■ A control and status counter to configure its clock, enable the counter, enable the SysTick interrupt, and determine counter status. ■ The reload value for the counter, used to provide the counter's wrap value. ■ The current value of the counter. A fourth register, the SysTick Calibration Value Register, is not implemented in the Stellaris devices. When enabled, the timer counts down from the reload value to zero, reloads (wraps) to the value in the SysTick Reload Value register on the next clock edge, then decrements on subsequent clocks. Writing a value of zero to the Reload Value register disables the counter on the next wrap. When the counter reaches zero, the COUNTFLAG status bit is set. The COUNTFLAG bit clears on reads. ® 40 Preliminary November 30, 2007 LM3S6965 Microcontroller Writing to the Current Value register clears the register and the COUNTFLAG status bit. The write does not trigger the SysTick exception logic. On a read, the current value is the value of the register at the time the register is accessed. If the core is in debug state (halted), the counter will not decrement. The timer is clocked with respect to a reference clock. The reference clock can be the core clock or an external clock source. SysTick Control and Status Register Use the SysTick Control and Status Register to enable the SysTick features. The reset is 0x0000.0000. Bit/Field 31:17 Name reserved Type Reset Description RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Returns 1 if timer counted to 0 since last time this was read. Clears on read by application. If read by the debugger using the DAP, this bit is cleared on read-only if the MasterType bit in the AHB-AP Control Register is set to 0. Otherwise, the COUNTFLAG bit is not changed by the debugger read. Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 = external reference clock. (Not implemented for Stellaris microcontrollers.) 1 = core clock. If no reference clock is provided, it is held at 1 and so gives the same time as the core clock. The core clock must be at least 2.5 times faster than the reference clock. If it is not, the count values are unpredictable. 1 TICKINT R/W 0 1 = counting down to 0 pends the SysTick handler. 0 = counting down to 0 does not pend the SysTick handler. Software can use the COUNTFLAG to determine if ever counted to 0. 0 ENABLE R/W 0 1 = counter operates in a multi-shot way. That is, counter loads with the Reload value and then begins counting down. On reaching 0, it sets the COUNTFLAG to 1 and optionally pends the SysTick handler, based on TICKINT. It then loads the Reload value again, and begins counting. 0 = counter disabled. 16 COUNTFLAG R/W 0 15:3 reserved RO 0 2 CLKSOURCE R/W 0 SysTick Reload Value Register Use the SysTick Reload Value Register to specify the start value to load into the current value register when the counter reaches 0. It can be any value between 1 and 0x00FF.FFFF. A start value of 0 is possible, but has no effect because the SysTick interrupt and COUNTFLAG are activated when counting from 1 to 0. Therefore, as a multi-shot timer, repeated over and over, it fires every N+1 clock pulse, where N is any value from 1 to 0x00FF.FFFF. So, if the tick interrupt is required every 100 clock pulses, 99 must be written into the RELOAD. If a new value is written on each tick interrupt, so treated as single shot, then the actual count down must be written. For example, if a tick is next required after 400 clock pulses, 400 must be written into the RELOAD. Bit/Field 31:24 Name reserved Type Reset Description RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. November 30, 2007 Preliminary 41 ARM Cortex-M3 Processor Core Bit/Field 23:0 Name Type Reset Description Value to load into the SysTick Current Value Register when the counter reaches 0. RELOAD W1C SysTick Current Value Register Use the SysTick Current Value Register to find the current value in the register. Bit/Field 31:24 Name reserved Type Reset Description RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Current value at the time the register is accessed. No read-modify-write protection is provided, so change with care. This register is write-clear. Writing to it with any value clears the register to 0. Clearing this register also clears the COUNTFLAG bit of the SysTick Control and Status Register. 23:0 CURRENT W1C - SysTick Calibration Value Register The SysTick Calibration Value register is not implemented. 42 Preliminary November 30, 2007 LM3S6965 Microcontroller 3 Memory Map The memory map for the LM3S6965 controller is provided in Table 3-1 on page 43. In this manual, register addresses are given as a hexadecimal increment, relative to the module’s base address as shown in the memory map. See also Chapter 4, “Memory Map” in the ARM® Cortex™-M3 Technical Reference Manual. Important: In Table 3-1 on page 43, addresses not listed are reserved. Table 3-1. Memory Map Start a End Description For details on registers, see page ... b c Memory 0x0000.0000 0x2000.0000 0x2010.0000 0x2200.0000 0x2400.0000 FiRM Peripherals 0x4000.0000 0x4000.4000 0x4000.5000 0x4000.6000 0x4000.7000 0x4000.8000 0x4000.C000 0x4000.D000 0x4000.E000 Peripherals 0x4002.0000 0x4002.0800 0x4002.1000 0x4002.1800 0x4002.4000 0x4002.5000 0x4002.6000 0x4002.8000 0x4002.C000 0x4002.D000 0x4003.0000 0x4003.1000 0x4003.2000 0x4003.3000 0x4002.07FF 0x4002.0FFF 0x4002.17FF 0x4002.1FFF 0x4002.4FFF 0x4002.5FFF 0x4002.6FFF 0x4002.8FFF 0x4002.CFFF 0x4002.DFFF 0x4003.0FFF 0x4003.1FFF 0x4003.2FFF 0x4003.3FFF I2C Master 0 I2C Slave 0 I2C Master 1 I2C Slave 1 GPIO Port E GPIO Port F GPIO Port G PWM QEI0 QEI1 Timer0 Timer1 Timer2 Timer3 387 400 387 400 169 169 169 472 505 505 215 215 215 215 0x4000.0FFF 0x4000.4FFF 0x4000.5FFF 0x4000.6FFF 0x4000.7FFF 0x4000.8FFF 0x4000.CFFF 0x4000.DFFF 0x4000.EFFF Watchdog timer GPIO Port A GPIO Port B GPIO Port C GPIO Port D SSI0 UART0 UART1 UART2 242 169 169 169 169 348 303 303 303 0x0003.FFFF 0x2000.FFFF 0x21FF.FFFF 0x23FF.FFFF 0x3FFF.FFFF On-chip flash 143 143 139 - Bit-banded on-chip SRAM Reserved non-bit-banded SRAM space Bit-band alias of 0x2000.0000 through 0x200F.FFFF Reserved non-bit-banded SRAM space November 30, 2007 Preliminary 43 Memory Map Start End Description For details on registers, see page ... 269 453 417 126 143 66 - 0x4003.8000 0x4003.C000 0x4004.8000 0x400F.C000 0x400F.D000 0x400F.E000 0x4200.0000 Private Peripheral Bus 0xE000.0000 0xE000.1000 0xE000.2000 0xE000.3000 0xE000.E000 0xE000.F000 0xE004.0000 0xE004.1000 0xE004.2000 0xE010.0000 0x4003.8FFF 0x4003.CFFF 0x4004.8FFF 0x400F.CFFF 0x400F.DFFF 0x400F.EFFF 0x43FF.FFFF ADC Analog Comparators Ethernet Controller Hibernation Module Flash control System control Bit-banded alias of 0x4000.0000 through 0x400F.FFFF 0xE000.0FFF 0xE000.1FFF 0xE000.2FFF 0xE000.DFFF 0xE000.EFFF 0xE003.FFFF 0xE004.0FFF 0xE004.1FFF 0xE00F.FFFF 0xFFFF.FFFF Instrumentation Trace Macrocell (ITM) Data Watchpoint and Trace (DWT) Flash Patch and Breakpoint (FPB) Reserved Nested Vectored Interrupt Controller (NVIC) Reserved Trace Port Interface Unit (TPIU) Reserved Reserved Reserved for vendor peripherals ARM® Cortex™-M3 Technical Reference Manual - a. All reserved space returns a bus fault when read or written. b. The unavailable flash will bus fault throughout this range. c. The unavailable SRAM will bus fault throughout this range. 44 Preliminary November 30, 2007 LM3S6965 Microcontroller 4 Interrupts The ARM Cortex-M3 processor and the Nested Vectored Interrupt Controller (NVIC) prioritize and handle all exceptions. All exceptions are handled in Handler Mode. The processor state is automatically stored to the stack on an exception, and automatically restored from the stack at the end of the Interrupt Service Routine (ISR). The vector is fetched in parallel to the state saving, which enables efficient interrupt entry. The processor supports tail-chaining, which enables back-to-back interrupts to be performed without the overhead of state saving and restoration. Table 4-1 on page 45 lists all the exceptions. Software can set eight priority levels on seven of these exceptions (system handlers) as well as on 38 interrupts (listed in Table 4-2 on page 46). Priorities on the system handlers are set with the NVIC System Handler Priority registers. Interrupts are enabled through the NVIC Interrupt Set Enable register and prioritized with the NVIC Interrupt Priority registers. You can also group priorities by splitting priority levels into pre-emption priorities and subpriorities. All the interrupt registers are described in Chapter 8, “Nested Vectored Interrupt Controller” in the ARM® Cortex™-M3 Technical Reference Manual. Internally, the highest user-settable priority (0) is treated as fourth priority, after a Reset, NMI, and a Hard Fault. Note that 0 is the default priority for all the settable priorities. If you assign the same priority level to two or more interrupts, their hardware priority (the lower the position number) determines the order in which the processor activates them. For example, if both GPIO Port A and GPIO Port B are priority level 1, then GPIO Port A has higher priority. See Chapter 5, “Exceptions” and Chapter 8, “Nested Vectored Interrupt Controller” in the ARM® Cortex™-M3 Technical Reference Manual for more information on exceptions and interrupts. Note: In Table 4-2 on page 46 interrupts not listed are reserved. Table 4-1. Exception Types Exception Type Reset Position 0 1 Priority a Description Stack top is loaded from first entry of vector table on reset. -3 (highest) Invoked on power up and warm reset. On first instruction, drops to lowest priority (and then is called the base level of activation). This is asynchronous. -2 Cannot be stopped or preempted by any exception but reset. This is asynchronous. An NMI is only producible by software, using the NVIC Interrupt Control State register. Non-Maskable Interrupt (NMI) 2 Hard Fault Memory Management 3 4 -1 settable All classes of Fault, when the fault cannot activate due to priority or the configurable fault handler has been disabled. This is synchronous. MPU mismatch, including access violation and no match. This is synchronous. The priority of this exception can be changed. Bus Fault 5 settable Pre-fetch fault, memory access fault, and other address/memory related faults. This is synchronous when precise and asynchronous when imprecise. You can enable or disable this fault. Usage Fault SVCall 6 7-10 11 settable settable Usage fault, such as undefined instruction executed or illegal state transition attempt. This is synchronous. Reserved. System service call with SVC instruction. This is synchronous. November 30, 2007 Preliminary 45 Interrupts Exception Type Debug Monitor Position 12 Priority a Description Debug monitor (when not halting). This is synchronous, but only active when enabled. It does not activate if lower priority than the current activation. Reserved. Pendable request for system service. This is asynchronous and only pended by software. System tick timer has fired. This is asynchronous. Asserted from outside the ARM Cortex-M3 core and fed through the NVIC (prioritized). These are all asynchronous. Table 4-2 on page 46 lists the interrupts on the LM3S6965 controller. settable PendSV SysTick Interrupts 13 14 15 16 and above settable settable settable a. 0 is the default priority for all the settable priorities. Table 4-2. Interrupts Interrupt (Bit in Interrupt Registers) Description 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 28 29 30 GPIO Port A GPIO Port B GPIO Port C GPIO Port D GPIO Port E UART0 UART1 SSI0 I2C0 PWM Fault PWM Generator 0 PWM Generator 1 PWM Generator 2 QEI0 ADC Sequence 0 ADC Sequence 1 ADC Sequence 2 ADC Sequence 3 Watchdog timer Timer0 A Timer0 B Timer1 A Timer1 B Timer2 A Timer2 B Analog Comparator 0 Analog Comparator 1 System Control Flash Control GPIO Port F 46 Preliminary November 30, 2007 LM3S6965 Microcontroller Interrupt (Bit in Interrupt Registers) Description 31 33 35 36 37 38 42 43 GPIO Port G UART2 Timer3 A Timer3 B I2C1 QEI1 Ethernet Controller Hibernation Module November 30, 2007 Preliminary 47 JTAG Interface 5 JTAG Interface The Joint Test Action Group (JTAG) port is an IEEE standard that defines a Test Access Port and Boundary Scan Architecture for digital integrated circuits and provides a standardized serial interface for controlling the associated test logic. The TAP, Instruction Register (IR), and Data Registers (DR) can be used to test the interconnections of assembled printed circuit boards and obtain manufacturing information on the components. The JTAG Port also provides a means of accessing and controlling design-for-test features such as I/O pin observation and control, scan testing, and debugging. The JTAG port is comprised of the standard five pins: TRST, TCK, TMS, TDI, and TDO. Data is transmitted serially into the controller on TDI and out of the controller on TDO. The interpretation of this data is dependent on the current state of the TAP controller. For detailed information on the operation of the JTAG port and TAP controller, please refer to the IEEE Standard 1149.1-Test Access Port and Boundary-Scan Architecture. The Luminary Micro JTAG controller works with the ARM JTAG controller built into the Cortex-M3 core. This is implemented by multiplexing the TDO outputs from both JTAG controllers. ARM JTAG instructions select the ARM TDO output while Luminary Micro JTAG instructions select the Luminary Micro TDO outputs. The multiplexer is controlled by the Luminary Micro JTAG controller, which has comprehensive programming for the ARM, Luminary Micro, and unimplemented JTAG instructions. The JTAG module has the following features: ■ IEEE 1149.1-1990 compatible Test Access Port (TAP) controller ■ Four-bit Instruction Register (IR) chain for storing JTAG instructions ■ IEEE standard instructions: – BYPASS instruction – IDCODE instruction – SAMPLE/PRELOAD instruction – EXTEST instruction – INTEST instruction ■ ARM additional instructions: – APACC instruction – DPACC instruction – ABORT instruction ■ Integrated ARM Serial Wire Debug (SWD) See the ARM® Cortex™-M3 Technical Reference Manual for more information on the ARM JTAG controller. 48 Preliminary November 30, 2007 LM3S6965 Microcontroller 5.1 Block Diagram Figure 5-1. JTAG Module Block Diagram TRST TCK TMS TDI TAP Controller Instruction Register (IR) BYPASS Data Register Boundar y Scan Data Register IDCODE Data Register ABORT Data Register DPACC Data Register APACC Data Register TDO Cor tex-M3 Debug Por t 5.2 Functional Description A high-level conceptual drawing of the JTAG module is shown in Figure 5-1 on page 49. The JTAG module is composed of the Test Access Port (TAP) controller and serial shift chains with parallel update registers. The TAP controller is a simple state machine controlled by the TRST, TCK and TMS inputs. The current state of the TAP controller depends on the current value of TRST and the sequence of values captured on TMS at the rising edge of TCK. The TAP controller determines when the serial shift chains capture new data, shift data from TDI towards TDO, and update the parallel load registers. The current state of the TAP controller also determines whether the Instruction Register (IR) chain or one of the Data Register (DR) chains is being accessed. The serial shift chains with parallel load registers are comprised of a single Instruction Register (IR) chain and multiple Data Register (DR) chains. The current instruction loaded in the parallel load register determines which DR chain is captured, shifted, or updated during the sequencing of the TAP controller. Some instructions, like EXTEST and INTEST, operate on data currently in a DR chain and do not capture, shift, or update any of the chains. Instructions that are not implemented decode to the BYPASS instruction to ensure that the serial path between TDI and TDO is always connected (see Table 5-2 on page 55 for a list of implemented instructions). See “JTAG and Boundary Scan” on page 546 for JTAG timing diagrams. November 30, 2007 Preliminary 49 JTAG Interface 5.2.1 JTAG Interface Pins The JTAG interface consists of five standard pins: TRST, TCK, TMS, TDI, and TDO. These pins and their associated reset state are given in Table 5-1 on page 50. Detailed information on each pin follows. Table 5-1. JTAG Port Pins Reset State Pin Name TRST TCK TMS TDI TDO Data Direction Input Input Input Input Output Internal Pull-Up Enabled Enabled Enabled Enabled Enabled Internal Pull-Down Disabled Disabled Disabled Disabled Disabled Drive Strength N/A N/A N/A N/A 2-mA driver Drive Value N/A N/A N/A N/A High-Z 5.2.1.1 Test Reset Input (TRST) The TRST pin is an asynchronous active Low input signal for initializing and resetting the JTAG TAP controller and associated JTAG circuitry. When TRST is asserted, the TAP controller resets to the Test-Logic-Reset state and remains there while TRST is asserted. When the TAP controller enters the Test-Logic-Reset state, the JTAG Instruction Register (IR) resets to the default instruction, IDCODE. By default, the internal pull-up resistor on the TRST pin is enabled after reset. Changes to the pull-up resistor settings on GPIO Port B should ensure that the internal pull-up resistor remains enabled on PB7/TRST; otherwise JTAG communication could be lost. 5.2.1.2 Test Clock Input (TCK) The TCK pin is the clock for the JTAG module. This clock is provided so the test logic can operate independently of any other system clocks. In addition, it ensures that multiple JTAG TAP controllers that are daisy-chained together can synchronously communicate serial test data between components. During normal operation, TCK is driven by a free-running clock with a nominal 50% duty cycle. When necessary, TCK can be stopped at 0 or 1 for extended periods of time. While TCK is stopped at 0 or 1, the state of the TAP controller does not change and data in the JTAG Instruction and Data Registers is not lost. By default, the internal pull-up resistor on the TCK pin is enabled after reset. This assures that no clocking occurs if the pin is not driven from an external source. The internal pull-up and pull-down resistors can be turned off to save internal power as long as the TCK pin is constantly being driven by an external source. 5.2.1.3 Test Mode Select (TMS) The TMS pin selects the next state of the JTAG TAP controller. TMS is sampled on the rising edge of TCK. Depending on the current TAP state and the sampled value of TMS, the next state is entered. Because the TMS pin is sampled on the rising edge of TCK, the IEEE Standard 1149.1 expects the value on TMS to change on the falling edge of TCK. Holding TMS high for five consecutive TCK cycles drives the TAP controller state machine to the Test-Logic-Reset state. When the TAP controller enters the Test-Logic-Reset state, the JTAG Instruction Register (IR) resets to the default instruction, IDCODE. Therefore, this sequence can be used as a reset mechanism, similar to asserting TRST. The JTAG Test Access Port state machine can be seen in its entirety in Figure 5-2 on page 52. 50 Preliminary November 30, 2007 LM3S6965 Microcontroller By default, the internal pull-up resistor on the TMS pin is enabled after reset. Changes to the pull-up resistor settings on GPIO Port C should ensure that the internal pull-up resistor remains enabled on PC1/TMS; otherwise JTAG communication could be lost. 5.2.1.4 Test Data Input (TDI) The TDI pin provides a stream of serial information to the IR chain and the DR chains. TDI is sampled on the rising edge of TCK and, depending on the current TAP state and the current instruction, presents this data to the proper shift register chain. Because the TDI pin is sampled on the rising edge of TCK, the IEEE Standard 1149.1 expects the value on TDI to change on the falling edge of TCK. By default, the internal pull-up resistor on the TDI pin is enabled after reset. Changes to the pull-up resistor settings on GPIO Port C should ensure that the internal pull-up resistor remains enabled on PC2/TDI; otherwise JTAG communication could be lost. 5.2.1.5 Test Data Output (TDO) The TDO pin provides an output stream of serial information from the IR chain or the DR chains. The value of TDO depends on the current TAP state, the current instruction, and the data in the chain being accessed. In order to save power when the JTAG port is not being used, the TDO pin is placed in an inactive drive state when not actively shifting out data. Because TDO can be connected to the TDI of another controller in a daisy-chain configuration, the IEEE Standard 1149.1 expects the value on TDO to change on the falling edge of TCK. By default, the internal pull-up resistor on the TDO pin is enabled after reset. This assures that the pin remains at a constant logic level when the JTAG port is not being used. The internal pull-up and pull-down resistors can be turned off to save internal power if a High-Z output value is acceptable during certain TAP controller states. 5.2.2 JTAG TAP Controller The JTAG TAP controller state machine is shown in Figure 5-2 on page 52. The TAP controller state machine is reset to the Test-Logic-Reset state on the assertion of a Power-On-Reset (POR) or the assertion of TRST. Asserting the correct sequence on the TMS pin allows the JTAG module to shift in new instructions, shift in data, or idle during extended testing sequences. For detailed information on the function of the TAP controller and the operations that occur in each state, please refer to IEEE Standard 1149.1. November 30, 2007 Preliminary 51 JTAG Interface Figure 5-2. Test Access Port State Machine Test Logic Reset 1 0 Run Test Idle 1 Select DR Scan 0 1 Capture DR 0 Shift DR 1 Exit 1 DR 0 Pause DR 1 0 Exit 2 DR 1 Update DR 1 0 0 0 0 1 1 1 Select IR Scan 0 Capture IR 0 Shift IR 1 Exit 1 IR 0 Pause IR 1 Exit 2 IR 1 Update IR 1 0 0 0 1 1 0 5.2.3 Shift Registers The Shift Registers consist of a serial shift register chain and a parallel load register. The serial shift register chain samples specific information during the TAP controller ’s CAPTURE states and allows this information to be shifted out of TDO during the TAP controller ’s SHIFT states. While the sampled data is being shifted out of the chain on TDO, new data is being shifted into the serial shift register on TDI. This new data is stored in the parallel load register during the TAP controller ’s UPDATE states. Each of the shift registers is discussed in detail in “Register Descriptions” on page 55. 5.2.4 Operational Considerations There are certain operational considerations when using the JTAG module. Because the JTAG pins can be programmed to be GPIOs, board configuration and reset conditions on these pins must be considered. In addition, because the JTAG module has integrated ARM Serial Wire Debug, the method for switching between these two operational modes is described below. 52 Preliminary November 30, 2007 LM3S6965 Microcontroller 5.2.4.1 GPIO Functionality When the controller is reset with either a POR or RST, the JTAG/SWD port pins default to their JTAG/SWD configurations. The default configuration includes enabling digital functionality (setting GPIODEN to 1), enabling the pull-up resistors (setting GPIOPUR to 1), and enabling the alternate hardware function (setting GPIOAFSEL to 1) for the PB7 and PC[3:0] JTAG/SWD pins. It is possible for software to configure these pins as GPIOs after reset by writing 0s to PB7 and PC[3:0] in the GPIOAFSEL register. If the user does not require the JTAG/SWD port for debugging or board-level testing, this provides five more GPIOs for use in the design. Caution – If the JTAG pins are used as GPIOs in a design, PB7 and PC2 cannot have external pull-down resistors connected to both of them at the same time. If both pins are pulled Low during reset, the controller has unpredictable behavior. If this happens, remove one or both of the pull-down resistors, and apply RST or power-cycle the part. In addition, it is possible to create a software sequence that prevents the debugger from connecting to the Stellaris® microcontroller. If the program code loaded into flash immediately changes the JTAG pins to their GPIO functionality, the debugger may not have enough time to connect and halt the controller before the JTAG pin functionality switches. This may lock the debugger out of the part. This can be avoided with a software routine that restores JTAG functionality based on an external or software trigger. The commit control registers provide a layer of protection against accidental programming of critical hardware peripherals. Writes to protected bits of the GPIO Alternate Function Select (GPIOAFSEL) register (see page 179) are not committed to storage unless the GPIO Lock (GPIOLOCK) register (see page 189) has been unlocked and the appropriate bits of the GPIO Commit (GPIOCR) register (see page 190) have been set to 1. Recovering a "Locked" Device If software configures any of the JTAG/SWD pins as GPIO and loses the ability to communicate with the debugger, there is a debug sequence that can be used to recover the device. Performing a total of ten JTAG-to-SWD and SWD-to-JTAG switch sequences while holding the device in reset mass erases the flash memory. The sequence to recover the device is: 1. Assert and hold the RST signal. 2. Perform the JTAG-to-SWD switch sequence. 3. Perform the SWD-to-JTAG switch sequence. 4. Perform the JTAG-to-SWD switch sequence. 5. Perform the SWD-to-JTAG switch sequence. 6. Perform the JTAG-to-SWD switch sequence. 7. Perform the SWD-to-JTAG switch sequence. 8. Perform the JTAG-to-SWD switch sequence. 9. Perform the SWD-to-JTAG switch sequence. 10. Perform the JTAG-to-SWD switch sequence. 11. Perform the SWD-to-JTAG switch sequence. November 30, 2007 Preliminary 53 JTAG Interface 12. Release the RST signal. The JTAG-to-SWD and SWD-to-JTAG switch sequences are described in “ARM Serial Wire Debug (SWD)” on page 54. When performing switch sequences for the purpose of recovering the debug capabilities of the device, only steps 1 and 2 of the switch sequence need to be performed. 5.2.4.2 ARM Serial Wire Debug (SWD) In order to seamlessly integrate the ARM Serial Wire Debug (SWD) functionality, a serial-wire debugger must be able to connect to the Cortex-M3 core without having to perform, or have any knowledge of, JTAG cycles. This is accomplished with a SWD preamble that is issued before the SWD session begins. The preamble used to enable the SWD interface of the SWJ-DP module starts with the TAP controller in the Test-Logic-Reset state. From here, the preamble sequences the TAP controller through the following states: Run Test Idle, Select DR, Select IR, Test Logic Reset, Test Logic Reset, Run Test Idle, Run Test Idle, Select DR, Select IR, Test Logic Reset, Test Logic Reset, Run Test Idle, Run Test Idle, Select DR, Select IR, and Test Logic Reset states. Stepping through this sequences of the TAP state machine enables the SWD interface and disables the JTAG interface. For more information on this operation and the SWD interface, see the ARM® Cortex™-M3 Technical Reference Manual and the ARM® CoreSight Technical Reference Manual. Because this sequence is a valid series of JTAG operations that could be issued, the ARM JTAG TAP controller is not fully compliant to the IEEE Standard 1149.1. This is the only instance where the ARM JTAG TAP controller does not meet full compliance with the specification. Due to the low probability of this sequence occurring during normal operation of the TAP controller, it should not affect normal performance of the JTAG interface. JTAG-to-SWD Switching To switch the operating mode of the Debug Access Port (DAP) from JTAG to SWD mode, the external debug hardware must send a switch sequence to the device. The 16-bit switch sequence for switching to SWD mode is defined as b1110011110011110, transmitted LSB first. This can also be represented as 16'hE79E when transmitted LSB first. The complete switch sequence should consist of the following transactions on the TCK/SWCLK and TMS/SWDIO signals: 1. Send at least 50 TCK/SWCLK cycles with TMS/SWDIO set to 1. This ensures that both JTAG and SWD are in their reset/idle states. 2. Send the 16-bit JTAG-to-SWD switch sequence, 16'hE79E. 3. Send at least 50 TCK/SWCLK cycles with TMS/SWDIO set to 1. This ensures that if SWJ-DP was already in SWD mode, before sending the switch sequence, the SWD goes into the line reset state. SWD-to-JTAG Switching To switch the operating mode of the Debug Access Port (DAP) from SWD to JTAG mode, the external debug hardware must send a switch sequence to the device. The 16-bit switch sequence for switching to JTAG mode is defined as b1110011110011110, transmitted LSB first. This can also be represented as 16'hE73C when transmitted LSB first. The complete switch sequence should consist of the following transactions on the TCK/SWCLK and TMS/SWDIO signals: 1. Send at least 50 TCK/SWCLK cycles with TMS/SWDIO set to 1. This ensures that both JTAG and SWD are in their reset/idle states. 54 Preliminary November 30, 2007 LM3S6965 Microcontroller 2. Send the 16-bit SWD-to-JTAG switch sequence, 16'hE73C. 3. Send at least 5 TCK/SWCLK cycles with TMS/SWDIO set to 1. This ensures that if SWJ-DP was already in JTAG mode, before sending the switch sequence, the JTAG goes into the Test Logic Reset state. 5.3 Initialization and Configuration After a Power-On-Reset or an external reset (RST), the JTAG pins are automatically configured for JTAG communication. No user-defined initialization or configuration is needed. However, if the user application changes these pins to their GPIO function, they must be configured back to their JTAG functionality before JTAG communication can be restored. This is done by enabling the five JTAG pins (PB7 and PC[3:0]) for their alternate function using the GPIOAFSEL register. 5.4 Register Descriptions There are no APB-accessible registers in the JTAG TAP Controller or Shift Register chains. The registers within the JTAG controller are all accessed serially through the TAP Controller. The registers can be broken down into two main categories: Instruction Registers and Data Registers. 5.4.1 Instruction Register (IR) The JTAG TAP Instruction Register (IR) is a four-bit serial scan chain with a parallel load register connected between the JTAG TDI and TDO pins. When the TAP Controller is placed in the correct states, bits can be shifted into the Instruction Register. Once these bits have been shifted into the chain and updated, they are interpreted as the current instruction. The decode of the Instruction Register bits is shown in Table 5-2 on page 55. A detailed explanation of each instruction, along with its associated Data Register, follows. Table 5-2. JTAG Instruction Register Commands IR[3:0] 0000 0001 0010 1000 1010 1011 1110 1111 All Others Instruction EXTEST INTEST Description Drives the values preloaded into the Boundary Scan Chain by the SAMPLE/PRELOAD instruction onto the pads. Drives the values preloaded into the Boundary Scan Chain by the SAMPLE/PRELOAD instruction into the controller. SAMPLE / PRELOAD Captures the current I/O values and shifts the sampled values out of the Boundary Scan Chain while new preload data is shifted in. ABORT DPACC APACC IDCODE BYPASS Reserved Shifts data into the ARM Debug Port Abort Register. Shifts data into and out of the ARM DP Access Register. Shifts data into and out of the ARM AC Access Register. Loads manufacturing information defined by the IEEE Standard 1149.1 into the IDCODE chain and shifts it out. Connects TDI to TDO through a single Shift Register chain. Defaults to the BYPASS instruction to ensure that TDI is always connected to TDO. 5.4.1.1 EXTEST Instruction The EXTEST instruction does not have an associated Data Register chain. The EXTEST instruction uses the data that has been preloaded into the Boundary Scan Data Register using the SAMPLE/PRELOAD instruction. When the EXTEST instruction is present in the Instruction Register, the preloaded data in the Boundary Scan Data Register associated with the outputs and output enables are used to drive the GPIO pads rather than the signals coming from the core. This allows November 30, 2007 Preliminary 55 JTAG Interface tests to be developed that drive known values out of the controller, which can be used to verify connectivity. 5.4.1.2 INTEST Instruction The INTEST instruction does not have an associated Data Register chain. The INTEST instruction uses the data that has been preloaded into the Boundary Scan Data Register using the SAMPLE/PRELOAD instruction. When the INTEST instruction is present in the Instruction Register, the preloaded data in the Boundary Scan Data Register associated with the inputs are used to drive the signals going into the core rather than the signals coming from the GPIO pads. This allows tests to be developed that drive known values into the controller, which can be used for testing. It is important to note that although the RST input pin is on the Boundary Scan Data Register chain, it is only observable. 5.4.1.3 SAMPLE/PRELOAD Instruction The SAMPLE/PRELOAD instruction connects the Boundary Scan Data Register chain between TDI and TDO. This instruction samples the current state of the pad pins for observation and preloads new test data. Each GPIO pad has an associated input, output, and output enable signal. When the TAP controller enters the Capture DR state during this instruction, the input, output, and output-enable signals to each of the GPIO pads are captured. These samples are serially shifted out of TDO while the TAP controller is in the Shift DR state and can be used for observation or comparison in various tests. While these samples of the inputs, outputs, and output enables are being shifted out of the Boundary Scan Data Register, new data is being shifted into the Boundary Scan Data Register from TDI. Once the new data has been shifted into the Boundary Scan Data Register, the data is saved in the parallel load registers when the TAP controller enters the Update DR state. This update of the parallel load register preloads data into the Boundary Scan Data Register that is associated with each input, output, and output enable. This preloaded data can be used with the EXTEST and INTEST instructions to drive data into or out of the controller. Please see “Boundary Scan Data Register” on page 58 for more information. 5.4.1.4 ABORT Instruction The ABORT instruction connects the associated ABORT Data Register chain between TDI and TDO. This instruction provides read and write access to the ABORT Register of the ARM Debug Access Port (DAP). Shifting the proper data into this Data Register clears various error bits or initiates a DAP abort of a previous request. Please see the “ABORT Data Register” on page 58 for more information. 5.4.1.5 DPACC Instruction The DPACC instruction connects the associated DPACC Data Register chain between TDI and TDO. This instruction provides read and write access to the DPACC Register of the ARM Debug Access Port (DAP). Shifting the proper data into this register and reading the data output from this register allows read and write access to the ARM debug and status registers. Please see “DPACC Data Register” on page 58 for more information. 5.4.1.6 APACC Instruction The APACC instruction connects the associated APACC Data Register chain between TDI and TDO. This instruction provides read and write access to the APACC Register of the ARM Debug Access Port (DAP). Shifting the proper data into this register and reading the data output from this register allows read and write access to internal components and buses through the Debug Port. Please see “APACC Data Register” on page 58 for more information. 56 Preliminary November 30, 2007 LM3S6965 Microcontroller 5.4.1.7 IDCODE Instruction The IDCODE instruction connects the associated IDCODE Data Register chain between TDI and TDO. This instruction provides information on the manufacturer, part number, and version of the ARM core. This information can be used by testing equipment and debuggers to automatically configure their input and output data streams. IDCODE is the default instruction that is loaded into the JTAG Instruction Register when a power-on-reset (POR) is asserted, TRST is asserted, or the Test-Logic-Reset state is entered. Please see “IDCODE Data Register” on page 57 for more information. 5.4.1.8 BYPASS Instruction The BYPASS instruction connects the associated BYPASS Data Register chain between TDI and TDO. This instruction is used to create a minimum length serial path between the TDI and TDO ports. The BYPASS Data Register is a single-bit shift register. This instruction improves test efficiency by allowing components that are not needed for a specific test to be bypassed in the JTAG scan chain by loading them with the BYPASS instruction. Please see “BYPASS Data Register” on page 57 for more information. 5.4.2 Data Registers The JTAG module contains six Data Registers. These include: IDCODE, BYPASS, Boundary Scan, APACC, DPACC, and ABORT serial Data Register chains. Each of these Data Registers is discussed in the following sections. 5.4.2.1 IDCODE Data Register The format for the 32-bit IDCODE Data Register defined by the IEEE Standard 1149.1 is shown in Figure 5-3 on page 57. The standard requires that every JTAG-compliant device implement either the IDCODE instruction or the BYPASS instruction as the default instruction. The LSB of the IDCODE Data Register is defined to be a 1 to distinguish it from the BYPASS instruction, which has an LSB of 0. This allows auto configuration test tools to determine which instruction is the default instruction. The major uses of the JTAG port are for manufacturer testing of component assembly, and program development and debug. To facilitate the use of auto-configuration debug tools, the IDCODE instruction outputs a value of 0x3BA00477. This value indicates an ARM Cortex-M3, Version 1 processor. This allows the debuggers to automatically configure themselves to work correctly with the Cortex-M3 during debug. Figure 5-3. IDCODE Register Format 5.4.2.2 BYPASS Data Register The format for the 1-bit BYPASS Data Register defined by the IEEE Standard 1149.1 is shown in Figure 5-4 on page 58. The standard requires that every JTAG-compliant device implement either the BYPASS instruction or the IDCODE instruction as the default instruction. The LSB of the BYPASS Data Register is defined to be a 0 to distinguish it from the IDCODE instruction, which has an LSB of 1. This allows auto configuration test tools to determine which instruction is the default instruction. November 30, 2007 Preliminary 57 JTAG Interface Figure 5-4. BYPASS Register Format 5.4.2.3 Boundary Scan Data Register The format of the Boundary Scan Data Register is shown in Figure 5-5 on page 58. Each GPIO pin, in a counter-clockwise direction from the JTAG port pins, is included in the Boundary Scan Data Register. Each GPIO pin has three associated digital signals that are included in the chain. These signals are input, output, and output enable, and are arranged in that order as can be seen in the figure. In addition to the GPIO pins, the controller reset pin, RST, is included in the chain. Because the reset pin is always an input, only the input signal is included in the Data Register chain. When the Boundary Scan Data Register is accessed with the SAMPLE/PRELOAD instruction, the input, output, and output enable from each digital pad are sampled and then shifted out of the chain to be verified. The sampling of these values occurs on the rising edge of TCK in the Capture DR state of the TAP controller. While the sampled data is being shifted out of the Boundary Scan chain in the Shift DR state of the TAP controller, new data can be preloaded into the chain for use with the EXTEST and INTEST instructions. These instructions either force data out of the controller, with the EXTEST instruction, or into the controller, with the INTEST instruction. Figure 5-5. Boundary Scan Register Format TDI I N O U T G PIO PB6 O E ... I N O U T GP IO m O E I N RST I N O U T GPIO m+ 1 O E ... I N O U T G PIO n O TDO E For detailed information on the order of the input, output, and output enable bits for each of the ® GPIO ports, please refer to the Stellaris Family Boundary Scan Description Language (BSDL) files, downloadable from www.luminarymicro.com. 5.4.2.4 APACC Data Register The format for the 35-bit APACC Data Register defined by ARM is described in the ARM® Cortex™-M3 Technical Reference Manual. 5.4.2.5 DPACC Data Register The format for the 35-bit DPACC Data Register defined by ARM is described in the ARM® Cortex™-M3 Technical Reference Manual. 5.4.2.6 ABORT Data Register The format for the 35-bit ABORT Data Register defined by ARM is described in the ARM® Cortex™-M3 Technical Reference Manual. 58 Preliminary November 30, 2007 LM3S6965 Microcontroller 6 System Control System control determines the overall operation of the device. It provides information about the device, controls the clocking to the core and individual peripherals, and handles reset detection and reporting. 6.1 Functional Description The System Control module provides the following capabilities: ■ Device identification, see “Device Identification” on page 59 ■ Local control, such as reset (see “Reset Control” on page 59), power (see “Power Control” on page 62) and clock control (see “Clock Control” on page 62) ■ System control (Run, Sleep, and Deep-Sleep modes), see “System Control” on page 64 6.1.1 Device Identification Seven read-only registers provide software with information on the microcontroller, such as version, part number, SRAM size, flash size, and other features. See the DID0, DID1, and DC0-DC4 registers. 6.1.2 Reset Control This section discusses aspects of hardware functions during reset as well as system software requirements following the reset sequence. 6.1.2.1 CMOD0 and CMOD1 Test-Mode Control Pins Two pins, CMOD0 and CMOD1, are defined for use by Luminary Micro for testing the devices during manufacture. They have no end-user function and should not be used. The CMOD pins should be connected to ground. 6.1.2.2 Reset Sources The controller has five sources of reset: 1. External reset input pin (RST) assertion, see “RST Pin Assertion” on page 59. 2. Power-on reset (POR), see “Power-On Reset (POR)” on page 60. 3. Internal brown-out (BOR) detector, see “Brown-Out Reset (BOR)” on page 60. 4. Software-initiated reset (with the software reset registers), see “Software Reset” on page 61. 5. A watchdog timer reset condition violation, see “Watchdog Timer Reset” on page 61. After a reset, the Reset Cause (RESC) register is set with the reset cause. The bits in this register are sticky and maintain their state across multiple reset sequences, except when an internal POR is the cause, and then all the other bits in the RESC register are cleared except for the POR indicator. 6.1.2.3 RST Pin Assertion The external reset pin (RST) resets the controller. This resets the core and all the peripherals except the JTAG TAP controller (see “JTAG Interface” on page 48). The external reset sequence is as follows: November 30, 2007 Preliminary 59 System Control 1. The external reset pin (RST) is asserted and then de-asserted. 2. The internal reset is released and the core loads from memory the initial stack pointer, the initial program counter, the first instruction designated by the program counter, and begins execution. A few clocks cycles from RST de-assertion to the start of the reset sequence is necessary for synchronization. The external reset timing is shown in Figure 23-11 on page 548. 6.1.2.4 Power-On Reset (POR) The Power-On Reset (POR) circuit monitors the power supply voltage (VDD). The POR circuit generates a reset signal to the internal logic when the power supply ramp reaches a threshold value (VTH). If the application only uses the POR circuit, the RST input needs to be connected to the power supply (VDD) through a pull-up resistor (1K to 10K Ω). The device must be operating within the specified operating parameters at the point when the on-chip power-on reset pulse is complete. The 3.3-V power supply to the device must reach 3.0 V within 10 msec of it crossing 2.0 V to guarantee proper operation. For applications that require the use of an external reset to hold the device in reset longer than the internal POR, the RST input may be used with the circuit as shown in Figure 6-1 on page 60. Figure 6-1. External Circuitry to Extend Reset Stellaris D1 R1 RST C1 R2 The R1 and C1 components define the power-on delay. The R2 resistor mitigates any leakage from the RST input. The diode (D1) discharges C1 rapidly when the power supply is turned off. The Power-On Reset sequence is as follows: 1. The controller waits for the later of external reset (RST) or internal POR to go inactive. 2. The internal reset is released and the core loads from memory the initial stack pointer, the initial program counter, the first instruction designated by the program counter, and begins execution. The internal POR is only active on the initial power-up of the controller. The Power-On Reset timing is shown in Figure 23-12 on page 549. Note: The power-on reset also resets the JTAG controller. An external reset does not. 6.1.2.5 Brown-Out Reset (BOR) A drop in the input voltage resulting in the assertion of the internal brown-out detector can be used to reset the controller. This is initially disabled and may be enabled by software. The system provides a brown-out detection circuit that triggers if the power supply (VDD) drops below a brown-out threshold voltage (VBTH). If a brown-out condition is detected, the system may generate a controller interrupt or a system reset. 60 Preliminary November 30, 2007 LM3S6965 Microcontroller Brown-out resets are controlled with the Power-On and Brown-Out Reset Control (PBORCTL) register. The BORIOR bit in the PBORCTL register must be set for a brown-out condition to trigger a reset. The brown-out reset is equivelent to an assertion of the external RST input and the reset is held active until the proper VDD level is restored. The RESC register can be examined in the reset interrupt handler to determine if a Brown-Out condition was the cause of the reset, thus allowing software to determine what actions are required to recover. The internal Brown-Out Reset timing is shown in Figure 23-13 on page 549. 6.1.2.6 Software Reset Software can reset a specific peripheral or generate a reset to the entire system . Peripherals can be individually reset by software via three registers that control reset signals to each peripheral (see the SRCRn registers). If the bit position corresponding to a peripheral is set and subsequently cleared, the peripheral is reset. The encoding of the reset registers is consistent with the encoding of the clock gating control for peripherals and on-chip functions (see “System Control” on page 64). Note that all reset signals for all clocks of the specified unit are asserted as a result of a software-initiated reset. The entire system can be reset by software by setting the SYSRESETREQ bit in the Cortex-M3 Application Interrupt and Reset Control register resets the entire system including the core. The software-initiated system reset sequence is as follows: 1. A software system reset is initiated by writing the SYSRESETREQ bit in the ARM Cortex-M3 Application Interrupt and Reset Control register. 2. An internal reset is asserted. 3. The internal reset is deasserted and the controller loads from memory the initial stack pointer, the initial program counter, and the first instruction designated by the program counter, and then begins execution. The software-initiated system reset timing is shown in Figure 23-14 on page 549. 6.1.2.7 Watchdog Timer Reset The watchdog timer module's function is to prevent system hangs. The watchdog timer can be configured to generate an interrupt to the controller on its first time-out, and to generate a reset signal on its second time-out. After the first time-out event, the 32-bit counter is reloaded with the value of the Watchdog Timer Load (WDTLOAD) register, and the timer resumes counting down from that value. If the timer counts down to its zero state again before the first time-out interrupt is cleared, and the reset signal has been enabled, the watchdog timer asserts its reset signal to the system. The watchdog timer reset sequence is as follows: 1. The watchdog timer times out for the second time without being serviced. 2. An internal reset is asserted. 3. The internal reset is released and the controller loads from memory the initial stack pointer, the initial program counter, the first instruction designated by the program counter, and begins execution. November 30, 2007 Preliminary 61 System Control The watchdog reset timing is shown in Figure 23-15 on page 549. 6.1.3 Power Control The Stellaris microcontroller provides an integrated LDO regulator that may be used to provide power to the majority of the controller's internal logic. The LDO regulator provides software a mechanism to adjust the regulated value, in small increments (VSTEP), over the range of 2.25 V to 2.75 V (inclusive)—or 2.5 V ± 10%. The adjustment is made by changing the value of the VADJ field in the LDO Power Control (LDOPCTL) register. Note: The use of the LDO is optional. The internal logic may be supplied by the on-chip LDO or by an external regulator. If the LDO is used, the LDO output pin is connected to the VDD25 pins on the printed circuit board. The LDO requires decoupling capacitors on the printed circuit board. If an external regulator is used, it is strongly recommended that the external regulator supply the controller only and not be shared with other devices on the printed circuit board. ® 6.1.4 6.1.4.1 Clock Control System control determines the control of clocks in this part. Fundamental Clock Sources There are four clock sources for use in the device: ■ Internal Oscillator (IOSC): The internal oscillator is an on-chip clock source. It does not require the use of any external components. The frequency of the internal oscillator is 12 MHz ± 30%. Applications that do not depend on accurate clock sources may use this clock source to reduce system cost. The internal oscillator is the clock source the device uses during and following POR. If the main oscillator is required, software must enable the main oscillator following reset and allow the main oscillator to stabilize before changing the clock reference. ■ Main Oscillator: The main oscillator provides a frequency-accurate clock source by one of two means: an external single-ended clock source is connected to the OSC0 input pin, or an external crystal is connected across the OSC0 input and OSC1 output pins. The crystal value allowed depends on whether the main oscillator is used as the clock reference source to the PLL. If so, the crystal must be one of the supported frequencies between 3.579545 MHz through 8.192 MHz (inclusive). If the PLL is not being used, the crystal may be any one of the supported frequencies between 1 MHz and 8.192 MHz. The single-ended clock source range is from DC through the specified speed of the device. The supported crystals are listed in the XTAL bit in the RCC register (see page 75). ■ Internal 30-kHz Oscillator: The internal 30-kHz oscillator is similar to the internal oscillator, except that it provides an operational frequency of 30 kHz ± 30%. It is intended for use during Deep-Sleep power-saving modes. This power-savings mode benefits from reduced internal switching and also allows the main oscillator to be powered down. ■ External Real-Time Oscillator: The external real-time oscillator provides a low-frequency, accurate clock reference. It is intended to provide the system with a real-time clock source. The real-time oscillator is part of the Hibernation Module (“Hibernation Module” on page 120) and may also provide an accurate source of Deep-Sleep or Hibernate mode power savings. The internal system clock (sysclk), is derived from any of the four sources plus two others: the output of the internal PLL, and the internal oscillator divided by four (3 MHz ± 30%). The frequency of the PLL clock reference must be in the range of 3.579545 MHz to 8.192 MHz (inclusive). 62 Preliminary November 30, 2007 LM3S6965 Microcontroller The Run-Mode Clock Configuration (RCC) and Run-Mode Clock Configuration 2 (RCC2) registers provide control for the system clock. The RCC2 register is provided to extend fields that offer additional encodings over the RCC register. When used, the RCC2 register field values are used by the logic over the corresponding field in the RCC register. In particular, RCC2 provides for a larger assortment of clock configuration options. 6.1.4.2 Crystal Configuration for the Main Oscillator (MOSC) The main oscillator supports the use of a select number of crystals. If the main oscillator is used by the PLL as a reference clock, the supported range of crystals is 3.579545 to 8.192 MHz, otherwise, the range of supported crystals is 1 to 8.192 MHz. The XTAL bit in the RCC register (see page 75) describes the available crystal choices and default programming values. Software configures the RCC register XTAL field with the crystal number. If the PLL is used in the design, the XTAL field value is internally translated to the PLL settings. 6.1.4.3 PLL Frequency Configuration The PLL is disabled by default during power-on reset and is enabled later by software if required. Software configures the PLL input reference clock source, specifies the output divisor to set the system clock frequency, and enables the PLL to drive the output. If the main oscillator provides the clock reference to the PLL, the translation provided by hardware and used to program the PLL is available for software in the XTAL to PLL Translation (PLLCFG) register (see page 79). The internal translation provides a translation within ± 1% of the targeted PLL VCO frequency. The Crystal Value field (XTAL) on page 75 describes the available crystal choices and default programming of the PLLCFG register. The crystal number is written into the XTAL field of the Run-Mode Clock Configuration (RCC) register. Any time the XTAL field changes, the new settings are translated and the internal PLL settings are updated. 6.1.4.4 PLL Modes The PLL has two modes of operation: Normal and Power-Down ■ Normal: The PLL multiplies the input clock reference and drives the output. ■ Power-Down: Most of the PLL internal circuitry is disabled and the PLL does not drive the output. The modes are programmed using the RCC/RCC2 register fields (see page 75 and page 80). 6.1.4.5 PLL Operation If the PLL configuration is changed, the PLL output frequency is unstable until it reconverges (relocks) to the new setting. The time between the configuration change and relock is TREADY (see Table 23-6 on page 538). During this time, the PLL is not usable as a clock reference. The PLL is changed by one of the following: ■ Change to the XTAL value in the RCC register—writes of the same value do not cause a relock. ■ Change in the PLL from Power-Down to Normal mode. A counter is defined to measure the TREADY requirement. The counter is clocked by the main oscillator. The range of the main oscillator has been taken into account and the down counter is set November 30, 2007 Preliminary 63 System Control to 0x1200 (that is, ~600 μs at an 8.192 MHz external oscillator clock). . Hardware is provided to keep the PLL from being used as a system clock until the TREADY condition is met after one of the two changes above. It is the user's responsibility to have a stable clock source (like the main oscillator) before the RCC/RCC2 register is switched to use the PLL. 6.1.5 System Control For power-savings purposes, the RCGCn , SCGCn , and DCGCn registers control the clock gating logic for each peripheral or block in the system while the controller is in Run, Sleep, and Deep-Sleep mode, respectively. In Run mode, the processor executes code. In Sleep mode, the clock frequency of the active peripherals is unchanged, but the processor is not clocked and therefore no longer executes code. In Deep-Sleep mode, the clock frequency of the active peripherals may change (depending on the Run mode clock configuration) in addition to the processor clock being stopped. An interrupt returns the device to Run mode from one of the sleep modes; the sleep modes are entered on request from the code. Each mode is described in more detail below. There are four levels of operation for the device defined as: ■ Run Mode. Run mode provides normal operation of the processor and all of the peripherals that are currently enabled by the RCGCn registers. The system clock can be any of the available clock sources including the PLL. ■ Sleep Mode. Sleep mode is entered by the Cortex-M3 core executing a WFI (Wait for Interrupt) instruction. Any properly configured interrupt event in the system will bring the processor back into Run mode. See the system control NVIC section of the ARM® Cortex™-M3 Technical Reference Manual for more details. In Sleep mode, the Cortex-M3 processor core and the memory subsystem are not clocked. Peripherals are clocked that are enabled in the SCGCn register when auto-clock gating is enabled (see the RCC register) or the RCGCn register when the auto-clock gating is disabled. The system clock has the same source and frequency as that during Run mode. ■ Deep-Sleep Mode. Deep-Sleep mode is entered by first writing the Deep Sleep Enable bit in the ARM Cortex-M3 NVIC system control register and then executing a WFI instruction. Any properly configured interrupt event in the system will bring the processor back into Run mode. See the system control NVIC section of the ARM® Cortex™-M3 Technical Reference Manual for more details. The Cortex-M3 processor core and the memory subsystem are not clocked. Peripherals are clocked that are enabled in the DCGCn register when auto-clock gating is enabled (see the RCC register) or the RCGCn register when auto-clock gating is disabled. The system clock source is the main oscillator by default or the internal oscillator specified in the DSLPCLKCFG register if one is enabled. When the DSLPCLKCFG register is used, the internal oscillator is powered up, if necessary, and the main oscillator is powered down. If the PLL is running at the time of the WFI instruction, hardware will power the PLL down and override the SYSDIV field of the active RCC/RCC2 register to be /16 or /64, respectively. When the Deep-Sleep exit event occurs, hardware brings the system clock back to the source and frequency it had at the onset of Deep-Sleep mode before enabling the clocks that had been stopped during the Deep-Sleep duration. ■ Hibernate Mode. In this mode, the power supplies are turned off to the main part of the device and only the Hibernation module's circuitry is active. An external wake event or RTC event is required to bring the device back to Run mode. The Cortex-M3 processor and peripherals outside 64 Preliminary November 30, 2007 LM3S6965 Microcontroller of the Hibernation module see a normal "power on" sequence and the processor starts running code. It can determine that it has been restarted from Hibernate mode by inspecting the Hibernation module registers. 6.2 Initialization and Configuration The PLL is configured using direct register writes to the RCC/RCC2 register. If the RCC2 register is being used, the USERCC2 bit must be set and the appropriate RCC2 bit/field is used. The steps required to successfully change the PLL-based system clock are: 1. Bypass the PLL and system clock divider by setting the BYPASS bit and clearing the USESYS bit in the RCC register. This configures the system to run off a “raw” clock source (using the main oscillator or internal oscillator) and allows for the new PLL configuration to be validated before switching the system clock to the PLL. 2. Select the crystal value (XTAL) and oscillator source (OSCSRC), and clear the PWRDN bit in RCC/RCC2. Setting the XTAL field automatically pulls valid PLL configuration data for the appropriate crystal, and clearing the PWRDN bit powers and enables the PLL and its output. 3. Select the desired system divider (SYSDIV) in RCC/RCC2 and set the USESYS bit in RCC. The SYSDIV field determines the system frequency for the microcontroller. 4. Wait for the PLL to lock by polling the PLLLRIS bit in the Raw Interrupt Status (RIS) register. 5. Enable use of the PLL by clearing the BYPASS bit in RCC/RCC2. 6.3 Register Map Table 6-1 on page 65 lists the System Control registers, grouped by function. The offset listed is a hexadecimal increment to the register ’s address, relative to the System Control base address of 0x400F.E000. Note: Spaces in the System Control register space that are not used are reserved for future or internal use by Luminary Micro, Inc. Software should not modify any reserved memory address. Table 6-1. System Control Register Map Offset 0x000 0x004 0x008 0x010 0x014 0x018 0x01C 0x030 0x034 Name DID0 DID1 DC0 DC1 DC2 DC3 DC4 PBORCTL LDOPCTL Type RO RO RO RO RO RO RO R/W R/W Reset 0x00FF.007F 0x0011.33FF 0x030F.5317 0x0F0F.87FF 0x5000.007F 0x0000.7FFD 0x0000.0000 Description Device Identification 0 Device Identification 1 Device Capabilities 0 Device Capabilities 1 Device Capabilities 2 Device Capabilities 3 Device Capabilities 4 Brown-Out Reset Control LDO Power Control See page 67 83 85 86 88 90 92 69 70 November 30, 2007 Preliminary 65 System Control Offset 0x040 0x044 0x048 0x050 0x054 0x058 0x05C 0x060 0x064 0x070 0x100 0x104 0x108 0x110 0x114 0x118 0x120 0x124 0x128 0x144 Name SRCR0 SRCR1 SRCR2 RIS IMC MISC RESC RCC PLLCFG RCC2 RCGC0 RCGC1 RCGC2 SCGC0 SCGC1 SCGC2 DCGC0 DCGC1 DCGC2 DSLPCLKCFG Type R/W R/W R/W RO R/W R/W1C R/W R/W RO R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 0x00000000 0x00000000 0x00000000 0x0000.0000 0x0000.0000 0x0000.0000 0x07AE.3AD1 0x0780.2800 0x00000040 0x00000000 0x00000000 0x00000040 0x00000000 0x00000000 0x00000040 0x00000000 0x00000000 0x0780.0000 Description Software Reset Control 0 Software Reset Control 1 Software Reset Control 2 Raw Interrupt Status Interrupt Mask Control Masked Interrupt Status and Clear Reset Cause Run-Mode Clock Configuration XTAL to PLL Translation Run-Mode Clock Configuration 2 Run Mode Clock Gating Control Register 0 Run Mode Clock Gating Control Register 1 Run Mode Clock Gating Control Register 2 Sleep Mode Clock Gating Control Register 0 Sleep Mode Clock Gating Control Register 1 Sleep Mode Clock Gating Control Register 2 Deep Sleep Mode Clock Gating Control Register 0 Deep Sleep Mode Clock Gating Control Register 1 Deep Sleep Mode Clock Gating Control Register 2 Deep Sleep Clock Configuration See page 115 116 118 71 72 73 74 75 79 80 94 100 109 96 103 111 98 106 113 82 6.4 Register Descriptions All addresses given are relative to the System Control base address of 0x400F.E000. 66 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 1: Device Identification 0 (DID0), offset 0x000 This register identifies the version of the device. Device Identification 0 (DID0) Base 0x400F.E000 Offset 0x000 Type RO, reset 31 reserved Type Reset RO 0 15 RO 0 14 30 29 VER RO 0 13 RO 1 12 MAJOR Type Reset RO RO RO RO RO RO RO RO RO RO RO RO 0 11 28 27 26 25 24 23 22 21 20 CLASS RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 MINOR RO RO RO RO RO RO 0 3 RO 0 2 RO 0 1 RO 1 0 19 18 17 16 reserved RO 0 10 RO 0 9 Bit/Field 31 Name reserved Type RO Reset 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. DID0 Version This field defines the DID0 register format version. The version number is numeric. The value of the VER field is encoded as follows: Value Description 0x1 First revision of the DID0 register format, for Stellaris® Fury-class devices . 30:28 VER RO 0x1 27:24 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Device Class The CLASS field value identifies the internal design from which all mask sets are generated for all devices in a particular product line. The CLASS field value is changed for new product lines, for changes in fab process (for example, a remap or shrink), or any case where the MAJOR or MINOR fields require differentiation from prior devices. The value of the CLASS field is encoded as follows (all other encodings are reserved): Value Description 0x0 0x1 Stellaris® Sandstorm-class devices. Stellaris® Fury-class devices. 23:16 CLASS RO 0x1 November 30, 2007 Preliminary 67 System Control Bit/Field 15:8 Name MAJOR Type RO Reset - Description Major Revision This field specifies the major revision number of the device. The major revision reflects changes to base layers of the design. The major revision number is indicated in the part number as a letter (A for first revision, B for second, and so on). This field is encoded as follows: Value Description 0x0 0x1 0x2 Revision A (initial device) Revision B (first base layer revision) Revision C (second base layer revision) and so on. 7:0 MINOR RO Minor Revision This field specifies the minor revision number of the device. The minor revision reflects changes to the metal layers of the design. The MINOR field value is reset when the MAJOR field is changed. This field is numeric and is encoded as follows: Value Description 0x0 0x1 0x2 Initial device, or a major revision update. First metal layer change. Second metal layer change. and so on. 68 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 2: Brown-Out Reset Control (PBORCTL), offset 0x030 This register is responsible for controlling reset conditions after initial power-on reset. Brown-Out Reset Control (PBORCTL) Base 0x400F.E000 Offset 0x030 Type R/W, reset 0x0000.7FFD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 BORIOR reserved R/W 0 RO 0 Bit/Field 31:2 Name reserved Type RO Reset 0x0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. BOR Interrupt or Reset This bit controls how a BOR event is signaled to the controller. If set, a reset is signaled. Otherwise, an interrupt is signaled. 1 BORIOR R/W 0 0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. November 30, 2007 Preliminary 69 System Control Register 3: LDO Power Control (LDOPCTL), offset 0x034 The VADJ field in this register adjusts the on-chip output voltage (VOUT). LDO Power Control (LDOPCTL) Base 0x400F.E000 Offset 0x034 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 VADJ RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:6 Name reserved Type RO Reset 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. LDO Output Voltage This field sets the on-chip output voltage. The programming values for the VADJ field are provided below. Value 0x00 0x01 0x02 0x03 0x04 0x05 VOUT (V) 2.50 2.45 2.40 2.35 2.30 2.25 5:0 VADJ R/W 0x0 0x06-0x3F Reserved 0x1B 0x1C 0x1D 0x1E 0x1F 2.75 2.70 2.65 2.60 2.55 70 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 4: Raw Interrupt Status (RIS), offset 0x050 Central location for system control raw interrupts. These are set and cleared by hardware. Raw Interrupt Status (RIS) Base 0x400F.E000 Offset 0x050 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 PLLLRIS RO 0 RO 0 RO 0 5 RO 0 4 reserved RO 0 RO 0 RO 0 RO 0 3 RO 0 2 RO 0 1 RO 0 0 BORRIS reserved RO 0 RO 0 Bit/Field 31:7 Name reserved Type RO Reset 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. PLL Lock Raw Interrupt Status This bit is set when the PLL TREADY Timer asserts. 6 PLLLRIS RO 0 5:2 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Brown-Out Reset Raw Interrupt Status This bit is the raw interrupt status for any brown-out conditions. If set, a brown-out condition is currently active. This is an unregistered signal from the brown-out detection circuit. An interrupt is reported if the BORIM bit in the IMC register is set and the BORIOR bit in the PBORCTL register is cleared. 1 BORRIS RO 0 0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. November 30, 2007 Preliminary 71 System Control Register 5: Interrupt Mask Control (IMC), offset 0x054 Central location for system control interrupt masks. Interrupt Mask Control (IMC) Base 0x400F.E000 Offset 0x054 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 PLLLIM R/W 0 RO 0 RO 0 5 RO 0 4 reserved RO 0 RO 0 RO 0 RO 0 3 RO 0 2 RO 0 1 BORIM R/W 0 RO 0 0 reserved RO 0 Bit/Field 31:7 Name reserved Type RO Reset 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. PLL Lock Interrupt Mask This bit specifies whether a current limit detection is promoted to a controller interrupt. If set, an interrupt is generated if PLLLRIS in RIS is set; otherwise, an interrupt is not generated. 6 PLLLIM R/W 0 5:2 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Brown-Out Reset Interrupt Mask This bit specifies whether a brown-out condition is promoted to a controller interrupt. If set, an interrupt is generated if BORRIS is set; otherwise, an interrupt is not generated. 1 BORIM R/W 0 0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 72 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 6: Masked Interrupt Status and Clear (MISC), offset 0x058 Central location for system control result of RIS AND IMC to generate an interrupt to the controller. All of the bits are R/W1C and this action also clears the corresponding raw interrupt bit in the RIS register (see page 71). Masked Interrupt Status and Clear (MISC) Base 0x400F.E000 Offset 0x058 Type R/W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 PLLLMIS R/W1C 0 RO 0 RO 0 5 RO 0 4 reserved RO 0 RO 0 RO 0 RO 0 3 RO 0 2 RO 0 1 RO 0 0 BORMIS reserved R/W1C 0 RO 0 Bit/Field 31:7 Name reserved Type RO Reset 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. PLL Lock Masked Interrupt Status This bit is set when the PLL TREADY timer asserts. The interrupt is cleared by writing a 1 to this bit. 6 PLLLMIS R/W1C 0 5:2 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. BOR Masked Interrupt Status The BORMIS is simply the BORRIS ANDed with the mask value, BORIM. 1 BORMIS R/W1C 0 0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. November 30, 2007 Preliminary 73 System Control Register 7: Reset Cause (RESC), offset 0x05C This register is set with the reset cause after reset. The bits in this register are sticky and maintain their state across multiple reset sequences, except when an external reset is the cause, and then all the other bits in the RESC register are cleared. Reset Cause (RESC) Base 0x400F.E000 Offset 0x05C Type R/W, reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 LDO RO 0 RO 0 RO 0 RO 0 R/W RO 0 4 SW R/W RO 0 3 WDT R/W RO 0 2 BOR R/W RO 0 1 POR R/W RO 0 0 EXT R/W - reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:6 Name reserved Type RO Reset 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. LDO Reset When set, indicates the LDO circuit has lost regulation and has generated a reset event. 5 LDO R/W - 4 SW R/W - Software Reset When set, indicates a software reset is the cause of the reset event. 3 WDT R/W - Watchdog Timer Reset When set, indicates a watchdog reset is the cause of the reset event. 2 BOR R/W - Brown-Out Reset When set, indicates a brown-out reset is the cause of the reset event. 1 POR R/W - Power-On Reset When set, indicates a power-on reset is the cause of the reset event. 0 EXT R/W - External Reset When set, indicates an external reset (RST assertion) is the cause of the reset event. 74 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 8: Run-Mode Clock Configuration (RCC), offset 0x060 This register is defined to provide source control and frequency speed. Run-Mode Clock Configuration (RCC) Base 0x400F.E000 Offset 0x060 Type R/W, reset 0x07AE.3AD1 31 30 29 28 27 ACG RO 0 12 R/W 0 11 R/W 1 10 26 25 24 23 22 USESYSDIV 21 20 19 18 PWMDIV 17 16 reserved reserved Type Reset RO 0 15 RO 0 14 RO 0 13 SYSDIV R/W 1 9 R/W 1 8 XTAL R/W 1 R/W 0 R/W 1 R/W 1 7 reserved USEPWMDIV RO 0 5 R/W 0 4 R/W 1 3 R/W 0 6 R/W 1 2 R/W 1 1 RO 0 0 reserved Type Reset RO 0 RO 0 PWRDN reserved BYPASS reserved R/W 1 RO 1 R/W 1 RO 0 OSCSRC R/W 1 R/W 0 R/W 1 reserved RO 0 RO 0 IOSCDIS MOSCDIS R/W 0 R/W 1 Bit/Field 31:28 Name reserved Type RO Reset 0x0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Auto Clock Gating This bit specifies whether the system uses the Sleep-Mode Clock Gating Control (SCGCn) registers and Deep-Sleep-Mode Clock Gating Control (DCGCn) registers if the controller enters a Sleep or Deep-Sleep mode (respectively). If set, the SCGCn or DCGCn registers are used to control the clocks distributed to the peripherals when the controller is in a sleep mode. Otherwise, the Run-Mode Clock Gating Control (RCGCn) registers are used when the controller enters a sleep mode. The RCGCn registers are always used to control the clocks in Run mode. This allows peripherals to consume less power when the controller is in a sleep mode and the peripheral is unused. 27 ACG R/W 0 November 30, 2007 Preliminary 75 System Control Bit/Field 26:23 Name SYSDIV Type R/W Reset 0xF Description System Clock Divisor Specifies which divisor is used to generate the system clock from the PLL output. The PLL VCO frequency is 400 MHz. Value Divisor (BYPASS=1) Frequency (BYPASS=0) 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF reserved /2 /3 /4 /5 /6 /7 /8 /9 /10 /11 /12 /13 /14 /15 /16 reserved reserved reserved 50 MHz 40 MHz 33.33 MHz 28.57 MHz 25 MHz 22.22 MHz 20 MHz 18.18 MHz 16.67 MHz 15.38 MHz 14.29 MHz 13.33 MHz 12.5 MHz (default) When reading the Run-Mode Clock Configuration (RCC) register (see page 75), the SYSDIV value is MINSYSDIV if a lower divider was requested and the PLL is being used. This lower value is allowed to divide a non-PLL source. 22 USESYSDIV R/W 0 Enable System Clock Divider Use the system clock divider as the source for the system clock. The system clock divider is forced to be used when the PLL is selected as the source. 21 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Enable PWM Clock Divisor Use the PWM clock divider as the source for the PWM clock. 20 USEPWMDIV R/W 0 76 Preliminary November 30, 2007 LM3S6965 Microcontroller Bit/Field 19:17 Name PWMDIV Type R/W Reset 0x7 Description PWM Unit Clock Divisor This field specifies the binary divisor used to predivide the system clock down for use as the timing reference for the PWM module. This clock is only power 2 divide and rising edge is synchronous without phase shift from the system clock. Value Divisor 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 /2 /4 /8 /16 /32 /64 /64 /64 (default) 16:14 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. PLL Power Down This bit connects to the PLL PWRDN input. The reset value of 1 powers down the PLL. 13 PWRDN R/W 1 12 reserved RO 1 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. PLL Bypass Chooses whether the system clock is derived from the PLL output or the OSC source. If set, the clock that drives the system is the OSC source. Otherwise, the clock that drives the system is the PLL output clock divided by the system divider. Note: The ADC must be clocked from the PLL or directly from a 14-MHz to 18-MHz clock source to operate properly. While the ADC works in a 14-18 MHz range, to maintain a 1 M sample/second rate, the ADC must be provided a 16-MHz clock source. 11 BYPASS R/W 1 10 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. November 30, 2007 Preliminary 77 System Control Bit/Field 9:6 Name XTAL Type R/W Reset 0xB Description Crystal Value This field specifies the crystal value attached to the main oscillator. The encoding for this field is provided below. Value 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF Crystal Frequency (MHz) Not Using the PLL 1.000 1.8432 2.000 2.4576 3.579545 MHz 3.6864 MHz 4 MHz 4.096 MHz 4.9152 MHz 5 MHz 5.12 MHz 6 MHz (reset value) 6.144 MHz 7.3728 MHz 8 MHz 8.192 MHz Crystal Frequency (MHz) Using the PLL reserved reserved reserved reserved 5:4 OSCSRC R/W 0x1 Oscillator Source Picks among the four input sources for the OSC. The values are: Value Input Source 0x0 0x1 0x2 0x3 Main oscillator (default) Internal oscillator (default) Internal oscillator / 4 (this is necessary if used as input to PLL) reserved 3:2 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Internal Oscillator Disable 0: Internal oscillator (IOSC) is enabled. 1: Internal oscillator is disabled. 1 IOSCDIS R/W 0 0 MOSCDIS R/W 1 Main Oscillator Disable 0: Main oscillator is enabled. 1: Main oscillator is disabled (default). 78 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 9: XTAL to PLL Translation (PLLCFG), offset 0x064 This register provides a means of translating external crystal frequencies into the appropriate PLL settings. This register is initialized during the reset sequence and updated anytime that the XTAL field changes in the Run-Mode Clock Configuration (RCC) register (see page 75). The PLL frequency is calculated using the PLLCFG field values, as follows: PLLFreq = OSCFreq * F / (R + 1) XTAL to PLL Translation (PLLCFG) Base 0x400F.E000 Offset 0x064 Type RO, reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 F RO RO RO RO RO RO RO RO RO RO RO RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 R RO RO RO RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 Bit/Field 31:14 Name reserved Type RO Reset 0x0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. PLL F Value This field specifies the value supplied to the PLL’s F input. 13:5 F RO - 4:0 R RO - PLL R Value This field specifies the value supplied to the PLL’s R input. November 30, 2007 Preliminary 79 System Control Register 10: Run-Mode Clock Configuration 2 (RCC2), offset 0x070 This register overrides the RCC equivalent register fields when the USERCC2 bit is set. This allows RCC2 to be used to extend the capabilities, while also providing a means to be backward-compatible to previous parts. The fields within the RCC2 register occupy the same bit positions as they do within the RCC register as LSB-justified. The SYSDIV2 field is wider so that additional larger divisors are possible. This allows a lower system clock frequency for improved Deep Sleep power consumption. Run-Mode Clock Configuration 2 (RCC2) Base 0x400F.E000 Offset 0x070 Type R/W, reset 0x0780.2800 31 USERCC2 Type Reset R/W 0 15 30 29 28 27 26 25 24 23 22 21 20 19 reserved R/W 1 8 reserved RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 1 7 RO 0 6 RO 0 5 OSCSRC2 R/W 0 R/W 0 RO 0 RO 0 4 RO 0 3 RO 0 2 reserved RO 0 RO 0 RO 0 RO 0 1 RO 0 0 18 17 16 reserved RO 0 14 RO 0 13 R/W 0 12 R/W 0 11 SYSDIV2 R/W 1 10 R/W 1 9 reserved Type Reset RO 0 RO 0 PWRDN2 reserved BYPASS2 R/W 1 RO 0 R/W 1 Bit/Field 31 Name USERCC2 Type R/W Reset 0 Description Use RCC2 When set, overrides the RCC register fields. 30:29 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. System Clock Divisor Specifies which divisor is used to generate the system clock from the PLL output. The PLL VCO frequency is 400 MHz. This field is wider than the RCC register SYSDIV field in order to provide additional divisor values. This permits the system clock to be run at much lower frequencies during Deep Sleep mode. For example, where the RCC register SYSDIV encoding of 1111 provides /16, the RCC2 register SYSDIV2 encoding of 111111 provides /64. 28:23 SYSDIV2 R/W 0x0F 22:14 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Power-Down PLL When set, powers down the PLL. 13 PWRDN2 R/W 1 12 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Bypass PLL When set, bypasses the PLL for the clock source. 11 BYPASS2 R/W 1 80 Preliminary November 30, 2007 LM3S6965 Microcontroller Bit/Field 10:7 Name reserved Type RO Reset 0x0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. System Clock Source Value Description 0x0 0x1 0x2 0x3 0x7 Main oscillator (MOSC) Internal oscillator (IOSC) Internal oscillator / 4 30 kHz internal oscillator 32 kHz external oscillator 6:4 OSCSRC2 R/W 0x0 3:0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. November 30, 2007 Preliminary 81 System Control Register 11: Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 This register provides configuration information for the hardware control of Deep Sleep Mode. Deep Sleep Clock Configuration (DSLPCLKCFG) Base 0x400F.E000 Offset 0x144 Type R/W, reset 0x0780.0000 31 30 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 R/W 0 12 R/W 0 11 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 29 28 27 26 25 24 23 22 21 20 19 reserved R/W 1 8 R/W 1 7 RO 0 6 RO 0 5 DSOSCSRC R/W 0 R/W 0 RO 0 RO 0 4 RO 0 3 RO 0 2 reserved RO 0 RO 0 RO 0 RO 0 1 RO 0 0 18 17 16 DSDIVORIDE R/W 1 10 R/W 1 9 Bit/Field 31:29 Name reserved Type RO Reset 0x0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Divider Field Override 6-bit system divider field to override when Deep-Sleep occurs with PLL running. 28:23 DSDIVORIDE R/W 0x0F 22:7 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Clock Source When set, forces IOSC to be clock source during Deep Sleep mode. Value Name 0x0 0x1 0x3 0x7 Description 6:4 DSOSCSRC R/W 0x0 NOORIDE No override to the oscillator clock source is done IOSC 30kHz 32kHz Use internal 12 MHz oscillator as source Use 30 kHz internal oscillator Use 32 kHz external oscillator 3:0 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 82 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 12: Device Identification 1 (DID1), offset 0x004 This register identifies the device family, part number, temperature range, pin count, and package type. Device Identification 1 (DID1) Base 0x400F.E000 Offset 0x004 Type RO, reset 31 30 VER Type Reset RO 0 15 RO 0 14 PINCOUNT Type Reset RO 0 RO 1 RO 0 RO 0 RO 0 RO 0 13 RO 1 12 RO 0 11 RO 0 10 reserved RO 0 RO 0 RO 0 RO 0 29 28 27 26 FAM RO 0 9 RO 0 8 RO 0 7 RO 1 6 TEMP RO 0 RO 1 RO 0 RO 1 5 25 24 23 22 21 20 19 18 17 16 PARTNO RO 1 4 PKG RO 1 RO 0 3 RO 0 2 ROHS RO 1 RO RO 1 1 QUAL RO RO 1 0 Bit/Field 31:28 Name VER Type RO Reset 0x1 Description DID1 Version This field defines the DID1 register format version. The version number is numeric. The value of the VER field is encoded as follows (all other encodings are reserved): Value Description 0x1 First revision of the DID1 register format, indicating a Stellaris Fury-class device. 27:24 FAM RO 0x0 Family This field provides the family identification of the device within the Luminary Micro product portfolio. The value is encoded as follows (all other encodings are reserved): Value Description 0x0 Stellaris family of microcontollers, that is, all devices with external part numbers starting with LM3S. 23:16 PARTNO RO 0x73 Part Number This field provides the part number of the device within the family. The value is encoded as follows (all other encodings are reserved): Value Description 0x73 LM3S6965 15:13 PINCOUNT RO 0x2 Package Pin Count This field specifies the number of pins on the device package. The value is encoded as follows (all other encodings are reserved): Value Description 0x2 100-pin package November 30, 2007 Preliminary 83 System Control Bit/Field 12:8 Name reserved Type RO Reset 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Temperature Range This field specifies the temperature rating of the device. The value is encoded as follows (all other encodings are reserved): Value Description 0x1 Industrial temperature range (-40°C to 85°C) 7:5 TEMP RO 0x1 4:3 PKG RO 0x1 Package Type This field specifies the package type. The value is encoded as follows (all other encodings are reserved): Value Description 0x1 LQFP package 2 ROHS RO 1 RoHS-Compliance This bit specifies whether the device is RoHS-compliant. A 1 indicates the part is RoHS-compliant. 1:0 QUAL RO - Qualification Status This field specifies the qualification status of the device. The value is encoded as follows (all other encodings are reserved): Value Description 0x0 0x1 0x2 Engineering Sample (unqualified) Pilot Production (unqualified) Fully Qualified 84 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 13: Device Capabilities 0 (DC0), offset 0x008 This register is predefined by the part and can be used to verify features. Device Capabilities 0 (DC0) Base 0x400F.E000 Offset 0x008 Type RO, reset 0x00FF.007F 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SRAMSZ Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 1 7 RO 1 6 RO 1 5 RO 1 4 RO 1 3 RO 1 2 RO 1 1 RO 1 0 FLASHSZ Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 Bit/Field 31:16 Name SRAMSZ Type RO Reset 0x00FF Description SRAM Size Indicates the size of the on-chip SRAM memory. Value Description 0x00FF 64 KB of SRAM 15:0 FLASHSZ RO 0x007F Flash Size Indicates the size of the on-chip flash memory. Value Description 0x007F 256 KB of Flash November 30, 2007 Preliminary 85 System Control Register 14: Device Capabilities 1 (DC1), offset 0x010 This register provides a list of features available in the system. The Stellaris family uses this register format to indicate the availability of the following family features in the specific device: CANs, PWM, ADC, Watchdog timer, Hibernation module, and debug capabilities. This register also indicates the maximum clock frequency and maximum ADC sample rate. The format of this register is consistent with the RCGC0, SCGC0, and DCGC0 clock control registers and the SRCR0 software reset control register. Device Capabilities 1 (DC1) Base 0x400F.E000 Offset 0x010 Type RO, reset 0x0011.33FF 31 30 29 28 27 26 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 MPU RO 1 RO 1 RO 0 6 HIB RO 1 RO 0 5 TEMPSNS RO 1 25 24 23 22 21 20 PWM RO 1 4 PLL RO 1 RO 0 3 WDT RO 1 19 18 reserved RO 0 2 SWO RO 1 RO 0 1 SWD RO 1 17 16 ADC RO 1 0 JTAG RO 1 MINSYSDIV Type Reset RO 0 RO 0 RO 1 RO 1 RO 0 MAXADCSPD RO 0 RO 1 Bit/Field 31:21 Name reserved Type RO Reset 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. PWM Module Present When set, indicates that the PWM module is present. 20 PWM RO 1 19:17 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. ADC Module Present When set, indicates that the ADC module is present. 16 ADC RO 1 15:12 MINSYSDIV RO 0x3 System Clock Divider Minimum 4-bit divider value for system clock. The reset value is hardware-dependent. See the RCC register for how to change the system clock divisor using the SYSDIV bit. Value Description 0x3 Specifies a 50-MHz CPU clock with a PLL divider of 4. 11:8 MAXADCSPD RO 0x3 Max ADC Speed Indicates the maximum rate at which the ADC samples data. Value Description 0x3 1M samples/second 86 Preliminary November 30, 2007 LM3S6965 Microcontroller Bit/Field 7 Name MPU Type RO Reset 1 Description MPU Present When set, indicates that the Cortex-M3 Memory Protection Unit (MPU) module is present. See the ARM Cortex-M3 Technical Reference Manual for details on the MPU. 6 HIB RO 1 Hibernation Module Present When set, indicates that the Hibernation module is present. 5 TEMPSNS RO 1 Temp Sensor Present When set, indicates that the on-chip temperature sensor is present. 4 PLL RO 1 PLL Present When set, indicates that the on-chip Phase Locked Loop (PLL) is present. 3 WDT RO 1 Watchdog Timer Present When set, indicates that a watchdog timer is present. 2 SWO RO 1 SWO Trace Port Present When set, indicates that the Serial Wire Output (SWO) trace port is present. 1 SWD RO 1 SWD Present When set, indicates that the Serial Wire Debugger (SWD) is present. 0 JTAG RO 1 JTAG Present When set, indicates that the JTAG debugger interface is present. November 30, 2007 Preliminary 87 System Control Register 15: Device Capabilities 2 (DC2), offset 0x014 This register provides a list of features available in the system. The Stellaris family uses this register format to indicate the availability of the following family features in the specific device: Analog Comparators, General-Purpose Timers, I2Cs, QEIs, SSIs, and UARTs. The format of this register is consistent with the RCGC1, SCGC1, and DCGC1 clock control registers and the SRCR1 software reset control register. Device Capabilities 2 (DC2) Base 0x400F.E000 Offset 0x014 Type RO, reset 0x030F.5317 31 30 29 28 27 26 25 COMP1 RO 0 11 RO 0 10 RO 1 9 QEI1 RO 1 24 COMP0 RO 1 8 QEI0 RO 1 RO 0 RO 0 7 23 22 21 20 19 TIMER3 RO 0 4 SSI0 RO 0 RO 1 RO 1 3 reserved RO 0 18 TIMER2 RO 1 2 UART2 RO 1 17 TIMER1 RO 1 1 UART1 RO 1 16 TIMER0 RO 1 0 UART0 RO 1 reserved Type Reset RO 0 15 reserved Type Reset RO 0 RO 0 14 I2C1 RO 1 RO 0 13 reserved RO 0 RO 0 12 I2C0 RO 1 reserved RO 0 6 reserved RO 0 RO 0 5 reserved RO 0 RO 0 Bit/Field 31:26 Name reserved Type RO Reset 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Analog Comparator 1 Present When set, indicates that analog comparator 1 is present. 25 COMP1 RO 1 24 COMP0 RO 1 Analog Comparator 0 Present When set, indicates that analog comparator 0 is present. 23:20 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Timer 3 Present When set, indicates that General-Purpose Timer module 3 is present. 19 TIMER3 RO 1 18 TIMER2 RO 1 Timer 2 Present When set, indicates that General-Purpose Timer module 2 is present. 17 TIMER1 RO 1 Timer 1 Present When set, indicates that General-Purpose Timer module 1 is present. 16 TIMER0 RO 1 Timer 0 Present When set, indicates that General-Purpose Timer module 0 is present. 15 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. I2C Module 1 Present When set, indicates that I2C module 1 is present. 14 I2C1 RO 1 88 Preliminary November 30, 2007 LM3S6965 Microcontroller Bit/Field 13 Name reserved Type RO Reset 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. I2C Module 0 Present When set, indicates that I2C module 0 is present. 12 I2C0 RO 1 11:10 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. QEI1 Present When set, indicates that QEI module 1 is present. 9 QEI1 RO 1 8 QEI0 RO 1 QEI0 Present When set, indicates that QEI module 0 is present. 7:5 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SSI0 Present When set, indicates that SSI module 0 is present. 4 SSI0 RO 1 3 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. UART2 Present When set, indicates that UART module 2 is present. 2 UART2 RO 1 1 UART1 RO 1 UART1 Present When set, indicates that UART module 1 is present. 0 UART0 RO 1 UART0 Present When set, indicates that UART module 0 is present. November 30, 2007 Preliminary 89 System Control Register 16: Device Capabilities 3 (DC3), offset 0x018 This register provides a list of features available in the system. The Stellaris family uses this register format to indicate the availability of the following family features in the specific device: Analog Comparator I/Os, CCP I/Os, ADC I/Os, and PWM I/Os. Device Capabilities 3 (DC3) Base 0x400F.E000 Offset 0x018 Type RO, reset 0x0F0F.87FF 31 30 29 28 27 CCP3 RO 0 12 RO 1 11 26 CCP2 RO 1 10 25 CCP1 RO 1 9 24 CCP0 RO 1 8 C0O RO 1 RO 0 7 23 22 21 20 19 ADC3 RO 0 4 PWM4 RO 1 RO 1 3 PWM3 RO 1 18 ADC2 RO 1 2 PWM2 RO 1 17 ADC1 RO 1 1 PWM1 RO 1 16 ADC0 RO 1 0 PWM0 RO 1 reserved Type Reset RO 0 15 PWMFAUL T Type Reset RO 1 RO 0 RO 0 14 RO 0 13 reserved RO 0 6 RO 0 5 PWM5 RO 1 reserved RO 0 RO 0 RO 0 C1PLUS C1MINUS RO 1 RO 1 C0PLUS C0MINUS RO 1 RO 1 Bit/Field 31:28 Name reserved Type RO Reset 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. CCP3 Pin Present When set, indicates that Capture/Compare/PWM pin 3 is present. 27 CCP3 RO 1 26 CCP2 RO 1 CCP2 Pin Present When set, indicates that Capture/Compare/PWM pin 2 is present. 25 CCP1 RO 1 CCP1 Pin Present When set, indicates that Capture/Compare/PWM pin 1 is present. 24 CCP0 RO 1 CCP0 Pin Present When set, indicates that Capture/Compare/PWM pin 0 is present. 23:20 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. ADC3 Pin Present When set, indicates that ADC pin 3 is present. 19 ADC3 RO 1 18 ADC2 RO 1 ADC2 Pin Present When set, indicates that ADC pin 2 is present. 17 ADC1 RO 1 ADC1 Pin Present When set, indicates that ADC pin 1 is present. 16 ADC0 RO 1 ADC0 Pin Present When set, indicates that ADC pin 0 is present. 90 Preliminary November 30, 2007 LM3S6965 Microcontroller Bit/Field 15 Name PWMFAULT Type RO Reset 1 Description PWM Fault Pin Present When set, indicates that the PWM Fault pin is present. 14:11 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. C1+ Pin Present When set, indicates that the analog comparator 1 (+) input pin is present. 10 C1PLUS RO 1 9 C1MINUS RO 1 C1- Pin Present When set, indicates that the analog comparator 1 (-) input pin is present. 8 C0O RO 1 C0o Pin Present When set, indicates that the analog comparator 0 output pin is present. 7 C0PLUS RO 1 C0+ Pin Present When set, indicates that the analog comparator 0 (+) input pin is present. 6 C0MINUS RO 1 C0- Pin Present When set, indicates that the analog comparator 0 (-) input pin is present. 5 PWM5 RO 1 PWM5 Pin Present When set, indicates that the PWM pin 5 is present. 4 PWM4 RO 1 PWM4 Pin Present When set, indicates that the PWM pin 4 is present. 3 PWM3 RO 1 PWM3 Pin Present When set, indicates that the PWM pin 3 is present. 2 PWM2 RO 1 PWM2 Pin Present When set, indicates that the PWM pin 2 is present. 1 PWM1 RO 1 PWM1 Pin Present When set, indicates that the PWM pin 1 is present. 0 PWM0 RO 1 PWM0 Pin Present When set, indicates that the PWM pin 0 is present. November 30, 2007 Preliminary 91 System Control Register 17: Device Capabilities 4 (DC4), offset 0x01C This register provides a list of features available in the system. The Stellaris family uses this register format to indicate the availability of the following family features in the specific device: Ethernet MAC and PHY, GPIOs, and CCP I/Os. The format of this register is consistent with the RCGC2, SCGC2, and DCGC2 clock control registers and the SRCR2 software reset control register. Device Capabilities 4 (DC4) Base 0x400F.E000 Offset 0x01C Type RO, reset 0x5000.007F 31 reserved Type Reset RO 0 15 30 EPHY0 RO 1 14 29 reserved RO 0 13 28 EMAC0 RO 1 12 RO 0 11 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 10 RO 0 9 RO 0 8 RO 0 7 27 26 25 24 23 22 21 20 19 18 17 16 reserved RO 0 6 GPIOG RO 1 RO 0 5 GPIOF RO 1 RO 0 4 GPIOE RO 1 RO 0 3 GPIOD RO 1 RO 0 2 GPIOC RO 1 RO 0 1 GPIOB RO 1 RO 0 0 GPIOA RO 1 Bit/Field 31 Name reserved Type RO Reset 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Ethernet PHY0 Present When set, indicates that Ethernet PHY module 0 is present. 30 EPHY0 RO 1 29 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Ethernet MAC0 Present When set, indicates that Ethernet MAC module 0 is present. 28 EMAC0 RO 1 27:7 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPIO Port G Present When set, indicates that GPIO Port G is present. 6 GPIOG RO 1 5 GPIOF RO 1 GPIO Port F Present When set, indicates that GPIO Port F is present. 4 GPIOE RO 1 GPIO Port E Present When set, indicates that GPIO Port E is present. 3 GPIOD RO 1 GPIO Port D Present When set, indicates that GPIO Port D is present. 2 GPIOC RO 1 GPIO Port C Present When set, indicates that GPIO Port C is present. 92 Preliminary November 30, 2007 LM3S6965 Microcontroller Bit/Field 1 Name GPIOB Type RO Reset 1 Description GPIO Port B Present When set, indicates that GPIO Port B is present. 0 GPIOA RO 1 GPIO Port A Present When set, indicates that GPIO Port A is present. November 30, 2007 Preliminary 93 System Control Register 18: Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100 This register controls the clock gating logic. Each bit controls a clock enable for a given interface, function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or units to control. This is to assure reasonable code compatibility with other family and future parts. RCGC0 is the clock configuration register for running operation, SCGC0 for Sleep operation, and DCGC0 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep modes. Run Mode Clock Gating Control Register 0 (RCGC0) Base 0x400F.E000 Offset 0x100 Type R/W, reset 0x00000040 31 30 29 28 27 26 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 reserved R/W 0 RO 0 RO 0 6 HIB R/W 0 RO 0 5 reserved RO 0 RO 0 25 24 23 22 21 20 PWM R/W 0 4 RO 0 3 WDT R/W 0 RO 0 19 18 reserved RO 0 2 RO 0 1 reserved RO 0 RO 0 17 16 ADC R/W 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 R/W 0 MAXADCSPD R/W 0 R/W 0 Bit/Field 31:21 Name reserved Type RO Reset 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. PWM Clock Gating Control This bit controls the clock gating for the PWM module. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, a read or write to the unit generates a bus fault. 20 PWM R/W 0 19:17 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. ADC0 Clock Gating Control This bit controls the clock gating for SAR ADC module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, a read or write to the unit generates a bus fault. 16 ADC R/W 0 15:12 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 94 Preliminary November 30, 2007 LM3S6965 Microcontroller Bit/Field 11:8 Name MAXADCSPD Type R/W Reset 0 Description ADC Sample Speed This field sets the rate at which the ADC samples data. You cannot set the rate higher than the maximum rate. You can set the sample rate by setting the MAXADCSPD bit as follows: Value Description 0x3 0x2 0x1 0x0 1M samples/second 500K samples/second 250K samples/second 125K samples/second 7 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. HIB Clock Gating Control This bit controls the clock gating for the Hibernation module. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. 6 HIB R/W 0 5:4 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. WDT Clock Gating Control This bit controls the clock gating for the WDT module. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, a read or write to the unit generates a bus fault. 3 WDT R/W 0 2:0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. November 30, 2007 Preliminary 95 System Control Register 19: Sleep Mode Clock Gating Control Register 0 (SCGC0), offset 0x110 This register controls the clock gating logic. Each bit controls a clock enable for a given interface, function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or units to control. This is to assure reasonable code compatibility with other family and future parts. RCGC0 is the clock configuration register for running operation, SCGC0 for Sleep operation, and DCGC0 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep modes. Sleep Mode Clock Gating Control Register 0 (SCGC0) Base 0x400F.E000 Offset 0x110 Type R/W, reset 0x00000040 31 30 29 28 27 26 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 reserved R/W 0 RO 0 RO 0 6 HIB R/W 0 RO 0 5 reserved RO 0 RO 0 25 24 23 22 21 20 PWM R/W 0 4 RO 0 3 WDT R/W 0 RO 0 19 18 reserved RO 0 2 RO 0 1 reserved RO 0 RO 0 17 16 ADC R/W 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 R/W 0 MAXADCSPD R/W 0 R/W 0 Bit/Field 31:21 Name reserved Type RO Reset 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. PWM Clock Gating Control This bit controls the clock gating for the PWM module. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, a read or write to the unit generates a bus fault. 20 PWM R/W 0 19:17 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. ADC0 Clock Gating Control This bit controls the clock gating for SAR ADC module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, a read or write to the unit generates a bus fault. 16 ADC R/W 0 15:12 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 96 Preliminary November 30, 2007 LM3S6965 Microcontroller Bit/Field 11:8 Name MAXADCSPD Type R/W Reset 0 Description ADC Sample Speed This field sets the rate at which the ADC samples data. You cannot set the rate higher than the maximum rate. You can set the sample rate by setting the MAXADCSPD bit as follows: Value Description 0x3 0x2 0x1 0x0 1M samples/second 500K samples/second 250K samples/second 125K samples/second 7 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. HIB Clock Gating Control This bit controls the clock gating for the Hibernation module. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. 6 HIB R/W 0 5:4 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. WDT Clock Gating Control This bit controls the clock gating for the WDT module. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, a read or write to the unit generates a bus fault. 3 WDT R/W 0 2:0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. November 30, 2007 Preliminary 97 System Control Register 20: Deep Sleep Mode Clock Gating Control Register 0 (DCGC0), offset 0x120 This register controls the clock gating logic. Each bit controls a clock enable for a given interface, function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or units to control. This is to assure reasonable code compatibility with other family and future parts. RCGC0 is the clock configuration register for running operation, SCGC0 for Sleep operation, and DCGC0 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep modes. Deep Sleep Mode Clock Gating Control Register 0 (DCGC0) Base 0x400F.E000 Offset 0x120 Type R/W, reset 0x00000040 31 30 29 28 27 26 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 reserved R/W 0 RO 0 RO 0 6 HIB R/W 0 RO 0 5 reserved RO 0 RO 0 25 24 23 22 21 20 PWM R/W 0 4 RO 0 3 WDT R/W 0 RO 0 19 18 reserved RO 0 2 RO 0 1 reserved RO 0 RO 0 17 16 ADC R/W 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 R/W 0 MAXADCSPD R/W 0 R/W 0 Bit/Field 31:21 Name reserved Type RO Reset 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. PWM Clock Gating Control This bit controls the clock gating for the PWM module. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, a read or write to the unit generates a bus fault. 20 PWM R/W 0 19:17 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. ADC0 Clock Gating Control This bit controls the clock gating for SAR ADC module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, a read or write to the unit generates a bus fault. 16 ADC R/W 0 15:12 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 98 Preliminary November 30, 2007 LM3S6965 Microcontroller Bit/Field 11:8 Name MAXADCSPD Type R/W Reset 0 Description ADC Sample Speed This field sets the rate at which the ADC samples data. You cannot set the rate higher than the maximum rate. You can set the sample rate by setting the MAXADCSPD bit as follows: Value Description 0x3 0x2 0x1 0x0 1M samples/second 500K samples/second 250K samples/second 125K samples/second 7 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. HIB Clock Gating Control This bit controls the clock gating for the Hibernation module. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. 6 HIB R/W 0 5:4 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. WDT Clock Gating Control This bit controls the clock gating for the WDT module. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, a read or write to the unit generates a bus fault. 3 WDT R/W 0 2:0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. November 30, 2007 Preliminary 99 System Control Register 21: Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104 This register controls the clock gating logic. Each bit controls a clock enable for a given interface, function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or units to control. This is to assure reasonable code compatibility with other family and future parts. RCGC1 is the clock configuration register for running operation, SCGC1 for Sleep operation, and DCGC1 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep modes. Run Mode Clock Gating Control Register 1 (RCGC1) Base 0x400F.E000 Offset 0x104 Type R/W, reset 0x00000000 31 30 29 28 27 26 25 COMP1 RO 0 11 RO 0 10 R/W 0 9 QEI1 R/W 0 24 COMP0 R/W 0 8 QEI0 R/W 0 RO 0 RO 0 7 23 22 21 20 19 TIMER3 RO 0 4 SSI0 RO 0 R/W 0 R/W 0 3 reserved RO 0 18 TIMER2 R/W 0 2 UART2 R/W 0 17 TIMER1 R/W 0 1 UART1 R/W 0 16 TIMER0 R/W 0 0 UART0 R/W 0 reserved Type Reset RO 0 15 reserved Type Reset RO 0 RO 0 14 I2C1 R/W 0 RO 0 13 reserved RO 0 RO 0 12 I2C0 R/W 0 reserved RO 0 6 reserved RO 0 RO 0 5 reserved RO 0 RO 0 Bit/Field 31:26 Name reserved Type RO Reset 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Analog Comparator 1 Clock Gating This bit controls the clock gating for analog comparator 1. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 25 COMP1 R/W 0 24 COMP0 R/W 0 Analog Comparator 0 Clock Gating This bit controls the clock gating for analog comparator 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 23:20 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Timer 3 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 3. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 19 TIMER3 R/W 0 100 Preliminary November 30, 2007 LM3S6965 Microcontroller Bit/Field 18 Name TIMER2 Type R/W Reset 0 Description Timer 2 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 2. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 17 TIMER1 R/W 0 Timer 1 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 1. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 16 TIMER0 R/W 0 Timer 0 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 15 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. I2C1 Clock Gating Control This bit controls the clock gating for I2C module 1. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 14 I2C1 R/W 0 13 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. I2C0 Clock Gating Control This bit controls the clock gating for I2C module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 12 I2C0 R/W 0 11:10 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. QEI1 Clock Gating Control This bit controls the clock gating for QEI module 1. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 9 QEI1 R/W 0 8 QEI0 R/W 0 QEI0 Clock Gating Control This bit controls the clock gating for QEI module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 7:5 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. November 30, 2007 Preliminary 101 System Control Bit/Field 4 Name SSI0 Type R/W Reset 0 Description SSI0 Clock Gating Control This bit controls the clock gating for SSI module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 3 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. UART2 Clock Gating Control This bit controls the clock gating for UART module 2. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 2 UART2 R/W 0 1 UART1 R/W 0 UART1 Clock Gating Control This bit controls the clock gating for UART module 1. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 UART0 R/W 0 UART0 Clock Gating Control This bit controls the clock gating for UART module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 102 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 22: Sleep Mode Clock Gating Control Register 1 (SCGC1), offset 0x114 This register controls the clock gating logic. Each bit controls a clock enable for a given interface, function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or units to control. This is to assure reasonable code compatibility with other family and future parts. RCGC1 is the clock configuration register for running operation, SCGC1 for Sleep operation, and DCGC1 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep modes. Sleep Mode Clock Gating Control Register 1 (SCGC1) Base 0x400F.E000 Offset 0x114 Type R/W, reset 0x00000000 31 30 29 28 27 26 25 COMP1 RO 0 11 RO 0 10 R/W 0 9 QEI1 R/W 0 24 COMP0 R/W 0 8 QEI0 R/W 0 RO 0 RO 0 7 23 22 21 20 19 TIMER3 RO 0 4 SSI0 RO 0 R/W 0 R/W 0 3 reserved RO 0 18 TIMER2 R/W 0 2 UART2 R/W 0 17 TIMER1 R/W 0 1 UART1 R/W 0 16 TIMER0 R/W 0 0 UART0 R/W 0 reserved Type Reset RO 0 15 reserved Type Reset RO 0 RO 0 14 I2C1 R/W 0 RO 0 13 reserved RO 0 RO 0 12 I2C0 R/W 0 reserved RO 0 6 reserved RO 0 RO 0 5 reserved RO 0 RO 0 Bit/Field 31:26 Name reserved Type RO Reset 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Analog Comparator 1 Clock Gating This bit controls the clock gating for analog comparator 1. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 25 COMP1 R/W 0 24 COMP0 R/W 0 Analog Comparator 0 Clock Gating This bit controls the clock gating for analog comparator 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 23:20 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Timer 3 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 3. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 19 TIMER3 R/W 0 November 30, 2007 Preliminary 103 System Control Bit/Field 18 Name TIMER2 Type R/W Reset 0 Description Timer 2 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 2. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 17 TIMER1 R/W 0 Timer 1 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 1. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 16 TIMER0 R/W 0 Timer 0 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 15 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. I2C1 Clock Gating Control This bit controls the clock gating for I2C module 1. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 14 I2C1 R/W 0 13 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. I2C0 Clock Gating Control This bit controls the clock gating for I2C module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 12 I2C0 R/W 0 11:10 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. QEI1 Clock Gating Control This bit controls the clock gating for QEI module 1. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 9 QEI1 R/W 0 8 QEI0 R/W 0 QEI0 Clock Gating Control This bit controls the clock gating for QEI module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 7:5 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 104 Preliminary November 30, 2007 LM3S6965 Microcontroller Bit/Field 4 Name SSI0 Type R/W Reset 0 Description SSI0 Clock Gating Control This bit controls the clock gating for SSI module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 3 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. UART2 Clock Gating Control This bit controls the clock gating for UART module 2. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 2 UART2 R/W 0 1 UART1 R/W 0 UART1 Clock Gating Control This bit controls the clock gating for UART module 1. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 UART0 R/W 0 UART0 Clock Gating Control This bit controls the clock gating for UART module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. November 30, 2007 Preliminary 105 System Control Register 23: Deep Sleep Mode Clock Gating Control Register 1 (DCGC1), offset 0x124 This register controls the clock gating logic. Each bit controls a clock enable for a given interface, function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or units to control. This is to assure reasonable code compatibility with other family and future parts. RCGC1 is the clock configuration register for running operation, SCGC1 for Sleep operation, and DCGC1 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep modes. Deep Sleep Mode Clock Gating Control Register 1 (DCGC1) Base 0x400F.E000 Offset 0x124 Type R/W, reset 0x00000000 31 30 29 28 27 26 25 COMP1 RO 0 11 RO 0 10 R/W 0 9 QEI1 R/W 0 24 COMP0 R/W 0 8 QEI0 R/W 0 RO 0 RO 0 7 23 22 21 20 19 TIMER3 RO 0 4 SSI0 RO 0 R/W 0 R/W 0 3 reserved RO 0 18 TIMER2 R/W 0 2 UART2 R/W 0 17 TIMER1 R/W 0 1 UART1 R/W 0 16 TIMER0 R/W 0 0 UART0 R/W 0 reserved Type Reset RO 0 15 reserved Type Reset RO 0 RO 0 14 I2C1 R/W 0 RO 0 13 reserved RO 0 RO 0 12 I2C0 R/W 0 reserved RO 0 6 reserved RO 0 RO 0 5 reserved RO 0 RO 0 Bit/Field 31:26 Name reserved Type RO Reset 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Analog Comparator 1 Clock Gating This bit controls the clock gating for analog comparator 1. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 25 COMP1 R/W 0 24 COMP0 R/W 0 Analog Comparator 0 Clock Gating This bit controls the clock gating for analog comparator 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 23:20 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Timer 3 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 3. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 19 TIMER3 R/W 0 106 Preliminary November 30, 2007 LM3S6965 Microcontroller Bit/Field 18 Name TIMER2 Type R/W Reset 0 Description Timer 2 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 2. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 17 TIMER1 R/W 0 Timer 1 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 1. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 16 TIMER0 R/W 0 Timer 0 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 15 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. I2C1 Clock Gating Control This bit controls the clock gating for I2C module 1. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 14 I2C1 R/W 0 13 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. I2C0 Clock Gating Control This bit controls the clock gating for I2C module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 12 I2C0 R/W 0 11:10 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. QEI1 Clock Gating Control This bit controls the clock gating for QEI module 1. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 9 QEI1 R/W 0 8 QEI0 R/W 0 QEI0 Clock Gating Control This bit controls the clock gating for QEI module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 7:5 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. November 30, 2007 Preliminary 107 System Control Bit/Field 4 Name SSI0 Type R/W Reset 0 Description SSI0 Clock Gating Control This bit controls the clock gating for SSI module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 3 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. UART2 Clock Gating Control This bit controls the clock gating for UART module 2. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 2 UART2 R/W 0 1 UART1 R/W 0 UART1 Clock Gating Control This bit controls the clock gating for UART module 1. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 UART0 R/W 0 UART0 Clock Gating Control This bit controls the clock gating for UART module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 108 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 24: Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108 This register controls the clock gating logic. Each bit controls a clock enable for a given interface, function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or units to control. This is to assure reasonable code compatibility with other family and future parts. RCGC2 is the clock configuration register for running operation, SCGC2 for Sleep operation, and DCGC2 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep modes. Run Mode Clock Gating Control Register 2 (RCGC2) Base 0x400F.E000 Offset 0x108 Type R/W, reset 0x00000000 31 reserved Type Reset RO 0 15 30 EPHY0 R/W 0 14 29 reserved RO 0 13 28 EMAC0 R/W 0 12 RO 0 11 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 10 RO 0 9 RO 0 8 RO 0 7 27 26 25 24 23 22 21 20 19 18 17 16 reserved RO 0 6 GPIOG R/W 0 RO 0 5 GPIOF R/W 0 RO 0 4 GPIOE R/W 0 RO 0 3 GPIOD R/W 0 RO 0 2 GPIOC R/W 0 RO 0 1 GPIOB R/W 0 RO 0 0 GPIOA R/W 0 Bit/Field 31 Name reserved Type RO Reset 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. PHY0 Clock Gating Control This bit controls the clock gating for Ethernet PHY unit 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 30 EPHY0 R/W 0 29 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. MAC0 Clock Gating Control This bit controls the clock gating for Ethernet MAC unit 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 28 EMAC0 R/W 0 27:7 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Port G Clock Gating Control This bit controls the clock gating for Port G. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 6 GPIOG R/W 0 November 30, 2007 Preliminary 109 System Control Bit/Field 5 Name GPIOF Type R/W Reset 0 Description Port F Clock Gating Control This bit controls the clock gating for Port F. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 4 GPIOE R/W 0 Port E Clock Gating Control This bit controls the clock gating for Port E. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 3 GPIOD R/W 0 Port D Clock Gating Control This bit controls the clock gating for Port D. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 2 GPIOC R/W 0 Port C Clock Gating Control This bit controls the clock gating for Port C. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 1 GPIOB R/W 0 Port B Clock Gating Control This bit controls the clock gating for Port B. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 GPIOA R/W 0 Port A Clock Gating Control This bit controls the clock gating for Port A. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 110 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 25: Sleep Mode Clock Gating Control Register 2 (SCGC2), offset 0x118 This register controls the clock gating logic. Each bit controls a clock enable for a given interface, function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or units to control. This is to assure reasonable code compatibility with other family and future parts. RCGC2 is the clock configuration register for running operation, SCGC2 for Sleep operation, and DCGC2 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep modes. Sleep Mode Clock Gating Control Register 2 (SCGC2) Base 0x400F.E000 Offset 0x118 Type R/W, reset 0x00000000 31 reserved Type Reset RO 0 15 30 EPHY0 R/W 0 14 29 reserved RO 0 13 28 EMAC0 R/W 0 12 RO 0 11 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 10 RO 0 9 RO 0 8 RO 0 7 27 26 25 24 23 22 21 20 19 18 17 16 reserved RO 0 6 GPIOG R/W 0 RO 0 5 GPIOF R/W 0 RO 0 4 GPIOE R/W 0 RO 0 3 GPIOD R/W 0 RO 0 2 GPIOC R/W 0 RO 0 1 GPIOB R/W 0 RO 0 0 GPIOA R/W 0 Bit/Field 31 Name reserved Type RO Reset 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. PHY0 Clock Gating Control This bit controls the clock gating for Ethernet PHY unit 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 30 EPHY0 R/W 0 29 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. MAC0 Clock Gating Control This bit controls the clock gating for Ethernet MAC unit 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 28 EMAC0 R/W 0 27:7 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. November 30, 2007 Preliminary 111 System Control Bit/Field 6 Name GPIOG Type R/W Reset 0 Description Port G Clock Gating Control This bit controls the clock gating for Port G. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 5 GPIOF R/W 0 Port F Clock Gating Control This bit controls the clock gating for Port F. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 4 GPIOE R/W 0 Port E Clock Gating Control This bit controls the clock gating for Port E. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 3 GPIOD R/W 0 Port D Clock Gating Control This bit controls the clock gating for Port D. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 2 GPIOC R/W 0 Port C Clock Gating Control This bit controls the clock gating for Port C. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 1 GPIOB R/W 0 Port B Clock Gating Control This bit controls the clock gating for Port B. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 GPIOA R/W 0 Port A Clock Gating Control This bit controls the clock gating for Port A. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 112 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 26: Deep Sleep Mode Clock Gating Control Register 2 (DCGC2), offset 0x128 This register controls the clock gating logic. Each bit controls a clock enable for a given interface, function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault. The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. It is the responsibility of software to enable the ports necessary for the application. Note that these registers may contain more bits than there are interfaces, functions, or units to control. This is to assure reasonable code compatibility with other family and future parts. RCGC2 is the clock configuration register for running operation, SCGC2 for Sleep operation, and DCGC2 for Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register specifies that the system uses sleep modes. Deep Sleep Mode Clock Gating Control Register 2 (DCGC2) Base 0x400F.E000 Offset 0x128 Type R/W, reset 0x00000000 31 reserved Type Reset RO 0 15 30 EPHY0 R/W 0 14 29 reserved RO 0 13 28 EMAC0 R/W 0 12 RO 0 11 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 10 RO 0 9 RO 0 8 RO 0 7 27 26 25 24 23 22 21 20 19 18 17 16 reserved RO 0 6 GPIOG R/W 0 RO 0 5 GPIOF R/W 0 RO 0 4 GPIOE R/W 0 RO 0 3 GPIOD R/W 0 RO 0 2 GPIOC R/W 0 RO 0 1 GPIOB R/W 0 RO 0 0 GPIOA R/W 0 Bit/Field 31 Name reserved Type RO Reset 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. PHY0 Clock Gating Control This bit controls the clock gating for Ethernet PHY unit 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 30 EPHY0 R/W 0 29 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. MAC0 Clock Gating Control This bit controls the clock gating for Ethernet MAC unit 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 28 EMAC0 R/W 0 27:7 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. November 30, 2007 Preliminary 113 System Control Bit/Field 6 Name GPIOG Type R/W Reset 0 Description Port G Clock Gating Control This bit controls the clock gating for Port G. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 5 GPIOF R/W 0 Port F Clock Gating Control This bit controls the clock gating for Port F. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 4 GPIOE R/W 0 Port E Clock Gating Control This bit controls the clock gating for Port E. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 3 GPIOD R/W 0 Port D Clock Gating Control This bit controls the clock gating for Port D. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 2 GPIOC R/W 0 Port C Clock Gating Control This bit controls the clock gating for Port C. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 1 GPIOB R/W 0 Port B Clock Gating Control This bit controls the clock gating for Port B. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 GPIOA R/W 0 Port A Clock Gating Control This bit controls the clock gating for Port A. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 114 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 27: Software Reset Control 0 (SRCR0), offset 0x040 Writes to this register are masked by the bits in the Device Capabilities 1 (DC1) register. Software Reset Control 0 (SRCR0) Base 0x400F.E000 Offset 0x040 Type R/W, reset 0x00000000 31 30 29 28 27 26 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 HIB R/W 0 RO 0 5 reserved RO 0 RO 0 25 24 23 22 21 20 PWM R/W 0 4 RO 0 3 WDT R/W 0 RO 0 19 18 reserved RO 0 2 RO 0 1 reserved RO 0 RO 0 17 16 ADC R/W 0 0 Bit/Field 31:21 Name reserved Type RO Reset 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. PWM Reset Control Reset control for PWM module. 20 PWM R/W 0 19:17 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. ADC0 Reset Control Reset control for SAR ADC module 0. 16 ADC R/W 0 15:7 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. HIB Reset Control Reset control for the Hibernation module. 6 HIB R/W 0 5:4 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. WDT Reset Control Reset control for Watchdog unit. 3 WDT R/W 0 2:0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. November 30, 2007 Preliminary 115 System Control Register 28: Software Reset Control 1 (SRCR1), offset 0x044 Writes to this register are masked by the bits in the Device Capabilities 2 (DC2) register. Software Reset Control 1 (SRCR1) Base 0x400F.E000 Offset 0x044 Type R/W, reset 0x00000000 31 30 29 28 27 26 25 COMP1 RO 0 11 RO 0 10 R/W 0 9 QEI1 R/W 0 24 COMP0 R/W 0 8 QEI0 R/W 0 RO 0 RO 0 7 23 22 21 20 19 TIMER3 RO 0 4 SSI0 RO 0 R/W 0 R/W 0 3 reserved RO 0 18 TIMER2 R/W 0 2 UART2 R/W 0 17 TIMER1 R/W 0 1 UART1 R/W 0 16 TIMER0 R/W 0 0 UART0 R/W 0 reserved Type Reset RO 0 15 reserved Type Reset RO 0 RO 0 14 I2C1 R/W 0 RO 0 13 reserved RO 0 RO 0 12 I2C0 R/W 0 reserved RO 0 6 reserved RO 0 RO 0 5 reserved RO 0 RO 0 Bit/Field 31:26 Name reserved Type RO Reset 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Analog Comp 1 Reset Control Reset control for analog comparator 1. 25 COMP1 R/W 0 24 COMP0 R/W 0 Analog Comp 0 Reset Control Reset control for analog comparator 0. 23:20 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Timer 3 Reset Control Reset control for General-Purpose Timer module 3. 19 TIMER3 R/W 0 18 TIMER2 R/W 0 Timer 2 Reset Control Reset control for General-Purpose Timer module 2. 17 TIMER1 R/W 0 Timer 1 Reset Control Reset control for General-Purpose Timer module 1. 16 TIMER0 R/W 0 Timer 0 Reset Control Reset control for General-Purpose Timer module 0. 15 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. I2C1 Reset Control Reset control for I2C unit 1. 14 I2C1 R/W 0 13 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 116 Preliminary November 30, 2007 LM3S6965 Microcontroller Bit/Field 12 Name I2C0 Type R/W Reset 0 Description I2C0 Reset Control Reset control for I2C unit 0. 11:10 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. QEI1 Reset Control Reset control for QEI unit 1. 9 QEI1 R/W 0 8 QEI0 R/W 0 QEI0 Reset Control Reset control for QEI unit 0. 7:5 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SSI0 Reset Control Reset control for SSI unit 0. 4 SSI0 R/W 0 3 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. UART2 Reset Control Reset control for UART unit 2. 2 UART2 R/W 0 1 UART1 R/W 0 UART1 Reset Control Reset control for UART unit 1. 0 UART0 R/W 0 UART0 Reset Control Reset control for UART unit 0. November 30, 2007 Preliminary 117 System Control Register 29: Software Reset Control 2 (SRCR2), offset 0x048 Writes to this register are masked by the bits in the Device Capabilities 4 (DC4) register. Software Reset Control 2 (SRCR2) Base 0x400F.E000 Offset 0x048 Type R/W, reset 0x00000000 31 reserved Type Reset RO 0 15 30 EPHY0 R/W 0 14 29 reserved RO 0 13 28 EMAC0 R/W 0 12 RO 0 11 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 10 RO 0 9 RO 0 8 RO 0 7 27 26 25 24 23 22 21 20 19 18 17 16 reserved RO 0 6 GPIOG R/W 0 RO 0 5 GPIOF R/W 0 RO 0 4 GPIOE R/W 0 RO 0 3 GPIOD R/W 0 RO 0 2 GPIOC R/W 0 RO 0 1 GPIOB R/W 0 RO 0 0 GPIOA R/W 0 Bit/Field 31 Name reserved Type RO Reset 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. PHY0 Reset Control Reset control for Ethernet PHY unit 0. 30 EPHY0 R/W 0 29 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. MAC0 Reset Control Reset control for Ethernet MAC unit 0. 28 EMAC0 R/W 0 27:7 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Port G Reset Control Reset control for GPIO Port G. 6 GPIOG R/W 0 5 GPIOF R/W 0 Port F Reset Control Reset control for GPIO Port F. 4 GPIOE R/W 0 Port E Reset Control Reset control for GPIO Port E. 3 GPIOD R/W 0 Port D Reset Control Reset control for GPIO Port D. 2 GPIOC R/W 0 Port C Reset Control Reset control for GPIO Port C. 1 GPIOB R/W 0 Port B Reset Control Reset control for GPIO Port B. 118 Preliminary November 30, 2007 LM3S6965 Microcontroller Bit/Field 0 Name GPIOA Type R/W Reset 0 Description Port A Reset Control Reset control for GPIO Port A. November 30, 2007 Preliminary 119 Hibernation Module 7 Hibernation Module The Hibernation Module manages removal and restoration of power to the rest of the microcontroller to provide a means for reducing power consumption. When the processor and peripherals are idle, power can be completely removed with only the Hibernation Module remaining powered. Power can be restored based on an external signal, or at a certain time using the built-in real-time clock (RTC). The Hibernation module can be independently supplied from a battery or an auxiliary power supply. The Hibernation module has the following features: ■ Power-switching logic to discrete external regulator ■ Dedicated pin for waking from an external signal ■ Low-battery detection, signaling, and interrupt generation ■ 32-bit real-time counter (RTC) ■ Two 32-bit RTC match registers for timed wake-up and interrupt generation ■ Clock source from a 32.768-kHz external oscillator or a 4.194304-MHz crystal ■ RTC predivider trim for making fine adjustments to the clock rate ■ 64 32-bit words of non-volatile memory ■ Programmable interrupts for RTC match, external wake, and low battery events 120 Preliminary November 30, 2007 LM3S6965 Microcontroller 7.1 Block Diagram Figure 7-1. Hibernation Module Block Diagram HIBCTL.CLK32EN XOSC0 XOSC1 /128 HIBCTL.CLKSEL RTC HIBRTCC HIBRTCLD HIBRTCM0 HIBRTCM1 Pre-Divider HIBRTCT Interrupts HIBIM HIBRIS HIBMIS HIBIC MATCH0/1 Interrupts to CPU Non-Volatile Memory HIBDATA WAKE LOWBAT VDD VBAT Low Battery Detect HIBCTL.LOWBATEN HIBCTL.PWRCUT HIBCTL.RTCWEN HIBCTL.EXTWEN HIBCTL.VABORT Power Sequence Logic HIB 7.2 Functional Description The Hibernation module controls the power to the processor with an enable signal (HIB) that signals an external voltage regulator to turn off. The Hibernation module power is determined dynamically. The supply voltage of the Hibernation module is the larger of the main voltage source (VDD) or the battery/auxilliary voltage source (VBAT). A voting circuit indicates the larger and an internal power switch selects the appropriate voltage source. The Hibernation module also has a separate clock source to maintain a real-time clock (RTC). Once in hibernation, the module signals an external voltage regulator to turn back on the power when an external pin (WAKE) is asserted, or when the internal RTC reaches a certain value. The Hibernation module can also detect when the battery voltage is low, and optionally prevent hibernation when this occurs. Power-up from a power cut to code execution is defined as the regulator turn-on time (specifed at tHIB_TO_VDD maximum) plus the normal chip POR (see “Hibernation Module” on page 544). 7.2.1 Register Access Timing Because the Hibernation module has an independent clocking domain, certain registers must be written only with a timing gap between accesses. The delay time is tHIB_REG_WRITE, therefore software must guarantee that a delay of tHIB_REG_WRITE is inserted between back-to-back writes to certain Hibernation registers, or between a write followed by a read to those same registers. There is no November 30, 2007 Preliminary 121 Hibernation Module restriction on timing for back-to-back reads from the Hibernation module. Refer to “Register Descriptions” on page 126 for details about which registers are subject to this timing restriction. 7.2.2 Clock Source The Hibernation module must be clocked by an external source, even if the RTC feature will not be used. An external oscillator or crystal can be used for this purpose. To use a crystal, a 4.194304-MHz crystal is connected to the XOSC0 and XOSC1 pins. This clock signal is divided by 128 internally to produce the 32.768-kHz clock reference. To use a more precise clock source, a 32.768-kHz oscillator can be connected to the XOSC0 pin. The clock source is enabled by setting the CLK32EN bit of the HIBCTL register. The type of clock source is selected by setting the CLKSEL bit to 0 for a 4.194304-MHz clock source, and to 1 for a 32.768-kHz clock source. If the bit is set to 0, the input clock is divided by 128, resulting in a 32.768-kHz clock source. If a crystal is used for the clock source, the software must leave a delay of tXOSC_SETTLE after setting the CLK32EN bit and before any other accesses to the Hibernation module registers. The delay allows the crystal to power up and stabilize. If an oscillator is used for the clock source, no delay is needed. 7.2.3 Battery Management The Hibernation module can be independently powered by a battery or an auxiliary power source. The module can monitor the voltage level of the battery and detect when the voltage becomes too low. When this happens, an interrupt can be generated. The module can also be configured so that it will not go into Hibernate mode if the battery voltage is too low. Note that the Hibernation module draws power from whichever source (VBAT or VDD) has the higher voltage. Therefore, it is important to design the circuit to ensure that VDD is higher that VBAT under nominal conditions or else the Hibernation module draws power from the battery even when VDD is available. The Hibernation module can be configured to detect a low battery condition by setting the LOWBATEN bit of the HIBCTL register. In this configuration, the LOWBAT bit of the HIBRIS register will be set when the battery level is low. If the VABORT bit is also set, then the module is prevented from entering Hibernation mode when a low battery is detected. The module can also be configured to generate an interrupt for the low-battery condition (see “Interrupts and Status” on page 123). 7.2.4 Real-Time Clock The Hibernation module includes a 32-bit counter that increments once per second with a proper clock source and configuration (see “Clock Source” on page 122). The 32.768-kHz clock signal is fed into a predivider register which counts down the 32.768-kHz clock ticks to achieve a once per second clock rate for the RTC. The rate can be adjusted to compensate for inaccuracies in the clock source by using the predivider trim register. This register has a nominal value of 0x7FFF, and is used for one second out of every 64 seconds to divide the input clock. This allows the software to make fine corrections to the clock rate by adjusting the predivider trim register up or down from 0x7FFF. The predivider trim should be adjusted up from 0x7FFF in order to slow down the RTC rate, and down from 0x7FFF in order to speed up the RTC rate. The Hibernation module includes two 32-bit match registers that are compared to the value of the RTC counter. The match registers can be used to wake the processor from hibernation mode, or to generate an interrupt to the processor if it is not in hibernation. The RTC must be enabled with the RTCEN bit of the HIBCTL register. The value of the RTC can be set at any time by writing to the HIBRTCLD register. The predivider trim can be adjusted by reading and writing the HIBRTCT register. The predivider uses this register once every 64 seconds to adjust 122 Preliminary November 30, 2007 LM3S6965 Microcontroller the clock rate. The two match registers can be set by writing to the HIBRTCM0 and HIBRTCM1 registers. The RTC can be configured to generate interrupts by using the interrupt registers (see “Interrupts and Status” on page 123). 7.2.5 Non-Volatile Memory The Hibernation module contains 64 32-bit words of memory which are retained during hibernation. This memory is powered from the battery or auxiliary power supply during hibernation. The processor software can save state information in this memory prior to hibernation, and can then recover the state upon waking. The non-volatile memory can be accessed through the HIBDATA registers. 7.2.6 Power Control The Hibernation module controls power to the processor through the use of the HIB pin, which is intended to be connected to the enable signal of the external regulator(s) providing 3.3 V and/or 2.5 V to the microcontroller. When the HIB signal is asserted by the Hibernation module, the external regulator is turned off and no longer powers the microcontroller. The Hibernation module remains powered from the VBAT supply, which could be a battery or an auxiliary power source. Hibernation mode is initiated by the microcontroller setting the HIBREQ bit of the HIBCTL register. Prior to doing this, a wake-up condition must be configured, either from the external WAKE pin, or by using an RTC match. The Hibernation module is configured to wake from the external WAKE pin by setting the PINWEN bit of the HIBCTL register. It is configured to wake from RTC match by setting the RTCWEN bit. Either one or both of these bits can be set prior to going into hibernation. The WAKE pin includes a weak internal pull-up. Note that both the HIB and WAKE pins use the Hibernation module's internal power supply as the logic 1 reference. When the Hibernation module wakes, the microcontroller will see a normal power-on reset. It can detect that the power-on was due to a wake from hibernation by examining the raw interrupt status register (see “Interrupts and Status” on page 123) and by looking for state data in the non-volatile memory (see “Non-Volatile Memory” on page 123). When the HIB signal deasserts, enabling the external regulator, the external regulator must reach the operating voltage within tHIB_TO_VDD. 7.2.7 Interrupts and Status The Hibernation module can generate interrupts when the following conditions occur: ■ Assertion of WAKE pin ■ RTC match ■ Low battery detected All of the interrupts are ORed together before being sent to the interrupt controller, so the Hibernate module can only generate a single interrupt request to the controller at any given time. The software interrupt handler can service multiple interrupt events by reading the HIBMIS register. Software can also read the status of the Hibernation module at any time by reading the HIBRIS register which shows all of the pending events. This register can be used at power-on to see if a wake condition is pending, which indicates to the software that a hibernation wake occurred. The events that can trigger an interrupt are configured by setting the appropriate bits in the HIBIM register. Pending interrupts can be cleared by writing the corresponding bit in the HIBIC register. November 30, 2007 Preliminary 123 Hibernation Module 7.3 Initialization and Configuration The Hibernation module can be configured in several different combinations. The following sections show the recommended programming sequence for various scenarios. The examples below assume that a 32.768-kHz oscillator is used, and thus always show bit 2 (CLKSEL) of the HIBCTL register set to 1. If a 4.194304-MHz crystal is used instead, then the CLKSEL bit remains cleared. Because the Hibernation module runs at 32 kHz and is asynchronous to the rest of the system, software must allow a delay of tHIB_REG_WRITE after writes to certain registers (see “Register Access Timing” on page 121). The registers that require a delay are denoted with a footnote in Table 7-1 on page 125. 7.3.1 Initialization The clock source must be enabled first, even if the RTC will not be used. If a 4.194304-MHz crystal is used, perform the following steps: 1. Write 0x40 to the HIBCTL register at offset 0x10 to enable the crystal and select the divide-by-128 input path. 2. Wait for a time of tXOSC_SETTLE for the crystal to power up and stabilize before performing any other operations with the Hibernation module. If a 32.678-kHz oscillator is used, then perform the following steps: 1. Write 0x44 to the HIBCTL register at offset 0x10 to enable the oscillator input. 2. No delay is necessary. The above is only necessary when the entire system is initialized for the first time. If the processor is powered due to a wake from hibernation, then the Hibernation module has already been powered up and the above steps are not necessary. The software can detect that the Hibernation module and clock are already powered by examining the CLK32EN bit of the HIBCTL register. 7.3.2 RTC Match Functionality (No Hibernation) The following steps are needed to use the RTC match functionality of the Hibernation module: 1. Write the required RTC match value to one of the HIBRTCMn registers at offset 0x004 or 0x008. 2. Write the required RTC load value to the HIBRTCLD register at offset 0x00C. 3. Set the required RTC match interrupt mask in the RTCALT0 and RTCALT1 bits (bits 1:0) in the HIBIM register at offset 0x014. 4. Write 0x0000.0041 to the HIBCTL register at offset 0x010 to enable the RTC to begin counting. 7.3.3 RTC Match/Wake-Up from Hibernation The following steps are needed to use the RTC match and wake-up functionality of the Hibernation module: 1. Write the required RTC match value to the HIBRTCMn registers at offset 0x004 or 0x008. 2. Write the required RTC load value to the HIBRTCLD register at offset 0x00C. 3. Write any data to be retained during power cut to the HIBDATA register at offsets 0x030-0x12C. 124 Preliminary November 30, 2007 LM3S6965 Microcontroller 4. Set the RTC Match Wake-Up and start the hibernation sequence by writing 0x0000.004F to the HIBCTL register at offset 0x010. 7.3.4 External Wake-Up from Hibernation The following steps are needed to use the Hibernation module with the external WAKE pin as the wake-up source for the microcontroller: 1. Write any data to be retained during power cut to the HIBDATA register at offsets 0x030-0x12C. 2. Enable the external wake and start the hibernation sequence by writing 0x0000.0056 to the HIBCTL register at offset 0x010. 7.3.5 RTC/External Wake-Up from Hibernation 1. Write the required RTC match value to the HIBRTCMn registers at offset 0x004 or 0x008. 2. Write the required RTC load value to the HIBRTCLD register at offset 0x00C. 3. Write any data to be retained during power cut to the HIBDATA register at offsets 0x030-0x12C. 4. Set the RTC Match/External Wake-Up and start the hibernation sequence by writing 0x0000.005F to the HIBCTL register at offset 0x010. 7.4 Register Map Table 7-1 on page 125 lists the Hibernation registers. All addresses given are relative to the Hibernation Module base address at 0x400F.C000. Note: HIBRTCC, HIBRTCM0, HIBRTCM1, HIBRTCLD, HIBRTCT, and HIBDATA are on the Hibernation module clock domain and require a delay of tHIB_REG_WRITE between write accesses. See “Register Access Timing” on page 121. Table 7-1. Hibernation Module Register Map Offset 0x000 0x004 0x008 0x00C 0x010 0x014 0x018 0x01C 0x020 0x024 0x0300x12C Name HIBRTCC HIBRTCM0 HIBRTCM1 HIBRTCLD HIBCTL HIBIM HIBRIS HIBMIS HIBIC HIBRTCT HIBDATA Type RO R/W R/W R/W R/W R/W RO RO R/W1C R/W R/W Reset 0x0000.0000 0xFFFF.FFFF 0xFFFF.FFFF 0xFFFF.FFFF 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.7FFF 0x0000.0000 Description Hibernation RTC Counter Hibernation RTC Match 0 Hibernation RTC Match 1 Hibernation RTC Load Hibernation Control Hibernation Interrupt Mask Hibernation Raw Interrupt Status Hibernation Masked Interrupt Status Hibernation Interrupt Clear Hibernation RTC Trim Hibernation Data See page 127 128 129 130 131 133 134 135 136 137 138 November 30, 2007 Preliminary 125 Hibernation Module 7.5 Register Descriptions The remainder of this section lists and describes the Hibernation module registers, in numerical order by address offset. 126 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 1: Hibernation RTC Counter (HIBRTCC), offset 0x000 This register is the current 32-bit value of the RTC counter. Hibernation RTC Counter (HIBRTCC) Base 0x400F.C000 Offset 0x000 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 RTCC Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RTCC Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 23 22 21 20 19 18 17 16 Bit/Field 31:0 Name RTCC Type RO Reset Description 0x0000.0000 RTC Counter A read returns the 32-bit counter value. This register is read-only. To change the value, use the HIBRTCLD register. November 30, 2007 Preliminary 127 Hibernation Module Register 2: Hibernation RTC Match 0 (HIBRTCM0), offset 0x004 This register is the 32-bit match 0 register for the RTC counter. Hibernation RTC Match 0 (HIBRTCM0) Base 0x400F.C000 Offset 0x004 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 RTCM0 Type Reset R/W 1 15 R/W 1 14 R/W 1 13 R/W 1 12 R/W 1 11 R/W 1 10 R/W 1 9 R/W 1 8 RTCM0 Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 7 R/W 1 6 R/W 1 5 R/W 1 4 R/W 1 3 R/W 1 2 R/W 1 1 R/W 1 0 23 22 21 20 19 18 17 16 Bit/Field 31:0 Name RTCM0 Type R/W Reset Description 0xFFFF.FFFF RTC Match 0 A write loads the value into the RTC match register. A read returns the current match value. 128 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 3: Hibernation RTC Match 1 (HIBRTCM1), offset 0x008 This register is the 32-bit match 1 register for the RTC counter. Hibernation RTC Match 1 (HIBRTCM1) Base 0x400F.C000 Offset 0x008 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 RTCM1 Type Reset R/W 1 15 R/W 1 14 R/W 1 13 R/W 1 12 R/W 1 11 R/W 1 10 R/W 1 9 R/W 1 8 RTCM1 Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 7 R/W 1 6 R/W 1 5 R/W 1 4 R/W 1 3 R/W 1 2 R/W 1 1 R/W 1 0 23 22 21 20 19 18 17 16 Bit/Field 31:0 Name RTCM1 Type R/W Reset Description 0xFFFF.FFFF RTC Match 1 A write loads the value into the RTC match register. A read returns the current match value. November 30, 2007 Preliminary 129 Hibernation Module Register 4: Hibernation RTC Load (HIBRTCLD), offset 0x00C This register is the 32-bit value loaded into the RTC counter. Hibernation RTC Load (HIBRTCLD) Base 0x400F.C000 Offset 0x00C Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 RTCLD Type Reset R/W 1 15 R/W 1 14 R/W 1 13 R/W 1 12 R/W 1 11 R/W 1 10 R/W 1 9 R/W 1 8 RTCLD Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 7 R/W 1 6 R/W 1 5 R/W 1 4 R/W 1 3 R/W 1 2 R/W 1 1 R/W 1 0 23 22 21 20 19 18 17 16 Bit/Field 31:0 Name RTCLD Type R/W Reset Description 0xFFFF.FFFF RTC Load A write loads the current value into the RTC counter (RTCC). A read returns the 32-bit load value. 130 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 5: Hibernation Control (HIBCTL), offset 0x010 This register is the control register for the Hibernation module. Hibernation Control (HIBCTL) Base 0x400F.C000 Offset 0x010 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 RTCEN R/W 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 VABORT CLK32EN LOWBA TEN PINWEN RTCWEN CLKSEL HIBREQ R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Power Cut Abort Enable 0: Power cut occurs during a low-battery alert 1: Power cut is aborted 7 VABORT R/W 0 6 CLK32EN R/W 0 32-kHz Oscillator Enable 0: Disabled 1: Enabled This bit must be enabled to use the Hibernation module. If a crystal is used, then software should wait 20 ms after setting this bit to allow the crystal to power up and stabilize. 5 LOWBATEN R/W 0 Low Battery Monitoring Enable 0: Disabled 1: Enabled When set, low battery voltage detection is enabled. 4 PINWEN R/W 0 External WAKE Pin Enable 0: Disabled 1: Enabled When set, an external event on the WAKE pin will re-power the device. 3 RTCWEN R/W 0 RTC Wake-up Enable 0: Disabled 1: Enabled When set, an RTC match event (RTCM0 or RTCM1) will re-power the device based on the RTC counter value matching the corresponding match register 0 or 1. November 30, 2007 Preliminary 131 Hibernation Module Bit/Field 2 Name CLKSEL Type R/W Reset 0 Description Hibernation Module Clock Select 0: Use Divide by 128 output. Use this value for a 4-MHz crystal. 1: Use raw output. Use this value for a 32-kHz oscillator. 1 HIBREQ R/W 0 Hibernation Request 0: Disabled 1: Hibernation initiated After a wake-up event, this bit is cleared by hardware. 0 RTCEN R/W 0 RTC Timer Enable 0: Disabled 1: Enabled 132 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 6: Hibernation Interrupt Mask (HIBIM), offset 0x014 This register is the interrupt mask register for the Hibernation module interrupt sources. Hibernation Interrupt Mask (HIBIM) Base 0x400F.C000 Offset 0x014 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 EXTW R/W 0 RO 0 2 RO 0 1 RO 0 0 LOWBAT RTCALT1 RTCALT0 R/W 0 R/W 0 R/W 0 Bit/Field 31:4 Name reserved Type RO Reset 0x000.0000 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. External Wake-Up Interrupt Mask 0: Masked 1: Unmasked 3 EXTW R/W 0 2 LOWBAT R/W 0 Low Battery Voltage Interrupt Mask 0: Masked 1: Unmasked 1 RTCALT1 R/W 0 RTC Alert1 Interrupt Mask 0: Masked 1: Unmasked 0 RTCALT0 R/W 0 RTC Alert0 Interrupt Mask 0: Masked 1: Unmasked November 30, 2007 Preliminary 133 Hibernation Module Register 7: Hibernation Raw Interrupt Status (HIBRIS), offset 0x018 This register is the raw interrupt status for the Hibernation module interrupt sources. Hibernation Raw Interrupt Status (HIBRIS) Base 0x400F.C000 Offset 0x018 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 EXTW RO 0 RO 0 2 RO 0 1 RO 0 0 LOWBAT RTCALT1 RTCALT0 RO 0 RO 0 RO 0 Bit/Field 31:4 Name reserved Type RO Reset 0x000.0000 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. External Wake-Up Raw Interrupt Status Low Battery Voltage Raw Interrupt Status RTC Alert1 Raw Interrupt Status RTC Alert0 Raw Interrupt Status 3 2 1 0 EXTW LOWBAT RTCALT1 RTCALT0 RO RO RO RO 0 0 0 0 134 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 8: Hibernation Masked Interrupt Status (HIBMIS), offset 0x01C This register is the masked interrupt status for the Hibernation module interrupt sources. Hibernation Masked Interrupt Status (HIBMIS) Base 0x400F.C000 Offset 0x01C Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 EXTW RO 0 RO 0 2 RO 0 1 RO 0 0 LOWBAT RTCALT1 RTCALT0 RO 0 RO 0 RO 0 Bit/Field 31:4 Name reserved Type RO Reset 0x000.0000 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. External Wake-Up Masked Interrupt Status Low Battery Voltage Masked Interrupt Status RTC Alert1 Masked Interrupt Status RTC Alert0 Masked Interrupt Status 3 2 1 0 EXTW LOWBAT RTCALT1 RTCALT0 RO RO RO RO 0 0 0 0 November 30, 2007 Preliminary 135 Hibernation Module Register 9: Hibernation Interrupt Clear (HIBIC), offset 0x020 This register is the interrupt write-one-to-clear register for the Hibernation module interrupt sources. Hibernation Interrupt Clear (HIBIC) Base 0x400F.C000 Offset 0x020 Type R/W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 EXTW R/W1C 0 RO 0 2 RO 0 1 RO 0 0 LOWBAT RTCALT1 RTCALT0 R/W1C 0 R/W1C 0 R/W1C 0 Bit/Field 31:4 Name reserved Type RO Reset 0x000.0000 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. External Wake-Up Masked Interrupt Clear Reads return an indeterminate value. 3 EXTW R/W1C 0 2 LOWBAT R/W1C 0 Low Battery Voltage Masked Interrupt Clear Reads return an indeterminate value. 1 RTCALT1 R/W1C 0 RTC Alert1 Masked Interrupt Clear Reads return an indeterminate value. 0 RTCALT0 R/W1C 0 RTC Alert0 Masked Interrupt Clear Reads return an indeterminate value. 136 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 10: Hibernation RTC Trim (HIBRTCT), offset 0x024 This register contains the value that is used to trim the RTC clock predivider. It represents the computed underflow value that is used during the trim cycle. It is represented as 0x7FFF ± N clock cycles. Hibernation RTC Trim (HIBRTCT) Base 0x400F.C000 Offset 0x024 Type R/W, reset 0x0000.7FFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 TRIM Type Reset R/W 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 Bit/Field 31:16 Name reserved Type RO Reset 0x0000 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. RTC Trim Value This value is loaded into the RTC predivider every 64 seconds. It is used to adjust the RTC rate to account for drift and inaccuracy in the clock source. The compensation is made by software by adjusting the default value of 0x7FFF up or down. 15:0 TRIM R/W 0x7FFF November 30, 2007 Preliminary 137 Hibernation Module Register 11: Hibernation Data (HIBDATA), offset 0x030-0x12C This address space is implemented as a 64x32-bit memory (256 bytes). It can be loaded by the system processor in order to store any non-volatile state data and will not lose power during a power cut operation. Hibernation Data (HIBDATA) Base 0x400F.C000 Offset 0x030-0x12C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 RTD Type Reset R/W 0 15 R/W 0 14 R/W 0 13 R/W 0 12 R/W 0 11 R/W 0 10 R/W 0 9 R/W 0 8 RTD Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 23 22 21 20 19 18 17 16 Bit/Field 31:0 Name RTD Type R/W Reset Description 0x0000.0000 Hibernation Module NV Registers[63:0] 138 Preliminary November 30, 2007 LM3S6965 Microcontroller 8 Internal Memory The LM3S6965 microcontroller comes with 64 KB of bit-banded SRAM and 256 KB of flash memory. The flash controller provides a user-friendly interface, making flash programming a simple task. Flash protection can be applied to the flash memory on a 2-KB block basis. 8.1 Block Diagram Figure 8-1. Flash Block Diagram Flash Timing USECRL Flash Control ICode Cortex-M3 DCode FMA FMD FMC System Bus FCRIS FCIM FCMISC Bridge APB Flash Array Flash Protection FMPREn SRAM Array FMPPEn User Registers USER_DBG USER_REG0 USER_REG1 8.2 8.2.1 Functional Description This section describes the functionality of both the flash and SRAM memories. SRAM Memory The internal SRAM of the Stellaris devices is located at address 0x2000.0000 of the device memory map. To reduce the number of time consuming read-modify-write (RMW) operations, ARM has introduced bit-banding technology in the Cortex-M3 processor. With a bit-band-enabled processor, certain regions in the memory map (SRAM and peripheral space) can use address aliases to access individual bits in a single, atomic operation. The bit-band alias is calculated by using the formula: ® November 30, 2007 Preliminary 139 Internal Memory bit-band alias = bit-band base + (byte offset * 32) + (bit number * 4) For example, if bit 3 at address 0x2000.1000 is to be modified, the bit-band alias is calculated as: 0x2200.0000 + (0x1000 * 32) + (3 * 4) = 0x2202.000C With the alias address calculated, an instruction performing a read/write to address 0x2202.000C allows direct access to only bit 3 of the byte at address 0x2000.1000. For details about bit-banding, please refer to Chapter 4, “Memory Map” in the ARM® Cortex™-M3 Technical Reference Manual. 8.2.2 Flash Memory The flash is organized as a set of 1-KB blocks that can be individually erased. Erasing a block causes the entire contents of the block to be reset to all 1s. An individual 32-bit word can be programmed to change bits that are currently 1 to a 0. These blocks are paired into a set of 2-KB blocks that can be individually protected. The protection allows blocks to be marked as read-only or execute-only, providing different levels of code protection. Read-only blocks cannot be erased or programmed, protecting the contents of those blocks from being modified. Execute-only blocks cannot be erased or programmed, and can only be read by the controller instruction fetch mechanism, protecting the contents of those blocks from being read by either the controller or by a debugger. See also “Serial Flash Loader” on page 552 for a preprogrammed flash-resident utility used to download code to the flash memory of a device without the use of a debug interface. 8.2.2.1 Flash Memory Timing The timing for the flash is automatically handled by the flash controller. However, in order to do so, it must know the clock rate of the system in order to time its internal signals properly. The number of clock cycles per microsecond must be provided to the flash controller for it to accomplish this timing. It is software's responsibility to keep the flash controller updated with this information via the USec Reload (USECRL) register. On reset, the USECRL register is loaded with a value that configures the flash timing so that it works with the maximum clock rate of the part. If software changes the system operating frequency, the new operating frequency minus 1 (in MHz) must be loaded into USECRL before any flash modifications are attempted. For example, if the device is operating at a speed of 20 MHz, a value of 0x13 (20-1) must be written to the USECRL register. 8.2.2.2 Flash Memory Protection The user is provided two forms of flash protection per 2-KB flash blocks in four pairs of 32-bit wide registers. The protection policy for each form is controlled by individual bits (per policy per block) in the FMPPEn and FMPREn registers. ■ Flash Memory Protection Program Enable (FMPPEn): If set, the block may be programmed (written) or erased. If cleared, the block may not be changed. ■ Flash Memory Protection Read Enable (FMPREn): If set, the block may be executed or read by software or debuggers. If cleared, the block may only be executed. The contents of the memory block are prohibited from being accessed as data and traversing the DCode bus. The policies may be combined as shown in Table 8-1 on page 141. 140 Preliminary November 30, 2007 LM3S6965 Microcontroller Table 8-1. Flash Protection Policy Combinations FMPPEn FMPREn Protection 0 1 0 1 0 0 1 1 Execute-only protection. The block may only be executed and may not be written or erased. This mode is used to protect code. The block may be written, erased or executed, but not read. This combination is unlikely to be used. Read-only protection. The block may be read or executed but may not be written or erased. This mode is used to lock the block from further modification while allowing any read or execute access. No protection. The block may be written, erased, executed or read. An access that attempts to program or erase a PE-protected block is prohibited. A controller interrupt may be optionally generated (by setting the AMASK bit in the FIM register) to alert software developers of poorly behaving software during the development and debug phases. An access that attempts to read an RE-protected block is prohibited. Such accesses return data filled with all 0s. A controller interrupt may be optionally generated to alert software developers of poorly behaving software during the development and debug phases. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This implements a policy of open access and programmability. The register bits may be changed by writing the specific register bit. The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. Details on programming these bits are discussed in “Nonvolatile Register Programming” on page 142. 8.3 8.3.1 Flash Memory Initialization and Configuration Flash Programming The Stellaris devices provide a user-friendly interface for flash programming. All erase/program operations are handled via three registers: FMA, FMD, and FMC. ® 8.3.1.1 To program a 32-bit word 1. Write source data to the FMD register. 2. Write the target address to the FMA register. 3. Write the flash write key and the WRITE bit (a value of 0xA442.0001) to the FMC register. 4. Poll the FMC register until the WRITE bit is cleared. 8.3.1.2 To perform an erase of a 1-KB page 1. Write the page address to the FMA register. 2. Write the flash write key and the ERASE bit (a value of 0xA442.0002) to the FMC register. 3. Poll the FMC register until the ERASE bit is cleared. 8.3.1.3 To perform a mass erase of the flash 1. Write the flash write key and the MERASE bit (a value of 0xA442.0004) to the FMC register. 2. Poll the FMC register until the MERASE bit is cleared. November 30, 2007 Preliminary 141 Internal Memory 8.3.2 Nonvolatile Register Programming This section discusses how to update registers that are resident within the flash memory itself. These registers exist in a separate space from the main flash array and are not affected by an ERASE or MASS ERASE operation. These nonvolatile registers are updated by using the COMT bit in the FMC register to activate a write operation. For the USER_DBG register, the data to be written must be loaded into the FMD register before it is "committed". All other registers are R/W and can have their operation tried before committing them to nonvolatile memory. Important: These registers can only have bits changed from 1 to 0 by the user and there is no mechanism for the user to erase them back to a 1 value. In addition, the USER_REG0, USER_REG1, and USER_DBG use bit 31 (NW) of their respective registers to indicate that they are available for user write. These three registers can only be written once whereas the flash protection registers may be written multiple times. Table 8-2 on page 142 provides the FMA address required for commitment of each of the registers and the source of the data to be written when the COMT bit of the FMC register is written with a value of 0xA442.0008. After writing the COMT bit, the user may poll the FMC register to wait for the commit operation to complete. Table 8-2. Flash Resident Registers Register to be Committed FMA Value FMPRE0 FMPRE1 FMPRE2 FMPRE3 FMPPE0 FMPPE1 FMPPE2 FMPPE3 USER_REG0 USER_REG1 USER_DBG a Data Source 0x0000.0000 FMPRE0 0x0000.0002 FMPRE1 0x0000.0004 FMPRE2 0x0000.0008 FMPRE3 0x0000.0001 FMPPE0 0x0000.0003 FMPPE1 0x0000.0005 FMPPE2 0x0000.0007 FMPPE3 0x8000.0000 USER_REG0 0x8000.0001 USER_REG1 0x7510.0000 FMD ® a. Which FMPREn and FMPPEn registers are available depend on the flash size of your particular Stellaris device. 8.4 Register Map Table 8-3 on page 142 lists the Flash memory and control registers. The offset listed is a hexadecimal increment to the register's address. The FMA, FMD, FMC, FCRIS, FCIM, and FCMISC registers are relative to the Flash control base address of 0x400F.D000. The FMPREn, FMPPEn, USECRL, USER_DBG, and USER_REGn registers are relative to the System Control base address of 0x400F.E000. Table 8-3. Flash Register Map Offset Name Type Reset Description See page Flash Control Offset 0x000 FMA R/W 0x0000.0000 Flash Memory Address 144 142 Preliminary November 30, 2007 LM3S6965 Microcontroller Offset 0x004 0x008 0x00C 0x010 0x014 Name FMD FMC FCRIS FCIM FCMISC Type R/W R/W RO R/W R/W1C Reset 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 Description Flash Memory Data Flash Memory Control Flash Controller Raw Interrupt Status Flash Controller Interrupt Mask Flash Controller Masked Interrupt Status and Clear See page 145 146 148 149 150 System Control Offset 0x130 0x200 0x134 0x400 0x140 0x1D0 0x1E0 0x1E4 0x204 0x208 0x20C 0x404 0x408 0x40C FMPRE0 FMPRE0 FMPPE0 FMPPE0 USECRL USER_DBG USER_REG0 USER_REG1 FMPRE1 FMPRE2 FMPRE3 FMPPE1 FMPPE2 FMPPE3 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0xFFFF.FFFF 0xFFFF.FFFF 0xFFFF.FFFF 0xFFFF.FFFF 0x31 0xFFFF.FFFE 0xFFFF.FFFF 0xFFFF.FFFF 0xFFFF.FFFF 0xFFFF.FFFF 0xFFFF.FFFF 0xFFFF.FFFF 0xFFFF.FFFF 0xFFFF.FFFF Flash Memory Protection Read Enable 0 Flash Memory Protection Read Enable 0 Flash Memory Protection Program Enable 0 Flash Memory Protection Program Enable 0 USec Reload User Debug User Register 0 User Register 1 Flash Memory Protection Read Enable 1 Flash Memory Protection Read Enable 2 Flash Memory Protection Read Enable 3 Flash Memory Protection Program Enable 1 Flash Memory Protection Program Enable 2 Flash Memory Protection Program Enable 3 152 152 153 153 151 154 155 156 157 158 159 160 161 162 8.5 Flash Register Descriptions (Flash Control Offset) The remainder of this section lists and describes the Flash Memory registers, in numerical order by address offset. Registers in this section are relative to the Flash control base address of 0x400F.D000. November 30, 2007 Preliminary 143 Internal Memory Register 1: Flash Memory Address (FMA), offset 0x000 During a write operation, this register contains a 4-byte-aligned address and specifies where the data is written. During erase operations, this register contains a 1 KB-aligned address and specifies which page is erased. Note that the alignment requirements must be met by software or the results of the operation are unpredictable. Flash Memory Address (FMA) Base 0x400F.D000 Offset 0x000 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 OFFSET Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 OFFSET R/W 0 1 R/W 0 0 R/W 0 R/W 0 Bit/Field 31:18 Name reserved Type RO Reset 0x0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Address Offset Address offset in flash where operation is performed, except for nonvolatile registers (see “Nonvolatile Register Programming” on page 142 for details on values for this field). 17:0 OFFSET R/W 0x0 144 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 2: Flash Memory Data (FMD), offset 0x004 This register contains the data to be written during the programming cycle or read during the read cycle. Note that the contents of this register are undefined for a read access of an execute-only block. This register is not used during the erase cycles. Flash Memory Data (FMD) Base 0x400F.D000 Offset 0x004 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 DATA Type Reset R/W 0 15 R/W 0 14 R/W 0 13 R/W 0 12 R/W 0 11 R/W 0 10 R/W 0 9 R/W 0 8 DATA Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 23 22 21 20 19 18 17 16 Bit/Field 31:0 Name DATA Type R/W Reset 0x0 Description Data Value Data value for write operation. November 30, 2007 Preliminary 145 Internal Memory Register 3: Flash Memory Control (FMC), offset 0x008 When this register is written, the flash controller initiates the appropriate access cycle for the location specified by the Flash Memory Address (FMA) register (see page 144). If the access is a write access, the data contained in the Flash Memory Data (FMD) register (see page 145) is written. This is the final register written and initiates the memory operation. There are four control bits in the lower byte of this register that, when set, initiate the memory operation. The most used of these register bits are the ERASE and WRITE bits. It is a programming error to write multiple control bits and the results of such an operation are unpredictable. Flash Memory Control (FMC) Base 0x400F.D000 Offset 0x008 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 WRKEY Type Reset WO 0 15 WO 0 14 WO 0 13 WO 0 12 WO 0 11 WO 0 10 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 WO 0 9 WO 0 8 WO 0 7 WO 0 6 WO 0 5 WO 0 4 WO 0 3 COMT R/W 0 WO 0 2 WO 0 1 WO 0 0 WRITE R/W 0 MERASE ERASE R/W 0 R/W 0 Bit/Field 31:16 Name WRKEY Type WO Reset 0x0 Description Flash Write Key This field contains a write key, which is used to minimize the incidence of accidental flash writes. The value 0xA442 must be written into this field for a write to occur. Writes to the FMC register without this WRKEY value are ignored. A read of this field returns the value 0. 15:4 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Commit Register Value Commit (write) of register value to nonvolatile storage. A write of 0 has no effect on the state of this bit. If read, the state of the previous commit access is provided. If the previous commit access is complete, a 0 is returned; otherwise, if the commit access is not complete, a 1 is returned. This can take up to 50 μs. 3 COMT R/W 0 2 MERASE R/W 0 Mass Erase Flash Memory If this bit is set, the flash main memory of the device is all erased. A write of 0 has no effect on the state of this bit. If read, the state of the previous mass erase access is provided. If the previous mass erase access is complete, a 0 is returned; otherwise, if the previous mass erase access is not complete, a 1 is returned. This can take up to 250 ms. 146 Preliminary November 30, 2007 LM3S6965 Microcontroller Bit/Field 1 Name ERASE Type R/W Reset 0 Description Erase a Page of Flash Memory If this bit is set, the page of flash main memory as specified by the contents of FMA is erased. A write of 0 has no effect on the state of this bit. If read, the state of the previous erase access is provided. If the previous erase access is complete, a 0 is returned; otherwise, if the previous erase access is not complete, a 1 is returned. This can take up to 25 ms. 0 WRITE R/W 0 Write a Word into Flash Memory If this bit is set, the data stored in FMD is written into the location as specified by the contents of FMA. A write of 0 has no effect on the state of this bit. If read, the state of the previous write update is provided. If the previous write access is complete, a 0 is returned; otherwise, if the write access is not complete, a 1 is returned. This can take up to 50 µs. November 30, 2007 Preliminary 147 Internal Memory Register 4: Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C This register indicates that the flash controller has an interrupt condition. An interrupt is only signaled if the corresponding FCIM register bit is set. Flash Controller Raw Interrupt Status (FCRIS) Base 0x400F.D000 Offset 0x00C Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 PRIS RO 0 RO 0 0 ARIS RO 0 Bit/Field 31:2 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Programming Raw Interrupt Status This bit indicates the current state of the programming cycle. If set, the programming cycle completed; if cleared, the programming cycle has not completed. Programming cycles are either write or erase actions generated through the Flash Memory Control (FMC) register bits (see page 146). 1 PRIS RO 0 0 ARIS RO 0 Access Raw Interrupt Status This bit indicates if the flash was improperly accessed. If set, the program tried to access the flash counter to the policy as set in the Flash Memory Protection Read Enable (FMPREn) and Flash Memory Protection Program Enable (FMPPEn) registers. Otherwise, no access has tried to improperly access the flash. 148 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 5: Flash Controller Interrupt Mask (FCIM), offset 0x010 This register controls whether the flash controller generates interrupts to the controller. Flash Controller Interrupt Mask (FCIM) Base 0x400F.D000 Offset 0x010 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 PMASK R/W 0 RO 0 0 AMASK R/W 0 Bit/Field 31:2 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Programming Interrupt Mask This bit controls the reporting of the programming raw interrupt status to the controller. If set, a programming-generated interrupt is promoted to the controller. Otherwise, interrupts are recorded but suppressed from the controller. 1 PMASK R/W 0 0 AMASK R/W 0 Access Interrupt Mask This bit controls the reporting of the access raw interrupt status to the controller. If set, an access-generated interrupt is promoted to the controller. Otherwise, interrupts are recorded but suppressed from the controller. November 30, 2007 Preliminary 149 Internal Memory Register 6: Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014 This register provides two functions. First, it reports the cause of an interrupt by indicating which interrupt source or sources are signalling the interrupt. Second, it serves as the method to clear the interrupt reporting. Flash Controller Masked Interrupt Status and Clear (FCMISC) Base 0x400F.D000 Offset 0x014 Type R/W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 PMISC R/W1C 0 RO 0 0 AMISC R/W1C 0 Bit/Field 31:2 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Programming Masked Interrupt Status and Clear This bit indicates whether an interrupt was signaled because a programming cycle completed and was not masked. This bit is cleared by writing a 1. The PRIS bit in the FCRIS register (see page 148) is also cleared when the PMISC bit is cleared. 1 PMISC R/W1C 0 0 AMISC R/W1C 0 Access Masked Interrupt Status and Clear This bit indicates whether an interrupt was signaled because an improper access was attempted and was not masked. This bit is cleared by writing a 1. The ARIS bit in the FCRIS register is also cleared when the AMISC bit is cleared. 8.6 Flash Register Descriptions (System Control Offset) The remainder of this section lists and describes the Flash Memory registers, in numerical order by address offset. Registers in this section are relative to the System Control base address of 0x400F.E000. 150 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 7: USec Reload (USECRL), offset 0x140 Note: Offset is relative to System Control base address of 0x400F.E000 This register is provided as a means of creating a 1-μs tick divider reload value for the flash controller. The internal flash has specific minimum and maximum requirements on the length of time the high voltage write pulse can be applied. It is required that this register contain the operating frequency (in MHz -1) whenever the flash is being erased or programmed. The user is required to change this value if the clocking conditions are changed for a flash erase/program operation. USec Reload (USECRL) Base 0x400F.E000 Offset 0x140 Type R/W, reset 0x31 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 USEC RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 1 R/W 1 R/W 0 R/W 0 R/W 0 R/W 1 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Microsecond Reload Value MHz -1 of the controller clock when the flash is being erased or programmed. USEC should be set to 0x31 (50 MHz) whenever the flash is being erased or programmed. 7:0 USEC R/W 0x31 November 30, 2007 Preliminary 151 Internal Memory Register 8: Flash Memory Protection Read Enable 0 (FMPRE0), offset 0x130 and 0x200 Note: Note: This register is aliased for backwards compatability. Offset is relative to System Control base address of 0x400FE000. This register stores the read-only protection bits for each 2-KB flash block (FMPPEn stores the execute-only bits). This register is loaded during the power-on reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves a policy of open access and programmability. The register bits may be changed by writing the specific register bit. However, this register is R/W0; the user can only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. For additional information, see the "Flash Memory Protection" section. Flash Memory Protection Read Enable 0 (FMPRE0) Base 0x400F.D000 Offset 0x130 and 0x200 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 READ_ENABLE Type Reset R/W 1 15 R/W 1 14 R/W 1 13 R/W 1 12 R/W 1 11 R/W 1 10 R/W 1 9 R/W 1 8 R/W 1 7 R/W 1 6 R/W 1 5 R/W 1 4 R/W 1 3 R/W 1 2 R/W 1 1 R/W 1 0 READ_ENABLE Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 Bit/Field 31:0 Name READ_ENABLE Type R/W Reset Description 0xFFFFFFFF Flash Read Enable Enables 2-KB flash blocks to be executed or read. The policies may be combined as shown in the table “Flash Protection Policy Combinations”. Value Description 0xFFFFFFFF Enables 256 KB of flash. 152 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 9: Flash Memory Protection Program Enable 0 (FMPPE0), offset 0x134 and 0x400 Note: Note: This register is aliased for backwards compatability. Offset is relative to System Control base address of 0x400FE000. This register stores the execute-only protection bits for each 2-KB flash block (FMPREn stores the execute-only bits). This register is loaded during the power-on reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves a policy of open access and programmability. The register bits may be changed by writing the specific register bit. However, this register is R/W0; the user can only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. For additional information, see the "Flash Memory Protection" section. Flash Memory Protection Program Enable 0 (FMPPE0) Base 0x400F.D000 Offset 0x134 and 0x400 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PROG_ENABLE Type Reset R/W 1 15 R/W 1 14 R/W 1 13 R/W 1 12 R/W 1 11 R/W 1 10 R/W 1 9 R/W 1 8 R/W 1 7 R/W 1 6 R/W 1 5 R/W 1 4 R/W 1 3 R/W 1 2 R/W 1 1 R/W 1 0 PROG_ENABLE Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 Bit/Field 31:0 Name PROG_ENABLE Type R/W Reset Description 0xFFFFFFFF Flash Programming Enable Configures 2-KB flash blocks to be execute only. The policies may be combined as shown in the table “Flash Protection Policy Combinations”. Value Description 0xFFFFFFFF Enables 256 KB of flash. November 30, 2007 Preliminary 153 Internal Memory Register 10: User Debug (USER_DBG), offset 0x1D0 Note: Offset is relative to System Control base address of 0x400FE000. This register provides a write-once mechanism to disable external debugger access to the device in addition to 27 additional bits of user-defined data. The DBG0 bit (bit 0) is set to 0 from the factory and the DBG1 bit (bit 1) is set to 1, which enables external debuggers. Changing the DBG1 bit to 0 disables any external debugger access to the device permanently, starting with the next power-up cycle of the device. The NOTWRITTEN bit (bit 31) indicates that the register is available to be written and is controlled through hardware to ensure that the register is only written once. User Debug (USER_DBG) Base 0x400F.E000 Offset 0x1D0 Type R/W, reset 0xFFFF.FFFE 31 NW Type Reset R/W 1 15 R/W 1 14 R/W 1 13 R/W 1 12 R/W 1 11 R/W 1 10 R/W 1 9 DATA Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 8 30 29 28 27 26 25 24 23 DATA R/W 1 7 R/W 1 6 R/W 1 5 R/W 1 4 R/W 1 3 R/W 1 2 R/W 1 1 DBG1 R/W 1 R/W 1 0 DBG0 R/W 0 22 21 20 19 18 17 16 Bit/Field 31 Name NW Type R/W Reset 1 Description User Debug Not Written Specifies that this 32-bit dword has not been written. 30:2 DATA R/W 0x1FFFFFFF User Data Contains the user data value. This field is initialized to all 1s and can only be written once. 1 DBG1 R/W 1 Debug Control 1 The DBG1 bit must be 1 and DBG0 must be 0 for debug to be available. 0 DBG0 R/W 0 Debug Control 0 The DBG1 bit must be 1 and DBG0 must be 0 for debug to be available. 154 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 11: User Register 0 (USER_REG0), offset 0x1E0 Note: Offset is relative to System Control base address of 0x400FE000. This register provides 31 bits of user-defined data that is non-volatile and can only be written once. Bit 31 indicates that the register is available to be written and is controlled through hardware to ensure that the register is only written once. The write-once characteristics of this register are useful for keeping static information like communication addresses that need to be unique per part and would otherwise require an external EEPROM or other non-volatile device. User Register 0 (USER_REG0) Base 0x400F.E000 Offset 0x1E0 Type R/W, reset 0xFFFF.FFFF 31 NW Type Reset R/W 1 15 R/W 1 14 R/W 1 13 R/W 1 12 R/W 1 11 R/W 1 10 R/W 1 9 R/W 1 8 DATA Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 30 29 28 27 26 25 24 23 DATA R/W 1 7 R/W 1 6 R/W 1 5 R/W 1 4 R/W 1 3 R/W 1 2 R/W 1 1 R/W 1 0 22 21 20 19 18 17 16 Bit/Field 31 Name NW Type R/W Reset 1 Description Not Written Specifies that this 32-bit dword has not been written. 30:0 DATA R/W 0x7FFFFFFF User Data Contains the user data value. This field is initialized to all 1s and can only be written once. November 30, 2007 Preliminary 155 Internal Memory Register 12: User Register 1 (USER_REG1), offset 0x1E4 Note: Offset is relative to System Control base address of 0x400FE000. This register provides 31 bits of user-defined data that is non-volatile and can only be written once. Bit 31 indicates that the register is available to be written and is controlled through hardware to ensure that the register is only written once. The write-once characteristics of this register are useful for keeping static information like communication addresses that need to be unique per part and would otherwise require an external EEPROM or other non-volatile device. User Register 1 (USER_REG1) Base 0x400F.E000 Offset 0x1E4 Type R/W, reset 0xFFFF.FFFF 31 NW Type Reset R/W 1 15 R/W 1 14 R/W 1 13 R/W 1 12 R/W 1 11 R/W 1 10 R/W 1 9 R/W 1 8 DATA Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 30 29 28 27 26 25 24 23 DATA R/W 1 7 R/W 1 6 R/W 1 5 R/W 1 4 R/W 1 3 R/W 1 2 R/W 1 1 R/W 1 0 22 21 20 19 18 17 16 Bit/Field 31 Name NW Type R/W Reset 1 Description Not Written Specifies that this 32-bit dword has not been written. 30:0 DATA R/W 0x7FFFFFFF User Data Contains the user data value. This field is initialized to all 1s and can only be written once. 156 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 13: Flash Memory Protection Read Enable 1 (FMPRE1), offset 0x204 Note: Offset is relative to System Control base address of 0x400FE000. This register stores the read-only protection bits for each 2-KB flash block (FMPPEn stores the execute-only bits). This register is loaded during the power-on reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves a policy of open access and programmability. The register bits may be changed by writing the specific register bit. However, this register is R/W0; the user can only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. For additional information, see the "Flash Memory Protection" section. Flash Memory Protection Read Enable 1 (FMPRE1) Base 0x400F.E000 Offset 0x204 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 READ_ENABLE Type Reset R/W 1 15 R/W 1 14 R/W 1 13 R/W 1 12 R/W 1 11 R/W 1 10 R/W 1 9 R/W 1 8 R/W 1 7 R/W 1 6 R/W 1 5 R/W 1 4 R/W 1 3 R/W 1 2 R/W 1 1 R/W 1 0 READ_ENABLE Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 Bit/Field 31:0 Name READ_ENABLE Type R/W Reset Description 0xFFFFFFFF Flash Read Enable Enables 2-KB flash blocks to be executed or read. The policies may be combined as shown in the table “Flash Protection Policy Combinations”. Value Description 0xFFFFFFFF Enables 256 KB of flash. November 30, 2007 Preliminary 157 Internal Memory Register 14: Flash Memory Protection Read Enable 2 (FMPRE2), offset 0x208 Note: Offset is relative to System Control base address of 0x400FE000. This register stores the read-only protection bits for each 2-KB flash block (FMPPEn stores the execute-only bits). This register is loaded during the power-on reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves a policy of open access and programmability. The register bits may be changed by writing the specific register bit. However, this register is R/W0; the user can only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. For additional information, see the "Flash Memory Protection" section. Flash Memory Protection Read Enable 2 (FMPRE2) Base 0x400F.E000 Offset 0x208 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 READ_ENABLE Type Reset R/W 1 15 R/W 1 14 R/W 1 13 R/W 1 12 R/W 1 11 R/W 1 10 R/W 1 9 R/W 1 8 R/W 1 7 R/W 1 6 R/W 1 5 R/W 1 4 R/W 1 3 R/W 1 2 R/W 1 1 R/W 1 0 READ_ENABLE Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 Bit/Field 31:0 Name READ_ENABLE Type R/W Reset Description 0xFFFFFFFF Flash Read Enable Enables 2-KB flash blocks to be executed or read. The policies may be combined as shown in the table “Flash Protection Policy Combinations”. Value Description 0xFFFFFFFF Enables 256 KB of flash. 158 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 15: Flash Memory Protection Read Enable 3 (FMPRE3), offset 0x20C Note: Offset is relative to System Control base address of 0x400FE000. This register stores the read-only protection bits for each 2-KB flash block (FMPPEn stores the execute-only bits). This register is loaded during the power-on reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves a policy of open access and programmability. The register bits may be changed by writing the specific register bit. However, this register is R/W0; the user can only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. For additional information, see the "Flash Memory Protection" section. Flash Memory Protection Read Enable 3 (FMPRE3) Base 0x400F.E000 Offset 0x20C Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 READ_ENABLE Type Reset R/W 1 15 R/W 1 14 R/W 1 13 R/W 1 12 R/W 1 11 R/W 1 10 R/W 1 9 R/W 1 8 R/W 1 7 R/W 1 6 R/W 1 5 R/W 1 4 R/W 1 3 R/W 1 2 R/W 1 1 R/W 1 0 READ_ENABLE Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 Bit/Field 31:0 Name READ_ENABLE Type R/W Reset Description 0xFFFFFFFF Flash Read Enable Enables 2-KB flash blocks to be executed or read. The policies may be combined as shown in the table “Flash Protection Policy Combinations”. Value Description 0xFFFFFFFF Enables 256 KB of flash. November 30, 2007 Preliminary 159 Internal Memory Register 16: Flash Memory Protection Program Enable 1 (FMPPE1), offset 0x404 Note: Offset is relative to System Control base address of 0x400FE000. This register stores the execute-only protection bits for each 2-KB flash block (FMPREn stores the execute-only bits). This register is loaded during the power-on reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves a policy of open access and programmability. The register bits may be changed by writing the specific register bit. However, this register is R/W0; the user can only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. For additional information, see the "Flash Memory Protection" section. Flash Memory Protection Program Enable 1 (FMPPE1) Base 0x400F.E000 Offset 0x404 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PROG_ENABLE Type Reset R/W 1 15 R/W 1 14 R/W 1 13 R/W 1 12 R/W 1 11 R/W 1 10 R/W 1 9 R/W 1 8 R/W 1 7 R/W 1 6 R/W 1 5 R/W 1 4 R/W 1 3 R/W 1 2 R/W 1 1 R/W 1 0 PROG_ENABLE Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 Bit/Field 31:0 Name PROG_ENABLE Type R/W Reset Description 0xFFFFFFFF Flash Programming Enable Configures 2-KB flash blocks to be execute only. The policies may be combined as shown in the table “Flash Protection Policy Combinations”. Value Description 0xFFFFFFFF Enables 256 KB of flash. 160 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 17: Flash Memory Protection Program Enable 2 (FMPPE2), offset 0x408 Note: Offset is relative to System Control base address of 0x400FE000. This register stores the execute-only protection bits for each 2-KB flash block (FMPREn stores the execute-only bits). This register is loaded during the power-on reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves a policy of open access and programmability. The register bits may be changed by writing the specific register bit. However, this register is R/W0; the user can only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. For additional information, see the "Flash Memory Protection" section. Flash Memory Protection Program Enable 2 (FMPPE2) Base 0x400F.E000 Offset 0x408 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PROG_ENABLE Type Reset R/W 1 15 R/W 1 14 R/W 1 13 R/W 1 12 R/W 1 11 R/W 1 10 R/W 1 9 R/W 1 8 R/W 1 7 R/W 1 6 R/W 1 5 R/W 1 4 R/W 1 3 R/W 1 2 R/W 1 1 R/W 1 0 PROG_ENABLE Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 Bit/Field 31:0 Name PROG_ENABLE Type R/W Reset Description 0xFFFFFFFF Flash Programming Enable Configures 2-KB flash blocks to be execute only. The policies may be combined as shown in the table “Flash Protection Policy Combinations”. Value Description 0xFFFFFFFF Enables 256 KB of flash. November 30, 2007 Preliminary 161 Internal Memory Register 18: Flash Memory Protection Program Enable 3 (FMPPE3), offset 0x40C Note: Offset is relative to System Control base address of 0x400FE000. This register stores the execute-only protection bits for each 2-KB flash block (FMPREn stores the execute-only bits). This register is loaded during the power-on reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks. This achieves a policy of open access and programmability. The register bits may be changed by writing the specific register bit. However, this register is R/W0; the user can only change the protection bit from a 1 to a 0 (and may NOT change a 0 to a 1). The changes are not permanent until the register is committed (saved), at which point the bit change is permanent. If a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. For additional information, see the "Flash Memory Protection" section. Flash Memory Protection Program Enable 3 (FMPPE3) Base 0x400F.E000 Offset 0x40C Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PROG_ENABLE Type Reset R/W 1 15 R/W 1 14 R/W 1 13 R/W 1 12 R/W 1 11 R/W 1 10 R/W 1 9 R/W 1 8 R/W 1 7 R/W 1 6 R/W 1 5 R/W 1 4 R/W 1 3 R/W 1 2 R/W 1 1 R/W 1 0 PROG_ENABLE Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 Bit/Field 31:0 Name PROG_ENABLE Type R/W Reset Description 0xFFFFFFFF Flash Programming Enable Configures 2-KB flash blocks to be execute only. The policies may be combined as shown in the table “Flash Protection Policy Combinations”. Value Description 0xFFFFFFFF Enables 256 KB of flash. 162 Preliminary November 30, 2007 LM3S6965 Microcontroller 9 General-Purpose Input/Outputs (GPIOs) The GPIO module is composed of seven physical GPIO blocks, each corresponding to an individual GPIO port (Port A, Port B, Port C, Port D, Port E, Port F, and Port G, ). The GPIO module is FiRM-compliant and supports 0-42 programmable input/output pins, depending on the peripherals being used. The GPIO module has the following features: ■ Programmable control for GPIO interrupts – Interrupt generation masking – Edge-triggered on rising, falling, or both – Level-sensitive on High or Low values ■ 5-V-tolerant input/outputs ■ Bit masking in both read and write operations through address lines ■ Programmable control for GPIO pad configuration – Weak pull-up or pull-down resistors – 2-mA, 4-mA, and 8-mA pad drive – Slew rate control for the 8-mA drive – Open drain enables – Digital input enables 9.1 Functional Description Important: All GPIO pins are tri-stated by default (GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0, and GPIOPUR=0), with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]). The JTAG/SWD pins default to their JTAG/SWD functionality (GPIOAFSEL=1, GPIODEN=1 and GPIOPUR=1). A Power-On-Reset (POR) or asserting RST puts both groups of pins back to their default state. Each GPIO port is a separate hardware instantiation of the same physical block (see Figure 9-1 on page 164). The LM3S6965 microcontroller contains seven ports and thus seven of these physical GPIO blocks. November 30, 2007 Preliminary 163 General-Purpose Input/Outputs (GPIOs) Figure 9-1. GPIO Port Block Diagram Commit Control GPIOLOCK GPIOCR Alternate Input Alternate Output Alternate Output Enable Pad Output Mode Control GPIOAFSEL DEMUX MUX Pad Input Data Control GPIODATA GPIODIR GPIO Input GPIO Output Digital I/O Pad Package I/O Pin MUX GPIO Output Enable Pad Output Enable Interrupt Control Interrupt Pad Control GPIODR2R GPIODR4R GPIODR8R GPIOSLR GPIOPUR GPIOPDR GPIOODR GPIODEN GPIOIS GPIOIBE GPIOIEV GPIOIM GPIORIS GPIOMIS GPIOICR Identification Registers GPIOPeriphID0 GPIOPeriphID1 GPIOPeriphID2 GPIOPeriphID3 GPIOPeriphID4 GPIOPeriphID5 GPIOPeriphID6 GPIOPeriphID7 GPIOPCellID0 GPIOPCellID1 GPIOPCellID2 GPIOPCellID3 9.1.1 Data Control The data control registers allow software to configure the operational modes of the GPIOs. The data direction register configures the GPIO as an input or an output while the data register either captures incoming data or drives it out to the pads. 9.1.1.1 Data Direction Operation The GPIO Direction (GPIODIR) register (see page 171) is used to configure each individual pin as an input or output. When the data direction bit is set to 0, the GPIO is configured as an input and the corresponding data register bit will capture and store the value on the GPIO port. When the data direction bit is set to 1, the GPIO is configured as an output and the corresponding data register bit will be driven out on the GPIO port. 9.1.1.2 Data Register Operation To aid in the efficiency of software, the GPIO ports allow for the modification of individual bits in the GPIO Data (GPIODATA) register (see page 170) by using bits [9:2] of the address bus as a mask. This allows software drivers to modify individual GPIO pins in a single instruction, without affecting the state of the other pins. This is in contrast to the "typical" method of doing a read-modify-write operation to set or clear an individual GPIO pin. To accommodate this feature, the GPIODATA register covers 256 locations in the memory map. During a write, if the address bit associated with that data bit is set to 1, the value of the GPIODATA register is altered. If it is cleared to 0, it is left unchanged. 164 Preliminary November 30, 2007 LM3S6965 Microcontroller For example, writing a value of 0xEB to the address GPIODATA + 0x098 would yield as shown in Figure 9-2 on page 165, where u is data unchanged by the write. Figure 9-2. GPIODATA Write Example ADDR[9:2] 0x098 0xEB GPIODATA 9 0 8 0 7 1 6 0 5 0 4 1 3 1 2 0 1 1 0 0 1 1 1 0 1 0 1 1 u 7 u 6 1 5 u 4 u 3 0 2 1 1 u 0 During a read, if the address bit associated with the data bit is set to 1, the value is read. If the address bit associated with the data bit is set to 0, it is read as a zero, regardless of its actual value. For example, reading address GPIODATA + 0x0C4 yields as shown in Figure 9-3 on page 165. Figure 9-3. GPIODATA Read Example ADDR[9:2] 0x0C4 GPIODATA Returned Value 9 0 8 0 7 1 6 1 5 0 4 0 3 0 2 1 1 0 0 0 1 0 1 1 1 1 1 0 0 7 0 6 1 5 1 4 0 3 0 2 0 1 0 0 9.1.2 Interrupt Control The interrupt capabilities of each GPIO port are controlled by a set of seven registers. With these registers, it is possible to select the source of the interrupt, its polarity, and the edge properties. When one or more GPIO inputs cause an interrupt, a single interrupt output is sent to the interrupt controller for the entire GPIO port. For edge-triggered interrupts, software must clear the interrupt to enable any further interrupts. For a level-sensitive interrupt, it is assumed that the external source holds the level constant for the interrupt to be recognized by the controller. Three registers are required to define the edge or sense that causes interrupts: ■ GPIO Interrupt Sense (GPIOIS) register (see page 172) ■ GPIO Interrupt Both Edges (GPIOIBE) register (see page 173) ■ GPIO Interrupt Event (GPIOIEV) register (see page 174) Interrupts are enabled/disabled via the GPIO Interrupt Mask (GPIOIM) register (see page 175). When an interrupt condition occurs, the state of the interrupt signal can be viewed in two locations: the GPIO Raw Interrupt Status (GPIORIS) and GPIO Masked Interrupt Status (GPIOMIS) registers (see page 176 and page 177). As the name implies, the GPIOMIS register only shows interrupt conditions that are allowed to be passed to the controller. The GPIORIS register indicates that a GPIO pin meets the conditions for an interrupt, but has not necessarily been sent to the controller. November 30, 2007 Preliminary 165 General-Purpose Input/Outputs (GPIOs) In addition to providing GPIO functionality, PB4 can also be used as an external trigger for the ADC. If PB4 is configured as a non-masked interrupt pin (GPIOIM is set to 1), not only is an interrupt for PortB generated, but an external trigger signal is sent to the ADC. If the ADC Event Multiplexer Select (ADCEMUX) register is configured to use the external trigger, an ADC conversion is initiated. If no other PortB pins are being used to generate interrupts, the ARM Integrated Nested Vectored Interrupt Controller (NVIC) Interrupt Set Enable (SETNA) register can disable the PortB interrupts and the ADC interrupt can be used to read back the converted data. Otherwise, the PortB interrupt handler needs to ignore and clear interrupts on B4, and wait for the ADC interrupt or the ADC interrupt needs to be disabled in the SETNA register and the PortB interrupt handler polls the ADC registers until the conversion is completed. Interrupts are cleared by writing a 1 to the GPIO Interrupt Clear (GPIOICR) register (see page 178). When programming the following interrupt control registers, the interrupts should be masked (GPIOIM set to 0). Writing any value to an interrupt control register (GPIOIS, GPIOIBE, or GPIOIEV) can generate a spurious interrupt if the corresponding bits are enabled. 9.1.3 Mode Control The GPIO pins can be controlled by either hardware or software. When hardware control is enabled via the GPIO Alternate Function Select (GPIOAFSEL) register (see page 179), the pin state is controlled by its alternate function (that is, the peripheral). Software control corresponds to GPIO mode, where the GPIODATA register is used to read/write the corresponding pins. 9.1.4 Commit Control The commit control registers provide a layer of protection against accidental programming of critical hardware peripherals. Writes to protected bits of the GPIO Alternate Function Select (GPIOAFSEL) register (see page 179) are not committed to storage unless the GPIO Lock (GPIOLOCK) register (see page 189) has been unlocked and the appropriate bits of the GPIO Commit (GPIOCR) register (see page 190) have been set to 1. 9.1.5 Pad Control The pad control registers allow for GPIO pad configuration by software based on the application requirements. The pad control registers include the GPIODR2R, GPIODR4R, GPIODR8R, GPIOODR, GPIOPUR, GPIOPDR, GPIOSLR, and GPIODEN registers. 9.1.6 Identification The identification registers configured at reset allow software to detect and identify the module as a GPIO block. The identification registers include the GPIOPeriphID0-GPIOPeriphID7 registers as well as the GPIOPCellID0-GPIOPCellID3 registers. 9.2 Initialization and Configuration To use the GPIO, the peripheral clock must be enabled by setting the appropriate GPIO Port bit field (GPIOn) in the RCGC2 register. On reset, all GPIO pins (except for the five JTAG pins) are configured out of reset to be undriven (tristate): GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0, and GPIOPUR=0. Table 9-1 on page 167 shows all possible configurations of the GPIO pads and the control register settings required to achieve them. Table 9-2 on page 167 shows how a rising edge interrupt would be configured for pin 2 of a GPIO port. 166 Preliminary November 30, 2007 LM3S6965 Microcontroller Table 9-1. GPIO Pad Configuration Examples Configuration GPIO Register Bit Value AFSEL Digital Input (GPIO) Digital Output (GPIO) Open Drain Input (GPIO) Open Drain Output (GPIO) Open Drain Input/Output (I2C) Digital Input (Timer CCP) Digital Input (QEI) Digital Output (PWM) Digital Output (Timer PWM) Digital Input/Output (SSI) Digital Input/Output (UART) Analog Input (Comparator) Digital Output (Comparator) 0 0 0 0 1 1 1 1 1 1 1 0 1 DIR 0 1 0 1 X X X X X X X 0 X a ODR 0 0 1 1 1 0 0 0 0 0 0 0 0 DEN 1 1 1 1 1 1 1 1 1 1 1 0 1 PUR ? ? X X X ? ? ? ? ? ? 0 ? PDR ? ? X X X ? ? ? ? ? ? 0 ? DR2R X ? X ? ? X X ? ? ? ? X ? DR4R X ? X ? ? X X ? ? ? ? X ? DR8R X ? X ? ? X X ? ? ? ? X ? SLR X ? X ? ? X X ? ? ? ? X ? a. X=Ignored (don’t care bit) ?=Can be either 0 or 1, depending on the configuration Table 9-2. GPIO Interrupt Configuration Example Register Desired Interrupt Event Trigger 0=edge 1=level GPIOIBE 0=single edge 1=both edges GPIOIEV 0=Low level, or negative edge 1=High level, or positive edge GPIOIM 0=masked 1=not masked a. X=Ignored (don’t care bit) 0 0 0 0 0 1 0 0 X X X X X 1 X X X X X X X 0 X X Pin 2 Bit Value 7 6 a 5 4 3 2 1 0 GPIOIS X X X X X 0 X X November 30, 2007 Preliminary 167 General-Purpose Input/Outputs (GPIOs) 9.3 Register Map Table 9-3 on page 168 lists the GPIO registers. The offset listed is a hexadecimal increment to the register ’s address, relative to that GPIO port’s base address: ■ GPIO Port A: 0x4000.4000 ■ GPIO Port B: 0x4000.5000 ■ GPIO Port C: 0x4000.6000 ■ GPIO Port D: 0x4000.7000 ■ GPIO Port E: 0x4002.4000 ■ GPIO Port F: 0x4002.5000 ■ GPIO Port G: 0x4002.6000 Important: The GPIO registers in this chapter are duplicated in each GPIO block, however, depending on the block, all eight bits may not be connected to a GPIO pad. In those cases, writing to those unconnected bits has no effect and reading those unconnected bits returns no meaningful data. Note: The default reset value for the GPIOAFSEL, GPIOPUR, and GPIODEN registers are 0x0000.0000 for all GPIO pins, with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]). These five pins default to JTAG/SWD functionality. Because of this, the default reset value of these registers for GPIO Port B is 0x0000.0080 while the default reset value for Port C is 0x0000.000F. The default register type for the GPIOCR register is RO for all GPIO pins, with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]). These five pins are currently the only GPIOs that are protected by the GPIOCR register. Because of this, the register type for GPIO Port B7 and GPIO Port C[3:0] is R/W. The default reset value for the GPIOCR register is 0x0000.00FF for all GPIO pins, with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]). To ensure that the JTAG port is not accidentally programmed as a GPIO, these five pins default to non-commitable. Because of this, the default reset value of GPIOCR for GPIO Port B is 0x0000.007F while the default reset value of GPIOCR for Port C is 0x0000.00F0. Table 9-3. GPIO Register Map Offset 0x000 0x400 0x404 0x408 0x40C 0x410 Name GPIODATA GPIODIR GPIOIS GPIOIBE GPIOIEV GPIOIM Type R/W R/W R/W R/W R/W R/W Reset 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 Description GPIO Data GPIO Direction GPIO Interrupt Sense GPIO Interrupt Both Edges GPIO Interrupt Event GPIO Interrupt Mask See page 170 171 172 173 174 175 168 Preliminary November 30, 2007 LM3S6965 Microcontroller Offset 0x414 0x418 0x41C 0x420 0x500 0x504 0x508 0x50C 0x510 0x514 0x518 0x51C 0x520 0x524 0xFD0 0xFD4 0xFD8 0xFDC 0xFE0 0xFE4 0xFE8 0xFEC 0xFF0 0xFF4 0xFF8 0xFFC Name GPIORIS GPIOMIS GPIOICR GPIOAFSEL GPIODR2R GPIODR4R GPIODR8R GPIOODR GPIOPUR GPIOPDR GPIOSLR GPIODEN GPIOLOCK GPIOCR GPIOPeriphID4 GPIOPeriphID5 GPIOPeriphID6 GPIOPeriphID7 GPIOPeriphID0 GPIOPeriphID1 GPIOPeriphID2 GPIOPeriphID3 GPIOPCellID0 GPIOPCellID1 GPIOPCellID2 GPIOPCellID3 Type RO RO W1C R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W RO RO RO RO RO RO RO RO RO RO RO RO Reset 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.00FF 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0001 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0061 0x0000.0000 0x0000.0018 0x0000.0001 0x0000.000D 0x0000.00F0 0x0000.0005 0x0000.00B1 Description GPIO Raw Interrupt Status GPIO Masked Interrupt Status GPIO Interrupt Clear GPIO Alternate Function Select GPIO 2-mA Drive Select GPIO 4-mA Drive Select GPIO 8-mA Drive Select GPIO Open Drain Select GPIO Pull-Up Select GPIO Pull-Down Select GPIO Slew Rate Control Select GPIO Digital Enable GPIO Lock GPIO Commit GPIO Peripheral Identification 4 GPIO Peripheral Identification 5 GPIO Peripheral Identification 6 GPIO Peripheral Identification 7 GPIO Peripheral Identification 0 GPIO Peripheral Identification 1 GPIO Peripheral Identification 2 GPIO Peripheral Identification 3 GPIO PrimeCell Identification 0 GPIO PrimeCell Identification 1 GPIO PrimeCell Identification 2 GPIO PrimeCell Identification 3 See page 176 177 178 179 181 182 183 184 185 186 187 188 189 190 192 193 194 195 196 197 198 199 200 201 202 203 9.4 Register Descriptions The remainder of this section lists and describes the GPIO registers, in numerical order by address offset. November 30, 2007 Preliminary 169 General-Purpose Input/Outputs (GPIOs) Register 1: GPIO Data (GPIODATA), offset 0x000 The GPIODATA register is the data register. In software control mode, values written in the GPIODATA register are transferred onto the GPIO port pins if the respective pins have been configured as outputs through the GPIO Direction (GPIODIR) register (see page 171). In order to write to GPIODATA, the corresponding bits in the mask, resulting from the address bus bits [9:2], must be High. Otherwise, the bit values remain unchanged by the write. Similarly, the values read from this register are determined for each bit by the mask bit derived from the address used to access the data register, bits [9:2]. Bits that are 1 in the address mask cause the corresponding bits in GPIODATA to be read, and bits that are 0 in the address mask cause the corresponding bits in GPIODATA to be read as 0, regardless of their value. A read from GPIODATA returns the last bit value written if the respective pins are configured as outputs, or it returns the value on the corresponding input pin when these are configured as inputs. All bits are cleared by a reset. GPIO Data (GPIODATA) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x000 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 DATA RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPIO Data This register is virtually mapped to 256 locations in the address space. To facilitate the reading and writing of data to these registers by independent drivers, the data read from and the data written to the registers are masked by the eight address lines ipaddr[9:2]. Reads from this register return its current state. Writes to this register only affect bits that are not masked by ipaddr[9:2] and are configured as outputs. See “Data Register Operation” on page 164 for examples of reads and writes. 7:0 DATA R/W 0x00 170 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 2: GPIO Direction (GPIODIR), offset 0x400 The GPIODIR register is the data direction register. Bits set to 1 in the GPIODIR register configure the corresponding pin to be an output, while bits set to 0 configure the pins to be inputs. All bits are cleared by a reset, meaning all GPIO pins are inputs by default. GPIO Direction (GPIODIR) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x400 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 DIR RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPIO Data Direction The DIR values are defined as follows: Value Description 0 1 Pins are inputs. Pins are outputs. 7:0 DIR R/W 0x00 November 30, 2007 Preliminary 171 General-Purpose Input/Outputs (GPIOs) Register 3: GPIO Interrupt Sense (GPIOIS), offset 0x404 The GPIOIS register is the interrupt sense register. Bits set to 1 in GPIOIS configure the corresponding pins to detect levels, while bits set to 0 configure the pins to detect edges. All bits are cleared by a reset. GPIO Interrupt Sense (GPIOIS) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x404 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 IS RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPIO Interrupt Sense The IS values are defined as follows: Value Description 0 1 Edge on corresponding pin is detected (edge-sensitive). Level on corresponding pin is detected (level-sensitive). 7:0 IS R/W 0x00 172 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 4: GPIO Interrupt Both Edges (GPIOIBE), offset 0x408 The GPIOIBE register is the interrupt both-edges register. When the corresponding bit in the GPIO Interrupt Sense (GPIOIS) register (see page 172) is set to detect edges, bits set to High in GPIOIBE configure the corresponding pin to detect both rising and falling edges, regardless of the corresponding bit in the GPIO Interrupt Event (GPIOIEV) register (see page 174). Clearing a bit configures the pin to be controlled by GPIOIEV. All bits are cleared by a reset. GPIO Interrupt Both Edges (GPIOIBE) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x408 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 IBE RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPIO Interrupt Both Edges The IBE values are defined as follows: Value Description 0 1 Interrupt generation is controlled by the GPIO Interrupt Event (GPIOIEV) register (see page 174). Both edges on the corresponding pin trigger an interrupt. Note: Single edge is determined by the corresponding bit in GPIOIEV. 7:0 IBE R/W 0x00 November 30, 2007 Preliminary 173 General-Purpose Input/Outputs (GPIOs) Register 5: GPIO Interrupt Event (GPIOIEV), offset 0x40C The GPIOIEV register is the interrupt event register. Bits set to High in GPIOIEV configure the corresponding pin to detect rising edges or high levels, depending on the corresponding bit value in the GPIO Interrupt Sense (GPIOIS) register (see page 172). Clearing a bit configures the pin to detect falling edges or low levels, depending on the corresponding bit value in GPIOIS. All bits are cleared by a reset. GPIO Interrupt Event (GPIOIEV) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x40C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 IEV RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPIO Interrupt Event The IEV values are defined as follows: Value Description 0 1 Falling edge or Low levels on corresponding pins trigger interrupts. Rising edge or High levels on corresponding pins trigger interrupts. 7:0 IEV R/W 0x00 174 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 6: GPIO Interrupt Mask (GPIOIM), offset 0x410 The GPIOIM register is the interrupt mask register. Bits set to High in GPIOIM allow the corresponding pins to trigger their individual interrupts and the combined GPIOINTR line. Clearing a bit disables interrupt triggering on that pin. All bits are cleared by a reset. GPIO Interrupt Mask (GPIOIM) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x410 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 IME RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPIO Interrupt Mask Enable The IME values are defined as follows: Value Description 0 1 Corresponding pin interrupt is masked. Corresponding pin interrupt is not masked. 7:0 IME R/W 0x00 November 30, 2007 Preliminary 175 General-Purpose Input/Outputs (GPIOs) Register 7: GPIO Raw Interrupt Status (GPIORIS), offset 0x414 The GPIORIS register is the raw interrupt status register. Bits read High in GPIORIS reflect the status of interrupt trigger conditions detected (raw, prior to masking), indicating that all the requirements have been met, before they are finally allowed to trigger by the GPIO Interrupt Mask (GPIOIM) register (see page 175). Bits read as zero indicate that corresponding input pins have not initiated an interrupt. All bits are cleared by a reset. GPIO Raw Interrupt Status (GPIORIS) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x414 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RIS RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPIO Interrupt Raw Status Reflects the status of interrupt trigger condition detection on pins (raw, prior to masking). The RIS values are defined as follows: Value Description 0 1 Corresponding pin interrupt requirements not met. Corresponding pin interrupt has met requirements. 7:0 RIS RO 0x00 176 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 8: GPIO Masked Interrupt Status (GPIOMIS), offset 0x418 The GPIOMIS register is the masked interrupt status register. Bits read High in GPIOMIS reflect the status of input lines triggering an interrupt. Bits read as Low indicate that either no interrupt has been generated, or the interrupt is masked. In addition to providing GPIO functionality, PB4 can also be used as an external trigger for the ADC. If PB4 is configured as a non-masked interrupt pin (GPIOIM is set to 1), not only is an interrupt for PortB generated, but an external trigger signal is sent to the ADC. If the ADC Event Multiplexer Select (ADCEMUX) register is configured to use the external trigger, an ADC conversion is initiated. If no other PortB pins are being used to generate interrupts, the ARM Integrated Nested Vectored Interrupt Controller (NVIC) Interrupt Set Enable (SETNA) register can disable the PortB interrupts and the ADC interrupt can be used to read back the converted data. Otherwise, the PortB interrupt handler needs to ignore and clear interrupts on B4, and wait for the ADC interrupt or the ADC interrupt needs to be disabled in the SETNA register and the PortB interrupt handler polls the ADC registers until the conversion is completed. GPIOMIS is the state of the interrupt after masking. GPIO Masked Interrupt Status (GPIOMIS) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x418 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 MIS RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPIO Masked Interrupt Status Masked value of interrupt due to corresponding pin. The MIS values are defined as follows: Value Description 0 1 Corresponding GPIO line interrupt not active. Corresponding GPIO line asserting interrupt. 7:0 MIS RO 0x00 November 30, 2007 Preliminary 177 General-Purpose Input/Outputs (GPIOs) Register 9: GPIO Interrupt Clear (GPIOICR), offset 0x41C The GPIOICR register is the interrupt clear register. Writing a 1 to a bit in this register clears the corresponding interrupt edge detection logic register. Writing a 0 has no effect. GPIO Interrupt Clear (GPIOICR) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x41C Type W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 IC RO 0 RO 0 RO 0 W1C 0 W1C 0 W1C 0 W1C 0 W1C 0 W1C 0 W1C 0 W1C 0 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPIO Interrupt Clear The IC values are defined as follows: Value Description 0 1 Corresponding interrupt is unaffected. Corresponding interrupt is cleared. 7:0 IC W1C 0x00 178 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 10: GPIO Alternate Function Select (GPIOAFSEL), offset 0x420 The GPIOAFSEL register is the mode control select register. Writing a 1 to any bit in this register selects the hardware control for the corresponding GPIO line. All bits are cleared by a reset, therefore no GPIO line is set to hardware control by default. The commit control registers provide a layer of protection against accidental programming of critical hardware peripherals. Writes to protected bits of the GPIO Alternate Function Select (GPIOAFSEL) register (see page 179) are not committed to storage unless the GPIO Lock (GPIOLOCK) register (see page 189) has been unlocked and the appropriate bits of the GPIO Commit (GPIOCR) register (see page 190) have been set to 1. Important: All GPIO pins are tri-stated by default (GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0, and GPIOPUR=0), with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]). The JTAG/SWD pins default to their JTAG/SWD functionality (GPIOAFSEL=1, GPIODEN=1 and GPIOPUR=1). A Power-On-Reset (POR) or asserting RST puts both groups of pins back to their default state. Caution – If the JTAG pins are used as GPIOs in a design, PB7 and PC2 cannot have external pull-down resistors connected to both of them at the same time. If both pins are pulled Low during reset, the controller has unpredictable behavior. If this happens, remove one or both of the pull-down resistors, and apply RST or power-cycle the part. In addition, it is possible to create a software sequence that prevents the debugger from connecting to the Stellaris® microcontroller. If the program code loaded into flash immediately changes the JTAG pins to their GPIO functionality, the debugger may not have enough time to connect and halt the controller before the JTAG pin functionality switches. This may lock the debugger out of the part. This can be avoided with a software routine that restores JTAG functionality based on an external or software trigger. GPIO Alternate Function Select (GPIOAFSEL) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x420 Type R/W, reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 AFSEL RO 0 RO 0 RO 0 R/W R/W R/W R/W R/W R/W R/W R/W RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. November 30, 2007 Preliminary 179 General-Purpose Input/Outputs (GPIOs) Bit/Field 7:0 Name AFSEL Type R/W Reset - Description GPIO Alternate Function Select The AFSEL values are defined as follows: Value Description 0 1 Software control of corresponding GPIO line (GPIO mode). Hardware control of corresponding GPIO line (alternate hardware function). Note: The default reset value for the GPIOAFSEL, GPIOPUR, and GPIODEN registers are 0x0000.0000 for all GPIO pins, with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]). These five pins default to JTAG/SWD functionality. Because of this, the default reset value of these registers for GPIO Port B is 0x0000.0080 while the default reset value for Port C is 0x0000.000F. 180 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 11: GPIO 2-mA Drive Select (GPIODR2R), offset 0x500 The GPIODR2R register is the 2-mA drive control register. It allows for each GPIO signal in the port to be individually configured without affecting the other pads. When writing a DRV2 bit for a GPIO signal, the corresponding DRV4 bit in the GPIODR4R register and the DRV8 bit in the GPIODR8R register are automatically cleared by hardware. GPIO 2-mA Drive Select (GPIODR2R) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x500 Type R/W, reset 0x0000.00FF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 DRV2 RO 0 RO 0 RO 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Output Pad 2-mA Drive Enable A write of 1 to either GPIODR4[n] or GPIODR8[n] clears the corresponding 2-mA enable bit. The change is effective on the second clock cycle after the write. 7:0 DRV2 R/W 0xFF November 30, 2007 Preliminary 181 General-Purpose Input/Outputs (GPIOs) Register 12: GPIO 4-mA Drive Select (GPIODR4R), offset 0x504 The GPIODR4R register is the 4-mA drive control register. It allows for each GPIO signal in the port to be individually configured without affecting the other pads. When writing the DRV4 bit for a GPIO signal, the corresponding DRV2 bit in the GPIODR2R register and the DRV8 bit in the GPIODR8R register are automatically cleared by hardware. GPIO 4-mA Drive Select (GPIODR4R) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x504 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 DRV4 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Output Pad 4-mA Drive Enable A write of 1 to either GPIODR2[n] or GPIODR8[n] clears the corresponding 4-mA enable bit. The change is effective on the second clock cycle after the write. 7:0 DRV4 R/W 0x00 182 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 13: GPIO 8-mA Drive Select (GPIODR8R), offset 0x508 The GPIODR8R register is the 8-mA drive control register. It allows for each GPIO signal in the port to be individually configured without affecting the other pads. When writing the DRV8 bit for a GPIO signal, the corresponding DRV2 bit in the GPIODR2R register and the DRV4 bit in the GPIODR4R register are automatically cleared by hardware. GPIO 8-mA Drive Select (GPIODR8R) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x508 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 DRV8 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Output Pad 8-mA Drive Enable A write of 1 to either GPIODR2[n] or GPIODR4[n] clears the corresponding 8-mA enable bit. The change is effective on the second clock cycle after the write. 7:0 DRV8 R/W 0x00 November 30, 2007 Preliminary 183 General-Purpose Input/Outputs (GPIOs) Register 14: GPIO Open Drain Select (GPIOODR), offset 0x50C The GPIOODR register is the open drain control register. Setting a bit in this register enables the open drain configuration of the corresponding GPIO pad. When open drain mode is enabled, the corresponding bit should also be set in the GPIO Digital Input Enable (GPIODEN) register (see page 188). Corresponding bits in the drive strength registers (GPIODR2R, GPIODR4R, GPIODR8R, and GPIOSLR ) can be set to achieve the desired rise and fall times. The GPIO acts as an open drain input if the corresponding bit in the GPIODIR register is set to 0; and as an open drain output when set to 1. When using the I2C module, the GPIO Alternate Function Select (GPIOAFSEL) register bit for PB2 and PB3 should be set to 1 (see examples in “Initialization and Configuration” on page 166). GPIO Open Drain Select (GPIOODR) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x50C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 ODE RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Output Pad Open Drain Enable The ODE values are defined as follows: Value Description 0 1 Open drain configuration is disabled. Open drain configuration is enabled. 7:0 ODE R/W 0x00 184 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 15: GPIO Pull-Up Select (GPIOPUR), offset 0x510 The GPIOPUR register is the pull-up control register. When a bit is set to 1, it enables a weak pull-up resistor on the corresponding GPIO signal. Setting a bit in GPIOPUR automatically clears the corresponding bit in the GPIO Pull-Down Select (GPIOPDR) register (see page 186). GPIO Pull-Up Select (GPIOPUR) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x510 Type R/W, reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 PUE RO 0 RO 0 RO 0 R/W R/W R/W R/W R/W R/W R/W R/W RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Pad Weak Pull-Up Enable A write of 1 to GPIOPDR[n] clears the corresponding GPIOPUR[n] enables. The change is effective on the second clock cycle after the write. Note: The default reset value for the GPIOAFSEL, GPIOPUR, and GPIODEN registers are 0x0000.0000 for all GPIO pins, with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]). These five pins default to JTAG/SWD functionality. Because of this, the default reset value of these registers for GPIO Port B is 0x0000.0080 while the default reset value for Port C is 0x0000.000F. 7:0 PUE R/W - November 30, 2007 Preliminary 185 General-Purpose Input/Outputs (GPIOs) Register 16: GPIO Pull-Down Select (GPIOPDR), offset 0x514 The GPIOPDR register is the pull-down control register. When a bit is set to 1, it enables a weak pull-down resistor on the corresponding GPIO signal. Setting a bit in GPIOPDR automatically clears the corresponding bit in the GPIO Pull-Up Select (GPIOPUR) register (see page 185). GPIO Pull-Down Select (GPIOPDR) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x514 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 PDE RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Pad Weak Pull-Down Enable A write of 1 to GPIOPUR[n] clears the corresponding GPIOPDR[n] enables. The change is effective on the second clock cycle after the write. 7:0 PDE R/W 0x00 186 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 17: GPIO Slew Rate Control Select (GPIOSLR), offset 0x518 The GPIOSLR register is the slew rate control register. Slew rate control is only available when using the 8-mA drive strength option via the GPIO 8-mA Drive Select (GPIODR8R) register (see page 183). GPIO Slew Rate Control Select (GPIOSLR) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x518 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 SRL RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Slew Rate Limit Enable (8-mA drive only) The SRL values are defined as follows: Value Description 0 1 Slew rate control disabled. Slew rate control enabled. 7:0 SRL R/W 0x00 November 30, 2007 Preliminary 187 General-Purpose Input/Outputs (GPIOs) Register 18: GPIO Digital Enable (GPIODEN), offset 0x51C The GPIODEN register is the digital enable register. By default, with the exception of the GPIO signals used for JTAG/SWD function, all other GPIO signals are configured out of reset to be undriven (tristate). Their digital function is disabled; they do not drive a logic value on the pin and they do not allow the pin voltage into the GPIO receiver. To use the pin in a digital function (either GPIO or alternate function), the corresponding GPIODEN bit must be set. GPIO Digital Enable (GPIODEN) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x51C Type R/W, reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 DEN RO 0 RO 0 RO 0 R/W R/W R/W R/W R/W R/W R/W R/W RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Digital Enable The DEN values are defined as follows: Value Description 0 1 Digital functions disabled. Digital functions enabled. Note: The default reset value for the GPIOAFSEL, GPIOPUR, and GPIODEN registers are 0x0000.0000 for all GPIO pins, with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]). These five pins default to JTAG/SWD functionality. Because of this, the default reset value of these registers for GPIO Port B is 0x0000.0080 while the default reset value for Port C is 0x0000.000F. 7:0 DEN R/W - 188 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 19: GPIO Lock (GPIOLOCK), offset 0x520 The GPIOLOCK register enables write access to the GPIOCR register (see page 190). Writing 0x1ACCE551 to the GPIOLOCK register will unlock the GPIOCR register. Writing any other value to the GPIOLOCK register re-enables the locked state. Reading the GPIOLOCK register returns the lock status rather than the 32-bit value that was previously written. Therefore, when write accesses are disabled, or locked, reading the GPIOLOCK register returns 0x00000001. When write accesses are enabled, or unlocked, reading the GPIOLOCK register returns 0x00000000. GPIO Lock (GPIOLOCK) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x520 Type R/W, reset 0x0000.0001 31 30 29 28 27 26 25 24 LOCK Type Reset R/W 0 15 R/W 0 14 R/W 0 13 R/W 0 12 R/W 0 11 R/W 0 10 R/W 0 9 R/W 0 8 LOCK Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 1 R/W 0 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 23 22 21 20 19 18 17 16 Bit/Field 31:0 Name LOCK Type R/W Reset Description 0x0000.0001 GPIO Lock A write of the value 0x1ACCE551 unlocks the GPIO Commit (GPIOCR) register for write access. A write of any other value reapplies the lock, preventing any register updates. A read of this register returns the following values: Value Description 0x0000.0001 locked 0x0000.0000 unlocked November 30, 2007 Preliminary 189 General-Purpose Input/Outputs (GPIOs) Register 20: GPIO Commit (GPIOCR), offset 0x524 The GPIOCR register is the commit register. The value of the GPIOCR register determines which bits of the GPIOAFSEL register will be committed when a write to the GPIOAFSEL register is performed. If a bit in the GPIOCR register is a zero, the data being written to the corresponding bit in the GPIOAFSEL register will not be committed and will retain its previous value. If a bit in the GPIOCR register is a one, the data being written to the corresponding bit of the GPIOAFSEL register will be committed to the register and will reflect the new value. The contents of the GPIOCR register can only be modified if the GPIOLOCK register is unlocked. Writes to the GPIOCR register will be ignored if the GPIOLOCK register is locked. Important: This register is designed to prevent accidental programming of the GPIOAFSEL registers that control connectivity to the JTAG/SWD debug hardware. By initializing the bits of the GPIOCR register to 0 for PB7 and PC[3:0], the JTAG/SWD debug port can only be converted to GPIOs through a deliberate set of writes to the GPIOLOCK, GPIOCR, and GPIOAFSEL registers. Because this protection is currently only implemented on the JTAG/SWD pins on PB7 and PC[3:0], all of the other bits in the GPIOCR registers cannot be written with 0x0. These bits are hardwired to 0x1, ensuring that it is always possible to commit new values to the GPIOAFSEL register bits of these other pins. GPIO Commit (GPIOCR) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0x524 Type -, reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 CR RO 0 RO 0 RO 0 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 190 Preliminary November 30, 2007 LM3S6965 Microcontroller Bit/Field 7:0 Name CR Type - Reset - Description GPIO Commit On a bit-wise basis, any bit set allows the corresponding GPIOAFSEL bit to be set to its alternate function. Note: The default register type for the GPIOCR register is RO for all GPIO pins, with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]). These five pins are currently the only GPIOs that are protected by the GPIOCR register. Because of this, the register type for GPIO Port B7 and GPIO Port C[3:0] is R/W. The default reset value for the GPIOCR register is 0x0000.00FF for all GPIO pins, with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]). To ensure that the JTAG port is not accidentally programmed as a GPIO, these five pins default to non-commitable. Because of this, the default reset value of GPIOCR for GPIO Port B is 0x0000.007F while the default reset value of GPIOCR for Port C is 0x0000.00F0. November 30, 2007 Preliminary 191 General-Purpose Input/Outputs (GPIOs) Register 21: GPIO Peripheral Identification 4 (GPIOPeriphID4), offset 0xFD0 The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, and GPIOPeriphID7 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 4 (GPIOPeriphID4) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0xFD0 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 PID4 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPIO Peripheral ID Register[7:0] 7:0 PID4 RO 0x00 192 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 22: GPIO Peripheral Identification 5 (GPIOPeriphID5), offset 0xFD4 The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, and GPIOPeriphID7 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 5 (GPIOPeriphID5) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0xFD4 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 PID5 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPIO Peripheral ID Register[15:8] 7:0 PID5 RO 0x00 November 30, 2007 Preliminary 193 General-Purpose Input/Outputs (GPIOs) Register 23: GPIO Peripheral Identification 6 (GPIOPeriphID6), offset 0xFD8 The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, and GPIOPeriphID7 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 6 (GPIOPeriphID6) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0xFD8 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 PID6 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPIO Peripheral ID Register[23:16] 7:0 PID6 RO 0x00 194 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 24: GPIO Peripheral Identification 7 (GPIOPeriphID7), offset 0xFDC The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, and GPIOPeriphID7 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 7 (GPIOPeriphID7) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0xFDC Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 PID7 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPIO Peripheral ID Register[31:24] 7:0 PID7 RO 0x00 November 30, 2007 Preliminary 195 General-Purpose Input/Outputs (GPIOs) Register 25: GPIO Peripheral Identification 0 (GPIOPeriphID0), offset 0xFE0 The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, and GPIOPeriphID3 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 0 (GPIOPeriphID0) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0xFE0 Type RO, reset 0x0000.0061 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 PID0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 1 RO 0 RO 0 RO 0 RO 0 RO 1 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPIO Peripheral ID Register[7:0] Can be used by software to identify the presence of this peripheral. 7:0 PID0 RO 0x61 196 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 26: GPIO Peripheral Identification 1 (GPIOPeriphID1), offset 0xFE4 The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, and GPIOPeriphID3 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 1 (GPIOPeriphID1) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0xFE4 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 PID1 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPIO Peripheral ID Register[15:8] Can be used by software to identify the presence of this peripheral. 7:0 PID1 RO 0x00 November 30, 2007 Preliminary 197 General-Purpose Input/Outputs (GPIOs) Register 27: GPIO Peripheral Identification 2 (GPIOPeriphID2), offset 0xFE8 The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, and GPIOPeriphID3 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 2 (GPIOPeriphID2) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0xFE8 Type RO, reset 0x0000.0018 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 PID2 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 1 RO 0 RO 0 RO 0 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPIO Peripheral ID Register[23:16] Can be used by software to identify the presence of this peripheral. 7:0 PID2 RO 0x18 198 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 28: GPIO Peripheral Identification 3 (GPIOPeriphID3), offset 0xFEC The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, and GPIOPeriphID3 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 3 (GPIOPeriphID3) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0xFEC Type RO, reset 0x0000.0001 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 PID3 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPIO Peripheral ID Register[31:24] Can be used by software to identify the presence of this peripheral. 7:0 PID3 RO 0x01 November 30, 2007 Preliminary 199 General-Purpose Input/Outputs (GPIOs) Register 29: GPIO PrimeCell Identification 0 (GPIOPCellID0), offset 0xFF0 The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide registers, that can conceptually be treated as one 32-bit register. The register is used as a standard cross-peripheral identification system. GPIO PrimeCell Identification 0 (GPIOPCellID0) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0xFF0 Type RO, reset 0x0000.000D 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 CID0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 1 RO 0 RO 1 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPIO PrimeCell ID Register[7:0] Provides software a standard cross-peripheral identification system. 7:0 CID0 RO 0x0D 200 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 30: GPIO PrimeCell Identification 1 (GPIOPCellID1), offset 0xFF4 The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide registers, that can conceptually be treated as one 32-bit register. The register is used as a standard cross-peripheral identification system. GPIO PrimeCell Identification 1 (GPIOPCellID1) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0xFF4 Type RO, reset 0x0000.00F0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 CID1 RO 0 RO 0 RO 0 RO 1 RO 1 RO 1 RO 1 RO 0 RO 0 RO 0 RO 0 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPIO PrimeCell ID Register[15:8] Provides software a standard cross-peripheral identification system. 7:0 CID1 RO 0xF0 November 30, 2007 Preliminary 201 General-Purpose Input/Outputs (GPIOs) Register 31: GPIO PrimeCell Identification 2 (GPIOPCellID2), offset 0xFF8 The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide registers, that can conceptually be treated as one 32-bit register. The register is used as a standard cross-peripheral identification system. GPIO PrimeCell Identification 2 (GPIOPCellID2) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0xFF8 Type RO, reset 0x0000.0005 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 CID2 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 0 RO 1 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPIO PrimeCell ID Register[23:16] Provides software a standard cross-peripheral identification system. 7:0 CID2 RO 0x05 202 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 32: GPIO PrimeCell Identification 3 (GPIOPCellID3), offset 0xFFC The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide registers, that can conceptually be treated as one 32-bit register. The register is used as a standard cross-peripheral identification system. GPIO PrimeCell Identification 3 (GPIOPCellID3) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 Offset 0xFFC Type RO, reset 0x0000.00B1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 CID3 RO 0 RO 0 RO 0 RO 1 RO 0 RO 1 RO 1 RO 0 RO 0 RO 0 RO 1 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPIO PrimeCell ID Register[31:24] Provides software a standard cross-peripheral identification system. 7:0 CID3 RO 0xB1 November 30, 2007 Preliminary 203 General-Purpose Timers 10 General-Purpose Timers Programmable timers can be used to count or time external events that drive the Timer input pins. ® The Stellaris General-Purpose Timer Module (GPTM) contains four GPTM blocks (Timer0, Timer1, Timer 2, and Timer 3). Each GPTM block provides two 16-bit timers/counters (referred to as TimerA and TimerB) that can be configured to operate independently as timers or event counters, or configured to operate as one 32-bit timer or one 32-bit Real-Time Clock (RTC). Timers can also be used to trigger analog-to-digital (ADC) conversions. The trigger signals from all of the general-purpose timers are ORed together before reaching the ADC module, so only one timer should be used to trigger ADC events. Note: Timer2 is an internal timer and can only be used to generate internal interrupts or trigger ADC events. ® The General-Purpose Timer Module is one timing resource available on the Stellaris microcontrollers. Other timer resources include the System Timer (SysTick) (see “System Timer (SysTick)” on page 40) and the PWM timer in the PWM module (see “PWM Timer” on page 465). The following modes are supported: ■ 32-bit Timer modes – Programmable one-shot timer – Programmable periodic timer – Real-Time Clock using 32.768-KHz input clock – Software-controlled event stalling (excluding RTC mode) ■ 16-bit Timer modes – General-purpose timer function with an 8-bit prescaler (for one-shot and periodic modes only) – Programmable one-shot timer – Programmable periodic timer – Software-controlled event stalling ■ 16-bit Input Capture modes – Input edge count capture – Input edge time capture ■ 16-bit PWM mode – Simple PWM mode with software-programmable output inversion of the PWM signal 10.1 Block Diagram Note: In Figure 10-1 on page 205, the specific CCP pins available depend on the Stellaris device. See Table 10-1 on page 205 for the available CCPs. ® 204 Preliminary November 30, 2007 LM3S6965 Microcontroller Figure 10-1. GPTM Module Block Diagram 0x0000 (Down Counter Modes) TimerA Control GPTMTAPMR GPTMTAPR GPTMTAMATCHR Interrupt / Config TimerA Interrupt GPTMCFG GPTMCTL GPTMIMR TimerB Interrupt GPTMRIS GPTMMIS GPTMICR GPTMTBPMR GPTMTBPR GPTMTBMATCHR GPTMTBILR GPTMTBMR TB Comparator TimerB Control GPTMTBR En Clock / Edge Detect Odd CCP Pin RTC Divider GPTMTAILR GPTMTAMR GPTMAR En Clock / Edge Detect TA Comparator 32 KHz or Even CCP Pin 0x0000 (Down Counter Modes) System Clock Table 10-1. Available CCP Pins Timer 16-Bit Up/Down Counter Even CCP Pin Odd CCP Pin CCP0 CCP2 CCP1 CCP3 Timer 0 TimerA TimerB Timer 1 TimerA TimerB Timer 2 TimerA TimerB Timer 3 TimerA TimerB 10.2 Functional Description The main components of each GPTM block are two free-running 16-bit up/down counters (referred to as TimerA and TimerB), two 16-bit match registers, two prescaler match registers, and two 16-bit load/initialization registers and their associated control functions. The exact functionality of each GPTM is controlled by software and configured through the register interface. Software configures the GPTM using the GPTM Configuration (GPTMCFG) register (see page 216), the GPTM TimerA Mode (GPTMTAMR) register (see page 217), and the GPTM TimerB Mode (GPTMTBMR) register (see page 219). When in one of the 32-bit modes, the timer can only act as a 32-bit timer. However, when configured in 16-bit mode, the GPTM can have its two 16-bit timers configured in any combination of the 16-bit modes. November 30, 2007 Preliminary 205 General-Purpose Timers 10.2.1 GPTM Reset Conditions After reset has been applied to the GPTM module, the module is in an inactive state, and all control registers are cleared and in their default states. Counters TimerA and TimerB are initialized to 0xFFFF, along with their corresponding load registers: the GPTM TimerA Interval Load (GPTMTAILR) register (see page 230) and the GPTM TimerB Interval Load (GPTMTBILR) register (see page 231). The prescale counters are initialized to 0x00: the GPTM TimerA Prescale (GPTMTAPR) register (see page 234) and the GPTM TimerB Prescale (GPTMTBPR) register (see page 235). 10.2.2 32-Bit Timer Operating Modes This section describes the three GPTM 32-bit timer modes (One-Shot, Periodic, and RTC) and their configuration. The GPTM is placed into 32-bit mode by writing a 0 (One-Shot/Periodic 32-bit timer mode) or a 1 (RTC mode) to the GPTM Configuration (GPTMCFG) register. In both configurations, certain GPTM registers are concatenated to form pseudo 32-bit registers. These registers include: ■ GPTM TimerA Interval Load (GPTMTAILR) register [15:0], see page 230 ■ GPTM TimerB Interval Load (GPTMTBILR) register [15:0], see page 231 ■ GPTM TimerA (GPTMTAR) register [15:0], see page 238 ■ GPTM TimerB (GPTMTBR) register [15:0], see page 239 In the 32-bit modes, the GPTM translates a 32-bit write access to GPTMTAILR into a write access to both GPTMTAILR and GPTMTBILR. The resulting word ordering for such a write operation is: GPTMTBILR[15:0]:GPTMTAILR[15:0] Likewise, a read access to GPTMTAR returns the value: GPTMTBR[15:0]:GPTMTAR[15:0] 10.2.2.1 32-Bit One-Shot/Periodic Timer Mode In 32-bit one-shot and periodic timer modes, the concatenated versions of the TimerA and TimerB registers are configured as a 32-bit down-counter. The selection of one-shot or periodic mode is determined by the value written to the TAMR field of the GPTM TimerA Mode (GPTMTAMR) register (see page 217), and there is no need to write to the GPTM TimerB Mode (GPTMTBMR) register. When software writes the TAEN bit in the GPTM Control (GPTMCTL) register (see page 221), the timer begins counting down from its preloaded value. Once the 0x0000.0000 state is reached, the timer reloads its start value from the concatenated GPTMTAILR on the next cycle. If configured to be a one-shot timer, the timer stops counting and clears the TAEN bit in the GPTMCTL register. If configured as a periodic timer, it continues counting. In addition to reloading the count value, the GPTM generates interrupts and output triggers when it reaches the 0x0000000 state. The GPTM sets the TATORIS bit in the GPTM Raw Interrupt Status (GPTMRIS) register (see page 226), and holds it until it is cleared by writing the GPTM Interrupt Clear (GPTMICR) register (see page 228). If the time-out interrupt is enabled in the GPTM Interrupt Mask (GPTIMR) register (see page 224), the GPTM also sets the TATOMIS bit in the GPTM Masked Interrupt Status (GPTMMIS) register (see page 227). 206 Preliminary November 30, 2007 LM3S6965 Microcontroller The output trigger is a one-clock-cycle pulse that is asserted when the counter hits the 0x0000.0000 state, and deasserted on the following clock cycle. It is enabled by setting the TAOTE bit in GPTMCTL, and can trigger SoC-level events such as ADC conversions. If software reloads the GPTMTAILR register while the counter is running, the counter loads the new value on the next clock cycle and continues counting from the new value. If the TASTALL bit in the GPTMCTL register is asserted, the timer freezes counting until the signal is deasserted. 10.2.2.2 32-Bit Real-Time Clock Timer Mode In Real-Time Clock (RTC) mode, the concatenated versions of the TimerA and TimerB registers are configured as a 32-bit up-counter. When RTC mode is selected for the first time, the counter is loaded with a value of 0x0000.0001. All subsequent load values must be written to the GPTM TimerA Match (GPTMTAMATCHR) register (see page 232) by the controller. The input clock on the CCP0, CCP2, or CCP4 pins is required to be 32.768 KHz in RTC mode. The clock signal is then divided down to a 1 Hz rate and is passed along to the input of the 32-bit counter. When software writes the TAEN bit inthe GPTMCTL register, the counter starts counting up from its preloaded value of 0x0000.0001. When the current count value matches the preloaded value in the GPTMTAMATCHR register, it rolls over to a value of 0x0000.0000 and continues counting until either a hardware reset, or it is disabled by software (clearing the TAEN bit). When a match occurs, the GPTM asserts the RTCRIS bit in GPTMRIS. If the RTC interrupt is enabled in GPTIMR, the GPTM also sets the RTCMIS bit in GPTMISR and generates a controller interrupt. The status flags are cleared by writing the RTCCINT bit in GPTMICR. If the TASTALL and/or TBSTALL bits in the GPTMCTL register are set, the timer does not freeze if the RTCEN bit is set in GPTMCTL. 10.2.3 16-Bit Timer Operating Modes The GPTM is placed into global 16-bit mode by writing a value of 0x4 to the GPTM Configuration (GPTMCFG) register (see page 216). This section describes each of the GPTM 16-bit modes of operation. TimerA and TimerB have identical modes, so a single description is given using an n to reference both. 10.2.3.1 16-Bit One-Shot/Periodic Timer Mode In 16-bit one-shot and periodic timer modes, the timer is configured as a 16-bit down-counter with an optional 8-bit prescaler that effectively extends the counting range of the timer to 24 bits. The selection of one-shot or periodic mode is determined by the value written to the TnMR field of the GPTMTnMR register. The optional prescaler is loaded into the GPTM Timern Prescale (GPTMTnPR) register. When software writes the TnEN bit in the GPTMCTL register, the timer begins counting down from its preloaded value. Once the 0x0000 state is reached, the timer reloads its start value from GPTMTnILR and GPTMTnPR on the next cycle. If configured to be a one-shot timer, the timer stops counting and clears the TnEN bit in the GPTMCTL register. If configured as a periodic timer, it continues counting. In addition to reloading the count value, the timer generates interrupts and output triggers when it reaches the 0x0000 state. The GPTM sets the TnTORIS bit in the GPTMRIS register, and holds it until it is cleared by writing the GPTMICR register. If the time-out interrupt is enabled in GPTIMR, the GPTM also sets the TnTOMIS bit in GPTMISR and generates a controller interrupt. November 30, 2007 Preliminary 207 General-Purpose Timers The output trigger is a one-clock-cycle pulse that is asserted when the counter hits the 0x0000 state, and deasserted on the following clock cycle. It is enabled by setting the TnOTE bit in the GPTMCTL register, and can trigger SoC-level events such as ADC conversions. If software reloads the GPTMTAILR register while the counter is running, the counter loads the new value on the next clock cycle and continues counting from the new value. If the TnSTALL bit in the GPTMCTL register is enabled, the timer freezes counting until the signal is deasserted. The following example shows a variety of configurations for a 16-bit free running timer while using the prescaler. All values assume a 50-MHz clock with Tc=20 ns (clock period). Table 10-2. 16-Bit Timer With Prescaler Configurations Prescale #Clock (T c) Max Time Units 00000000 00000001 00000010 -----------11111100 11111110 11111111 1 2 3 -254 255 256 1.3107 2.6214 3.9321 -332.9229 334.2336 335.5443 mS mS mS -mS mS mS a a. Tc is the clock period. 10.2.3.2 16-Bit Input Edge Count Mode In Edge Count mode, the timer is configured as a down-counter capable of capturing three types of events: rising edge, falling edge, or both. To place the timer in Edge Count mode, the TnCMR bit of the GPTMTnMR register must be set to 0. The type of edge that the timer counts is determined by the TnEVENT fields of the GPTMCTL register. During initialization, the GPTM Timern Match (GPTMTnMATCHR) register is configured so that the difference between the value in the GPTMTnILR register and the GPTMTnMATCHR register equals the number of edge events that must be counted. When software writes the TnEN bit in the GPTM Control (GPTMCTL) register, the timer is enabled for event capture. Each input event on the CCP pin decrements the counter by 1 until the event count matches GPTMTnMATCHR. When the counts match, the GPTM asserts the CnMRIS bit in the GPTMRIS register (and the CnMMIS bit, if the interrupt is not masked). The counter is then reloaded using the value in GPTMTnILR, and stopped since the GPTM automatically clears the TnEN bit in the GPTMCTL register. Once the event count has been reached, all further events are ignored until TnEN is re-enabled by software. Figure 10-2 on page 209 shows how input edge count mode works. In this case, the timer start value is set to GPTMnILR =0x000A and the match value is set to GPTMnMATCHR =0x0006 so that four edge events are counted. The counter is configured to detect both edges of the input signal. Note that the last two edges are not counted since the timer automatically clears the TnEN bit after the current count matches the value in the GPTMnMR register. 208 Preliminary November 30, 2007 LM3S6965 Microcontroller Figure 10-2. 16-Bit Input Edge Count Mode Example Timer reload on next cycle Ignored Ignored Count 0x000A 0x0009 0x0008 0x0007 0x0006 Timer stops, flags asserted Input Signal 10.2.3.3 16-Bit Input Edge Time Mode Note: The prescaler is not available in 16-Bit Input Edge Time mode. In Edge Time mode, the timer is configured as a free-running down-counter initialized to the value loaded in the GPTMTnILR register (or 0xFFFF at reset). This mode allows for event capture of both rising and falling edges. The timer is placed into Edge Time mode by setting the TnCMR bit in the GPTMTnMR register, and the type of event that the timer captures is determined by the TnEVENT fields of the GPTMCnTL register. When software writes the TnEN bit in the GPTMCTL register, the timer is enabled for event capture. When the selected input event is detected, the current Tn counter value is captured in the GPTMTnR register and is available to be read by the controller. The GPTM then asserts the CnERIS bit (and the CnEMIS bit, if the interrupt is not masked). After an event has been captured, the timer does not stop counting. It continues to count until the TnEN bit is cleared. When the timer reaches the 0x0000 state, it is reloaded with the value from the GPTMnILR register. Figure 10-3 on page 210 shows how input edge timing mode works. In the diagram, it is assumed that the start value of the timer is the default value of 0xFFFF, and the timer is configured to capture rising edge events. Each time a rising edge event is detected, the current count value is loaded into the GPTMTnR register, and is held there until another rising edge is detected (at which point the new count value is loaded into GPTMTnR). November 30, 2007 Preliminary 209 General-Purpose Timers Figure 10-3. 16-Bit Input Edge Time Mode Example Count 0xFFFF GPTMTnR=X GPTMTnR=Y GPTMTnR=Z Z X Y Time Input Signal 10.2.3.4 16-Bit PWM Mode The GPTM supports a simple PWM generation mode. In PWM mode, the timer is configured as a down-counter with a start value (and thus period) defined by GPTMTnILR. PWM mode is enabled with the GPTMTnMR register by setting the TnAMS bit to 0x1, the TnCMR bit to 0x0, and the TnMR field to 0x2. When software writes the TnEN bit in the GPTMCTL register, the counter begins counting down until it reaches the 0x0000 state. On the next counter cycle, the counter reloads its start value from GPTMTnILR (and GPTMTnPR if using a prescaler) and continues counting until disabled by software clearing the TnEN bit in the GPTMCTL register. No interrupts or status bits are asserted in PWM mode. The output PWM signal asserts when the counter is at the value of the GPTMTnILR register (its start state), and is deasserted when the counter value equals the value in the GPTM Timern Match Register (GPTMnMATCHR). Software has the capability of inverting the output PWM signal by setting the TnPWML bit in the GPTMCTL register. Figure 10-4 on page 211 shows how to generate an output PWM with a 1-ms period and a 66% duty cycle assuming a 50-MHz input clock and TnPWML =0 (duty cycle would be 33% for the TnPWML =1 configuration). For this example, the start value is GPTMnIRL=0xC350 and the match value is GPTMnMR=0x411A. 210 Preliminary November 30, 2007 LM3S6965 Microcontroller Figure 10-4. 16-Bit PWM Mode Example Count 0xC350 GPTMTnR=GPTMnMR GPTMTnR=GPTMnMR 0x411A Time TnEN set TnPWML = 0 Output Signal TnPWML = 1 10.3 Initialization and Configuration To use the general-purpose timers, the peripheral clock must be enabled by setting the TIMER0, TIMER1, TIMER2, and TIMER3 bits in the RCGC1 register. This section shows module initialization and configuration examples for each of the supported timer modes. 10.3.1 32-Bit One-Shot/Periodic Timer Mode The GPTM is configured for 32-bit One-Shot and Periodic modes by the following sequence: 1. Ensure the timer is disabled (the TAEN bit in the GPTMCTL register is cleared) before making any changes. 2. Write the GPTM Configuration Register (GPTMCFG) with a value of 0x0. 3. Set the TAMR field in the GPTM TimerA Mode Register (GPTMTAMR): a. Write a value of 0x1 for One-Shot mode. b. Write a value of 0x2 for Periodic mode. 4. Load the start value into the GPTM TimerA Interval Load Register (GPTMTAILR). 5. If interrupts are required, set the TATOIM bit in the GPTM Interrupt Mask Register (GPTMIMR). 6. Set the TAEN bit in the GPTMCTL register to enable the timer and start counting. November 30, 2007 Preliminary 211 General-Purpose Timers 7. Poll the TATORIS bit in the GPTMRIS register or wait for the interrupt to be generated (if enabled). In both cases, the status flags are cleared by writing a 1 to the TATOCINT bit of the GPTM Interrupt Clear Register (GPTMICR). In One-Shot mode, the timer stops counting after step 7 on page 212. To re-enable the timer, repeat the sequence. A timer configured in Periodic mode does not stop counting after it times out. 10.3.2 32-Bit Real-Time Clock (RTC) Mode To use the RTC mode, the timer must have a 32.768-KHz input signal on its CCP0, CCP2, or CCP4 pins. To enable the RTC feature, follow these steps: 1. Ensure the timer is disabled (the TAEN bit is cleared) before making any changes. 2. Write the GPTM Configuration Register (GPTMCFG) with a value of 0x1. 3. Write the desired match value to the GPTM TimerA Match Register (GPTMTAMATCHR). 4. Set/clear the RTCEN bit in the GPTM Control Register (GPTMCTL) as desired. 5. If interrupts are required, set the RTCIM bit in the GPTM Interrupt Mask Register (GPTMIMR). 6. Set the TAEN bit in the GPTMCTL register to enable the timer and start counting. When the timer count equals the value in the GPTMTAMATCHR register, the counter is re-loaded with 0x0000.0000 and begins counting. If an interrupt is enabled, it does not have to be cleared. 10.3.3 16-Bit One-Shot/Periodic Timer Mode A timer is configured for 16-bit One-Shot and Periodic modes by the following sequence: 1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes. 2. Write the GPTM Configuration Register (GPTMCFG) with a value of 0x4. 3. Set the TnMR field in the GPTM Timer Mode (GPTMTnMR) register: a. Write a value of 0x1 for One-Shot mode. b. Write a value of 0x2 for Periodic mode. 4. If a prescaler is to be used, write the prescale value to the GPTM Timern Prescale Register (GPTMTnPR). 5. Load the start value into the GPTM Timer Interval Load Register (GPTMTnILR). 6. If interrupts are required, set the TnTOIM bit in the GPTM Interrupt Mask Register (GPTMIMR). 7. Set the TnEN bit in the GPTM Control Register (GPTMCTL) to enable the timer and start counting. 8. Poll the TnTORIS bit in the GPTMRIS register or wait for the interrupt to be generated (if enabled). In both cases, the status flags are cleared by writing a 1 to the TnTOCINT bit of the GPTM Interrupt Clear Register (GPTMICR). 212 Preliminary November 30, 2007 LM3S6965 Microcontroller In One-Shot mode, the timer stops counting after step 8 on page 212. To re-enable the timer, repeat the sequence. A timer configured in Periodic mode does not stop counting after it times out. 10.3.4 16-Bit Input Edge Count Mode A timer is configured to Input Edge Count mode by the following sequence: 1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes. 2. Write the GPTM Configuration (GPTMCFG) register with a value of 0x4. 3. In the GPTM Timer Mode (GPTMTnMR) register, write the TnCMR field to 0x0 and the TnMR field to 0x3. 4. Configure the type of event(s) that the timer captures by writing the TnEVENT field of the GPTM Control (GPTMCTL) register. 5. Load the timer start value into the GPTM Timern Interval Load (GPTMTnILR) register. 6. Load the desired event count into the GPTM Timern Match (GPTMTnMATCHR) register. 7. If interrupts are required, set the CnMIM bit in the GPTM Interrupt Mask (GPTMIMR) register. 8. Set the TnEN bit in the GPTMCTL register to enable the timer and begin waiting for edge events. 9. Poll the CnMRIS bit in the GPTMRIS register or wait for the interrupt to be generated (if enabled). In both cases, the status flags are cleared by writing a 1 to the CnMCINT bit of the GPTM Interrupt Clear (GPTMICR) register. In Input Edge Count Mode, the timer stops after the desired number of edge events has been detected. To re-enable the timer, ensure that the TnEN bit is cleared and repeat step 4 on page 213 through step 9 on page 213. 10.3.5 16-Bit Input Edge Timing Mode A timer is configured to Input Edge Timing mode by the following sequence: 1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes. 2. Write the GPTM Configuration (GPTMCFG) register with a value of 0x4. 3. In the GPTM Timer Mode (GPTMTnMR) register, write the TnCMR field to 0x1 and the TnMR field to 0x3. 4. Configure the type of event that the timer captures by writing the TnEVENT field of the GPTM Control (GPTMCTL) register. 5. Load the timer start value into the GPTM Timern Interval Load (GPTMTnILR) register. 6. If interrupts are required, set the CnEIM bit in the GPTM Interrupt Mask (GPTMIMR) register. 7. Set the TnEN bit in the GPTM Control (GPTMCTL) register to enable the timer and start counting. 8. Poll the CnERIS bit in the GPTMRIS register or wait for the interrupt to be generated (if enabled). In both cases, the status flags are cleared by writing a 1 to the CnECINT bit of the GPTM November 30, 2007 Preliminary 213 General-Purpose Timers Interrupt Clear (GPTMICR) register. The time at which the event happened can be obtained by reading the GPTM Timern (GPTMTnR) register. In Input Edge Timing mode, the timer continues running after an edge event has been detected, but the timer interval can be changed at any time by writing the GPTMTnILR register. The change takes effect at the next cycle after the write. 10.3.6 16-Bit PWM Mode A timer is configured to PWM mode using the following sequence: 1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes. 2. Write the GPTM Configuration (GPTMCFG) register with a value of 0x4. 3. In the GPTM Timer Mode (GPTMTnMR) register, set the TnAMS bit to 0x1, the TnCMR bit to 0x0, and the TnMR field to 0x2. 4. Configure the output state of the PWM signal (whether or not it is inverted) in the TnEVENT field of the GPTM Control (GPTMCTL) register. 5. Load the timer start value into the GPTM Timern Interval Load (GPTMTnILR) register. 6. Load the GPTM Timern Match (GPTMTnMATCHR) register with the desired value. 7. If a prescaler is going to be used, configure the GPTM Timern Prescale (GPTMTnPR) register and the GPTM Timern Prescale Match (GPTMTnPMR) register. 8. Set the TnEN bit in the GPTM Control (GPTMCTL) register to enable the timer and begin generation of the output PWM signal. In PWM Timing mode, the timer continues running after the PWM signal has been generated. The PWM period can be adjusted at any time by writing the GPTMTnILR register, and the change takes effect at the next cycle after the write. 10.4 Register Map Table 10-3 on page 214 lists the GPTM registers. The offset listed is a hexadecimal increment to the register ’s address, relative to that timer ’s base address: ■ Timer0: 0x4003.0000 ■ Timer1: 0x4003.1000 ■ Timer2: 0x4003.2000 ■ Timer3: 0x4003.3000 Table 10-3. Timers Register Map Offset 0x000 0x004 Name GPTMCFG GPTMTAMR Type R/W R/W Reset 0x0000.0000 0x0000.0000 Description GPTM Configuration GPTM TimerA Mode See page 216 217 214 Preliminary November 30, 2007 LM3S6965 Microcontroller Offset 0x008 0x00C 0x018 0x01C 0x020 0x024 Name GPTMTBMR GPTMCTL GPTMIMR GPTMRIS GPTMMIS GPTMICR Type R/W R/W R/W RO RO W1C Reset 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.FFFF (16-bit mode) 0xFFFF.FFFF (32-bit mode) 0x0000.FFFF 0x0000.FFFF (16-bit mode) 0xFFFF.FFFF (32-bit mode) 0x0000.FFFF 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.FFFF (16-bit mode) 0xFFFF.FFFF (32-bit mode) 0x0000.FFFF Description GPTM TimerB Mode GPTM Control GPTM Interrupt Mask GPTM Raw Interrupt Status GPTM Masked Interrupt Status GPTM Interrupt Clear See page 219 221 224 226 227 228 0x028 GPTMTAILR R/W GPTM TimerA Interval Load 230 0x02C GPTMTBILR R/W GPTM TimerB Interval Load 231 0x030 GPTMTAMATCHR R/W GPTM TimerA Match 232 0x034 0x038 0x03C 0x040 0x044 GPTMTBMATCHR GPTMTAPR GPTMTBPR GPTMTAPMR GPTMTBPMR R/W R/W R/W R/W R/W GPTM TimerB Match GPTM TimerA Prescale GPTM TimerB Prescale GPTM TimerA Prescale Match GPTM TimerB Prescale Match 233 234 235 236 237 0x048 GPTMTAR RO GPTM TimerA 238 0x04C GPTMTBR RO GPTM TimerB 239 10.5 Register Descriptions The remainder of this section lists and describes the GPTM registers, in numerical order by address offset. November 30, 2007 Preliminary 215 General-Purpose Timers Register 1: GPTM Configuration (GPTMCFG), offset 0x000 This register configures the global operation of the GPTM module. The value written to this register determines whether the GPTM is in 32- or 16-bit mode. GPTM Configuration (GPTMCFG) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Timer3 base: 0x4003.3000 Offset 0x000 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 GPTMCFG R/W 0 R/W 0 RO 0 0 Bit/Field 31:3 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPTM Configuration The GPTMCFG values are defined as follows: Value 0x0 0x1 0x2 0x3 Description 32-bit timer configuration. 32-bit real-time clock (RTC) counter configuration. Reserved. Reserved. 2:0 GPTMCFG R/W 0x0 0x4-0x7 16-bit timer configuration, function is controlled by bits 1:0 of GPTMTAMR and GPTMTBMR. 216 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 2: GPTM TimerA Mode (GPTMTAMR), offset 0x004 This register configures the GPTM based on the configuration selected in the GPTMCFG register. When in 16-bit PWM mode, set the TAAMS bit to 0x1, the TACMR bit to 0x0, and the TAMR field to 0x2. GPTM TimerA Mode (GPTMTAMR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Timer3 base: 0x4003.3000 Offset 0x004 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 TAAMS R/W 0 RO 0 2 TACMR R/W 0 R/W 0 RO 0 1 TAMR R/W 0 RO 0 0 Bit/Field 31:4 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPTM TimerA Alternate Mode Select The TAAMS values are defined as follows: Value Description 0 1 Capture mode is enabled. PWM mode is enabled. Note: To enable PWM mode, you must also clear the TACMR bit and set the TAMR field to 0x2. 3 TAAMS R/W 0 2 TACMR R/W 0 GPTM TimerA Capture Mode The TACMR values are defined as follows: Value Description 0 1 Edge-Count mode. Edge-Time mode. November 30, 2007 Preliminary 217 General-Purpose Timers Bit/Field 1:0 Name TAMR Type R/W Reset 0x0 Description GPTM TimerA Mode The TAMR values are defined as follows: Value Description 0x0 Reserved. 0x1 One-Shot Timer mode. 0x2 Periodic Timer mode. 0x3 Capture mode. The Timer mode is based on the timer configuration defined by bits 2:0 in the GPTMCFG register (16-or 32-bit). In 16-bit timer configuration, TAMR controls the 16-bit timer modes for TimerA. In 32-bit timer configuration, this register controls the mode and the contents of GPTMTBMR are ignored. 218 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 3: GPTM TimerB Mode (GPTMTBMR), offset 0x008 This register configures the GPTM based on the configuration selected in the GPTMCFG register. When in 16-bit PWM mode, set the TBAMS bit to 0x1, the TBCMR bit to 0x0, and the TBMR field to 0x2. GPTM TimerB Mode (GPTMTBMR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Timer3 base: 0x4003.3000 Offset 0x008 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 TBAMS R/W 0 RO 0 2 TBCMR R/W 0 RO 0 1 TBMR R/W 0 R/W 0 RO 0 0 Bit/Field 31:4 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPTM TimerB Alternate Mode Select The TBAMS values are defined as follows: Value Description 0 1 Capture mode is enabled. PWM mode is enabled. Note: To enable PWM mode, you must also clear the TBCMR bit and set the TBMR field to 0x2. 3 TBAMS R/W 0 2 TBCMR R/W 0 GPTM TimerB Capture Mode The TBCMR values are defined as follows: Value Description 0 1 Edge-Count mode. Edge-Time mode. November 30, 2007 Preliminary 219 General-Purpose Timers Bit/Field 1:0 Name TBMR Type R/W Reset 0x0 Description GPTM TimerB Mode The TBMR values are defined as follows: Value Description 0x0 Reserved. 0x1 One-Shot Timer mode. 0x2 Periodic Timer mode. 0x3 Capture mode. The timer mode is based on the timer configuration defined by bits 2:0 in the GPTMCFG register. In 16-bit timer configuration, these bits control the 16-bit timer modes for TimerB. In 32-bit timer configuration, this register ’s contents are ignored and GPTMTAMR is used. 220 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 4: GPTM Control (GPTMCTL), offset 0x00C This register is used alongside the GPTMCFG and GMTMTnMR registers to fine-tune the timer configuration, and to enable other features such as timer stall and the output trigger. The output trigger can be used to initiate transfers on the ADC module. GPTM Control (GPTMCTL) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Timer3 base: 0x4003.3000 Offset 0x00C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 reserved RO 0 RO 0 11 RO 0 10 RO 0 9 TBSTALL R/W 0 RO 0 8 TBEN R/W 0 RO 0 7 RO 0 6 RO 0 5 TAOTE R/W 0 RO 0 4 RTCEN R/W 0 RO 0 3 RO 0 2 RO 0 1 TASTALL R/W 0 RO 0 0 TAEN R/W 0 reserved TBPWML TBOTE Type Reset RO 0 R/W 0 R/W 0 TBEVENT R/W 0 R/W 0 reserved TAPWML RO 0 R/W 0 TAEVENT R/W 0 R/W 0 Bit/Field 31:15 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPTM TimerB PWM Output Level The TBPWML values are defined as follows: Value Description 0 1 Output is unaffected. Output is inverted. 14 TBPWML R/W 0 13 TBOTE R/W 0 GPTM TimerB Output Trigger Enable The TBOTE values are defined as follows: Value Description 0 1 The output TimerB trigger is disabled. The output TimerB trigger is enabled. 12 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. November 30, 2007 Preliminary 221 General-Purpose Timers Bit/Field 11:10 Name TBEVENT Type R/W Reset 0x0 Description GPTM TimerB Event Mode The TBEVENT values are defined as follows: Value Description 0x0 Positive edge. 0x1 Negative edge. 0x2 Reserved 0x3 Both edges. 9 TBSTALL R/W 0 GPTM TimerB Stall Enable The TBSTALL values are defined as follows: Value Description 0 1 TimerB stalling is disabled. TimerB stalling is enabled. 8 TBEN R/W 0 GPTM TimerB Enable The TBEN values are defined as follows: Value Description 0 1 TimerB is disabled. TimerB is enabled and begins counting or the capture logic is enabled based on the GPTMCFG register. 7 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPTM TimerA PWM Output Level The TAPWML values are defined as follows: Value Description 0 1 Output is unaffected. Output is inverted. 6 TAPWML R/W 0 5 TAOTE R/W 0 GPTM TimerA Output Trigger Enable The TAOTE values are defined as follows: Value Description 0 1 The output TimerA trigger is disabled. The output TimerA trigger is enabled. 222 Preliminary November 30, 2007 LM3S6965 Microcontroller Bit/Field 4 Name RTCEN Type R/W Reset 0 Description GPTM RTC Enable The RTCEN values are defined as follows: Value Description 0 1 RTC counting is disabled. RTC counting is enabled. 3:2 TAEVENT R/W 0x0 GPTM TimerA Event Mode The TAEVENT values are defined as follows: Value Description 0x0 Positive edge. 0x1 Negative edge. 0x2 Reserved 0x3 Both edges. 1 TASTALL R/W 0 GPTM TimerA Stall Enable The TASTALL values are defined as follows: Value Description 0 1 TimerA stalling is disabled. TimerA stalling is enabled. 0 TAEN R/W 0 GPTM TimerA Enable The TAEN values are defined as follows: Value Description 0 1 TimerA is disabled. TimerA is enabled and begins counting or the capture logic is enabled based on the GPTMCFG register. November 30, 2007 Preliminary 223 General-Purpose Timers Register 5: GPTM Interrupt Mask (GPTMIMR), offset 0x018 This register allows software to enable/disable GPTM controller-level interrupts. Writing a 1 enables the interrupt, while writing a 0 disables it. GPTM Interrupt Mask (GPTMIMR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Timer3 base: 0x4003.3000 Offset 0x018 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 12 RO 0 11 RO 0 10 CBEIM R/W 0 RO 0 9 CBMIM R/W 0 RO 0 8 TBTOIM R/W 0 RO 0 RO 0 7 RO 0 6 reserved RO 0 RO 0 RO 0 RO 0 5 RO 0 4 RO 0 3 RTCIM R/W 0 RO 0 2 CAEIM R/W 0 RO 0 1 CAMIM R/W 0 RO 0 0 TATOIM R/W 0 Bit/Field 31:11 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPTM CaptureB Event Interrupt Mask The CBEIM values are defined as follows: Value Description 0 1 Interrupt is disabled. Interrupt is enabled. 10 CBEIM R/W 0 9 CBMIM R/W 0 GPTM CaptureB Match Interrupt Mask The CBMIM values are defined as follows: Value Description 0 1 Interrupt is disabled. Interrupt is enabled. 8 TBTOIM R/W 0 GPTM TimerB Time-Out Interrupt Mask The TBTOIM values are defined as follows: Value Description 0 1 Interrupt is disabled. Interrupt is enabled. 7:4 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 224 Preliminary November 30, 2007 LM3S6965 Microcontroller Bit/Field 3 Name RTCIM Type R/W Reset 0 Description GPTM RTC Interrupt Mask The RTCIM values are defined as follows: Value Description 0 1 Interrupt is disabled. Interrupt is enabled. 2 CAEIM R/W 0 GPTM CaptureA Event Interrupt Mask The CAEIM values are defined as follows: Value Description 0 1 Interrupt is disabled. Interrupt is enabled. 1 CAMIM R/W 0 GPTM CaptureA Match Interrupt Mask The CAMIM values are defined as follows: Value Description 0 1 Interrupt is disabled. Interrupt is enabled. 0 TATOIM R/W 0 GPTM TimerA Time-Out Interrupt Mask The TATOIM values are defined as follows: Value Description 0 1 Interrupt is disabled. Interrupt is enabled. November 30, 2007 Preliminary 225 General-Purpose Timers Register 6: GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C This register shows the state of the GPTM's internal interrupt signal. These bits are set whether or not the interrupt is masked in the GPTMIMR register. Each bit can be cleared by writing a 1 to its corresponding bit in GPTMICR. GPTM Raw Interrupt Status (GPTMRIS) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Timer3 base: 0x4003.3000 Offset 0x01C Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 reserved RO 0 RO 0 RO 0 RO 0 RO 0 5 RO 0 4 RO 0 3 RTCRIS RO 0 RO 0 2 RO 0 1 RO 0 0 CBERIS CBMRIS TBTORIS RO 0 RO 0 RO 0 CAERIS CAMRIS TATORIS RO 0 RO 0 RO 0 Bit/Field 31:11 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPTM CaptureB Event Raw Interrupt This is the CaptureB Event interrupt status prior to masking. 10 CBERIS RO 0 9 CBMRIS RO 0 GPTM CaptureB Match Raw Interrupt This is the CaptureB Match interrupt status prior to masking. 8 TBTORIS RO 0 GPTM TimerB Time-Out Raw Interrupt This is the TimerB time-out interrupt status prior to masking. 7:4 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPTM RTC Raw Interrupt This is the RTC Event interrupt status prior to masking. 3 RTCRIS RO 0 2 CAERIS RO 0 GPTM CaptureA Event Raw Interrupt This is the CaptureA Event interrupt status prior to masking. 1 CAMRIS RO 0 GPTM CaptureA Match Raw Interrupt This is the CaptureA Match interrupt status prior to masking. 0 TATORIS RO 0 GPTM TimerA Time-Out Raw Interrupt This the TimerA time-out interrupt status prior to masking. 226 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 7: GPTM Masked Interrupt Status (GPTMMIS), offset 0x020 This register show the state of the GPTM's controller-level interrupt. If an interrupt is unmasked in GPTMIMR, and there is an event that causes the interrupt to be asserted, the corresponding bit is set in this register. All bits are cleared by writing a 1 to the corresponding bit in GPTMICR. GPTM Masked Interrupt Status (GPTMMIS) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Timer3 base: 0x4003.3000 Offset 0x020 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 reserved RO 0 RO 0 RO 0 RO 0 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 CBEMIS CBMMIS TBTOMIS RO 0 RO 0 RO 0 RTCMIS CAEMIS CAMMIS TATOMIS RO 0 RO 0 RO 0 RO 0 Bit/Field 31:11 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPTM CaptureB Event Masked Interrupt This is the CaptureB event interrupt status after masking. 10 CBEMIS RO 0 9 CBMMIS RO 0 GPTM CaptureB Match Masked Interrupt This is the CaptureB match interrupt status after masking. 8 TBTOMIS RO 0 GPTM TimerB Time-Out Masked Interrupt This is the TimerB time-out interrupt status after masking. 7:4 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPTM RTC Masked Interrupt This is the RTC event interrupt status after masking. 3 RTCMIS RO 0 2 CAEMIS RO 0 GPTM CaptureA Event Masked Interrupt This is the CaptureA event interrupt status after masking. 1 CAMMIS RO 0 GPTM CaptureA Match Masked Interrupt This is the CaptureA match interrupt status after masking. 0 TATOMIS RO 0 GPTM TimerA Time-Out Masked Interrupt This is the TimerA time-out interrupt status after masking. November 30, 2007 Preliminary 227 General-Purpose Timers Register 8: GPTM Interrupt Clear (GPTMICR), offset 0x024 This register is used to clear the status bits in the GPTMRIS and GPTMMIS registers. Writing a 1 to a bit clears the corresponding bit in the GPTMRIS and GPTMMIS registers. GPTM Interrupt Clear (GPTMICR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Timer3 base: 0x4003.3000 Offset 0x024 Type W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 reserved RO 0 RO 0 RO 0 RO 0 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 CBECINT CBMCINT TBTOCINT W1C 0 W1C 0 W1C 0 RTCCINT CAECINT CAMCINT TATOCINT W1C 0 W1C 0 W1C 0 W1C 0 Bit/Field 31:11 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPTM CaptureB Event Interrupt Clear The CBECINT values are defined as follows: Value Description 0 1 The interrupt is unaffected. The interrupt is cleared. 10 CBECINT W1C 0 9 CBMCINT W1C 0 GPTM CaptureB Match Interrupt Clear The CBMCINT values are defined as follows: Value Description 0 1 The interrupt is unaffected. The interrupt is cleared. 8 TBTOCINT W1C 0 GPTM TimerB Time-Out Interrupt Clear The TBTOCINT values are defined as follows: Value Description 0 1 The interrupt is unaffected. The interrupt is cleared. 7:4 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 228 Preliminary November 30, 2007 LM3S6965 Microcontroller Bit/Field 3 Name RTCCINT Type W1C Reset 0 Description GPTM RTC Interrupt Clear The RTCCINT values are defined as follows: Value Description 0 1 The interrupt is unaffected. The interrupt is cleared. 2 CAECINT W1C 0 GPTM CaptureA Event Interrupt Clear The CAECINT values are defined as follows: Value Description 0 1 The interrupt is unaffected. The interrupt is cleared. 1 CAMCINT W1C 0 GPTM CaptureA Match Raw Interrupt This is the CaptureA match interrupt status after masking. 0 TATOCINT W1C 0 GPTM TimerA Time-Out Raw Interrupt The TATOCINT values are defined as follows: Value Description 0 1 The interrupt is unaffected. The interrupt is cleared. November 30, 2007 Preliminary 229 General-Purpose Timers Register 9: GPTM TimerA Interval Load (GPTMTAILR), offset 0x028 This register is used to load the starting count value into the timer. When GPTM is configured to one of the 32-bit modes, GPTMTAILR appears as a 32-bit register (the upper 16-bits correspond to the contents of the GPTM TimerB Interval Load (GPTMTBILR) register). In 16-bit mode, the upper 16 bits of this register read as 0s and have no effect on the state of GPTMTBILR. GPTM TimerA Interval Load (GPTMTAILR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Timer3 base: 0x4003.3000 Offset 0x028 Type R/W, reset 0x0000.FFFF (16-bit mode) and 0xFFFF.FFFF (32-bit mode) 31 30 29 28 27 26 25 24 TAILRH Type Reset R/W 0 15 R/W 1 14 R/W 1 13 R/W 0 12 R/W 1 11 R/W 0 10 R/W 1 9 R/W 1 8 TAILRL Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 7 R/W 1 6 R/W 0 5 R/W 1 4 R/W 1 3 R/W 1 2 R/W 1 1 R/W 0 0 23 22 21 20 19 18 17 16 Bit/Field 31:16 Name TAILRH Type R/W Reset Description 0xFFFF GPTM TimerA Interval Load Register High (32-bit mode) 0x0000 (16-bit When configured for 32-bit mode via the GPTMCFG register, the GPTM TimerB Interval Load (GPTMTBILR) register loads this value on a mode) write. A read returns the current value of GPTMTBILR. In 16-bit mode, this field reads as 0 and does not have an effect on the state of GPTMTBILR. 15:0 TAILRL R/W 0xFFFF GPTM TimerA Interval Load Register Low For both 16- and 32-bit modes, writing this field loads the counter for TimerA. A read returns the current value of GPTMTAILR. 230 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 10: GPTM TimerB Interval Load (GPTMTBILR), offset 0x02C This register is used to load the starting count value into TimerB. When the GPTM is configured to a 32-bit mode, GPTMTBILR returns the current value of TimerB and ignores writes. GPTM TimerB Interval Load (GPTMTBILR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Timer3 base: 0x4003.3000 Offset 0x02C Type R/W, reset 0x0000.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 TBILRL Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 Bit/Field 31:16 Name reserved Type RO Reset 0x0000 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPTM TimerB Interval Load Register When the GPTM is not configured as a 32-bit timer, a write to this field updates GPTMTBILR. In 32-bit mode, writes are ignored, and reads return the current value of GPTMTBILR. 15:0 TBILRL R/W 0xFFFF November 30, 2007 Preliminary 231 General-Purpose Timers Register 11: GPTM TimerA Match (GPTMTAMATCHR), offset 0x030 This register is used in 32-bit Real-Time Clock mode and 16-bit PWM and Input Edge Count modes. GPTM TimerA Match (GPTMTAMATCHR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Timer3 base: 0x4003.3000 Offset 0x030 Type R/W, reset 0x0000.FFFF (16-bit mode) and 0xFFFF.FFFF (32-bit mode) 31 30 29 28 27 26 25 24 TAMRH Type Reset R/W 0 15 R/W 1 14 R/W 1 13 R/W 0 12 R/W 1 11 R/W 0 10 R/W 1 9 R/W 1 8 TAMRL Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 7 R/W 1 6 R/W 0 5 R/W 1 4 R/W 1 3 R/W 1 2 R/W 1 1 R/W 0 0 23 22 21 20 19 18 17 16 Bit/Field 31:16 Name TAMRH Type R/W Reset Description 0xFFFF GPTM TimerA Match Register High (32-bit mode) 0x0000 (16-bit When configured for 32-bit Real-Time Clock (RTC) mode via the GPTMCFG register, this value is compared to the upper half of mode) GPTMTAR, to determine match events. In 16-bit mode, this field reads as 0 and does not have an effect on the state of GPTMTBMATCHR. 15:0 TAMRL R/W 0xFFFF GPTM TimerA Match Register Low When configured for 32-bit Real-Time Clock (RTC) mode via the GPTMCFG register, this value is compared to the lower half of GPTMTAR, to determine match events. When configured for PWM mode, this value along with GPTMTAILR, determines the duty cycle of the output PWM signal. When configured for Edge Count mode, this value along with GPTMTAILR, determines how many edge events are counted. The total number of edge events counted is equal to the value in GPTMTAILR minus this value. 232 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 12: GPTM TimerB Match (GPTMTBMATCHR), offset 0x034 This register is used in 32-bit Real-Time Clock mode and 16-bit PWM and Input Edge Count modes. GPTM TimerB Match (GPTMTBMATCHR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Timer3 base: 0x4003.3000 Offset 0x034 Type R/W, reset 0x0000.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 TBMRL Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 Bit/Field 31:16 Name reserved Type RO Reset 0x0000 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPTM TimerB Match Register Low When configured for PWM mode, this value along with GPTMTBILR, determines the duty cycle of the output PWM signal. When configured for Edge Count mode, this value along with GPTMTBILR, determines how many edge events are counted. The total number of edge events counted is equal to the value in GPTMTBILR minus this value. 15:0 TBMRL R/W 0xFFFF November 30, 2007 Preliminary 233 General-Purpose Timers Register 13: GPTM TimerA Prescale (GPTMTAPR), offset 0x038 This register allows software to extend the range of the 16-bit timers when operating in one-shot or periodic mode. GPTM TimerA Prescale (GPTMTAPR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Timer3 base: 0x4003.3000 Offset 0x038 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 TAPSR RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPTM TimerA Prescale The register loads this value on a write. A read returns the current value of the register. Refer to Table 10-2 on page 208 for more details and an example. 7:0 TAPSR R/W 0x00 234 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 14: GPTM TimerB Prescale (GPTMTBPR), offset 0x03C This register allows software to extend the range of the 16-bit timers when operating in one-shot or periodic mode. GPTM TimerB Prescale (GPTMTBPR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Timer3 base: 0x4003.3000 Offset 0x03C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 TBPSR RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPTM TimerB Prescale The register loads this value on a write. A read returns the current value of this register. Refer to Table 10-2 on page 208 for more details and an example. 7:0 TBPSR R/W 0x00 November 30, 2007 Preliminary 235 General-Purpose Timers Register 15: GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040 This register effectively extends the range of GPTMTAMATCHR to 24 bits when operating in 16-bit one-shot or periodic mode. GPTM TimerA Prescale Match (GPTMTAPMR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Timer3 base: 0x4003.3000 Offset 0x040 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 TAPSMR RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPTM TimerA Prescale Match This value is used alongside GPTMTAMATCHR to detect timer match events while using a prescaler. 7:0 TAPSMR R/W 0x00 236 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 16: GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044 This register effectively extends the range of GPTMTBMATCHR to 24 bits when operating in 16-bit one-shot or periodic mode. GPTM TimerB Prescale Match (GPTMTBPMR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Timer3 base: 0x4003.3000 Offset 0x044 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 TBPSMR RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPTM TimerB Prescale Match This value is used alongside GPTMTBMATCHR to detect timer match events while using a prescaler. 7:0 TBPSMR R/W 0x00 November 30, 2007 Preliminary 237 General-Purpose Timers Register 17: GPTM TimerA (GPTMTAR), offset 0x048 This register shows the current value of the TimerA counter in all cases except for Input Edge Count mode. When in this mode, this register contains the time at which the last edge event took place. GPTM TimerA (GPTMTAR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Timer3 base: 0x4003.3000 Offset 0x048 Type RO, reset 0x0000.FFFF (16-bit mode) and 0xFFFF.FFFF (32-bit mode) 31 30 29 28 27 26 25 24 TARH Type Reset RO 0 15 RO 1 14 RO 1 13 RO 0 12 RO 1 11 RO 0 10 RO 1 9 RO 1 8 TARL Type Reset RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 7 RO 1 6 RO 0 5 RO 1 4 RO 1 3 RO 1 2 RO 1 1 RO 0 0 23 22 21 20 19 18 17 16 Bit/Field 31:16 Name TARH Type RO Reset Description 0xFFFF GPTM TimerA Register High (32-bit mode) 0x0000 (16-bit If the GPTMCFG is in a 32-bit mode, TimerB value is read. If the GPTMCFG is in a 16-bit mode, this is read as zero. mode) 0xFFFF GPTM TimerA Register Low A read returns the current value of the GPTM TimerA Count Register, except in Input Edge Count mode, when it returns the timestamp from the last edge event. 15:0 TARL RO 238 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 18: GPTM TimerB (GPTMTBR), offset 0x04C This register shows the current value of the TimerB counter in all cases except for Input Edge Count mode. When in this mode, this register contains the time at which the last edge event took place. GPTM TimerB (GPTMTBR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Timer3 base: 0x4003.3000 Offset 0x04C Type RO, reset 0x0000.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 TBRL Type Reset RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 Bit/Field 31:16 Name reserved Type RO Reset 0x0000 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. GPTM TimerB A read returns the current value of the GPTM TimerB Count Register, except in Input Edge Count mode, when it returns the timestamp from the last edge event. 15:0 TBRL RO 0xFFFF November 30, 2007 Preliminary 239 Watchdog Timer 11 Watchdog Timer A watchdog timer can generate nonmaskable interrupts (NMIs) or a reset when a time-out value is reached. The watchdog timer is used to regain control when a system has failed due to a software error or due to the failure of an external device to respond in the expected way. The Stellaris Watchdog Timer module consists of a 32-bit down counter, a programmable load register, interrupt generation logic, a locking register, and user-enabled stalling. The Watchdog Timer can be configured to generate an interrupt to the controller on its first time-out, and to generate a reset signal on its second time-out. Once the Watchdog Timer has been configured, the lock register can be written to prevent the timer configuration from being inadvertently altered. ® 11.1 Block Diagram Figure 11-1. WDT Module Block Diagram Control / Clock / Interrupt Generation WDTCTL WDTICR Interrupt WDTRIS WDTMIS WDTLOCK System Clock WDTTEST Comparator WDTVALUE 32-Bit Down Counter 0x00000000 WDTLOAD Identification Registers WDTPCellID0 WDTPCellID1 WDTPCellID2 WDTPCellID3 WDTPeriphID0 WDTPeriphID1 WDTPeriphID2 WDTPeriphID3 WDTPeriphID4 WDTPeriphID5 WDTPeriphID6 WDTPeriphID7 11.2 Functional Description The Watchdog Timer module generates the first time-out signal when the 32-bit counter reaches the zero state after being enabled; enabling the counter also enables the watchdog timer interrupt. After the first time-out event, the 32-bit counter is re-loaded with the value of the Watchdog Timer Load (WDTLOAD) register, and the timer resumes counting down from that value. Once the 240 Preliminary November 30, 2007 LM3S6965 Microcontroller Watchdog Timer has been configured, the Watchdog Timer Lock (WDTLOCK) register is written, which prevents the timer configuration from being inadvertently altered by software. If the timer counts down to its zero state again before the first time-out interrupt is cleared, and the reset signal has been enabled (via the WatchdogResetEnable function), the Watchdog timer asserts its reset signal to the system. If the interrupt is cleared before the 32-bit counter reaches its second time-out, the 32-bit counter is loaded with the value in the WDTLOAD register, and counting resumes from that value. If WDTLOAD is written with a new value while the Watchdog Timer counter is counting, then the counter is loaded with the new value and continues counting. Writing to WDTLOAD does not clear an active interrupt. An interrupt must be specifically cleared by writing to the Watchdog Interrupt Clear (WDTICR) register. The Watchdog module interrupt and reset generation can be enabled or disabled as required. When the interrupt is re-enabled, the 32-bit counter is preloaded with the load register value and not its last state. 11.3 Initialization and Configuration To use the WDT, its peripheral clock must be enabled by setting the WDT bit in the RCGC0 register. The Watchdog Timer is configured using the following sequence: 1. Load the WDTLOAD register with the desired timer load value. 2. If the Watchdog is configured to trigger system resets, set the RESEN bit in the WDTCTL register. 3. Set the INTEN bit in the WDTCTL register to enable the Watchdog and lock the control register. If software requires that all of the watchdog registers are locked, the Watchdog Timer module can be fully locked by writing any value to the WDTLOCK register. To unlock the Watchdog Timer, write a value of 0x1ACC.E551. 11.4 Register Map Table 11-1 on page 241 lists the Watchdog registers. The offset listed is a hexadecimal increment to the register ’s address, relative to the Watchdog Timer base address of 0x4000.0000. Table 11-1. Watchdog Timer Register Map Offset 0x000 0x004 0x008 0x00C 0x010 0x014 0x418 0xC00 Name WDTLOAD WDTVALUE WDTCTL WDTICR WDTRIS WDTMIS WDTTEST WDTLOCK Type R/W RO R/W WO RO RO R/W R/W Reset 0xFFFF.FFFF 0xFFFF.FFFF 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 Description Watchdog Load Watchdog Value Watchdog Control Watchdog Interrupt Clear Watchdog Raw Interrupt Status Watchdog Masked Interrupt Status Watchdog Test Watchdog Lock See page 243 244 245 246 247 248 249 250 November 30, 2007 Preliminary 241 Watchdog Timer Offset 0xFD0 0xFD4 0xFD8 0xFDC 0xFE0 0xFE4 0xFE8 0xFEC 0xFF0 0xFF4 0xFF8 0xFFC Name WDTPeriphID4 WDTPeriphID5 WDTPeriphID6 WDTPeriphID7 WDTPeriphID0 WDTPeriphID1 WDTPeriphID2 WDTPeriphID3 WDTPCellID0 WDTPCellID1 WDTPCellID2 WDTPCellID3 Type RO RO RO RO RO RO RO RO RO RO RO RO Reset 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0005 0x0000.0018 0x0000.0018 0x0000.0001 0x0000.000D 0x0000.00F0 0x0000.0005 0x0000.00B1 Description Watchdog Peripheral Identification 4 Watchdog Peripheral Identification 5 Watchdog Peripheral Identification 6 Watchdog Peripheral Identification 7 Watchdog Peripheral Identification 0 Watchdog Peripheral Identification 1 Watchdog Peripheral Identification 2 Watchdog Peripheral Identification 3 Watchdog PrimeCell Identification 0 Watchdog PrimeCell Identification 1 Watchdog PrimeCell Identification 2 Watchdog PrimeCell Identification 3 See page 251 252 253 254 255 256 257 258 259 260 261 262 11.5 Register Descriptions The remainder of this section lists and describes the WDT registers, in numerical order by address offset. 242 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 1: Watchdog Load (WDTLOAD), offset 0x000 This register is the 32-bit interval value used by the 32-bit counter. When this register is written, the value is immediately loaded and the counter restarts counting down from the new value. If the WDTLOAD register is loaded with 0x0000.0000, an interrupt is immediately generated. Watchdog Load (WDTLOAD) Base 0x4000.0000 Offset 0x000 Type R/W, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 WDTLoad Type Reset R/W 1 15 R/W 1 14 R/W 1 13 R/W 1 12 R/W 1 11 R/W 1 10 R/W 1 9 R/W 1 8 R/W 1 7 R/W 1 6 R/W 1 5 R/W 1 4 R/W 1 3 R/W 1 2 R/W 1 1 R/W 1 0 WDTLoad Type Reset R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 Bit/Field 31:0 Name WDTLoad Type R/W Reset Description 0xFFFF.FFFF Watchdog Load Value November 30, 2007 Preliminary 243 Watchdog Timer Register 2: Watchdog Value (WDTVALUE), offset 0x004 This register contains the current count value of the timer. Watchdog Value (WDTVALUE) Base 0x4000.0000 Offset 0x004 Type RO, reset 0xFFFF.FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 WDTValue Type Reset RO 1 15 RO 1 14 RO 1 13 RO 1 12 RO 1 11 RO 1 10 RO 1 9 RO 1 8 RO 1 7 RO 1 6 RO 1 5 RO 1 4 RO 1 3 RO 1 2 RO 1 1 RO 1 0 WDTValue Type Reset RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 RO 1 Bit/Field 31:0 Name WDTValue Type RO Reset Description 0xFFFF.FFFF Watchdog Value Current value of the 32-bit down counter. 244 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 3: Watchdog Control (WDTCTL), offset 0x008 This register is the watchdog control register. The watchdog timer can be configured to generate a reset signal (on second time-out) or an interrupt on time-out. When the watchdog interrupt has been enabled, all subsequent writes to the control register are ignored. The only mechanism that can re-enable writes is a hardware reset. Watchdog Control (WDTCTL) Base 0x4000.0000 Offset 0x008 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RESEN R/W 0 RO 0 0 INTEN R/W 0 Bit/Field 31:2 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Watchdog Reset Enable The RESEN values are defined as follows: Value Description 0 1 Disabled. Enable the Watchdog module reset output. 1 RESEN R/W 0 0 INTEN R/W 0 Watchdog Interrupt Enable The INTEN values are defined as follows: Value Description 0 1 Interrupt event disabled (once this bit is set, it can only be cleared by a hardware reset). Interrupt event enabled. Once enabled, all writes are ignored. November 30, 2007 Preliminary 245 Watchdog Timer Register 4: Watchdog Interrupt Clear (WDTICR), offset 0x00C This register is the interrupt clear register. A write of any value to this register clears the Watchdog interrupt and reloads the 32-bit counter from the WDTLOAD register. Value for a read or reset is indeterminate. Watchdog Interrupt Clear (WDTICR) Base 0x4000.0000 Offset 0x00C Type WO, reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 WDTIntClr Type Reset WO 15 WO 14 WO 13 WO 12 WO 11 WO 10 WO 9 WO 8 WO 7 WO 6 WO 5 WO 4 WO 3 WO 2 WO 1 WO 0 WDTIntClr Type Reset WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO WO - Bit/Field 31:0 Name WDTIntClr Type WO Reset - Description Watchdog Interrupt Clear 246 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 5: Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 This register is the raw interrupt status register. Watchdog interrupt events can be monitored via this register if the controller interrupt is masked. Watchdog Raw Interrupt Status (WDTRIS) Base 0x4000.0000 Offset 0x010 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 WDTRIS RO 0 Bit/Field 31:1 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Watchdog Raw Interrupt Status Gives the raw interrupt state (prior to masking) of WDTINTR. 0 WDTRIS RO 0 November 30, 2007 Preliminary 247 Watchdog Timer Register 6: Watchdog Masked Interrupt Status (WDTMIS), offset 0x014 This register is the masked interrupt status register. The value of this register is the logical AND of the raw interrupt bit and the Watchdog interrupt enable bit. Watchdog Masked Interrupt Status (WDTMIS) Base 0x4000.0000 Offset 0x014 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 WDTMIS RO 0 Bit/Field 31:1 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Watchdog Masked Interrupt Status Gives the masked interrupt state (after masking) of the WDTINTR interrupt. 0 WDTMIS RO 0 248 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 7: Watchdog Test (WDTTEST), offset 0x418 This register provides user-enabled stalling when the microcontroller asserts the CPU halt flag during debug. Watchdog Test (WDTTEST) Base 0x4000.0000 Offset 0x418 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 11 RO 0 10 RO 0 9 RO 0 8 STALL R/W 0 RO 0 RO 0 RO 0 RO 0 7 RO 0 6 RO 0 5 RO 0 4 reserved RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 3 RO 0 2 RO 0 1 RO 0 0 Bit/Field 31:9 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Watchdog Stall Enable When set to 1, if the Stellaris microcontroller is stopped with a debugger, the watchdog timer stops counting. Once the microcontroller is restarted, the watchdog timer resumes counting. ® 8 STALL R/W 0 7:0 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. November 30, 2007 Preliminary 249 Watchdog Timer Register 8: Watchdog Lock (WDTLOCK), offset 0xC00 Writing 0x1ACC.E551 to the WDTLOCK register enables write access to all other registers. Writing any other value to the WDTLOCK register re-enables the locked state for register writes to all the other registers. Reading the WDTLOCK register returns the lock status rather than the 32-bit value written. Therefore, when write accesses are disabled, reading the WDTLOCK register returns 0x0000.0001 (when locked; otherwise, the returned value is 0x0000.0000 (unlocked)). Watchdog Lock (WDTLOCK) Base 0x4000.0000 Offset 0xC00 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 WDTLock Type Reset R/W 0 15 R/W 0 14 R/W 0 13 R/W 0 12 R/W 0 11 R/W 0 10 R/W 0 9 R/W 0 8 R/W 0 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 WDTLock Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field 31:0 Name WDTLock Type R/W Reset 0x0000 Description Watchdog Lock A write of the value 0x1ACC.E551 unlocks the watchdog registers for write access. A write of any other value reapplies the lock, preventing any register updates. A read of this register returns the following values: Value Description 0x0000.0001 Locked 0x0000.0000 Unlocked 250 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 9: Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0 The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 4 (WDTPeriphID4) Base 0x4000.0000 Offset 0xFD0 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 PID4 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. WDT Peripheral ID Register[7:0] 7:0 PID4 RO 0x00 November 30, 2007 Preliminary 251 Watchdog Timer Register 10: Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4 The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 5 (WDTPeriphID5) Base 0x4000.0000 Offset 0xFD4 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 PID5 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. WDT Peripheral ID Register[15:8] 7:0 PID5 RO 0x00 252 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 11: Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8 The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 6 (WDTPeriphID6) Base 0x4000.0000 Offset 0xFD8 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 PID6 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. WDT Peripheral ID Register[23:16] 7:0 PID6 RO 0x00 November 30, 2007 Preliminary 253 Watchdog Timer Register 12: Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 7 (WDTPeriphID7) Base 0x4000.0000 Offset 0xFDC Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 PID7 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. WDT Peripheral ID Register[31:24] 7:0 PID7 RO 0x00 254 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 13: Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 0 (WDTPeriphID0) Base 0x4000.0000 Offset 0xFE0 Type RO, reset 0x0000.0005 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 PID0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 0 RO 1 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Watchdog Peripheral ID Register[7:0] 7:0 PID0 RO 0x05 November 30, 2007 Preliminary 255 Watchdog Timer Register 14: Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 1 (WDTPeriphID1) Base 0x4000.0000 Offset 0xFE4 Type RO, reset 0x0000.0018 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 PID1 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 1 RO 0 RO 0 RO 0 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Watchdog Peripheral ID Register[15:8] 7:0 PID1 RO 0x18 256 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 15: Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 2 (WDTPeriphID2) Base 0x4000.0000 Offset 0xFE8 Type RO, reset 0x0000.0018 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 PID2 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 1 RO 0 RO 0 RO 0 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Watchdog Peripheral ID Register[23:16] 7:0 PID2 RO 0x18 November 30, 2007 Preliminary 257 Watchdog Timer Register 16: Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 3 (WDTPeriphID3) Base 0x4000.0000 Offset 0xFEC Type RO, reset 0x0000.0001 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 PID3 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Watchdog Peripheral ID Register[31:24] 7:0 PID3 RO 0x01 258 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 17: Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0 The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog PrimeCell Identification 0 (WDTPCellID0) Base 0x4000.0000 Offset 0xFF0 Type RO, reset 0x0000.000D 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 CID0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 1 RO 0 RO 1 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Watchdog PrimeCell ID Register[7:0] 7:0 CID0 RO 0x0D November 30, 2007 Preliminary 259 Watchdog Timer Register 18: Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4 The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog PrimeCell Identification 1 (WDTPCellID1) Base 0x4000.0000 Offset 0xFF4 Type RO, reset 0x0000.00F0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 CID1 RO 0 RO 0 RO 0 RO 1 RO 1 RO 1 RO 1 RO 0 RO 0 RO 0 RO 0 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Watchdog PrimeCell ID Register[15:8] 7:0 CID1 RO 0xF0 260 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 19: Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8 The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog PrimeCell Identification 2 (WDTPCellID2) Base 0x4000.0000 Offset 0xFF8 Type RO, reset 0x0000.0005 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 CID2 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 0 RO 1 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Watchdog PrimeCell ID Register[23:16] 7:0 CID2 RO 0x05 November 30, 2007 Preliminary 261 Watchdog Timer Register 20: Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog PrimeCell Identification 3 (WDTPCellID3) Base 0x4000.0000 Offset 0xFFC Type RO, reset 0x0000.00B1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 CID3 RO 0 RO 0 RO 0 RO 1 RO 0 RO 1 RO 1 RO 0 RO 0 RO 0 RO 1 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Watchdog PrimeCell ID Register[31:24] 7:0 CID3 RO 0xB1 262 Preliminary November 30, 2007 LM3S6965 Microcontroller 12 Analog-to-Digital Converter (ADC) An analog-to-digital converter (ADC) is a peripheral that converts a continuous analog voltage to a discrete digital number. The Stellaris ADC module features 10-bit conversion resolution and supports four input channels, plus an internal temperature sensor. The ADC module contains a programmable sequencer which allows for the sampling of multiple analog input sources without controller intervention. Each sample sequence provides flexible programming with fully configurable input source, trigger events, interrupt generation, and sequence priority. The Stellaris ADC provides the following features: ■ Four analog input channels ■ Single-ended and differential-input configurations ■ Internal temperature sensor ■ Sample rate of one million samples/second ■ Four programmable sample conversion sequences from one to eight entries long, with corresponding conversion result FIFOs ■ Flexible trigger control – Controller (software) – Timers – Analog Comparators – PWM – GPIO ■ Hardware averaging of up to 64 samples for improved accuracy ® ® November 30, 2007 Preliminary 263 Analog-to-Digital Converter (ADC) 12.1 Block Diagram Figure 12-1. ADC Module Block Diagram Trigger Events Comparator GPIO (PB4) Timer PWM Comparator GPIO (PB4) Timer PWM Comparator GPIO (PB4) Timer PWM Comparator GPIO (PB4) Timer PWM Control/Status SS3 ADCACTSS ADCOSTAT ADCUSTAT ADCSSPRI SS2 Sample Sequencer 1 ADCSSMUX1 ADCSSCTL1 SS1 ADCSSFSTAT1 Hardware Averager ADCSAC Sample Sequencer 0 ADCSSMUX0 ADCSSCTL0 ADCSSFSTAT0 Analog-to-Digital Converter Analog Inputs Sample Sequencer 2 SS0 ADCSSMUX2 ADCSSCTL2 ADCSSFSTAT2 ADCEMUX ADCPSSI Interrupt Control ADCIM ADCRIS ADCISC Sample Sequencer 3 ADCSSMUX3 ADCSSCTL3 ADCSSFSTAT3 FIFO Block ADCSSFIFO0 ADCSSFIFO1 ADCSSFIFO2 ADCSSFIFO3 SS0 Interrupt SS1 Interrupt SS2 Interrupt SS3 Interrupt 12.2 Functional Description The Stellaris ADC collects sample data by using a programmable sequence-based approach instead of the traditional single or double-sampling approach found on many ADC modules. Each sample sequence is a fully programmed series of consecutive (back-to-back) samples, allowing the ADC to collect data from multiple input sources without having to be re-configured or serviced by the controller. The programming of each sample in the sample sequence includes parameters such as the input source and mode (differential versus single-ended input), interrupt generation on sample completion, and the indicator for the last sample in the sequence. ® 12.2.1 Sample Sequencers The sampling control and data capture is handled by the Sample Sequencers. All of the sequencers are identical in implementation except for the number of samples that can be captured and the depth of the FIFO. Table 12-1 on page 264 shows the maximum number of samples that each Sequencer can capture and its corresponding FIFO depth. In this implementation, each FIFO entry is a 32-bit word, with the lower 10 bits containing the conversion result. Table 12-1. Samples and FIFO Depth of Sequencers Sequencer Number of Samples Depth of FIFO SS3 SS2 SS1 SS0 1 4 4 8 1 4 4 8 264 Preliminary November 30, 2007 LM3S6965 Microcontroller For a given sample sequence, each sample is defined by two 4-bit nibbles in the ADC Sample Sequence Input Multiplexer Select (ADCSSMUXn) and ADC Sample Sequence Control (ADCSSCTLn) registers, where "n" corresponds to the sequence number. The ADCSSMUXn nibbles select the input pin, while the ADCSSCTLn nibbles contain the sample control bits corresponding to parameters such as temperature sensor selection, interrupt enable, end of sequence, and differential input mode. Sample Sequencers are enabled by setting the respective ASENn bit in the ADC Active Sample Sequencer (ADCACTSS) register, but can be configured before being enabled. When configuring a sample sequence, multiple uses of the same input pin within the same sequence is allowed. In the ADCSSCTLn register, the Interrupt Enable (IE) bits can be set for any combination of samples, allowing interrupts to be generated after every sample in the sequence if necessary. Also, the END bit can be set at any point within a sample sequence. For example, if Sequencer 0 is used, the END bit can be set in the nibble associated with the fifth sample, allowing Sequencer 0 to complete execution of the sample sequence after the fifth sample. After a sample sequence completes execution, the result data can be retrieved from the ADC Sample Sequence Result FIFO (ADCSSFIFOn) registers. The FIFOs are simple circular buffers that read a single address to "pop" result data. For software debug purposes, the positions of the FIFO head and tail pointers are visible in the ADC Sample Sequence FIFO Status (ADCSSFSTATn) registers along with FULL and EMPTY status flags. Overflow and underflow conditions are monitored using the ADCOSTAT and ADCUSTAT registers. 12.2.2 Module Control Outside of the Sample Sequencers, the remainder of the control logic is responsible for tasks such as interrupt generation, sequence prioritization, and trigger configuration. Most of the ADC control logic runs at the ADC clock rate of 14-18 MHz. The internal ADC divider is configured automatically by hardware when the system XTAL is selected. The automatic clock ® divider configuration targets 16.667 MHz operation for all Stellaris devices. 12.2.2.1 Interrupts The Sample Sequencers dictate the events that cause interrupts, but they don't have control over whether the interrupt is actually sent to the interrupt controller. The ADC module's interrupt signal is controlled by the state of the MASK bits in the ADC Interrupt Mask (ADCIM) register. Interrupt status can be viewed at two locations: the ADC Raw Interrupt Status (ADCRIS) register, which shows the raw status of a Sample Sequencer's interrupt signal, and the ADC Interrupt Status and Clear (ADCISC) register, which shows the logical AND of the ADCRIS register ’s INR bit and the ADCIM register ’s MASK bits. Interrupts are cleared by writing a 1 to the corresponding IN bit in ADCISC. 12.2.2.2 Prioritization When sampling events (triggers) happen concurrently, they are prioritized for processing by the values in the ADC Sample Sequencer Priority (ADCSSPRI) register. Valid priority values are in the range of 0-3, with 0 being the highest priority and 3 being the lowest. Multiple active Sample Sequencer units with the same priority do not provide consistent results, so software must ensure that all active Sample Sequencer units have a unique priority value. 12.2.2.3 Sampling Events Sample triggering for each Sample Sequencer is defined in the ADC Event Multiplexer Select ® (ADCEMUX) register. The external peripheral triggering sources vary by Stellaris family member, November 30, 2007 Preliminary 265 Analog-to-Digital Converter (ADC) but all devices share the "Controller" and "Always" triggers. Software can initiate sampling by setting the CH bits in the ADC Processor Sample Sequence Initiate (ADCPSSI) register. When using the "Always" trigger, care must be taken. If a sequence's priority is too high, it is possible to starve other lower priority sequences. 12.2.3 Hardware Sample Averaging Circuit Higher precision results can be generated using the hardware averaging circuit, however, the improved results are at the cost of throughput. Up to 64 samples can be accumulated and averaged to form a single data entry in the sequencer FIFO. Throughput is decreased proportionally to the number of samples in the averaging calculation. For example, if the averaging circuit is configured to average 16 samples, the throughput is decreased by a factor of 16. By default the averaging circuit is off and all data from the converter passes through to the sequencer FIFO. The averaging hardware is controlled by the ADC Sample Averaging Control (ADCSAC) register (see page 281). There is a single averaging circuit and all input channels receive the same amount of averaging whether they are single-ended or differential. 12.2.4 Analog-to-Digital Converter The converter itself generates a 10-bit output value for selected analog input. Special analog pads are used to minimize the distortion on the input. 12.2.5 Test Modes There is a user-available test mode that allows for loopback operation within the digital portion of the ADC module. This can be useful for debugging software without having to provide actual analog stimulus. This mode is available through the ADC Test Mode Loopback (ADCTMLB) register (see page 294). 12.2.6 Internal Temperature Sensor The internal temperature sensor provides an analog temperature reading as well as a reference voltage. The voltage at the output terminal SENSO is given by the following equation: SENSO = 2.7 - ((T + 55) / 75) This relation is shown in Figure 12-2 on page 267. 266 Preliminary November 30, 2007 LM3S6965 Microcontroller Figure 12-2. Internal Temperature Sensor Characteristic 12.3 Initialization and Configuration In order for the ADC module to be used, the PLL must be enabled and using a supported crystal frequency (see the RCC register). Using unsupported frequencies can cause faulty operation in the ADC module. 12.3.1 Module Initialization Initialization of the ADC module is a simple process with very few steps. The main steps include enabling the clock to the ADC and reconfiguring the Sample Sequencer priorities (if needed). The initialization sequence for the ADC is as follows: 1. Enable the ADC clock by writing a value of 0x0001.0000 to the RCGC1 register (see page 100). 2. If required by the application, reconfigure the Sample Sequencer priorities in the ADCSSPRI register. The default configuration has Sample Sequencer 0 with the highest priority, and Sample Sequencer 3 as the lowest priority. 12.3.2 Sample Sequencer Configuration Configuration of the Sample Sequencers is slightly more complex than the module initialization since each sample sequence is completely programmable. The configuration for each Sample Sequencer should be as follows: 1. Ensure that the Sample Sequencer is disabled by writing a 0 to the corresponding ASEN bit in the ADCACTSS register. Programming of the Sample Sequencers is allowed without having them enabled. Disabling the Sequencer during programming prevents erroneous execution if a trigger event were to occur during the configuration process. 2. Configure the trigger event for the Sample Sequencer in the ADCEMUX register. 3. For each sample in the sample sequence, configure the corresponding input source in the ADCSSMUXn register. November 30, 2007 Preliminary 267 Analog-to-Digital Converter (ADC) 4. For each sample in the sample sequence, configure the sample control bits in the corresponding nibble in the ADCSSCTLn register. When programming the last nibble, ensure that the END bit is set. Failure to set the END bit causes unpredictable behavior. 5. If interrupts are to be used, write a 1 to the corresponding MASK bit in the ADCIM register. 6. Enable the Sample Sequencer logic by writing a 1 to the corresponding ASEN bit in the ADCACTSS register. 12.4 Register Map Table 12-2 on page 268 lists the ADC registers. The offset listed is a hexadecimal increment to the register ’s address, relative to the ADC base address of 0x4003.8000. Table 12-2. ADC Register Map Offset 0x000 0x004 0x008 0x00C 0x010 0x014 0x018 0x020 0x028 0x030 0x040 0x044 0x048 0x04C 0x060 0x064 0x068 0x06C 0x080 0x084 0x088 0x08C 0x0A0 Name ADCACTSS ADCRIS ADCIM ADCISC ADCOSTAT ADCEMUX ADCUSTAT ADCSSPRI ADCPSSI ADCSAC ADCSSMUX0 ADCSSCTL0 ADCSSFIFO0 ADCSSFSTAT0 ADCSSMUX1 ADCSSCTL1 ADCSSFIFO1 ADCSSFSTAT1 ADCSSMUX2 ADCSSCTL2 ADCSSFIFO2 ADCSSFSTAT2 ADCSSMUX3 Type R/W RO R/W R/W1C R/W1C R/W R/W1C R/W WO R/W R/W R/W RO RO R/W R/W RO RO R/W R/W RO RO R/W Reset 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.3210 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0100 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0100 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0100 0x0000.0000 Description ADC Active Sample Sequencer ADC Raw Interrupt Status ADC Interrupt Mask ADC Interrupt Status and Clear ADC Overflow Status ADC Event Multiplexer Select ADC Underflow Status ADC Sample Sequencer Priority ADC Processor Sample Sequence Initiate ADC Sample Averaging Control ADC Sample Sequence Input Multiplexer Select 0 ADC Sample Sequence Control 0 ADC Sample Sequence Result FIFO 0 ADC Sample Sequence FIFO 0 Status ADC Sample Sequence Input Multiplexer Select 1 ADC Sample Sequence Control 1 ADC Sample Sequence Result FIFO 1 ADC Sample Sequence FIFO 1 Status ADC Sample Sequence Input Multiplexer Select 2 ADC Sample Sequence Control 2 ADC Sample Sequence Result FIFO 2 ADC Sample Sequence FIFO 2 Status ADC Sample Sequence Input Multiplexer Select 3 See page 270 271 272 273 274 275 278 279 280 281 282 284 287 288 289 290 287 288 289 290 287 288 292 268 Preliminary November 30, 2007 LM3S6965 Microcontroller Offset 0x0A4 0x0A8 0x0AC 0x100 Name ADCSSCTL3 ADCSSFIFO3 ADCSSFSTAT3 ADCTMLB Type R/W RO RO R/W Reset 0x0000.0002 0x0000.0000 0x0000.0100 0x0000.0000 Description ADC Sample Sequence Control 3 ADC Sample Sequence Result FIFO 3 ADC Sample Sequence FIFO 3 Status ADC Test Mode Loopback See page 293 287 288 294 12.5 Register Descriptions The remainder of this section lists and describes the ADC registers, in numerical order by address offset. November 30, 2007 Preliminary 269 Analog-to-Digital Converter (ADC) Register 1: ADC Active Sample Sequencer (ADCACTSS), offset 0x000 This register controls the activation of the Sample Sequencers. Each Sample Sequencer can be enabled/disabled independently. ADC Active Sample Sequencer (ADCACTSS) Base 0x4003.8000 Offset 0x000 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 ASEN3 R/W 0 RO 0 2 ASEN2 R/W 0 RO 0 1 ASEN1 R/W 0 RO 0 0 ASEN0 R/W 0 Bit/Field 31:4 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. ADC SS3 Enable Specifies whether Sample Sequencer 3 is enabled. If set, the sample sequence logic for Sequencer 3 is active. Otherwise, the Sequencer is inactive. 3 ASEN3 R/W 0 2 ASEN2 R/W 0 ADC SS2 Enable Specifies whether Sample Sequencer 2 is enabled. If set, the sample sequence logic for Sequencer 2 is active. Otherwise, the Sequencer is inactive. 1 ASEN1 R/W 0 ADC SS1 Enable Specifies whether Sample Sequencer 1 is enabled. If set, the sample sequence logic for Sequencer 1 is active. Otherwise, the Sequencer is inactive. 0 ASEN0 R/W 0 ADC SS0 Enable Specifies whether Sample Sequencer 0 is enabled. If set, the sample sequence logic for Sequencer 0 is active. Otherwise, the Sequencer is inactive. 270 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 2: ADC Raw Interrupt Status (ADCRIS), offset 0x004 This register shows the status of the raw interrupt signal of each Sample Sequencer. These bits may be polled by software to look for interrupt conditions without having to generate controller interrupts. ADC Raw Interrupt Status (ADCRIS) Base 0x4003.8000 Offset 0x004 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 INR3 RO 0 RO 0 2 INR2 RO 0 RO 0 1 INR1 RO 0 RO 0 0 INR0 RO 0 Bit/Field 31:4 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SS3 Raw Interrupt Status Set by hardware when a sample with its respective ADCSSCTL3 IE bit has completed conversion. This bit is cleared by writing a 1 to the ADCISC IN3 bit. 3 INR3 RO 0 2 INR2 RO 0 SS2 Raw Interrupt Status Set by hardware when a sample with its respective ADCSSCTL2 IE bit has completed conversion. This bit is cleared by writing a 1 to the ADCISC IN2 bit. 1 INR1 RO 0 SS1 Raw Interrupt Status Set by hardware when a sample with its respective ADCSSCTL1 IE bit has completed conversion. This bit is cleared by writing a 1 to the ADCISC IN1 bit. 0 INR0 RO 0 SS0 Raw Interrupt Status Set by hardware when a sample with its respective ADCSSCTL0 IE bit has completed conversion. This bit is cleared by writing a 1 to the ADCISC IN0 bit. November 30, 2007 Preliminary 271 Analog-to-Digital Converter (ADC) Register 3: ADC Interrupt Mask (ADCIM), offset 0x008 This register controls whether the Sample Sequencer raw interrupt signals are promoted to controller interrupts. The raw interrupt signal for each Sample Sequencer can be masked independently. ADC Interrupt Mask (ADCIM) Base 0x4003.8000 Offset 0x008 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 MASK3 R/W 0 RO 0 2 MASK2 R/W 0 RO 0 1 MASK1 R/W 0 RO 0 0 MASK0 R/W 0 Bit/Field 31:4 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SS3 Interrupt Mask Specifies whether the raw interrupt signal from Sample Sequencer 3 (ADCRIS register INR3 bit) is promoted to a controller interrupt. If set, the raw interrupt signal is promoted to a controller interrupt. Otherwise, it is not. 3 MASK3 R/W 0 2 MASK2 R/W 0 SS2 Interrupt Mask Specifies whether the raw interrupt signal from Sample Sequencer 2 (ADCRIS register INR2 bit) is promoted to a controller interrupt. If set, the raw interrupt signal is promoted to a controller interrupt. Otherwise, it is not. 1 MASK1 R/W 0 SS1 Interrupt Mask Specifies whether the raw interrupt signal from Sample Sequencer 1 (ADCRIS register INR1 bit) is promoted to a controller interrupt. If set, the raw interrupt signal is promoted to a controller interrupt. Otherwise, it is not. 0 MASK0 R/W 0 SS0 Interrupt Mask Specifies whether the raw interrupt signal from Sample Sequencer 0 (ADCRIS register INR0 bit) is promoted to a controller interrupt. If set, the raw interrupt signal is promoted to a controller interrupt. Otherwise, it is not. 272 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 4: ADC Interrupt Status and Clear (ADCISC), offset 0x00C This register provides the mechanism for clearing interrupt conditions, and shows the status of controller interrupts generated by the Sample Sequencers. When read, each bit field is the logical AND of the respective INR and MASK bits. Interrupts are cleared by writing a 1 to the corresponding bit position. If software is polling the ADCRIS instead of generating interrupts, the INR bits are still cleared via the ADCISC register, even if the IN bit is not set. ADC Interrupt Status and Clear (ADCISC) Base 0x4003.8000 Offset 0x00C Type R/W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 IN3 R/W1C 0 RO 0 2 IN2 R/W1C 0 RO 0 1 IN1 R/W1C 0 RO 0 0 IN0 R/W1C 0 Bit/Field 31:4 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SS3 Interrupt Status and Clear This bit is set by hardware when the MASK3 and INR3 bits are both 1, providing a level-based interrupt to the controller. It is cleared by writing a 1, and also clears the INR3 bit. 3 IN3 R/W1C 0 2 IN2 R/W1C 0 SS2 Interrupt Status and Clear This bit is set by hardware when the MASK2 and INR2 bits are both 1, providing a level based interrupt to the controller. It is cleared by writing a 1, and also clears the INR2 bit. 1 IN1 R/W1C 0 SS1 Interrupt Status and Clear This bit is set by hardware when the MASK1 and INR1 bits are both 1, providing a level based interrupt to the controller. It is cleared by writing a 1, and also clears the INR1 bit. 0 IN0 R/W1C 0 SS0 Interrupt Status and Clear This bit is set by hardware when the MASK0 and INR0 bits are both 1, providing a level based interrupt to the controller. It is cleared by writing a 1, and also clears the INR0 bit. November 30, 2007 Preliminary 273 Analog-to-Digital Converter (ADC) Register 5: ADC Overflow Status (ADCOSTAT), offset 0x010 This register indicates overflow conditions in the Sample Sequencer FIFOs. Once the overflow condition has been handled by software, the condition can be cleared by writing a 1 to the corresponding bit position. ADC Overflow Status (ADCOSTAT) Base 0x4003.8000 Offset 0x010 Type R/W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 OV3 R/W1C 0 RO 0 2 OV2 R/W1C 0 RO 0 1 OV1 R/W1C 0 RO 0 0 OV0 R/W1C 0 Bit/Field 31:4 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SS3 FIFO Overflow This bit specifies that the FIFO for Sample Sequencer 3 has hit an overflow condition where the FIFO is full and a write was requested. When an overflow is detected, the most recent write is dropped and this bit is set by hardware to indicate the occurrence of dropped data. This bit is cleared by writing a 1. 3 OV3 R/W1C 0 2 OV2 R/W1C 0 SS2 FIFO Overflow This bit specifies that the FIFO for Sample Sequencer 2 has hit an overflow condition where the FIFO is full and a write was requested. When an overflow is detected, the most recent write is dropped and this bit is set by hardware to indicate the occurrence of dropped data. This bit is cleared by writing a 1. 1 OV1 R/W1C 0 SS1 FIFO Overflow This bit specifies that the FIFO for Sample Sequencer 1 has hit an overflow condition where the FIFO is full and a write was requested. When an overflow is detected, the most recent write is dropped and this bit is set by hardware to indicate the occurrence of dropped data. This bit is cleared by writing a 1. 0 OV0 R/W1C 0 SS0 FIFO Overflow This bit specifies that the FIFO for Sample Sequencer 0 has hit an overflow condition where the FIFO is full and a write was requested. When an overflow is detected, the most recent write is dropped and this bit is set by hardware to indicate the occurrence of dropped data. This bit is cleared by writing a 1. 274 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 6: ADC Event Multiplexer Select (ADCEMUX), offset 0x014 The ADCEMUX selects the event (trigger) that initiates sampling for each Sample Sequencer. Each Sample Sequencer can be configured with a unique trigger source. ADC Event Multiplexer Select (ADCEMUX) Base 0x4003.8000 Offset 0x014 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 EM3 Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 RO 0 13 RO 0 12 RO 0 11 RO 0 10 EM2 R/W 0 R/W 0 R/W 0 R/W 0 RO 0 9 RO 0 8 RO 0 7 RO 0 6 EM1 R/W 0 R/W 0 R/W 0 R/W 0 RO 0 5 RO 0 4 RO 0 3 RO 0 2 EM0 R/W 0 R/W 0 RO 0 1 RO 0 0 Bit/Field 31:16 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SS3 Trigger Select This field selects the trigger source for Sample Sequencer 3. The valid configurations for this field are: Value 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 Event Controller (default) Analog Comparator 0 Analog Comparator 1 Reserved External (GPIO PB4) Timer PWM0 PWM1 PWM2 15:12 EM3 R/W 0x00 0x9-0xE reserved 0xF Always (continuously sample) November 30, 2007 Preliminary 275 Analog-to-Digital Converter (ADC) Bit/Field 11:8 Name EM2 Type R/W Reset 0x00 Description SS2 Trigger Select This field selects the trigger source for Sample Sequencer 2. The valid configurations for this field are: Value 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 Event Controller (default) Analog Comparator 0 Analog Comparator 1 Reserved External (GPIO PB4) Timer PWM0 PWM1 PWM2 0x9-0xE reserved 0xF Always (continuously sample) 7:4 EM1 R/W 0x00 SS1 Trigger Select This field selects the trigger source for Sample Sequencer 1. The valid configurations for this field are: Value 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 Event Controller (default) Analog Comparator 0 Analog Comparator 1 Reserved External (GPIO PB4) Timer PWM0 PWM1 PWM2 0x9-0xE reserved 0xF Always (continuously sample) 276 Preliminary November 30, 2007 LM3S6965 Microcontroller Bit/Field 3:0 Name EM0 Type R/W Reset 0x00 Description SS0 Trigger Select This field selects the trigger source for Sample Sequencer 0. The valid configurations for this field are: Value 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 Event Controller (default) Analog Comparator 0 Analog Comparator 1 Reserved External (GPIO PB4) Timer PWM0 PWM1 PWM2 0x9-0xE reserved 0xF Always (continuously sample) November 30, 2007 Preliminary 277 Analog-to-Digital Converter (ADC) Register 7: ADC Underflow Status (ADCUSTAT), offset 0x018 This register indicates underflow conditions in the Sample Sequencer FIFOs. The corresponding underflow condition can be cleared by writing a 1 to the relevant bit position. ADC Underflow Status (ADCUSTAT) Base 0x4003.8000 Offset 0x018 Type R/W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 UV3 R/W1C 0 RO 0 2 UV2 R/W1C 0 RO 0 1 UV1 R/W1C 0 RO 0 0 UV0 R/W1C 0 Bit/Field 31:4 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SS3 FIFO Underflow This bit specifies that the FIFO for Sample Sequencer 3 has hit an underflow condition where the FIFO is empty and a read was requested. The problematic read does not move the FIFO pointers, and 0s are returned. This bit is cleared by writing a 1. 3 UV3 R/W1C 0 2 UV2 R/W1C 0 SS2 FIFO Underflow This bit specifies that the FIFO for Sample Sequencer 2 has hit an underflow condition where the FIFO is empty and a read was requested. The problematic read does not move the FIFO pointers, and 0s are returned. This bit is cleared by writing a 1. 1 UV1 R/W1C 0 SS1 FIFO Underflow This bit specifies that the FIFO for Sample Sequencer 1 has hit an underflow condition where the FIFO is empty and a read was requested. The problematic read does not move the FIFO pointers, and 0s are returned. This bit is cleared by writing a 1. 0 UV0 R/W1C 0 SS0 FIFO Underflow This bit specifies that the FIFO for Sample Sequencer 0 has hit an underflow condition where the FIFO is empty and a read was requested. The problematic read does not move the FIFO pointers, and 0s are returned. This bit is cleared by writing a 1. 278 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 8: ADC Sample Sequencer Priority (ADCSSPRI), offset 0x020 This register sets the priority for each of the Sample Sequencers. Out of reset, Sequencer 0 has the highest priority, and sample sequence 3 has the lowest priority. When reconfiguring sequence priorities, each sequence must have a unique priority or the ADC behavior is inconsistent. ADC Sample Sequencer Priority (ADCSSPRI) Base 0x4003.8000 Offset 0x020 Type R/W, reset 0x0000.3210 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 SS3 R/W 1 R/W 1 RO 0 12 RO 0 11 RO 0 10 RO 0 9 SS2 R/W 1 R/W 0 RO 0 8 RO 0 7 reserved RO 0 RO 0 R/W 0 RO 0 6 RO 0 5 SS1 R/W 1 RO 0 4 RO 0 3 reserved RO 0 RO 0 R/W 0 RO 0 2 RO 0 1 SS0 R/W 0 RO 0 0 reserved Type Reset RO 0 RO 0 reserved RO 0 RO 0 Bit/Field 31:14 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SS3 Priority The SS3 field contains a binary-encoded value that specifies the priority encoding of Sample Sequencer 3. A priority encoding of 0 is highest and 3 is lowest. The priorities assigned to the Sequencers must be uniquely mapped. ADC behavior is not consistent if two or more fields are equal. 13:12 SS3 R/W 0x3 11:10 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SS2 Priority The SS2 field contains a binary-encoded value that specifies the priority encoding of Sample Sequencer 2. 9:8 SS2 R/W 0x2 7:6 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SS1 Priority The SS1 field contains a binary-encoded value that specifies the priority encoding of Sample Sequencer 1. 5:4 SS1 R/W 0x1 3:2 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SS0 Priority The SS0 field contains a binary-encoded value that specifies the priority encoding of Sample Sequencer 0. 1:0 SS0 R/W 0x0 November 30, 2007 Preliminary 279 Analog-to-Digital Converter (ADC) Register 9: ADC Processor Sample Sequence Initiate (ADCPSSI), offset 0x028 This register provides a mechanism for application software to initiate sampling in the Sample Sequencers. Sample sequences can be initiated individually or in any combination. When multiple sequences are triggered simultaneously, the priority encodings in ADCSSPRI dictate execution order. ADC Processor Sample Sequence Initiate (ADCPSSI) Base 0x4003.8000 Offset 0x028 Type WO, reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset WO 15 WO 14 WO 13 WO 12 WO 11 WO 10 reserved Type Reset WO WO WO WO WO WO WO WO WO WO WO WO WO 9 WO 8 WO 7 WO 6 WO 5 WO 4 WO 3 SS3 WO WO 2 SS2 WO WO 1 SS1 WO WO 0 SS0 WO - Bit/Field 31:4 Name reserved Type WO Reset - Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SS3 Initiate Only a write by software is valid; a read of the register returns no meaningful data. When set by software, sampling is triggered on Sample Sequencer 3, assuming the Sequencer is enabled in the ADCACTSS register. 3 SS3 WO - 2 SS2 WO - SS2 Initiate Only a write by software is valid; a read of the register returns no meaningful data. When set by software, sampling is triggered on Sample Sequencer 2, assuming the Sequencer is enabled in the ADCACTSS register. 1 SS1 WO - SS1 Initiate Only a write by software is valid; a read of the register returns no meaningful data. When set by software, sampling is triggered on Sample Sequencer 1, assuming the Sequencer is enabled in the ADCACTSS register. 0 SS0 WO - SS0 Initiate Only a write by software is valid; a read of the register returns no meaningful data. When set by software, sampling is triggered on Sample Sequencer 0, assuming the Sequencer is enabled in the ADCACTSS register. 280 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 10: ADC Sample Averaging Control (ADCSAC), offset 0x030 This register controls the amount of hardware averaging applied to conversion results. The final conversion result stored in the FIFO is averaged from 2 AVG consecutive ADC samples at the specified ADC speed. If AVG is 0, the sample is passed directly through without any averaging. If AVG=6, then 64 consecutive ADC samples are averaged to generate one result in the sequencer FIFO. An AVG = 7 provides unpredictable results. ADC Sample Averaging Control (ADCSAC) Base 0x4003.8000 Offset 0x030 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 AVG R/W 0 R/W 0 RO 0 0 Bit/Field 31:3 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Hardware Averaging Control Specifies the amount of hardware averaging that will be applied to ADC samples. The AVG field can be any value between 0 and 6. Entering a value of 7 creates unpredictable results. Value Description 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 No hardware oversampling 2x hardware oversampling 4x hardware oversampling 8x hardware oversampling 16x hardware oversampling 32x hardware oversampling 64x hardware oversampling Reserved 2:0 AVG R/W 0x0 November 30, 2007 Preliminary 281 Analog-to-Digital Converter (ADC) Register 11: ADC Sample Sequence Input Multiplexer Select 0 (ADCSSMUX0), offset 0x040 This register defines the analog input configuration for each sample in a sequence executed with Sample Sequencer 0. This register is 32-bits wide and contains information for eight possible samples. ADC Sample Sequence Input Multiplexer Select 0 (ADCSSMUX0) Base 0x4003.8000 Offset 0x040 Type R/W, reset 0x0000.0000 31 30 29 MUX7 R/W 0 13 MUX3 R/W 0 R/W 0 R/W 0 12 28 27 26 25 MUX6 R/W 0 9 MUX2 R/W 0 R/W 0 R/W 0 8 24 23 22 21 MUX5 R/W 0 5 MUX1 R/W 0 R/W 0 R/W 0 4 20 19 18 17 MUX4 R/W 0 1 MUX0 R/W 0 R/W 0 R/W 0 0 16 reserved Type Reset RO 0 15 RO 0 14 reserved RO 0 11 RO 0 10 reserved RO 0 7 reserved RO 0 RO 0 RO 0 6 reserved RO 0 3 reserved RO 0 RO 0 RO 0 2 reserved Type Reset RO 0 RO 0 reserved RO 0 RO 0 Bit/Field 31:30 Name reserved Type RO Reset 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 8th Sample Input Select The MUX7 field is used during the eighth sample of a sequence executed with the Sample Sequencer. It specifies which of the analog inputs is sampled for the analog-to-digital conversion. The value set here indicates the corresponding pin, for example, a value of 1 indicates the input is ADC1. 29:28 MUX7 R/W 0 27:26 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7th Sample Input Select The MUX6 field is used during the seventh sample of a sequence executed with the Sample Sequencer and specifies which of the analog inputs is sampled for the analog-to-digital conversion. 25:24 MUX6 R/W 0 23:22 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 6th Sample Input Select The MUX5 field is used during the sixth sample of a sequence executed with the Sample Sequencer and specifies which of the analog inputs is sampled for the analog-to-digital conversion. 21:20 MUX5 R/W 0 19:18 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 282 Preliminary November 30, 2007 LM3S6965 Microcontroller Bit/Field 17:16 Name MUX4 Type R/W Reset 0 Description 5th Sample Input Select The MUX4 field is used during the fifth sample of a sequence executed with the Sample Sequencer and specifies which of the analog inputs is sampled for the analog-to-digital conversion. 15:14 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 4th Sample Input Select The MUX3 field is used during the fourth sample of a sequence executed with the Sample Sequencer and specifies which of the analog inputs is sampled for the analog-to-digital conversion. 13:12 MUX3 R/W 0 11:10 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3rd Sample Input Select The MUX2 field is used during the third sample of a sequence executed with the Sample Sequencer and specifies which of the analog inputs is sampled for the analog-to-digital conversion. 9:8 MUX2 R/W 0 7:6 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 2nd Sample Input Select The MUX1 field is used during the second sample of a sequence executed with the Sample Sequencer and specifies which of the analog inputs is sampled for the analog-to-digital conversion. 5:4 MUX1 R/W 0 3:2 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 1st Sample Input Select The MUX0 field is used during the first sample of a sequence executed with the Sample Sequencer and specifies which of the analog inputs is sampled for the analog-to-digital conversion. 1:0 MUX0 R/W 0 November 30, 2007 Preliminary 283 Analog-to-Digital Converter (ADC) Register 12: ADC Sample Sequence Control 0 (ADCSSCTL0), offset 0x044 This register contains the configuration information for each sample for a sequence executed with Sample Sequencer 0. When configuring a sample sequence, the END bit must be set at some point, whether it be after the first sample, last sample, or any sample in between. This register is 32-bits wide and contains information for eight possible samples. ADC Sample Sequence Control 0 (ADCSSCTL0) Base 0x4003.8000 Offset 0x044 Type R/W, reset 0x0000.0000 31 TS7 Type Reset R/W 0 15 TS3 Type Reset R/W 0 30 IE7 R/W 0 14 IE3 R/W 0 29 END7 R/W 0 13 END3 R/W 0 28 D7 R/W 0 12 D3 R/W 0 27 TS6 R/W 0 11 TS2 R/W 0 26 IE6 R/W 0 10 IE2 R/W 0 25 END6 R/W 0 9 END2 R/W 0 24 D6 R/W 0 8 D2 R/W 0 23 TS5 R/W 0 7 TS1 R/W 0 22 IE5 R/W 0 6 IE1 R/W 0 21 END5 R/W 0 5 END1 R/W 0 20 D5 R/W 0 4 D1 R/W 0 19 TS4 R/W 0 3 TS0 R/W 0 18 IE4 R/W 0 2 IE0 R/W 0 17 END4 R/W 0 1 END0 R/W 0 16 D4 R/W 0 0 D0 R/W 0 Bit/Field 31 Name TS7 Type R/W Reset 0 Description 8th Sample Temp Sensor Select The TS7 bit is used during the eighth sample of the sample sequence and specifies the input source of the sample. If set, the temperature sensor is read. Otherwise, the input pin specified by the ADCSSMUX register is read. 30 IE7 R/W 0 8th Sample Interrupt Enable The IE7 bit is used during the eighth sample of the sample sequence and specifies whether the raw interrupt signal (INR0 bit) is asserted at the end of the sample's conversion. If the MASK0 bit in the ADCIM register is set, the interrupt is promoted to a controller-level interrupt. When this bit is set, the raw interrupt is asserted, otherwise it is not. It is legal to have multiple samples within a sequence generate interrupts. 29 END7 R/W 0 8th Sample is End of Sequence The END7 bit indicates that this is the last sample of the sequence. It is possible to end the sequence on any sample position. Samples defined after the sample containing a set END are not requested for conversion even though the fields may be non-zero. It is required that software write the END bit somewhere within the sequence. (Sample Sequencer 3, which only has a single sample in the sequence, is hardwired to have the END0 bit set.) Setting this bit indicates that this sample is the last in the sequence. 28 D7 R/W 0 8th Sample Diff Input Select The D7 bit indicates that the analog input is to be differentially sampled. The corresponding ADCSSMUXx nibble must be set to the pair number "i", where the paired inputs are "2i and 2i+1". The temperature sensor does not have a differential option. When set, the analog inputs are differentially sampled. 27 TS6 R/W 0 7th Sample Temp Sensor Select Same definition as TS7 but used during the seventh sample. 284 Preliminary November 30, 2007 LM3S6965 Microcontroller Bit/Field 26 Name IE6 Type R/W Reset 0 Description 7th Sample Interrupt Enable Same definition as IE7 but used during the seventh sample. 25 END6 R/W 0 7th Sample is End of Sequence Same definition as END7 but used during the seventh sample. 24 D6 R/W 0 7th Sample Diff Input Select Same definition as D7 but used during the seventh sample. 23 TS5 R/W 0 6th Sample Temp Sensor Select Same definition as TS7 but used during the sixth sample. 22 IE5 R/W 0 6th Sample Interrupt Enable Same definition as IE7 but used during the sixth sample. 21 END5 R/W 0 6th Sample is End of Sequence Same definition as END7 but used during the sixth sample. 20 D5 R/W 0 6th Sample Diff Input Select Same definition as D7 but used during the sixth sample. 19 TS4 R/W 0 5th Sample Temp Sensor Select Same definition as TS7 but used during the fifth sample. 18 IE4 R/W 0 5th Sample Interrupt Enable Same definition as IE7 but used during the fifth sample. 17 END4 R/W 0 5th Sample is End of Sequence Same definition as END7 but used during the fifth sample. 16 D4 R/W 0 5th Sample Diff Input Select Same definition as D7 but used during the fifth sample. 15 TS3 R/W 0 4th Sample Temp Sensor Select Same definition as TS7 but used during the fourth sample. 14 IE3 R/W 0 4th Sample Interrupt Enable Same definition as IE7 but used during the fourth sample. 13 END3 R/W 0 4th Sample is End of Sequence Same definition as END7 but used during the fourth sample. 12 D3 R/W 0 4th Sample Diff Input Select Same definition as D7 but used during the fourth sample. 11 TS2 R/W 0 3rd Sample Temp Sensor Select Same definition as TS7 but used during the third sample. November 30, 2007 Preliminary 285 Analog-to-Digital Converter (ADC) Bit/Field 10 Name IE2 Type R/W Reset 0 Description 3rd Sample Interrupt Enable Same definition as IE7 but used during the third sample. 9 END2 R/W 0 3rd Sample is End of Sequence Same definition as END7 but used during the third sample. 8 D2 R/W 0 3rd Sample Diff Input Select Same definition as D7 but used during the third sample. 7 TS1 R/W 0 2nd Sample Temp Sensor Select Same definition as TS7 but used during the second sample. 6 IE1 R/W 0 2nd Sample Interrupt Enable Same definition as IE7 but used during the second sample. 5 END1 R/W 0 2nd Sample is End of Sequence Same definition as END7 but used during the second sample. 4 D1 R/W 0 2nd Sample Diff Input Select Same definition as D7 but used during the second sample. 3 TS0 R/W 0 1st Sample Temp Sensor Select Same definition as TS7 but used during the first sample. 2 IE0 R/W 0 1st Sample Interrupt Enable Same definition as IE7 but used during the first sample. 1 END0 R/W 0 1st Sample is End of Sequence Same definition as END7 but used during the first sample. Since this sequencer has only one entry, this bit must be set. 0 D0 R/W 0 1st Sample Diff Input Select Same definition as D7 but used during the first sample. 286 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 13: ADC Sample Sequence Result FIFO 0 (ADCSSFIFO0), offset 0x048 Register 14: ADC Sample Sequence Result FIFO 1 (ADCSSFIFO1), offset 0x068 Register 15: ADC Sample Sequence Result FIFO 2 (ADCSSFIFO2), offset 0x088 Register 16: ADC Sample Sequence Result FIFO 3 (ADCSSFIFO3), offset 0x0A8 This register contains the conversion results for samples collected with the Sample Sequencer (the ADCSSFIFO0 register is used for Sample Sequencer 0, ADCSSFIFO1 for Sequencer 1, ADCSSFIFO2 for Sequencer 2, and ADCSSFIFO3 for Sequencer 3). Reads of this register return conversion result data in the order sample 0, sample 1, and so on, until the FIFO is empty. If the FIFO is not properly handled by software, overflow and underflow conditions are registered in the ADCOSTAT and ADCUSTAT registers. ADC Sample Sequence Result FIFO 0 (ADCSSFIFO0) Base 0x4003.8000 Offset 0x048 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 DATA RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 Bit/Field 31:10 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Conversion Result Data 9:0 DATA RO 0x00 November 30, 2007 Preliminary 287 Analog-to-Digital Converter (ADC) Register 17: ADC Sample Sequence FIFO 0 Status (ADCSSFSTAT0), offset 0x04C Register 18: ADC Sample Sequence FIFO 1 Status (ADCSSFSTAT1), offset 0x06C Register 19: ADC Sample Sequence FIFO 2 Status (ADCSSFSTAT2), offset 0x08C Register 20: ADC Sample Sequence FIFO 3 Status (ADCSSFSTAT3), offset 0x0AC This register provides a window into the Sample Sequencer, providing full/empty status information as well as the positions of the head and tail pointers. The reset value of 0x100 indicates an empty FIFO. The ADCSSFSTAT0 register provides status on FIF0, ADCSSFSTAT1 on FIFO1, ADCSSFSTAT2 on FIFO2, and ADCSSFSTAT3 on FIFO3. ADC Sample Sequence FIFO 0 Status (ADCSSFSTAT0) Base 0x4003.8000 Offset 0x04C Type RO, reset 0x0000.0100 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 reserved Type Reset RO 0 RO 0 RO 0 RO 0 13 RO 0 12 FULL RO 0 RO 0 RO 0 11 RO 0 10 reserved RO 0 RO 0 RO 0 9 RO 0 8 EMPTY RO 1 RO 0 RO 0 RO 0 7 RO 0 6 HPTR RO 0 RO 0 RO 0 RO 0 RO 0 5 RO 0 4 RO 0 3 RO 0 2 TPTR RO 0 RO 0 RO 0 1 RO 0 0 Bit/Field 31:13 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. FIFO Full When set, indicates that the FIFO is currently full. 12 FULL RO 0 11:9 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. FIFO Empty When set, indicates that the FIFO is currently empty. 8 EMPTY RO 1 7:4 HPTR RO 0x00 FIFO Head Pointer This field contains the current "head" pointer index for the FIFO, that is, the next entry to be written. 3:0 TPTR RO 0x00 FIFO Tail Pointer This field contains the current "tail" pointer index for the FIFO, that is, the next entry to be read. 288 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 21: ADC Sample Sequence Input Multiplexer Select 1 (ADCSSMUX1), offset 0x060 Register 22: ADC Sample Sequence Input Multiplexer Select 2 (ADCSSMUX2), offset 0x080 This register defines the analog input configuration for each sample in a sequence executed with Sample Sequencer 1 or 2. These registers are 16-bits wide and contain information for four possible samples. See the ADCSSMUX0 register on page 282 for detailed bit descriptions. ADC Sample Sequence Input Multiplexer Select 1 (ADCSSMUX1) Base 0x4003.8000 Offset 0x060 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 MUX3 R/W 0 R/W 0 RO 0 12 RO 0 11 RO 0 10 RO 0 9 MUX2 R/W 0 R/W 0 RO 0 8 RO 0 7 reserved RO 0 RO 0 R/W 0 RO 0 6 RO 0 5 MUX1 R/W 0 RO 0 4 RO 0 3 reserved RO 0 RO 0 R/W 0 RO 0 2 RO 0 1 MUX0 R/W 0 RO 0 0 reserved Type Reset RO 0 RO 0 reserved RO 0 RO 0 Bit/Field 31:14 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 4th Sample Input Select Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 3rd Sample Input Select Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 2nd Sample Input Select Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 1st Sample Input Select 13:12 11:10 MUX3 reserved R/W RO 0 0 9:8 7:6 MUX2 reserved R/W RO 0 0 5:4 3:2 MUX1 reserved R/W RO 0 0 1:0 MUX0 R/W 0 November 30, 2007 Preliminary 289 Analog-to-Digital Converter (ADC) Register 23: ADC Sample Sequence Control 1 (ADCSSCTL1), offset 0x064 Register 24: ADC Sample Sequence Control 2 (ADCSSCTL2), offset 0x084 These registers contain the configuration information for each sample for a sequence executed with Sample Sequencer 1 or 2. When configuring a sample sequence, the END bit must be set at some point, whether it be after the first sample, last sample, or any sample in between. This register is 16-bits wide and contains information for four possible samples. See the ADCSSCTL0 register on page 284 for detailed bit descriptions. ADC Sample Sequence Control 1 (ADCSSCTL1) Base 0x4003.8000 Offset 0x064 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 TS3 Type Reset R/W 0 RO 0 14 IE3 R/W 0 RO 0 13 END3 R/W 0 RO 0 12 D3 R/W 0 RO 0 11 TS2 R/W 0 RO 0 10 IE2 R/W 0 RO 0 9 END2 R/W 0 RO 0 8 D2 R/W 0 RO 0 7 TS1 R/W 0 RO 0 6 IE1 R/W 0 RO 0 5 END1 R/W 0 RO 0 4 D1 R/W 0 RO 0 3 TS0 R/W 0 RO 0 2 IE0 R/W 0 RO 0 1 END0 R/W 0 RO 0 0 D0 R/W 0 Bit/Field 31:16 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 4th Sample Temp Sensor Select Same definition as TS7 but used during the fourth sample. 15 TS3 R/W 0 14 IE3 R/W 0 4th Sample Interrupt Enable Same definition as IE7 but used during the fourth sample. 13 END3 R/W 0 4th Sample is End of Sequence Same definition as END7 but used during the fourth sample. 12 D3 R/W 0 4th Sample Diff Input Select Same definition as D7 but used during the fourth sample. 11 TS2 R/W 0 3rd Sample Temp Sensor Select Same definition as TS7 but used during the third sample. 10 IE2 R/W 0 3rd Sample Interrupt Enable Same definition as IE7 but used during the third sample. 9 END2 R/W 0 3rd Sample is End of Sequence Same definition as END7 but used during the third sample. 8 D2 R/W 0 3rd Sample Diff Input Select Same definition as D7 but used during the third sample. 290 Preliminary November 30, 2007 LM3S6965 Microcontroller Bit/Field 7 Name TS1 Type R/W Reset 0 Description 2nd Sample Temp Sensor Select Same definition as TS7 but used during the second sample. 6 IE1 R/W 0 2nd Sample Interrupt Enable Same definition as IE7 but used during the second sample. 5 END1 R/W 0 2nd Sample is End of Sequence Same definition as END7 but used during the second sample. 4 D1 R/W 0 2nd Sample Diff Input Select Same definition as D7 but used during the second sample. 3 TS0 R/W 0 1st Sample Temp Sensor Select Same definition as TS7 but used during the first sample. 2 IE0 R/W 0 1st Sample Interrupt Enable Same definition as IE7 but used during the first sample. 1 END0 R/W 0 1st Sample is End of Sequence Same definition as END7 but used during the first sample. Since this sequencer has only one entry, this bit must be set. 0 D0 R/W 0 1st Sample Diff Input Select Same definition as D7 but used during the first sample. November 30, 2007 Preliminary 291 Analog-to-Digital Converter (ADC) Register 25: ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3), offset 0x0A0 This register defines the analog input configuration for each sample in a sequence executed with Sample Sequencer 3. This register is 4-bits wide and contains information for one possible sample. See the ADCSSMUX0 register on page 282 for detailed bit descriptions. ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3) Base 0x4003.8000 Offset 0x0A0 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 MUX0 R/W 0 RO 0 0 Bit/Field 31:2 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 1st Sample Input Select 1:0 MUX0 R/W 0 292 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 26: ADC Sample Sequence Control 3 (ADCSSCTL3), offset 0x0A4 This register contains the configuration information for each sample for a sequence executed with Sample Sequencer 3. The END bit is always set since there is only one sample in this sequencer. This register is 4-bits wide and contains information for one possible sample. See the ADCSSCTL0 register on page 284 for detailed bit descriptions. ADC Sample Sequence Control 3 (ADCSSCTL3) Base 0x4003.8000 Offset 0x0A4 Type R/W, reset 0x0000.0002 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 TS0 R/W 0 RO 0 2 IE0 R/W 0 RO 0 1 END0 R/W 1 RO 0 0 D0 R/W 0 Bit/Field 31:4 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 1st Sample Temp Sensor Select Same definition as TS7 but used during the first sample. 3 TS0 R/W 0 2 IE0 R/W 0 1st Sample Interrupt Enable Same definition as IE7 but used during the first sample. 1 END0 R/W 1 1st Sample is End of Sequence Same definition as END7 but used during the first sample. Since this sequencer has only one entry, this bit must be set. 0 D0 R/W 0 1st Sample Diff Input Select Same definition as D7 but used during the first sample. November 30, 2007 Preliminary 293 Analog-to-Digital Converter (ADC) Register 27: ADC Test Mode Loopback (ADCTMLB), offset 0x100 This register provides loopback operation within the digital logic of the ADC, which can be useful in debugging software without having to provide actual analog stimulus. This test mode is entered by writing a value of 0x0000.0001 to this register. When data is read from the FIFO in loopback mode, the read-only portion of this register is returned. Read-Only Register ADC Test Mode Loopback (ADCTMLB) Base 0x4003.8000 Offset 0x100 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 CNT RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 RO 0 6 RO 0 5 CONT RO 0 RO 0 4 DIFF RO 0 RO 0 3 TS RO 0 RO 0 RO 0 2 RO 0 1 MUX RO 0 RO 0 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 Bit/Field 31:10 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Continuous Sample Counter Continuous sample counter that is initialized to 0 and counts each sample as it processed. This helps provide a unique value for the data received. 9:6 CNT RO 0x0 5 CONT RO 0 Continuation Sample Indicator When set, indicates that this is a continuation sample. For example, if two sequencers were to run back-to-back, this indicates that the controller kept continuously sampling at full rate. 4 DIFF RO 0 Differential Sample Indicator When set, indicates that this is a differential sample. 3 TS RO 0 Temp Sensor Sample Indicator When set, indicates that this is a temperature sensor sample. 2:0 MUX RO 0x0 Analog Input Indicator Indicates which analog input is to be sampled. 294 Preliminary November 30, 2007 LM3S6965 Microcontroller Write-Only Register ADC Test Mode Loopback (ADCTMLB) Base 0x4003.8000 Offset 0x100 Type WO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 LB WO 0 Bit/Field 31:1 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Loopback Mode Enable When set, forces a loopback within the digital block to provide information on input and unique numbering. The 10-bit loopback data is defined as shown in the read for bits 9:0 above. 0 LB WO 0 November 30, 2007 Preliminary 295 Universal Asynchronous Receivers/Transmitters (UARTs) 13 Universal Asynchronous Receivers/Transmitters (UARTs) The Stellaris Universal Asynchronous Receiver/Transmitter (UART) provides fully programmable, 16C550-type serial interface characteristics. The LM3S6965 controller is equipped with three UART modules. Each UART has the following features: ■ Separate transmit and receive FIFOs ■ Programmable FIFO length, including 1-byte deep operation providing conventional double-buffered interface ■ FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8 ■ Programmable baud-rate generator allowing rates up to 3.125 Mbps ■ Standard asynchronous communication bits for start, stop, and parity ■ False start bit detection ■ Line-break generation and detection ■ Fully programmable serial interface characteristics: – 5, 6, 7, or 8 data bits – Even, odd, stick, or no-parity bit generation/detection – 1 or 2 stop bit generation ■ IrDA serial-IR (SIR) encoder/decoder providing: – Programmable use of IrDA Serial InfraRed (SIR) or UART input/output – Support of IrDA SIR encoder/decoder functions for data rates up to 115.2 Kbps half-duplex – Support of normal 3/16 and low-power (1.41-2.23 μs) bit durations – Programmable internal clock generator enabling division of reference clock by 1 to 256 for low-power mode bit duration ® 296 Preliminary November 30, 2007 LM3S6965 Microcontroller 13.1 Block Diagram Figure 13-1. UART Module Block Diagram System Clock Interrupt Interrupt Control UARTIFLS UARTIM UARTMIS TXFIFO 16x8 . . . Transmitter Baud Rate Generator UARTIBRD UARTFBRD Receiver UnRx UnTx Identification Registers UARTPCellID0 UARTPCellID1 UARTPCellID2 UARTPCellID3 UARTPeriphID0 UARTPeriphID1 UARTPeriphID2 UARTPeriphID3 UART PeriphID4 UARTRIS UARTICR UARTDR Control / Status UARTRSR/ECR RXFIFO 16x8 UARTPeriphID5 UARTFR UARTPeriphID6 UARTLCRH UARTPeriphID7 UARTCTL UARTILPR . . . 13.2 Functional Description Each Stellaris UART performs the functions of parallel-to-serial and serial-to-parallel conversions. It is similar in functionality to a 16C550 UART, but is not register compatible. The UART is configured for transmit and/or receive via the TXE and RXE bits of the UART Control (UARTCTL) register (see page 315). Transmit and receive are both enabled out of reset. Before any control registers are programmed, the UART must be disabled by clearing the UARTEN bit in UARTCTL. If the UART is disabled during a TX or RX operation, the current transaction is completed prior to the UART stopping. The UART peripheral also includes a serial IR (SIR) encoder/decoder block that can be connected to an infrared transceiver to implement an IrDA SIR physical layer. The SIR function is programmed using the UARTCTL register. ® 13.2.1 Transmit/Receive Logic The transmit logic performs parallel-to-serial conversion on the data read from the transmit FIFO. The control logic outputs the serial bit stream beginning with a start bit, and followed by the data November 30, 2007 Preliminary 297 Universal Asynchronous Receivers/Transmitters (UARTs) bits (LSB first), parity bit, and the stop bits according to the programmed configuration in the control registers. See Figure 13-2 on page 298 for details. The receive logic performs serial-to-parallel conversion on the received bit stream after a valid start pulse has been detected. Overrun, parity, frame error checking, and line-break detection are also performed, and their status accompanies the data that is written to the receive FIFO. Figure 13-2. UART Character Frame UnTX 1 0 n Star t LSB 5-8 data bits Parity bit if enabled MSB 1-2 stop bits 13.2.2 Baud-Rate Generation The baud-rate divisor is a 22-bit number consisting of a 16-bit integer and a 6-bit fractional part. The number formed by these two values is used by the baud-rate generator to determine the bit period. Having a fractional baud-rate divider allows the UART to generate all the standard baud rates. The 16-bit integer is loaded through the UART Integer Baud-Rate Divisor (UARTIBRD) register (see page 311) and the 6-bit fractional part is loaded with the UART Fractional Baud-Rate Divisor (UARTFBRD) register (see page 312). The baud-rate divisor (BRD) has the following relationship to the system clock (where BRDI is the integer part of the BRD and BRDF is the fractional part, separated by a decimal place.): BRD = BRDI + BRDF = SysClk / (16 * Baud Rate) The 6-bit fractional number (that is to be loaded into the DIVFRAC bit field in the UARTFBRD register) can be calculated by taking the fractional part of the baud-rate divisor, multiplying it by 64, and adding 0.5 to account for rounding errors: UARTFBRD[DIVFRAC] = integer(BRDF * 64 + 0.5) The UART generates an internal baud-rate reference clock at 16x the baud-rate (referred to as Baud16). This reference clock is divided by 16 to generate the transmit clock, and is used for error detection during receive operations. Along with the UART Line Control, High Byte (UARTLCRH) register (see page 313), the UARTIBRD and UARTFBRD registers form an internal 30-bit register. This internal register is only updated when a write operation to UARTLCRH is performed, so any changes to the baud-rate divisor must be followed by a write to the UARTLCRH register for the changes to take effect. To update the baud-rate registers, there are four possible sequences: ■ UARTIBRD write, UARTFBRD write, and UARTLCRH write ■ UARTFBRD write, UARTIBRD write, and UARTLCRH write ■ UARTIBRD write and UARTLCRH write ■ UARTFBRD write and UARTLCRH write 298 Preliminary November 30, 2007 LM3S6965 Microcontroller 13.2.3 Data Transmission Data received or transmitted is stored in two 16-byte FIFOs, though the receive FIFO has an extra four bits per character for status information. For transmission, data is written into the transmit FIFO. If the UART is enabled, it causes a data frame to start transmitting with the parameters indicated in the UARTLCRH register. Data continues to be transmitted until there is no data left in the transmit FIFO. The BUSY bit in the UART Flag (UARTFR) register (see page 308) is asserted as soon as data is written to the transmit FIFO (that is, if the FIFO is non-empty) and remains asserted while data is being transmitted. The BUSY bit is negated only when the transmit FIFO is empty, and the last character has been transmitted from the shift register, including the stop bits. The UART can indicate that it is busy even though the UART may no longer be enabled. When the receiver is idle (the UnRx is continuously 1) and the data input goes Low (a start bit has been received), the receive counter begins running and data is sampled on the eighth cycle of Baud16 (described in “Transmit/Receive Logic” on page 297). The start bit is valid if UnRx is still low on the eighth cycle of Baud16, otherwise a false start bit is detected and it is ignored. Start bit errors can be viewed in the UART Receive Status (UARTRSR) register (see page 306). If the start bit was valid, successive data bits are sampled on every 16th cycle of Baud16 (that is, one bit period later) according to the programmed length of the data characters. The parity bit is then checked if parity mode was enabled. Data length and parity are defined in the UARTLCRH register. Lastly, a valid stop bit is confirmed if UnRx is High, otherwise a framing error has occurred. When a full word is received, the data is stored in the receive FIFO, with any error bits associated with that word. 13.2.4 Serial IR (SIR) The UART peripheral includes an IrDA serial-IR (SIR) encoder/decoder block. The IrDA SIR block provides functionality that converts between an asynchronous UART data stream, and half-duplex serial SIR interface. No analog processing is performed on-chip. The role of the SIR block is to provide a digital encoded output, and decoded input to the UART. The UART signal pins can be connected to an infrared transceiver to implement an IrDA SIR physical layer link. The SIR block has two modes of operation: ■ In normal IrDA mode, a zero logic level is transmitted as high pulse of 3/16th duration of the selected baud rate bit period on the output pin, while logic one levels are transmitted as a static LOW signal. These levels control the driver of an infrared transmitter, sending a pulse of light for each zero. On the reception side, the incoming light pulses energize the photo transistor base of the receiver, pulling its output LOW. This drives the UART input pin LOW. ■ In low-power IrDA mode, the width of the transmitted infrared pulse is set to three times the period of the internally generated IrLPBaud16 signal (1.63 µs, assuming a nominal 1.8432 MHz frequency) by changing the appropriate bit in the UARTCR register. Figure 13-3 on page 300 shows the UART transmit and receive signals, with and without IrDA modulation. November 30, 2007 Preliminary 299 Universal Asynchronous Receivers/Transmitters (UARTs) Figure 13-3. IrDA Data Modulation Start bit Data bits 0 Stop bit 0 1 1 0 1 UnTx UnTx with IrDA 0 1 0 1 Bit period 3 16 Bit period UnRx with IrDA UnRx 0 Start 1 0 1 0 Data bits 0 1 1 0 1 Stop In both normal and low-power IrDA modes: ■ During transmission, the UART data bit is used as the base for encoding ■ During reception, the decoded bits are transferred to the UART receive logic The IrDA SIR physical layer specifies a half-duplex communication link, with a minimum 10 ms delay between transmission and reception. This delay must be generated by software because it is not automatically supported by the UART. The delay is required because the infrared receiver electronics might become biased, or even saturated from the optical power coupled from the adjacent transmitter LED. This delay is known as latency, or receiver setup time. 13.2.5 FIFO Operation The UART has two 16-entry FIFOs; one for transmit and one for receive. Both FIFOs are accessed via the UART Data (UARTDR) register (see page 304). Read operations of the UARTDR register return a 12-bit value consisting of 8 data bits and 4 error flags while write operations place 8-bit data in the transmit FIFO. Out of reset, both FIFOs are disabled and act as 1-byte-deep holding registers. The FIFOs are enabled by setting the FEN bit in UARTLCRH (page 313). FIFO status can be monitored via the UART Flag (UARTFR) register (see page 308) and the UART Receive Status (UARTRSR) register. Hardware monitors empty, full and overrun conditions. The UARTFR register contains empty and full flags (TXFE, TXFF, RXFE, and RXFF bits) and the UARTRSR register shows overrun status via the OE bit. The trigger points at which the FIFOs generate interrupts is controlled via the UART Interrupt FIFO Level Select (UARTIFLS) register (see page 317). Both FIFOs can be individually configured to trigger interrupts at different levels. Available configurations include 1/8, ¼, ½, ¾, and 7/8. For example, if the ¼ option is selected for the receive FIFO, the UART generates a receive interrupt after 4 data bytes are received. Out of reset, both FIFOs are configured to trigger an interrupt at the ½ mark. 13.2.6 Interrupts The UART can generate interrupts when the following conditions are observed: ■ Overrun Error ■ Break Error 300 Preliminary November 30, 2007 LM3S6965 Microcontroller ■ Parity Error ■ Framing Error ■ Receive Timeout ■ Transmit (when condition defined in the TXIFLSEL bit in the UARTIFLS register is met) ■ Receive (when condition defined in the RXIFLSEL bit in the UARTIFLS register is met) All of the interrupt events are ORed together before being sent to the interrupt controller, so the UART can only generate a single interrupt request to the controller at any given time. Software can service multiple interrupt events in a single interrupt service routine by reading the UART Masked Interrupt Status (UARTMIS) register (see page 322). The interrupt events that can trigger a controller-level interrupt are defined in the UART Interrupt Mask (UARTIM ) register (see page 319) by setting the corresponding IM bit to 1. If interrupts are not used, the raw interrupt status is always visible via the UART Raw Interrupt Status (UARTRIS) register (see page 321). Interrupts are always cleared (for both the UARTMIS and UARTRIS registers) by setting the corresponding bit in the UART Interrupt Clear (UARTICR) register (see page 323). The receive timeout interrupt is asserted when the receive FIFO is not empty, and no further data is received over a 32-bit period. The receive timeout interrupt is cleared either when the FIFO becomes empty through reading all the data (or by reading the holding register), or when a 1 is written to the corresponding bit in the UARTICR register. 13.2.7 Loopback Operation The UART can be placed into an internal loopback mode for diagnostic or debug work. This is accomplished by setting the LBE bit in the UARTCTL register (see page 315). In loopback mode, data transmitted on UnTx is received on the UnRx input. 13.2.8 IrDA SIR block The IrDA SIR block contains an IrDA serial IR (SIR) protocol encoder/decoder. When enabled, the SIR block uses the UnTx and UnRx pins for the SIR protocol, which should be connected to an IR transceiver. The SIR block can receive and transmit, but it is only half-duplex so it cannot do both at the same time. Transmission must be stopped before data can be received. The IrDA SIR physical layer specifies a minimum 10-ms delay between transmission and reception. 13.3 Initialization and Configuration To use the UARTs, the peripheral clock must be enabled by setting the UART0, UART1, or UART2 bits in the RCGC1 register. This section discusses the steps that are required for using a UART module. For this example, the system clock is assumed to be 20 MHz and the desired UART configuration is: ■ 115200 baud rate ■ Data length of 8 bits ■ One stop bit November 30, 2007 Preliminary 301 Universal Asynchronous Receivers/Transmitters (UARTs) ■ No parity ■ FIFOs disabled ■ No interrupts The first thing to consider when programming the UART is the baud-rate divisor (BRD), since the UARTIBRD and UARTFBRD registers must be written before the UARTLCRH register. Using the equation described in “Baud-Rate Generation” on page 298, the BRD can be calculated: BRD = 20,000,000 / (16 * 115,200) = 10.8507 which means that the DIVINT field of the UARTIBRD register (see page 311) should be set to 10. The value to be loaded into the UARTFBRD register (see page 312) is calculated by the equation: UARTFBRD[DIVFRAC] = integer(0.8507 * 64 + 0.5) = 54 With the BRD values in hand, the UART configuration is written to the module in the following order: 1. Disable the UART by clearing the UARTEN bit in the UARTCTL register. 2. Write the integer portion of the BRD to the UARTIBRD register. 3. Write the fractional portion of the BRD to the UARTFBRD register. 4. Write the desired serial parameters to the UARTLCRH register (in this case, a value of 0x0000.0060). 5. Enable the UART by setting the UARTEN bit in the UARTCTL register. 13.4 Register Map Table 13-1 on page 302 lists the UART registers. The offset listed is a hexadecimal increment to the register ’s address, relative to that UART’s base address: ■ UART0: 0x4000.C000 ■ UART1: 0x4000.D000 ■ UART2: 0x4000.E000 Note: The UART must be disabled (see the UARTEN bit in the UARTCTL register on page 315) before any of the control registers are reprogrammed. When the UART is disabled during a TX or RX operation, the current transaction is completed prior to the UART stopping. Table 13-1. UART Register Map Offset 0x000 0x004 0x018 0x020 Name UARTDR UARTRSR/UARTECR UARTFR UARTILPR Type R/W R/W RO R/W Reset 0x0000.0000 0x0000.0000 0x0000.0090 0x0000.0000 Description UART Data UART Receive Status/Error Clear UART Flag UART IrDA Low-Power Register See page 304 306 308 310 302 Preliminary November 30, 2007 LM3S6965 Microcontroller Offset 0x024 0x028 0x02C 0x030 0x034 0x038 0x03C 0x040 0x044 0xFD0 0xFD4 0xFD8 0xFDC 0xFE0 0xFE4 0xFE8 0xFEC 0xFF0 0xFF4 0xFF8 0xFFC Name UARTIBRD UARTFBRD UARTLCRH UARTCTL UARTIFLS UARTIM UARTRIS UARTMIS UARTICR UARTPeriphID4 UARTPeriphID5 UARTPeriphID6 UARTPeriphID7 UARTPeriphID0 UARTPeriphID1 UARTPeriphID2 UARTPeriphID3 UARTPCellID0 UARTPCellID1 UARTPCellID2 UARTPCellID3 Type R/W R/W R/W R/W R/W R/W RO RO W1C RO RO RO RO RO RO RO RO RO RO RO RO Reset 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0300 0x0000.0012 0x0000.0000 0x0000.000F 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0011 0x0000.0000 0x0000.0018 0x0000.0001 0x0000.000D 0x0000.00F0 0x0000.0005 0x0000.00B1 Description UART Integer Baud-Rate Divisor UART Fractional Baud-Rate Divisor UART Line Control UART Control UART Interrupt FIFO Level Select UART Interrupt Mask UART Raw Interrupt Status UART Masked Interrupt Status UART Interrupt Clear UART Peripheral Identification 4 UART Peripheral Identification 5 UART Peripheral Identification 6 UART Peripheral Identification 7 UART Peripheral Identification 0 UART Peripheral Identification 1 UART Peripheral Identification 2 UART Peripheral Identification 3 UART PrimeCell Identification 0 UART PrimeCell Identification 1 UART PrimeCell Identification 2 UART PrimeCell Identification 3 See page 311 312 313 315 317 319 321 322 323 325 326 327 328 329 330 331 332 333 334 335 336 13.5 Register Descriptions The remainder of this section lists and describes the UART registers, in numerical order by address offset. November 30, 2007 Preliminary 303 Universal Asynchronous Receivers/Transmitters (UARTs) Register 1: UART Data (UARTDR), offset 0x000 This register is the data register (the interface to the FIFOs). When FIFOs are enabled, data written to this location is pushed onto the transmit FIFO. If FIFOs are disabled, data is stored in the transmitter holding register (the bottom word of the transmit FIFO). A write to this register initiates a transmission from the UART. For received data, if the FIFO is enabled, the data byte and the 4-bit status (break, frame, parity, and overrun) is pushed onto the 12-bit wide receive FIFO. If FIFOs are disabled, the data byte and status are stored in the receiving holding register (the bottom word of the receive FIFO). The received data can be retrieved by reading this register. UART Data (UARTDR) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0x000 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 OE RO 0 RO 0 RO 0 10 BE RO 0 RO 0 9 PE RO 0 RO 0 8 FE RO 0 R/W 0 R/W 0 R/W 0 R/W 0 RO 0 7 RO 0 6 RO 0 5 RO 0 4 DATA R/W 0 R/W 0 R/W 0 R/W 0 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 Bit/Field 31:12 Name reserved Type RO Reset 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. UART Overrun Error The OE values are defined as follows: Value Description 0 1 There has been no data loss due to a FIFO overrun. New data was received when the FIFO was full, resulting in data loss. 11 OE RO 0 10 BE RO 0 UART Break Error This bit is set to 1 when a break condition is detected, indicating that the receive data input was held Low for longer than a full-word transmission time (defined as start, data, parity, and stop bits). In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the received data input goes to a 1 (marking state) and the next valid start bit is received. 304 Preliminary November 30, 2007 LM3S6965 Microcontroller Bit/Field 9 Name PE Type RO Reset 0 Description UART Parity Error This bit is set to 1 when the parity of the received data character does not match the parity defined by bits 2 and 7 of the UARTLCRH register. In FIFO mode, this error is associated with the character at the top of the FIFO. 8 FE RO 0 UART Framing Error This bit is set to 1 when the received character does not have a valid stop bit (a valid stop bit is 1). 7:0 DATA R/W 0 Data Transmitted or Received When written, the data that is to be transmitted via the UART. When read, the data that was received by the UART. November 30, 2007 Preliminary 305 Universal Asynchronous Receivers/Transmitters (UARTs) Register 2: UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 The UARTRSR/UARTECR register is the receive status register/error clear register. In addition to the UARTDR register, receive status can also be read from the UARTRSR register. If the status is read from this register, then the status information corresponds to the entry read from UARTDR prior to reading UARTRSR. The status information for overrun is set immediately when an overrun condition occurs. The UARTRSR register cannot be written. A write of any value to the UARTECR register clears the framing, parity, break, and overrun errors. All the bits are cleared to 0 on reset. Read-Only Receive Status (UARTRSR) Register UART Receive Status/Error Clear (UARTRSR/UARTECR) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0x004 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 OE RO 0 RO 0 2 BE RO 0 RO 0 1 PE RO 0 RO 0 0 FE RO 0 Bit/Field 31:4 Name reserved Type RO Reset 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. UART Overrun Error When this bit is set to 1, data is received and the FIFO is already full. This bit is cleared to 0 by a write to UARTECR. The FIFO contents remain valid since no further data is written when the FIFO is full, only the contents of the shift register are overwritten. The CPU must now read the data in order to empty the FIFO. 3 OE RO 0 2 BE RO 0 UART Break Error This bit is set to 1 when a break condition is detected, indicating that the received data input was held Low for longer than a full-word transmission time (defined as start, data, parity, and stop bits). This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state) and the next valid start bit is received. 306 Preliminary November 30, 2007 LM3S6965 Microcontroller Bit/Field 1 Name PE Type RO Reset 0 Description UART Parity Error This bit is set to 1 when the parity of the received data character does not match the parity defined by bits 2 and 7 of the UARTLCRH register. This bit is cleared to 0 by a write to UARTECR. 0 FE RO 0 UART Framing Error This bit is set to 1 when the received character does not have a valid stop bit (a valid stop bit is 1). This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. Write-Only Error Clear (UARTECR) Register UART Receive Status/Error Clear (UARTRSR/UARTECR) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0x004 Type WO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset WO 0 15 WO 0 14 WO 0 13 WO 0 12 WO 0 11 WO 0 10 WO 0 9 WO 0 8 WO 0 7 WO 0 6 WO 0 5 WO 0 4 DATA WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 3 WO 0 2 WO 0 1 WO 0 0 reserved Type Reset WO 0 WO 0 WO 0 WO 0 WO 0 Bit/Field 31:8 Name reserved Type WO Reset 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Error Clear A write to this register of any data clears the framing, parity, break, and overrun flags. 7:0 DATA WO 0 November 30, 2007 Preliminary 307 Universal Asynchronous Receivers/Transmitters (UARTs) Register 3: UART Flag (UARTFR), offset 0x018 The UARTFR register is the flag register. After reset, the TXFF, RXFF, and BUSY bits are 0, and TXFE and RXFE bits are 1. UART Flag (UARTFR) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0x018 Type RO, reset 0x0000.0090 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 TXFE RO 0 RO 0 RO 0 RO 1 RO 0 6 RXFF RO 0 RO 0 5 TXFF RO 0 RO 0 4 RXFE RO 1 RO 0 3 BUSY RO 0 RO 0 RO 0 2 RO 0 1 reserved RO 0 RO 0 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. UART Transmit FIFO Empty The meaning of this bit depends on the state of the FEN bit in the UARTLCRH register. If the FIFO is disabled (FEN is 0), this bit is set when the transmit holding register is empty. If the FIFO is enabled (FEN is 1), this bit is set when the transmit FIFO is empty. 7 TXFE RO 1 6 RXFF RO 0 UART Receive FIFO Full The meaning of this bit depends on the state of the FEN bit in the UARTLCRH register. If the FIFO is disabled, this bit is set when the receive holding register is full. If the FIFO is enabled, this bit is set when the receive FIFO is full. 5 TXFF RO 0 UART Transmit FIFO Full The meaning of this bit depends on the state of the FEN bit in the UARTLCRH register. If the FIFO is disabled, this bit is set when the transmit holding register is full. If the FIFO is enabled, this bit is set when the transmit FIFO is full. 308 Preliminary November 30, 2007 LM3S6965 Microcontroller Bit/Field 4 Name RXFE Type RO Reset 1 Description UART Receive FIFO Empty The meaning of this bit depends on the state of the FEN bit in the UARTLCRH register. If the FIFO is disabled, this bit is set when the receive holding register is empty. If the FIFO is enabled, this bit is set when the receive FIFO is empty. 3 BUSY RO 0 UART Busy When this bit is 1, the UART is busy transmitting data. This bit remains set until the complete byte, including all stop bits, has been sent from the shift register. This bit is set as soon as the transmit FIFO becomes non-empty (regardless of whether UART is enabled). 2:0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. November 30, 2007 Preliminary 309 Universal Asynchronous Receivers/Transmitters (UARTs) Register 4: UART IrDA Low-Power Register (UARTILPR), offset 0x020 The UARTILPR register is an 8-bit read/write register that stores the low-power counter divisor value used to generate the IrLPBaud16 signal by dividing down the system clock (SysClk). All the bits are cleared to 0 when reset. The IrLPBaud16 internal signal is generated by dividing down the UARTCLK signal according to the low-power divisor value written to UARTILPR. The low-power divisor value is calculated as follows: ILPDVSR = SysClk / FIrLPBaud16 where FIrLPBaud16 is nominally 1.8432 MHz. IrLPBaud16 is an internal signal used for SIR pulse generation when low-power mode is used. You must choose the divisor so that 1.42 MHz < FIrLPBaud16 < 2.12 MHz, which results in a low-power pulse duration of 1.41–2.11 μs (three times the period of IrLPBaud16). The minimum frequency of IrLPBaud16 ensures that pulses less than one period of IrLPBaud16 are rejected, but that pulses greater than 1.4 μs are accepted as valid pulses. Note: Zero is an illegal value. Programming a zero value results in no IrLPBaud16 pulses being generated. UART IrDA Low-Power Register (UARTILPR) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0x020 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 ILPDVSR R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field 31:8 Name reserved Type RO Reset 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. IrDA Low-Power Divisor This is an 8-bit low-power divisor value. 7:0 ILPDVSR R/W 0x00 310 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 5: UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 The UARTIBRD register is the integer part of the baud-rate divisor value. All the bits are cleared on reset. The minimum possible divide ratio is 1 (when UARTIBRD=0), in which case the UARTFBRD register is ignored. When changing the UARTIBRD register, the new value does not take effect until transmission/reception of the current character is complete. Any changes to the baud-rate divisor must be followed by a write to the UARTLCRH register. See “Baud-Rate Generation” on page 298 for configuration details. UART Integer Baud-Rate Divisor (UARTIBRD) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0x024 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 DIVINT Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 Bit/Field 31:16 Name reserved Type RO Reset 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Integer Baud-Rate Divisor 15:0 DIVINT R/W 0x0000 November 30, 2007 Preliminary 311 Universal Asynchronous Receivers/Transmitters (UARTs) Register 6: UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 The UARTFBRD register is the fractional part of the baud-rate divisor value. All the bits are cleared on reset. When changing the UARTFBRD register, the new value does not take effect until transmission/reception of the current character is complete. Any changes to the baud-rate divisor must be followed by a write to the UARTLCRH register. See “Baud-Rate Generation” on page 298 for configuration details. UART Fractional Baud-Rate Divisor (UARTFBRD) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0x028 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 DIVFRAC R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field 31:6 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Fractional Baud-Rate Divisor 5:0 DIVFRAC R/W 0x000 312 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 7: UART Line Control (UARTLCRH), offset 0x02C The UARTLCRH register is the line control register. Serial parameters such as data length, parity, and stop bit selection are implemented in this register. When updating the baud-rate divisor (UARTIBRD and/or UARTIFRD), the UARTLCRH register must also be written. The write strobe for the baud-rate divisor registers is tied to the UARTLCRH register. UART Line Control (UARTLCRH) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0x02C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 SPS RO 0 RO 0 RO 0 R/W 0 RO 0 6 WLEN R/W 0 R/W 0 RO 0 5 RO 0 4 FEN R/W 0 RO 0 3 STP2 R/W 0 RO 0 2 EPS R/W 0 RO 0 1 PEN R/W 0 RO 0 0 BRK R/W 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. UART Stick Parity Select When bits 1, 2, and 7 of UARTLCRH are set, the parity bit is transmitted and checked as a 0. When bits 1 and 7 are set and 2 is cleared, the parity bit is transmitted and checked as a 1. When this bit is cleared, stick parity is disabled. 7 SPS R/W 0 6:5 WLEN R/W 0 UART Word Length The bits indicate the number of data bits transmitted or received in a frame as follows: Value Description 0x3 8 bits 0x2 7 bits 0x1 6 bits 0x0 5 bits (default) 4 FEN R/W 0 UART Enable FIFOs If this bit is set to 1, transmit and receive FIFO buffers are enabled (FIFO mode). When cleared to 0, FIFOs are disabled (Character mode). The FIFOs become 1-byte-deep holding registers. November 30, 2007 Preliminary 313 Universal Asynchronous Receivers/Transmitters (UARTs) Bit/Field 3 Name STP2 Type R/W Reset 0 Description UART Two Stop Bits Select If this bit is set to 1, two stop bits are transmitted at the end of a frame. The receive logic does not check for two stop bits being received. 2 EPS R/W 0 UART Even Parity Select If this bit is set to 1, even parity generation and checking is performed during transmission and reception, which checks for an even number of 1s in data and parity bits. When cleared to 0, then odd parity is performed, which checks for an odd number of 1s. This bit has no effect when parity is disabled by the PEN bit. 1 PEN R/W 0 UART Parity Enable If this bit is set to 1, parity checking and generation is enabled; otherwise, parity is disabled and no parity bit is added to the data frame. 0 BRK R/W 0 UART Send Break If this bit is set to 1, a Low level is continually output on the UnTX output, after completing transmission of the current character. For the proper execution of the break command, the software must set this bit for at least two frames (character periods). For normal use, this bit must be cleared to 0. 314 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 8: UART Control (UARTCTL), offset 0x030 The UARTCTL register is the control register. All the bits are cleared on reset except for the Transmit Enable (TXE) and Receive Enable (RXE) bits, which are set to 1. To enable the UART module, the UARTEN bit must be set to 1. If software requires a configuration change in the module, the UARTEN bit must be cleared before the configuration changes are written. If the UART is disabled during a transmit or receive operation, the current transaction is completed prior to the UART stopping. UART Control (UARTCTL) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0x030 Type R/W, reset 0x0000.0300 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RXE RO 0 RO 0 R/W 1 RO 0 8 TXE R/W 1 RO 0 7 LBE R/W 0 RO 0 RO 0 6 RO 0 5 reserved RO 0 RO 0 RO 0 RO 0 4 RO 0 3 RO 0 2 SIRLP R/W 0 RO 0 1 SIREN R/W 0 RO 0 0 UARTEN R/W 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 Bit/Field 31:10 Name reserved Type RO Reset 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. UART Receive Enable If this bit is set to 1, the receive section of the UART is enabled. When the UART is disabled in the middle of a receive, it completes the current character before stopping. Note: To enable reception, the UARTEN bit must also be set. 9 RXE R/W 1 8 TXE R/W 1 UART Transmit Enable If this bit is set to 1, the transmit section of the UART is enabled. When the UART is disabled in the middle of a transmission, it completes the current character before stopping. Note: To enable transmission, the UARTEN bit must also be set. 7 LBE R/W 0 UART Loop Back Enable If this bit is set to 1, the UnTX path is fed through the UnRX path. 6:3 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. November 30, 2007 Preliminary 315 Universal Asynchronous Receivers/Transmitters (UARTs) Bit/Field 2 Name SIRLP Type R/W Reset 0 Description UART SIR Low Power Mode This bit selects the IrDA encoding mode. If this bit is cleared to 0, low-level bits are transmitted as an active High pulse with a width of 3/16th of the bit period. If this bit is set to 1, low-level bits are transmitted with a pulse width which is 3 times the period of the IrLPBaud16 input signal, regardless of the selected bit rate. Setting this bit uses less power, but might reduce transmission distances. See page 310 for more information. 1 SIREN R/W 0 UART SIR Enable If this bit is set to 1, the IrDA SIR block is enabled, and the UART will transmit and receive data using SIR protocol. 0 UARTEN R/W 0 UART Enable If this bit is set to 1, the UART is enabled. When the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. 316 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 9: UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 The UARTIFLS register is the interrupt FIFO level select register. You can use this register to define the FIFO level at which the TXRIS and RXRIS bits in the UARTRIS register are triggered. The interrupts are generated based on a transition through a level rather than being based on the level. That is, the interrupts are generated when the fill level progresses through the trigger level. For example, if the receive trigger level is set to the half-way mark, the interrupt is triggered as the module is receiving the 9th character. Out of reset, the TXIFLSEL and RXIFLSEL bits are configured so that the FIFOs trigger an interrupt at the half-way mark. UART Interrupt FIFO Level Select (UARTIFLS) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0x034 Type R/W, reset 0x0000.0012 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RXIFLSEL RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 1 R/W 0 R/W 0 RO 0 3 RO 0 2 RO 0 1 TXIFLSEL R/W 1 R/W 0 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:6 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. UART Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows: Value 0x0 0x1 0x2 0x3 0x4 Description RX FIFO ≥ 1/8 full RX FIFO ≥ ¼ full RX FIFO ≥ ½ full (default) RX FIFO ≥ ¾ full RX FIFO ≥ 7/8 full 5:3 RXIFLSEL R/W 0x2 0x5-0x7 Reserved November 30, 2007 Preliminary 317 Universal Asynchronous Receivers/Transmitters (UARTs) Bit/Field 2:0 Name TXIFLSEL Type R/W Reset 0x2 Description UART Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows: Value 0x0 0x1 0x2 0x3 0x4 Description TX FIFO ≤ 1/8 full TX FIFO ≤ ¼ full TX FIFO ≤ ½ full (default) TX FIFO ≤ ¾ full TX FIFO ≤ 7/8 full 0x5-0x7 Reserved 318 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 10: UART Interrupt Mask (UARTIM), offset 0x038 The UARTIM register is the interrupt mask set/clear register. On a read, this register gives the current value of the mask on the relevant interrupt. Writing a 1 to a bit allows the corresponding raw interrupt signal to be routed to the interrupt controller. Writing a 0 prevents the raw interrupt signal from being sent to the interrupt controller. UART Interrupt Mask (UARTIM) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0x038 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 12 RO 0 11 RO 0 10 OEIM R/W 0 RO 0 9 BEIM R/W 0 RO 0 8 PEIM R/W 0 RO 0 7 FEIM R/W 0 RO 0 6 RTIM R/W 0 RO 0 5 TXIM R/W 0 RO 0 4 RXIM R/W 0 RO 0 RO 0 3 RO 0 2 reserved RO 0 RO 0 RO 0 RO 0 1 RO 0 0 Bit/Field 31:11 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. UART Overrun Error Interrupt Mask On a read, the current mask for the OEIM interrupt is returned. Setting this bit to 1 promotes the OEIM interrupt to the interrupt controller. 10 OEIM R/W 0 9 BEIM R/W 0 UART Break Error Interrupt Mask On a read, the current mask for the BEIM interrupt is returned. Setting this bit to 1 promotes the BEIM interrupt to the interrupt controller. 8 PEIM R/W 0 UART Parity Error Interrupt Mask On a read, the current mask for the PEIM interrupt is returned. Setting this bit to 1 promotes the PEIM interrupt to the interrupt controller. 7 FEIM R/W 0 UART Framing Error Interrupt Mask On a read, the current mask for the FEIM interrupt is returned. Setting this bit to 1 promotes the FEIM interrupt to the interrupt controller. 6 RTIM R/W 0 UART Receive Time-Out Interrupt Mask On a read, the current mask for the RTIM interrupt is returned. Setting this bit to 1 promotes the RTIM interrupt to the interrupt controller. 5 TXIM R/W 0 UART Transmit Interrupt Mask On a read, the current mask for the TXIM interrupt is returned. Setting this bit to 1 promotes the TXIM interrupt to the interrupt controller. November 30, 2007 Preliminary 319 Universal Asynchronous Receivers/Transmitters (UARTs) Bit/Field 4 Name RXIM Type R/W Reset 0 Description UART Receive Interrupt Mask On a read, the current mask for the RXIM interrupt is returned. Setting this bit to 1 promotes the RXIM interrupt to the interrupt controller. 3:0 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 320 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 11: UART Raw Interrupt Status (UARTRIS), offset 0x03C The UARTRIS register is the raw interrupt status register. On a read, this register gives the current raw status value of the corresponding interrupt. A write has no effect. UART Raw Interrupt Status (UARTRIS) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0x03C Type RO, reset 0x0000.000F 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 12 RO 0 11 RO 0 10 OERIS RO 0 RO 0 9 BERIS RO 0 RO 0 8 PERIS RO 0 RO 0 7 FERIS RO 0 RO 0 6 RTRIS RO 0 RO 0 5 TXRIS RO 0 RO 0 4 RXRIS RO 0 RO 1 RO 0 3 RO 0 2 reserved RO 1 RO 1 RO 1 RO 0 1 RO 0 0 Bit/Field 31:11 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. UART Overrun Error Raw Interrupt Status Gives the raw interrupt state (prior to masking) of this interrupt. 10 OERIS RO 0 9 BERIS RO 0 UART Break Error Raw Interrupt Status Gives the raw interrupt state (prior to masking) of this interrupt. 8 PERIS RO 0 UART Parity Error Raw Interrupt Status Gives the raw interrupt state (prior to masking) of this interrupt. 7 FERIS RO 0 UART Framing Error Raw Interrupt Status Gives the raw interrupt state (prior to masking) of this interrupt. 6 RTRIS RO 0 UART Receive Time-Out Raw Interrupt Status Gives the raw interrupt state (prior to masking) of this interrupt. 5 TXRIS RO 0 UART Transmit Raw Interrupt Status Gives the raw interrupt state (prior to masking) of this interrupt. 4 RXRIS RO 0 UART Receive Raw Interrupt Status Gives the raw interrupt state (prior to masking) of this interrupt. 3:0 reserved RO 0xF Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. November 30, 2007 Preliminary 321 Universal Asynchronous Receivers/Transmitters (UARTs) Register 12: UART Masked Interrupt Status (UARTMIS), offset 0x040 The UARTMIS register is the masked interrupt status register. On a read, this register gives the current masked status value of the corresponding interrupt. A write has no effect. UART Masked Interrupt Status (UARTMIS) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0x040 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 12 RO 0 11 RO 0 10 OEMIS RO 0 RO 0 9 BEMIS RO 0 RO 0 8 PEMIS RO 0 RO 0 7 FEMIS RO 0 RO 0 6 RTMIS RO 0 RO 0 5 TXMIS RO 0 RO 0 4 RXMIS RO 0 RO 0 RO 0 3 RO 0 2 reserved RO 0 RO 0 RO 0 RO 0 1 RO 0 0 Bit/Field 31:11 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. UART Overrun Error Masked Interrupt Status Gives the masked interrupt state of this interrupt. 10 OEMIS RO 0 9 BEMIS RO 0 UART Break Error Masked Interrupt Status Gives the masked interrupt state of this interrupt. 8 PEMIS RO 0 UART Parity Error Masked Interrupt Status Gives the masked interrupt state of this interrupt. 7 FEMIS RO 0 UART Framing Error Masked Interrupt Status Gives the masked interrupt state of this interrupt. 6 RTMIS RO 0 UART Receive Time-Out Masked Interrupt Status Gives the masked interrupt state of this interrupt. 5 TXMIS RO 0 UART Transmit Masked Interrupt Status Gives the masked interrupt state of this interrupt. 4 RXMIS RO 0 UART Receive Masked Interrupt Status Gives the masked interrupt state of this interrupt. 3:0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 322 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 13: UART Interrupt Clear (UARTICR), offset 0x044 The UARTICR register is the interrupt clear register. On a write of 1, the corresponding interrupt (both raw interrupt and masked interrupt, if enabled) is cleared. A write of 0 has no effect. UART Interrupt Clear (UARTICR) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0x044 Type W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 12 RO 0 11 RO 0 10 OEIC W1C 0 RO 0 9 BEIC W1C 0 RO 0 8 PEIC W1C 0 RO 0 7 FEIC W1C 0 RO 0 6 RTIC W1C 0 RO 0 5 TXIC W1C 0 RO 0 4 RXIC W1C 0 RO 0 RO 0 3 RO 0 2 reserved RO 0 RO 0 RO 0 RO 0 1 RO 0 0 Bit/Field 31:11 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Overrun Error Interrupt Clear The OEIC values are defined as follows: Value Description 0 1 No effect on the interrupt. Clears interrupt. 10 OEIC W1C 0 9 BEIC W1C 0 Break Error Interrupt Clear The BEIC values are defined as follows: Value Description 0 1 No effect on the interrupt. Clears interrupt. 8 PEIC W1C 0 Parity Error Interrupt Clear The PEIC values are defined as follows: Value Description 0 1 No effect on the interrupt. Clears interrupt. November 30, 2007 Preliminary 323 Universal Asynchronous Receivers/Transmitters (UARTs) Bit/Field 7 Name FEIC Type W1C Reset 0 Description Framing Error Interrupt Clear The FEIC values are defined as follows: Value Description 0 1 No effect on the interrupt. Clears interrupt. 6 RTIC W1C 0 Receive Time-Out Interrupt Clear The RTIC values are defined as follows: Value Description 0 1 No effect on the interrupt. Clears interrupt. 5 TXIC W1C 0 Transmit Interrupt Clear The TXIC values are defined as follows: Value Description 0 1 No effect on the interrupt. Clears interrupt. 4 RXIC W1C 0 Receive Interrupt Clear The RXIC values are defined as follows: Value Description 0 1 No effect on the interrupt. Clears interrupt. 3:0 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 324 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 14: UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the reset values. UART Peripheral Identification 4 (UARTPeriphID4) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0xFD0 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 PID4 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. UART Peripheral ID Register[7:0] Can be used by software to identify the presence of this peripheral. 7:0 PID4 RO 0x0000 November 30, 2007 Preliminary 325 Universal Asynchronous Receivers/Transmitters (UARTs) Register 15: UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the reset values. UART Peripheral Identification 5 (UARTPeriphID5) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0xFD4 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 PID5 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. UART Peripheral ID Register[15:8] Can be used by software to identify the presence of this peripheral. 7:0 PID5 RO 0x0000 326 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 16: UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the reset values. UART Peripheral Identification 6 (UARTPeriphID6) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0xFD8 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 PID6 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. UART Peripheral ID Register[23:16] Can be used by software to identify the presence of this peripheral. 7:0 PID6 RO 0x0000 November 30, 2007 Preliminary 327 Universal Asynchronous Receivers/Transmitters (UARTs) Register 17: UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the reset values. UART Peripheral Identification 7 (UARTPeriphID7) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0xFDC Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 PID7 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. UART Peripheral ID Register[31:24] Can be used by software to identify the presence of this peripheral. 7:0 PID7 RO 0x0000 328 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 18: UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the reset values. UART Peripheral Identification 0 (UARTPeriphID0) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0xFE0 Type RO, reset 0x0000.0011 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 PID0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 0 RO 0 RO 0 RO 1 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. UART Peripheral ID Register[7:0] Can be used by software to identify the presence of this peripheral. 7:0 PID0 RO 0x11 November 30, 2007 Preliminary 329 Universal Asynchronous Receivers/Transmitters (UARTs) Register 19: UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the reset values. UART Peripheral Identification 1 (UARTPeriphID1) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0xFE4 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 PID1 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. UART Peripheral ID Register[15:8] Can be used by software to identify the presence of this peripheral. 7:0 PID1 RO 0x00 330 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 20: UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the reset values. UART Peripheral Identification 2 (UARTPeriphID2) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0xFE8 Type RO, reset 0x0000.0018 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 PID2 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 1 RO 0 RO 0 RO 0 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. UART Peripheral ID Register[23:16] Can be used by software to identify the presence of this peripheral. 7:0 PID2 RO 0x18 November 30, 2007 Preliminary 331 Universal Asynchronous Receivers/Transmitters (UARTs) Register 21: UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the reset values. UART Peripheral Identification 3 (UARTPeriphID3) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0xFEC Type RO, reset 0x0000.0001 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 PID3 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. UART Peripheral ID Register[31:24] Can be used by software to identify the presence of this peripheral. 7:0 PID3 RO 0x01 332 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 22: UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 The UARTPCellIDn registers are hard-coded and the fields within the registers determine the reset values. UART PrimeCell Identification 0 (UARTPCellID0) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0xFF0 Type RO, reset 0x0000.000D 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 CID0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 1 RO 0 RO 1 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. UART PrimeCell ID Register[7:0] Provides software a standard cross-peripheral identification system. 7:0 CID0 RO 0x0D November 30, 2007 Preliminary 333 Universal Asynchronous Receivers/Transmitters (UARTs) Register 23: UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 The UARTPCellIDn registers are hard-coded and the fields within the registers determine the reset values. UART PrimeCell Identification 1 (UARTPCellID1) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0xFF4 Type RO, reset 0x0000.00F0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 CID1 RO 0 RO 0 RO 0 RO 1 RO 1 RO 1 RO 1 RO 0 RO 0 RO 0 RO 0 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. UART PrimeCell ID Register[15:8] Provides software a standard cross-peripheral identification system. 7:0 CID1 RO 0xF0 334 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 24: UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 The UARTPCellIDn registers are hard-coded and the fields within the registers determine the reset values. UART PrimeCell Identification 2 (UARTPCellID2) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0xFF8 Type RO, reset 0x0000.0005 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 CID2 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 0 RO 1 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. UART PrimeCell ID Register[23:16] Provides software a standard cross-peripheral identification system. 7:0 CID2 RO 0x05 November 30, 2007 Preliminary 335 Universal Asynchronous Receivers/Transmitters (UARTs) Register 25: UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC The UARTPCellIDn registers are hard-coded and the fields within the registers determine the reset values. UART PrimeCell Identification 3 (UARTPCellID3) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 Offset 0xFFC Type RO, reset 0x0000.00B1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 CID3 RO 0 RO 0 RO 0 RO 1 RO 0 RO 1 RO 1 RO 0 RO 0 RO 0 RO 1 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. UART PrimeCell ID Register[31:24] Provides software a standard cross-peripheral identification system. 7:0 CID3 RO 0xB1 336 Preliminary November 30, 2007 LM3S6965 Microcontroller 14 Synchronous Serial Interface (SSI) The Stellaris Synchronous Serial Interface (SSI) is a master or slave interface for synchronous serial communication with peripheral devices that have either Freescale SPI, MICROWIRE, or Texas Instruments synchronous serial interfaces. The Stellaris SSI module has the following features: ■ Master or slave operation ■ Programmable clock bit rate and prescale ■ Separate transmit and receive FIFOs, 16 bits wide, 8 locations deep ■ Programmable interface operation for Freescale SPI, MICROWIRE, or Texas Instruments synchronous serial interfaces ■ Programmable data frame size from 4 to 16 bits ■ Internal loopback test mode for diagnostic/debug testing ® ® 14.1 Block Diagram Figure 14-1. SSI Module Block Diagram Interrupt Interrupt Control SSIIM SSIMIS Control / Status SSICR0 SSICR1 SSISR SSIDR RxFIFO 8 x 16 System Clock Clock Prescaler Identification Registers SSIPCellID0 SSIPCellID1 SSIPCellID2 SSIPCellID3 SSIPeriphID0 SSIPeriphID1 SSIPeriphID2 SSIPeriphID3 SSIPeriphID4 SSIPeriphID5 SSIPeriphID6 SSIPeriphID7 SSICPSR Transmit / Receive Logic SSIRIS SSIICR TxFIFO 8 x 16 . . . SSITx SSIRx SSIClk SSIFss . . . 14.2 Functional Description The SSI performs serial-to-parallel conversion on data received from a peripheral device. The CPU accesses data, control, and status information. The transmit and receive paths are buffered with November 30, 2007 Preliminary 337 Synchronous Serial Interface (SSI) internal FIFO memories allowing up to eight 16-bit values to be stored independently in both transmit and receive modes. 14.2.1 Bit Rate Generation The SSI includes a programmable bit rate clock divider and prescaler to generate the serial output clock. Bit rates are supported to 2 MHz and higher, although maximum bit rate is determined by peripheral devices. The serial bit rate is derived by dividing down the 50-MHz input clock. The clock is first divided by an even prescale value CPSDVSR from 2 to 254, which is programmed in the SSI Clock Prescale (SSICPSR) register (see page 356). The clock is further divided by a value from 1 to 256, which is 1 + SCR, where SCR is the value programmed in the SSI Control0 (SSICR0) register (see page 349). The frequency of the output clock SSIClk is defined by: FSSIClk = FSysClk / (CPSDVSR * (1 + SCR)) Note that although the SSIClk transmit clock can theoretically be 25 MHz, the module may not be able to operate at that speed. For master mode, the system clock must be at least two times faster than the SSIClk. For slave mode, the system clock must be at least 12 times faster than the SSIClk. See “Synchronous Serial Interface (SSI)” on page 544 to view SSI timing parameters. 14.2.2 FIFO Operation 14.2.2.1 Transmit FIFO The common transmit FIFO is a 16-bit wide, 8-locations deep, first-in, first-out memory buffer. The CPU writes data to the FIFO by writing the SSI Data (SSIDR) register (see page 353), and data is stored in the FIFO until it is read out by the transmission logic. When configured as a master or a slave, parallel data is written into the transmit FIFO prior to serial conversion and transmission to the attached slave or master, respectively, through the SSITx pin. 14.2.2.2 Receive FIFO The common receive FIFO is a 16-bit wide, 8-locations deep, first-in, first-out memory buffer. Received data from the serial interface is stored in the buffer until read out by the CPU, which accesses the read FIFO by reading the SSIDR register. When configured as a master or slave, serial data received through the SSIRx pin is registered prior to parallel loading into the attached slave or master receive FIFO, respectively. 14.2.3 Interrupts The SSI can generate interrupts when the following conditions are observed: ■ Transmit FIFO service ■ Receive FIFO service ■ Receive FIFO time-out ■ Receive FIFO overrun All of the interrupt events are ORed together before being sent to the interrupt controller, so the SSI can only generate a single interrupt request to the controller at any given time. You can mask each 338 Preliminary November 30, 2007 LM3S6965 Microcontroller of the four individual maskable interrupts by setting the appropriate bits in the SSI Interrupt Mask (SSIIM) register (see page 357). Setting the appropriate mask bit to 1 enables the interrupt. Provision of the individual outputs, as well as a combined interrupt output, allows use of either a global interrupt service routine, or modular device drivers to handle interrupts. The transmit and receive dynamic dataflow interrupts have been separated from the status interrupts so that data can be read or written in response to the FIFO trigger levels. The status of the individual interrupt sources can be read from the SSI Raw Interrupt Status (SSIRIS) and SSI Masked Interrupt Status (SSIMIS) registers (see page 359 and page 360, respectively). 14.2.4 Frame Formats Each data frame is between 4 and 16 bits long, depending on the size of data programmed, and is transmitted starting with the MSB. There are three basic frame types that can be selected: ■ Texas Instruments synchronous serial ■ Freescale SPI ■ MICROWIRE For all three formats, the serial clock (SSIClk) is held inactive while the SSI is idle, and SSIClk transitions at the programmed frequency only during active transmission or reception of data. The idle state of SSIClk is utilized to provide a receive timeout indication that occurs when the receive FIFO still contains data after a timeout period. For Freescale SPI and MICROWIRE frame formats, the serial frame (SSIFss ) pin is active Low, and is asserted (pulled down) during the entire transmission of the frame. For Texas Instruments synchronous serial frame format, the SSIFss pin is pulsed for one serial clock period starting at its rising edge, prior to the transmission of each frame. For this frame format, both the SSI and the off-chip slave device drive their output data on the rising edge of SSIClk, and latch data from the other device on the falling edge. Unlike the full-duplex transmission of the other two frame formats, the MICROWIRE format uses a special master-slave messaging technique, which operates at half-duplex. In this mode, when a frame begins, an 8-bit control message is transmitted to the off-chip slave. During this transmit, no incoming data is received by the SSI. After the message has been sent, the off-chip slave decodes it and, after waiting one serial clock after the last bit of the 8-bit control message has been sent, responds with the requested data. The returned data can be 4 to 16 bits in length, making the total frame length anywhere from 13 to 25 bits. 14.2.4.1 Texas Instruments Synchronous Serial Frame Format Figure 14-2 on page 339 shows the Texas Instruments synchronous serial frame format for a single transmitted frame. Figure 14-2. TI Synchronous Serial Frame Format (Single Transfer) SSIClk SSIFss SSITx/SSIRx MSB 4 to 16 bits LSB November 30, 2007 Preliminary 339 Synchronous Serial Interface (SSI) In this mode, SSIClk and SSIFss are forced Low, and the transmit data line SSITx is tristated whenever the SSI is idle. Once the bottom entry of the transmit FIFO contains data, SSIFss is pulsed High for one SSIClk period. The value to be transmitted is also transferred from the transmit FIFO to the serial shift register of the transmit logic. On the next rising edge of SSIClk, the MSB of the 4 to 16-bit data frame is shifted out on the SSITx pin. Likewise, the MSB of the received data is shifted onto the SSIRx pin by the off-chip serial slave device. Both the SSI and the off-chip serial slave device then clock each data bit into their serial shifter on the falling edge of each SSIClk. The received data is transferred from the serial shifter to the receive FIFO on the first rising edge of SSIClk after the LSB has been latched. Figure 14-3 on page 340 shows the Texas Instruments synchronous serial frame format when back-to-back frames are transmitted. Figure 14-3. TI Synchronous Serial Frame Format (Continuous Transfer) SSIClk SSIFss SSITx/SSIRx MSB 4 to 16 bits LSB 14.2.4.2 Freescale SPI Frame Format The Freescale SPI interface is a four-wire interface where the SSIFss signal behaves as a slave select. The main feature of the Freescale SPI format is that the inactive state and phase of the SSIClk signal are programmable through the SPO and SPH bits within the SSISCR0 control register. SPO Clock Polarity Bit When the SPO clock polarity control bit is Low, it produces a steady state Low value on the SSIClk pin. If the SPO bit is High, a steady state High value is placed on the SSIClk pin when data is not being transferred. SPH Phase Control Bit The SPH phase control bit selects the clock edge that captures data and allows it to change state. It has the most impact on the first bit transmitted by either allowing or not allowing a clock transition before the first data capture edge. When the SPH phase control bit is Low, data is captured on the first clock edge transition. If the SPH bit is High, data is captured on the second clock edge transition. 14.2.4.3 Freescale SPI Frame Format with SPO=0 and SPH=0 Single and continuous transmission signal sequences for Freescale SPI format with SPO=0 and SPH=0 are shown in Figure 14-4 on page 341 and Figure 14-5 on page 341. 340 Preliminary November 30, 2007 LM3S6965 Microcontroller Figure 14-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 SSIClk SSIFss SSIRx MSB 4 to 16 bits SSITx MSB LSB LSB Q Note: Q is undefined. Figure 14-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 SSIClk SSIFss SSIRx LSB MSB 4 to 16 bits SSITx LSB MSB LSB MSB LSB MSB In this configuration, during idle periods: ■ SSIClk is forced Low ■ SSIFss is forced High ■ The transmit data line SSITx is arbitrarily forced Low ■ When the SSI is configured as a master, it enables the SSIClk pad ■ When the SSI is configured as a slave, it disables the SSIClk pad If the SSI is enabled and there is valid data within the transmit FIFO, the start of transmission is signified by the SSIFss master signal being driven Low. This causes slave data to be enabled onto the SSIRx input line of the master. The master SSITx output pad is enabled. One half SSIClk period later, valid master data is transferred to the SSITx pin. Now that both the master and slave data have been set, the SSIClk master clock pin goes High after one further half SSIClk period. The data is now captured on the rising and propagated on the falling edges of the SSIClk signal. In the case of a single word transmission, after all bits of the data word have been transferred, the SSIFss line is returned to its idle High state one SSIClk period after the last bit has been captured. However, in the case of continuous back-to-back transmissions, the SSIFss signal must be pulsed High between each data word transfer. This is because the slave select pin freezes the data in its serial peripheral register and does not allow it to be altered if the SPH bit is logic zero. Therefore, the master device must raise the SSIFss pin of the slave device between each data transfer to enable the serial peripheral data write. On completion of the continuous transfer, the SSIFss pin is returned to its idle state one SSIClk period after the last bit has been captured. November 30, 2007 Preliminary 341 Synchronous Serial Interface (SSI) 14.2.4.4 Freescale SPI Frame Format with SPO=0 and SPH=1 The transfer signal sequence for Freescale SPI format with SPO=0 and SPH=1 is shown in Figure 14-6 on page 342, which covers both single and continuous transfers. Figure 14-6. Freescale SPI Frame Format with SPO=0 and SPH=1 SSIClk SSIFss SSIRx Q MSB 4 to 16 bits SSITx MSB LSB LSB Q Note: Q is undefined. In this configuration, during idle periods: ■ SSIClk is forced Low ■ SSIFss is forced High ■ The transmit data line SSITx is arbitrarily forced Low ■ When the SSI is configured as a master, it enables the SSIClk pad ■ When the SSI is configured as a slave, it disables the SSIClk pad If the SSI is enabled and there is valid data within the transmit FIFO, the start of transmission is signified by the SSIFss master signal being driven Low. The master SSITx output is enabled. After a further one half SSIClk period, both master and slave valid data is enabled onto their respective transmission lines. At the same time, the SSIClk is enabled with a rising edge transition. Data is then captured on the falling edges and propagated on the rising edges of the SSIClk signal. In the case of a single word transfer, after all bits have been transferred, the SSIFss line is returned to its idle High state one SSIClk period after the last bit has been captured. For continuous back-to-back transfers, the SSIFss pin is held Low between successive data words and termination is the same as that of the single word transfer. 14.2.4.5 Freescale SPI Frame Format with SPO=1 and SPH=0 Single and continuous transmission signal sequences for Freescale SPI format with SPO=1 and SPH=0 are shown in Figure 14-7 on page 343 and Figure 14-8 on page 343. 342 Preliminary November 30, 2007 LM3S6965 Microcontroller Figure 14-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 SSIClk SSIFss SSIRx MSB 4 to 16 bits SSITx MSB LSB LSB Q Note: Q is undefined. Figure 14-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 SSIClk SSIFss SSITx/SSIRxLSB MSB 4 to 16 bits LSB MSB In this configuration, during idle periods: ■ SSIClk is forced High ■ SSIFss is forced High ■ The transmit data line SSITx is arbitrarily forced Low ■ When the SSI is configured as a master, it enables the SSIClk pad ■ When the SSI is configured as a slave, it disables the SSIClk pad If the SSI is enabled and there is valid data within the transmit FIFO, the start of transmission is signified by the SSIFss master signal being driven Low, which causes slave data to be immediately transferred onto the SSIRx line of the master. The master SSITx output pad is enabled. One half period later, valid master data is transferred to the SSITx line. Now that both the master and slave data have been set, the SSIClk master clock pin becomes Low after one further half SSIClk period. This means that data is captured on the falling edges and propagated on the rising edges of the SSIClk signal. In the case of a single word transmission, after all bits of the data word are transferred, the SSIFss line is returned to its idle High state one SSIClk period after the last bit has been captured. However, in the case of continuous back-to-back transmissions, the SSIFss signal must be pulsed High between each data word transfer. This is because the slave select pin freezes the data in its serial peripheral register and does not allow it to be altered if the SPH bit is logic zero. Therefore, the master device must raise the SSIFss pin of the slave device between each data transfer to enable the serial peripheral data write. On completion of the continuous transfer, the SSIFss pin is returned to its idle state one SSIClk period after the last bit has been captured. November 30, 2007 Preliminary 343 Synchronous Serial Interface (SSI) 14.2.4.6 Freescale SPI Frame Format with SPO=1 and SPH=1 The transfer signal sequence for Freescale SPI format with SPO=1 and SPH=1 is shown in Figure 14-9 on page 344, which covers both single and continuous transfers. Figure 14-9. Freescale SPI Frame Format with SPO=1 and SPH=1 SSIClk SSIFss SSIRx Q MSB 4 to 16 bits SSITx MSB LSB LSB Q Note: Q is undefined. In this configuration, during idle periods: ■ SSIClk is forced High ■ SSIFss is forced High ■ The transmit data line SSITx is arbitrarily forced Low ■ When the SSI is configured as a master, it enables the SSIClk pad ■ When the SSI is configured as a slave, it disables the SSIClk pad If the SSI is enabled and there is valid data within the transmit FIFO, the start of transmission is signified by the SSIFss master signal being driven Low. The master SSITx output pad is enabled. After a further one-half SSIClk period, both master and slave data are enabled onto their respective transmission lines. At the same time, SSIClk is enabled with a falling edge transition. Data is then captured on the rising edges and propagated on the falling edges of the SSIClk signal. After all bits have been transferred, in the case of a single word transmission, the SSIFss line is returned to its idle high state one SSIClk period after the last bit has been captured. For continuous back-to-back transmissions, the SSIFss pin remains in its active Low state, until the final bit of the last word has been captured, and then returns to its idle state as described above. For continuous back-to-back transfers, the SSIFss pin is held Low between successive data words and termination is the same as that of the single word transfer. 14.2.4.7 MICROWIRE Frame Format Figure 14-10 on page 345 shows the MICROWIRE frame format, again for a single frame. Figure 14-11 on page 346 shows the same format when back-to-back frames are transmitted. 344 Preliminary November 30, 2007 LM3S6965 Microcontroller Figure 14-10. MICROWIRE Frame Format (Single Frame) SSIClk SSIFss SSITx SSIRx MSB LSB 8-bit control 0 MSB LSB 4 to 16 bits output data MICROWIRE format is very similar to SPI format, except that transmission is half-duplex instead of full-duplex, using a master-slave message passing technique. Each serial transmission begins with an 8-bit control word that is transmitted from the SSI to the off-chip slave device. During this transmission, no incoming data is received by the SSI. After the message has been sent, the off-chip slave decodes it and, after waiting one serial clock after the last bit of the 8-bit control message has been sent, responds with the required data. The returned data is 4 to 16 bits in length, making the total frame length anywhere from 13 to 25 bits. In this configuration, during idle periods: ■ SSIClk is forced Low ■ SSIFss is forced High ■ The transmit data line SSITx is arbitrarily forced Low A transmission is triggered by writing a control byte to the transmit FIFO. The falling edge of SSIFss causes the value contained in the bottom entry of the transmit FIFO to be transferred to the serial shift register of the transmit logic, and the MSB of the 8-bit control frame to be shifted out onto the SSITx pin. SSIFss remains Low for the duration of the frame transmission. The SSIRx pin remains tristated during this transmission. The off-chip serial slave device latches each control bit into its serial shifter on the rising edge of each SSIClk. After the last bit is latched by the slave device, the control byte is decoded during a one clock wait-state, and the slave responds by transmitting data back to the SSI. Each bit is driven onto the SSIRx line on the falling edge of SSIClk. The SSI in turn latches each bit on the rising edge of SSIClk. At the end of the frame, for single transfers, the SSIFss signal is pulled High one clock period after the last bit has been latched in the receive serial shifter, which causes the data to be transferred to the receive FIFO. Note: The off-chip slave device can tristate the receive line either on the falling edge of SSIClk after the LSB has been latched by the receive shifter, or when the SSIFss pin goes High. For continuous transfers, data transmission begins and ends in the same manner as a single transfer. However, the SSIFss line is continuously asserted (held Low) and transmission of data occurs back-to-back. The control byte of the next frame follows directly after the LSB of the received data from the current frame. Each of the received values is transferred from the receive shifter on the falling edge of SSIClk, after the LSB of the frame has been latched into the SSI. November 30, 2007 Preliminary 345 Synchronous Serial Interface (SSI) Figure 14-11. MICROWIRE Frame Format (Continuous Transfer) SSIClk SSIFss SSITx LSB MSB LSB 8-bit control SSIRx 0 MSB LSB MSB 4 to 16 bits output data In the MICROWIRE mode, the SSI slave samples the first bit of receive data on the rising edge of SSIClk after SSIFss has gone Low. Masters that drive a free-running SSIClk must ensure that the SSIFss signal has sufficient setup and hold margins with respect to the rising edge of SSIClk. Figure 14-12 on page 346 illustrates these setup and hold time requirements. With respect to the SSIClk rising edge on which the first bit of receive data is to be sampled by the SSI slave, SSIFss must have a setup of at least two times the period of SSIClk on which the SSI operates. With respect to the SSIClk rising edge previous to this edge, SSIFss must have a hold of at least one SSIClk period. Figure 14-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements tSetup=(2*tSSIClk ) tHold=tSSIClk SSIClk SSIFss SSIRx First RX data to be sampled by SSI slave 14.3 Initialization and Configuration To use the SSI, its peripheral clock must be enabled by setting the SSI bit in the RCGC1 register. For each of the frame formats, the SSI is configured using the following steps: 1. Ensure that the SSE bit in the SSICR1 register is disabled before making any configuration changes. 2. Select whether the SSI is a master or slave: a. For master operations, set the SSICR1 register to 0x0000.0000. b. For slave mode (output enabled), set the SSICR1 register to 0x0000.0004. c. For slave mode (output disabled), set the SSICR1 register to 0x0000.000C. 3. Configure the clock prescale divisor by writing the SSICPSR register. 346 Preliminary November 30, 2007 LM3S6965 Microcontroller 4. Write the SSICR0 register with the following configuration: ■ Serial clock rate (SCR) ■ Desired clock phase/polarity, if using Freescale SPI mode (SPH and SPO) ■ The protocol mode: Freescale SPI, TI SSF, MICROWIRE (FRF) ■ The data size (DSS) 5. Enable the SSI by setting the SSE bit in the SSICR1 register. As an example, assume the SSI must be configured to operate with the following parameters: ■ Master operation ■ Freescale SPI mode (SPO=1, SPH=1) ■ 1 Mbps bit rate ■ 8 data bits Assuming the system clock is 20 MHz, the bit rate calculation would be: FSSIClk = FSysClk / (CPSDVSR * (1 + SCR)) 1x106 = 20x106 / (CPSDVSR * (1 + SCR)) In this case, if CPSDVSR=2, SCR must be 9. The configuration sequence would be as follows: 1. Ensure that the SSE bit in the SSICR1 register is disabled. 2. Write the SSICR1 register with a value of 0x0000.0000. 3. Write the SSICPSR register with a value of 0x0000.0002. 4. Write the SSICR0 register with a value of 0x0000.09C7. 5. The SSI is then enabled by setting the SSE bit in the SSICR1 register to 1. 14.4 Register Map Table 14-1 on page 347 lists the SSI registers. The offset listed is a hexadecimal increment to the register ’s address, relative to that SSI module’s base address: ■ SSI0: 0x4000.8000 Note: The SSI must be disabled (see the SSE bit in the SSICR1 register) before any of the control registers are reprogrammed. Table 14-1. SSI Register Map Offset 0x000 Name SSICR0 Type R/W Reset 0x0000.0000 Description SSI Control 0 See page 349 November 30, 2007 Preliminary 347 Synchronous Serial Interface (SSI) Offset 0x004 0x008 0x00C 0x010 0x014 0x018 0x01C 0x020 0xFD0 0xFD4 0xFD8 0xFDC 0xFE0 0xFE4 0xFE8 0xFEC 0xFF0 0xFF4 0xFF8 0xFFC Name SSICR1 SSIDR SSISR SSICPSR SSIIM SSIRIS SSIMIS SSIICR SSIPeriphID4 SSIPeriphID5 SSIPeriphID6 SSIPeriphID7 SSIPeriphID0 SSIPeriphID1 SSIPeriphID2 SSIPeriphID3 SSIPCellID0 SSIPCellID1 SSIPCellID2 SSIPCellID3 Type R/W R/W RO R/W R/W RO RO W1C RO RO RO RO RO RO RO RO RO RO RO RO Reset 0x0000.0000 0x0000.0000 0x0000.0003 0x0000.0000 0x0000.0000 0x0000.0008 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0022 0x0000.0000 0x0000.0018 0x0000.0001 0x0000.000D 0x0000.00F0 0x0000.0005 0x0000.00B1 Description SSI Control 1 SSI Data SSI Status SSI Clock Prescale SSI Interrupt Mask SSI Raw Interrupt Status SSI Masked Interrupt Status SSI Interrupt Clear SSI Peripheral Identification 4 SSI Peripheral Identification 5 SSI Peripheral Identification 6 SSI Peripheral Identification 7 SSI Peripheral Identification 0 SSI Peripheral Identification 1 SSI Peripheral Identification 2 SSI Peripheral Identification 3 SSI PrimeCell Identification 0 SSI PrimeCell Identification 1 SSI PrimeCell Identification 2 SSI PrimeCell Identification 3 See page 351 353 354 356 357 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 14.5 Register Descriptions The remainder of this section lists and describes the SSI registers, in numerical order by address offset. 348 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 1: SSI Control 0 (SSICR0), offset 0x000 SSICR0 is control register 0 and contains bit fields that control various functions within the SSI module. Functionality such as protocol mode, clock rate, and data size are configured in this register. SSI Control 0 (SSICR0) SSI0 base: 0x4000.8000 Offset 0x000 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 SCR Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 SPH R/W 0 RO 0 6 SPO R/W 0 R/W 0 RO 0 5 FRF R/W 0 R/W 0 R/W 0 RO 0 4 RO 0 3 RO 0 2 DSS R/W 0 R/W 0 RO 0 1 RO 0 0 Bit/Field 31:16 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SSI Serial Clock Rate The value SCR is used to generate the transmit and receive bit rate of the SSI. The bit rate is: BR=FSSIClk/(CPSDVSR * (1 + SCR)) where CPSDVSR is an even value from 2-254 programmed in the SSICPSR register, and SCR is a value from 0-255. 15:8 SCR R/W 0x0000 7 SPH R/W 0 SSI Serial Clock Phase This bit is only applicable to the Freescale SPI Format. The SPH control bit selects the clock edge that captures data and allows it to change state. It has the most impact on the first bit transmitted by either allowing or not allowing a clock transition before the first data capture edge. When the SPH bit is 0, data is captured on the first clock edge transition. If SPH is 1, data is captured on the second clock edge transition. 6 SPO R/W 0 SSI Serial Clock Polarity This bit is only applicable to the Freescale SPI Format. When the SPO bit is 0, it produces a steady state Low value on the SSIClk pin. If SPO is 1, a steady state High value is placed on the SSIClk pin when data is not being transferred. November 30, 2007 Preliminary 349 Synchronous Serial Interface (SSI) Bit/Field 5:4 Name FRF Type R/W Reset 0x0 Description SSI Frame Format Select The FRF values are defined as follows: Value Frame Format 0x0 Freescale SPI Frame Format 0x1 Texas Intruments Synchronous Serial Frame Format 0x2 MICROWIRE Frame Format 0x3 Reserved 3:0 DSS R/W 0x00 SSI Data Size Select The DSS values are defined as follows: Value Data Size 0x0-0x2 Reserved 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF 4-bit data 5-bit data 6-bit data 7-bit data 8-bit data 9-bit data 10-bit data 11-bit data 12-bit data 13-bit data 14-bit data 15-bit data 16-bit data 350 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 2: SSI Control 1 (SSICR1), offset 0x004 SSICR1 is control register 1 and contains bit fields that control various functions within the SSI module. Master and slave mode functionality is controlled by this register. SSI Control 1 (SSICR1) SSI0 base: 0x4000.8000 Offset 0x004 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 SOD R/W 0 RO 0 2 MS R/W 0 RO 0 1 SSE R/W 0 RO 0 0 LBM R/W 0 Bit/Field 31:4 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SSI Slave Mode Output Disable This bit is relevant only in the Slave mode (MS=1). In multiple-slave systems, it is possible for the SSI master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto the serial output line. In such systems, the TXD lines from multiple slaves could be tied together. To operate in such a system, the SOD bit can be configured so that the SSI slave does not drive the SSITx pin. The SOD values are defined as follows: Value Description 0 1 SSI can drive SSITx output in Slave Output mode. SSI must not drive the SSITx output in Slave mode. 3 SOD R/W 0 2 MS R/W 0 SSI Master/Slave Select This bit selects Master or Slave mode and can be modified only when SSI is disabled (SSE=0). The MS values are defined as follows: Value Description 0 1 Device configured as a master. Device configured as a slave. November 30, 2007 Preliminary 351 Synchronous Serial Interface (SSI) Bit/Field 1 Name SSE Type R/W Reset 0 Description SSI Synchronous Serial Port Enable Setting this bit enables SSI operation. The SSE values are defined as follows: Value Description 0 1 SSI operation disabled. SSI operation enabled. Note: This bit must be set to 0 before any control registers are reprogrammed. 0 LBM R/W 0 SSI Loopback Mode Setting this bit enables Loopback Test mode. The LBM values are defined as follows: Value Description 0 1 Normal serial port operation enabled. Output of the transmit serial shift register is connected internally to the input of the receive serial shift register. 352 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 3: SSI Data (SSIDR), offset 0x008 SSIDR is the data register and is 16-bits wide. When SSIDR is read, the entry in the receive FIFO (pointed to by the current FIFO read pointer) is accessed. As data values are removed by the SSI receive logic from the incoming data frame, they are placed into the entry in the receive FIFO (pointed to by the current FIFO write pointer). When SSIDR is written to, the entry in the transmit FIFO (pointed to by the write pointer) is written to. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the SSITx pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits. Received data less than 16 bits is automatically right-justified in the receive buffer. When the SSI is programmed for MICROWIRE frame format, the default size for transmit data is eight bits (the most significant byte is ignored). The receive data size is controlled by the programmer. The transmit FIFO and the receive FIFO are not cleared even when the SSE bit in the SSICR1 register is set to zero. This allows the software to fill the transmit FIFO before enabling the SSI. SSI Data (SSIDR) SSI0 base: 0x4000.8000 Offset 0x008 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 DATA Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 Bit/Field 31:16 Name reserved Type RO Reset 0x0000 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SSI Receive/Transmit Data A read operation reads the receive FIFO. A write operation writes the transmit FIFO. Software must right-justify data when the SSI is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by the transmit logic. The receive logic automatically right-justifies the data. 15:0 DATA R/W 0x0000 November 30, 2007 Preliminary 353 Synchronous Serial Interface (SSI) Register 4: SSI Status (SSISR), offset 0x00C SSISR is a status register that contains bits that indicate the FIFO fill status and the SSI busy status. SSI Status (SSISR) SSI0 base: 0x4000.8000 Offset 0x00C Type RO, reset 0x0000.0003 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 BSY RO 0 RO 0 3 RFF RO 0 RO 0 2 RNE RO 0 RO 0 1 TNF RO 1 RO 0 0 TFE R0 1 Bit/Field 31:5 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SSI Busy Bit The BSY values are defined as follows: Value Description 0 1 SSI is idle. SSI is currently transmitting and/or receiving a frame, or the transmit FIFO is not empty. 4 BSY RO 0 3 RFF RO 0 SSI Receive FIFO Full The RFF values are defined as follows: Value Description 0 1 Receive FIFO is not full. Receive FIFO is full. 2 RNE RO 0 SSI Receive FIFO Not Empty The RNE values are defined as follows: Value Description 0 1 Receive FIFO is empty. Receive FIFO is not empty. 1 TNF RO 1 SSI Transmit FIFO Not Full The TNF values are defined as follows: Value Description 0 1 Transmit FIFO is full. Transmit FIFO is not full. 354 Preliminary November 30, 2007 LM3S6965 Microcontroller Bit/Field 0 Name TFE Type R0 Reset 1 Description SSI Transmit FIFO Empty The TFE values are defined as follows: Value Description 0 1 Transmit FIFO is not empty. Transmit FIFO is empty. November 30, 2007 Preliminary 355 Synchronous Serial Interface (SSI) Register 5: SSI Clock Prescale (SSICPSR), offset 0x010 SSICPSR is the clock prescale register and specifies the division factor by which the system clock must be internally divided before further use. The value programmed into this register must be an even number between 2 and 254. The least-significant bit of the programmed number is hard-coded to zero. If an odd number is written to this register, data read back from this register has the least-significant bit as zero. SSI Clock Prescale (SSICPSR) SSI0 base: 0x4000.8000 Offset 0x010 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 CPSDVSR R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SSI Clock Prescale Divisor This value must be an even number from 2 to 254, depending on the frequency of SSIClk. The LSB always returns 0 on reads. 7:0 CPSDVSR R/W 0x00 356 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 6: SSI Interrupt Mask (SSIIM), offset 0x014 The SSIIM register is the interrupt mask set or clear register. It is a read/write register and all bits are cleared to 0 on reset. On a read, this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask. SSI Interrupt Mask (SSIIM) SSI0 base: 0x4000.8000 Offset 0x014 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 TXIM R/W 0 RO 0 2 RXIM R/W 0 RO 0 1 RTIM R/W 0 RO 0 0 RORIM R/W 0 Bit/Field 31:4 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SSI Transmit FIFO Interrupt Mask The TXIM values are defined as follows: Value Description 0 1 TX FIFO half-full or less condition interrupt is masked. TX FIFO half-full or less condition interrupt is not masked. 3 TXIM R/W 0 2 RXIM R/W 0 SSI Receive FIFO Interrupt Mask The RXIM values are defined as follows: Value Description 0 1 RX FIFO half-full or more condition interrupt is masked. RX FIFO half-full or more condition interrupt is not masked. 1 RTIM R/W 0 SSI Receive Time-Out Interrupt Mask The RTIM values are defined as follows: Value Description 0 1 RX FIFO time-out interrupt is masked. RX FIFO time-out interrupt is not masked. November 30, 2007 Preliminary 357 Synchronous Serial Interface (SSI) Bit/Field 0 Name RORIM Type R/W Reset 0 Description SSI Receive Overrun Interrupt Mask The RORIM values are defined as follows: Value Description 0 1 RX FIFO overrun interrupt is masked. RX FIFO overrun interrupt is not masked. 358 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 7: SSI Raw Interrupt Status (SSIRIS), offset 0x018 The SSIRIS register is the raw interrupt status register. On a read, this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect. SSI Raw Interrupt Status (SSIRIS) SSI0 base: 0x4000.8000 Offset 0x018 Type RO, reset 0x0000.0008 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 TXRIS RO 1 RO 0 2 RXRIS RO 0 RO 0 1 RTRIS RO 0 RO 0 0 RORRIS RO 0 Bit/Field 31:4 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SSI Transmit FIFO Raw Interrupt Status Indicates that the transmit FIFO is half full or less, when set. 3 TXRIS RO 1 2 RXRIS RO 0 SSI Receive FIFO Raw Interrupt Status Indicates that the receive FIFO is half full or more, when set. 1 RTRIS RO 0 SSI Receive Time-Out Raw Interrupt Status Indicates that the receive time-out has occurred, when set. 0 RORRIS RO 0 SSI Receive Overrun Raw Interrupt Status Indicates that the receive FIFO has overflowed, when set. November 30, 2007 Preliminary 359 Synchronous Serial Interface (SSI) Register 8: SSI Masked Interrupt Status (SSIMIS), offset 0x01C The SSIMIS register is the masked interrupt status register. On a read, this register gives the current masked status value of the corresponding interrupt. A write has no effect. SSI Masked Interrupt Status (SSIMIS) SSI0 base: 0x4000.8000 Offset 0x01C Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 TXMIS RO 0 RO 0 2 RXMIS RO 0 RO 0 1 RTMIS RO 0 RO 0 0 RORMIS RO 0 Bit/Field 31:4 Name reserved Type RO Reset 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SSI Transmit FIFO Masked Interrupt Status Indicates that the transmit FIFO is half full or less, when set. 3 TXMIS RO 0 2 RXMIS RO 0 SSI Receive FIFO Masked Interrupt Status Indicates that the receive FIFO is half full or more, when set. 1 RTMIS RO 0 SSI Receive Time-Out Masked Interrupt Status Indicates that the receive time-out has occurred, when set. 0 RORMIS RO 0 SSI Receive Overrun Masked Interrupt Status Indicates that the receive FIFO has overflowed, when set. 360 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 9: SSI Interrupt Clear (SSIICR), offset 0x020 The SSIICR register is the interrupt clear register. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect. SSI Interrupt Clear (SSIICR) SSI0 base: 0x4000.8000 Offset 0x020 Type W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RTIC W1C 0 RO 0 0 RORIC W1C 0 Bit/Field 31:2 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SSI Receive Time-Out Interrupt Clear The RTIC values are defined as follows: Value Description 0 1 No effect on interrupt. Clears interrupt. 1 RTIC W1C 0 0 RORIC W1C 0 SSI Receive Overrun Interrupt Clear The RORIC values are defined as follows: Value Description 0 1 No effect on interrupt. Clears interrupt. November 30, 2007 Preliminary 361 Synchronous Serial Interface (SSI) Register 10: SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset value. SSI Peripheral Identification 4 (SSIPeriphID4) SSI0 base: 0x4000.8000 Offset 0xFD0 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 PID4 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SSI Peripheral ID Register[7:0] Can be used by software to identify the presence of this peripheral. 7:0 PID4 RO 0x00 362 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 11: SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset value. SSI Peripheral Identification 5 (SSIPeriphID5) SSI0 base: 0x4000.8000 Offset 0xFD4 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 PID5 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SSI Peripheral ID Register[15:8] Can be used by software to identify the presence of this peripheral. 7:0 PID5 RO 0x00 November 30, 2007 Preliminary 363 Synchronous Serial Interface (SSI) Register 12: SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset value. SSI Peripheral Identification 6 (SSIPeriphID6) SSI0 base: 0x4000.8000 Offset 0xFD8 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 PID6 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SSI Peripheral ID Register[23:16] Can be used by software to identify the presence of this peripheral. 7:0 PID6 RO 0x00 364 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 13: SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset value. SSI Peripheral Identification 7 (SSIPeriphID7) SSI0 base: 0x4000.8000 Offset 0xFDC Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 PID7 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SSI Peripheral ID Register[31:24] Can be used by software to identify the presence of this peripheral. 7:0 PID7 RO 0x00 November 30, 2007 Preliminary 365 Synchronous Serial Interface (SSI) Register 14: SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset value. SSI Peripheral Identification 0 (SSIPeriphID0) SSI0 base: 0x4000.8000 Offset 0xFE0 Type RO, reset 0x0000.0022 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 PID0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 0 RO 0 RO 0 RO 1 RO 0 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SSI Peripheral ID Register[7:0] Can be used by software to identify the presence of this peripheral. 7:0 PID0 RO 0x22 366 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 15: SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset value. SSI Peripheral Identification 1 (SSIPeriphID1) SSI0 base: 0x4000.8000 Offset 0xFE4 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 PID1 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SSI Peripheral ID Register [15:8] Can be used by software to identify the presence of this peripheral. 7:0 PID1 RO 0x00 November 30, 2007 Preliminary 367 Synchronous Serial Interface (SSI) Register 16: SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset value. SSI Peripheral Identification 2 (SSIPeriphID2) SSI0 base: 0x4000.8000 Offset 0xFE8 Type RO, reset 0x0000.0018 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 PID2 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 1 RO 0 RO 0 RO 0 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SSI Peripheral ID Register [23:16] Can be used by software to identify the presence of this peripheral. 7:0 PID2 RO 0x18 368 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 17: SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset value. SSI Peripheral Identification 3 (SSIPeriphID3) SSI0 base: 0x4000.8000 Offset 0xFEC Type RO, reset 0x0000.0001 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 PID3 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SSI Peripheral ID Register [31:24] Can be used by software to identify the presence of this peripheral. 7:0 PID3 RO 0x01 November 30, 2007 Preliminary 369 Synchronous Serial Interface (SSI) Register 18: SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 The SSIPCellIDn registers are hard-coded and the fields within the register determine the reset value. SSI PrimeCell Identification 0 (SSIPCellID0) SSI0 base: 0x4000.8000 Offset 0xFF0 Type RO, reset 0x0000.000D 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 CID0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 1 RO 0 RO 1 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SSI PrimeCell ID Register [7:0] Provides software a standard cross-peripheral identification system. 7:0 CID0 RO 0x0D 370 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 19: SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 The SSIPCellIDn registers are hard-coded and the fields within the register determine the reset value. SSI PrimeCell Identification 1 (SSIPCellID1) SSI0 base: 0x4000.8000 Offset 0xFF4 Type RO, reset 0x0000.00F0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 CID1 RO 0 RO 0 RO 0 RO 1 RO 1 RO 1 RO 1 RO 0 RO 0 RO 0 RO 0 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SSI PrimeCell ID Register [15:8] Provides software a standard cross-peripheral identification system. 7:0 CID1 RO 0xF0 November 30, 2007 Preliminary 371 Synchronous Serial Interface (SSI) Register 20: SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 The SSIPCellIDn registers are hard-coded and the fields within the register determine the reset value. SSI PrimeCell Identification 2 (SSIPCellID2) SSI0 base: 0x4000.8000 Offset 0xFF8 Type RO, reset 0x0000.0005 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 CID2 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 0 RO 1 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SSI PrimeCell ID Register [23:16] Provides software a standard cross-peripheral identification system. 7:0 CID2 RO 0x05 372 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 21: SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC The SSIPCellIDn registers are hard-coded and the fields within the register determine the reset value. SSI PrimeCell Identification 3 (SSIPCellID3) SSI0 base: 0x4000.8000 Offset 0xFFC Type RO, reset 0x0000.00B1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 CID3 RO 0 RO 0 RO 0 RO 1 RO 0 RO 1 RO 1 RO 0 RO 0 RO 0 RO 1 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SSI PrimeCell ID Register [31:24] Provides software a standard cross-peripheral identification system. 7:0 CID3 RO 0xB1 November 30, 2007 Preliminary 373 Inter-Integrated Circuit (I2C) Interface 15 Inter-Integrated Circuit (I2C) Interface The Inter-Integrated Circuit (I2C) bus provides bi-directional data transfer through a two-wire design (a serial data line SDA and a serial clock line SCL), and interfaces to external I2C devices such as serial memory (RAMs and ROMs), networking devices, LCDs, tone generators, and so on. The I2C bus may also be used for system testing and diagnostic purposes in product development and manufacture. The LM3S6965 microcontroller includes two I2C modules, providing the ability to interact (both send and receive) with other I2C devices on the bus. Devices on the I2C bus can be designated as either a master or a slave. Each Stellaris I2C module supports both sending and receiving data as either a master or a slave, and also supports the simultaneous operation as both a master and a slave. There are a total of four I2C modes: Master ® Transmit, Master Receive, Slave Transmit, and Slave Receive. The Stellaris I2C modules can operate at two speeds: Standard (100 Kbps) and Fast (400 Kbps). Both the I2C master and slave can generate interrupts; the I2C master generates interrupts when a transmit or receive operation completes (or aborts due to an error) and the I2C slave generates interrupts when data has been sent or requested by a master. ® 15.1 Block Diagram Figure 15-1. I2C Block Diagram I2C Control I2CMSA I2CMCS I2CMDR Interrupt I2CMTPR I2CMIMR I2CMRIS I2CMMIS I2CMICR I2CMCR I2CSOAR I2CSCSR I2CSDR I2CSIM I2CSRIS I2CSMIS I2CSICR I2C Slave Core I C Master Core 2 I2CSCL I2CSDA I2CSCL I C I/O Select I2CSDA I2CSCL 2 I2CSDA 15.2 Functional Description Each I2C module is comprised of both master and slave functions which are implemented as separate peripherals. For proper operation, the SDA and SCL pins must be connected to bi-directional open-drain pads. A typical I2C bus configuration is shown in Figure 15-2 on page 375. See “I2C” on page 540 for I2C timing diagrams. 374 Preliminary November 30, 2007 LM3S6965 Microcontroller Figure 15-2. I2C Bus Configuration SCL SDA I2CSCL I2CSDA RPUP RPUP I2C Bus SCL SDA SCL SDA StellarisTM 3rd Par ty Device with I2C Interface 3rd Par ty Device with I2C Interface 15.2.1 I2C Bus Functional Overview The I2C bus uses only two signals: SDA and SCL, named I2CSDA and I2CSCL on Stellaris microcontrollers. SDA is the bi-directional serial data line and SCL is the bi-directional serial clock line. The bus is considered idle when both lines are high. Every transaction on the I2C bus is nine bits long, consisting of eight data bits and a single acknowledge bit. The number of bytes per transfer (defined as the time between a valid START and STOP condition, described in “START and STOP Conditions” on page 375) is unrestricted, but each byte has to be followed by an acknowledge bit, and data must be transferred MSB first. When a receiver cannot receive another complete byte, it can hold the clock line SCL Low and force the transmitter into a wait state. The data transfer continues when the receiver releases the clock SCL. ® 15.2.1.1 START and STOP Conditions The protocol of the I2C bus defines two states to begin and end a transaction: START and STOP. A high-to-low transition on the SDA line while the SCL is high is defined as a START condition, and a low-to-high transition on the SDA line while SCL is high is defined as a STOP condition. The bus is considered busy after a START condition and free after a STOP condition. See Figure 15-3 on page 375. Figure 15-3. START and STOP Conditions SDA SCL START condition STOP condition SDA SCL 15.2.1.2 Data Format with 7-Bit Address Data transfers follow the format shown in Figure 15-4 on page 376. After the START condition, a slave address is sent. This address is 7-bits long followed by an eighth bit, which is a data direction bit (R/S bit in the I2CMSA register). A zero indicates a transmit operation (send), and a one indicates a request for data (receive). A data transfer is always terminated by a STOP condition generated by the master, however, a master can initiate communications with another device on the bus by generating a repeated START condition and addressing another slave without first generating a STOP condition. Various combinations of receive/send formats are then possible within a single transfer. November 30, 2007 Preliminary 375 Inter-Integrated Circuit (I2C) Interface Figure 15-4. Complete Data Transfer with a 7-Bit Address SDA MSB LSB R/S ACK MSB LSB ACK SCL 1 2 Slave add ress 7 8 9 1 2 Data 7 8 9 The first seven bits of the first byte make up the slave address (see Figure 15-5 on page 376). The eighth bit determines the direction of the message. A zero in the R/S position of the first byte means that the master will write (send) data to the selected slave, and a one in this position means that the master will receive data from the slave. Figure 15-5. R/S Bit in First Byte MSB LSB R/S Slave address 15.2.1.3 Data Validity The data on the SDA line must be stable during the high period of the clock, and the data line can only change when SCL is low (see Figure 15-6 on page 376). Figure 15-6. Data Validity During Bit Transfer on the I2C Bus SDA SCL g Data line Chan e stable of data allowed 15.2.1.4 Acknowledge All bus transactions have a required acknowledge clock cycle that is generated by the master. During the acknowledge cycle, the transmitter (which can be the master or slave) releases the SDA line. To acknowledge the transaction, the receiver must pull down SDA during the acknowledge clock cycle. The data sent out by the receiver during the acknowledge cycle must comply with the data validity requirements described in “Data Validity” on page 376. When a slave receiver does not acknowledge the slave address, SDA must be left high by the slave so that the master can generate a STOP condition and abort the current transfer. If the master device is acting as a receiver during a transfer, it is responsible for acknowledging each transfer made by the slave. Since the master controls the number of bytes in the transfer, it signals the end of data to the slave transmitter by not generating an acknowledge on the last data byte. The slave transmitter must then release SDA to allow the master to generate the STOP or a repeated START condition. 376 Preliminary November 30, 2007 LM3S6965 Microcontroller 15.2.1.5 Arbitration A master may start a transfer only if the bus is idle. It's possible for two or more masters to generate a START condition within minimum hold time of the START condition. In these situations, an arbitration scheme takes place on the SDA line, while SCL is high. During arbitration, the first of the competing master devices to place a '1' (high) on SDA while another master transmits a '0' (low) will switch off its data output stage and retire until the bus is idle again. Arbitration can take place over several bits. Its first stage is a comparison of address bits, and if both masters are trying to address the same device, arbitration continues on to the comparison of data bits. 15.2.2 Available Speed Modes The I2C clock rate is determined by the parameters: CLK_PRD, TIMER_PRD, SCL_LP, and SCL_HP. where: CLK_PRD is the system clock period SCL_LP is the low phase of SCL (fixed at 6) SCL_HP is the high phase of SCL (fixed at 4) TIMER_PRD is the programmed value in the I2C Master Timer Period (I2CMTPR) register (see page 394). The I2C clock period is calculated as follows: SCL_PERIOD = 2*(1 + TIMER_PRD)*(SCL_LP + SCL_HP)*CLK_PRD For example: CLK_PRD = 50 ns TIMER_PRD = 2 SCL_LP=6 SCL_HP=4 yields a SCL frequency of: 1/T = 333 Khz Table 15-1 on page 377 gives examples of timer period, system clock, and speed mode (Standard or Fast). Table 15-1. Examples of I2C Master Timer Period versus Speed Mode System Clock Timer Period Standard Mode Timer Period Fast Mode 4 Mhz 6 Mhz 12.5 Mhz 16.7 Mhz 20 Mhz 25 Mhz 33Mhz 40Mhz 0x01 0x02 0x06 0x08 0x09 0x0C 0x10 0x13 100 Kbps 100 Kbps 89 Kbps 93 Kbps 100 Kbps 96.2 Kbps 97.1 Kbps 100 Kbps 0x01 0x02 0x02 0x03 0x04 0x04 312 Kbps 278 Kbps 333 Kbps 312 Kbps 330 Kbps 400 Kbps November 30, 2007 Preliminary 377 Inter-Integrated Circuit (I2C) Interface System Clock Timer Period Standard Mode Timer Period Fast Mode 50Mhz 0x18 100 Kbps 0x06 357 Kbps 15.2.3 Interrupts The I2C can generate interrupts when the following conditions are observed: ■ Master transaction completed ■ Master transaction error ■ Slave transaction received ■ Slave transaction requested There is a separate interrupt signal for the I2C master and I2C modules. While both modules can generate interrupts for multiple conditions, only a single interrupt signal is sent to the interrupt controller. 15.2.3.1 I2C Master Interrupts The I2C master module generates an interrupt when a transaction completes (either transmit or receive), or when an error occurs during a transaction. To enable the I2C master interrupt, software must write a '1' to the I2C Master Interrupt Mask (I2CMIMR) register. When an interrupt condition is met, software must check the ERROR bit in the I2C Master Control/Status (I2CMCS) register to verify that an error didn't occur during the last transaction. An error condition is asserted if the last transaction wasn't acknowledge by the slave or if the master was forced to give up ownership of the bus due to a lost arbitration round with another master. If an error is not detected, the application can proceed with the transfer. The interrupt is cleared by writing a '1' to the I2C Master Interrupt Clear (I2CMICR) register. If the application doesn't require the use of interrupts, the raw interrupt status is always visible via the I2C Master Raw Interrupt Status (I2CMRIS) register. 15.2.3.2 I2C Slave Interrupts The slave module generates interrupts as it receives requests from an I2C master. To enable the I2C slave interrupt, write a '1' to the I2C Slave Interrupt Mask (I2CSIMR) register. Software determines whether the module should write (transmit) or read (receive) data from the I2C Slave Data (I2CSDR) register, by checking the RREQ and TREQ bits of the I2C Slave Control/Status (I2CSCSR) register. If the slave module is in receive mode and the first byte of a transfer is received, the FBR bit is set along with the RREQ bit. The interrupt is cleared by writing a '1' to the I2C Slave Interrupt Clear (I2CSICR) register. If the application doesn't require the use of interrupts, the raw interrupt status is always visible via the I2C Slave Raw Interrupt Status (I2CSRIS) register. 15.2.4 Loopback Operation The I2C modules can be placed into an internal loopback mode for diagnostic or debug work. This is accomplished by setting the LPBK bit in the I2C Master Configuration (I2CMCR) register. In loopback mode, the SDA and SCL signals from the master and slave modules are tied together. 378 Preliminary November 30, 2007 LM3S6965 Microcontroller 15.2.5 Command Sequence Flow Charts This section details the steps required to perform the various I2C transfer types in both master and slave mode. 15.2.5.1 I2C Master Command Sequences The figures that follow show the command sequences available for the I2C master. Figure 15-7. Master Single SEND Idle Write Slave Address to I2CMSA Sequence may be omitted in a Single Master system Write data to I2CMDR Read I2CMCS NO BUSBSY bit=0? YES Write ---0-111 to I2CMCS Read I2CMCS NO BUSY bit=0? YES Error Service NO ERROR bit=0? YES Idle November 30, 2007 Preliminary 379 Inter-Integrated Circuit (I2C) Interface Figure 15-8. Master Single RECEIVE Idle Write Slave Address to I2CMSA Sequence may be omitted in a Single Master system Read I2CMCS NO BUSBSY bit=0? YES Write ---00111 to I2CMCS Read I2CMCS NO BUSY bit=0? YES Error Service NO ERROR bit=0? YES Read data from I2CMDR Idle 380 Preliminary November 30, 2007 LM3S6965 Microcontroller Figure 15-9. Master Burst SEND Idle Write Slave Address to I2CMSA Sequence may be omitted in a Single Master system Read I2CMCS Write data to I2CMDR BUSY bit=0? NO Read I2CMCS YES ERROR bit=0? NO NO BUSBSY bit=0? YES YES Write data to I2CMDR NO ARBLST bit=1? Write ---0-011 to I2CMCS Write ---0-001 to I2CMCS NO YES Index=n? Write ---0-100 to I2CMCS YES Error Service Write ---0-101 to I2CMCS Idle Read I2CMCS NO BUSY bit=0? YES Error Service NO ERROR bit=0? YES Idle November 30, 2007 Preliminary 381 Inter-Integrated Circuit (I2C) Interface Figure 15-10. Master Burst RECEIVE Idle Sequence may be omitted in a Single Master system Write Slave Address to I2CMSA Read I2CMCS Read I2CMCS BUSY bit=0? NO YES NO BUSBSY bit=0? ERROR bit=0? YES NO Write ---01011 to I2CMCS Read data from I2CMDR NO ARBLST bit=1? YES Write ---01001 to I2CMCS NO Write ---0-100 to I2CMCS Index=m-1? Error Service YES Write ---00101 to I2CMCS Idle Read I2CMCS BUSY bit=0? NO YES NO ERROR bit=0? YES Error Service Read data from I2CMDR Idle 382 Preliminary November 30, 2007 LM3S6965 Microcontroller Figure 15-11. Master Burst RECEIVE after Burst SEND Idle Master operates in Master Transmit mode STOP condition is not generated Write Slave Address to I2CMSA Write ---01011 to I2CMCS Repeated START condition is generated with changing data direction Master operates in Master Receive mode Idle November 30, 2007 Preliminary 383 Inter-Integrated Circuit (I2C) Interface Figure 15-12. Master Burst SEND after Burst RECEIVE Idle Master operates in Master Receive mode STOP condition is not generated Write Slave Address to I2CMSA Write ---0-011 to I2CMCS Repeated START condition is generated with changing data direction Master operates in Master Transmit mode Idle 15.2.5.2 I2C Slave Command Sequences Figure 15-13 on page 385 presents the command sequence available for the I2C slave. 384 Preliminary November 30, 2007 LM3S6965 Microcontroller Figure 15-13. Slave Command Sequence Idle Write OWN Slave Address to I2CSOAR Write -------1 to I2CSCSR Read I2CSCSR NO TREQ bit=1? NO RREQ bit=1? YES FBR is also valid YES Write data to I2CSDR Read data from I2CSDR 15.3 Initialization and Configuration The following example shows how to configure the I2C module to send a single byte as a master. This assumes the system clock is 20 MHz. 1. Enable the I2C clock by writing a value of 0x0000.1000 to the RCGC1 register in the System Control module. 2. Enable the clock to the appropriate GPIO module via the RCGC2 register in the System Control module. 3. In the GPIO module, enable the appropriate pins for their alternate function using the GPIOAFSEL register. Also, be sure to enable the same pins for Open Drain operation. 4. Initialize the I2C Master by writing the I2CMCR register with a value of 0x0000.0020. 5. Set the desired SCL clock speed of 100 Kbps by writing the I2CMTPR register with the correct value. The value written to the I2CMTPR register represents the number of system clock periods in one SCL clock period. The TPR value is determined by the following equation: November 30, 2007 Preliminary 385 Inter-Integrated Circuit (I2C) Interface TPR = (System Clock / (2 * (SCL_LP + SCL_HP) * SCL_CLK)) - 1; TPR = (20MHz / (2 * (6 + 4) * 100000)) - 1; TPR = 9 Write the I2CMTPR register with the value of 0x0000.0009. 6. Specify the slave address of the master and that the next operation will be a Send by writing the I2CMSA register with a value of 0x0000.0076. This sets the slave address to 0x3B. 7. Place data (byte) to be sent in the data register by writing the I2CMDR register with the desired data. 8. Initiate a single byte send of the data from Master to Slave by writing the I2CMCS register with a value of 0x0000.0007 (STOP, START, RUN). 9. Wait until the transmission completes by polling the I2CMCS register ’s BUSBSY bit until it has been cleared. 15.4 I2C Register Map Table 15-2 on page 386 lists the I2C registers. All addresses given are relative to the I2C base addresses for the master and slave: ■ I2C Master 0: 0x4002.0000 ■ I2C Slave 0: 0x4002.0800 ■ I2C Master 1: 0x4002.1000 ■ I2C Slave 1: 0x4002.1800 Table 15-2. Inter-Integrated Circuit (I2C) Interface Register Map Offset I2C Master 0x000 0x004 0x008 0x00C 0x010 0x014 0x018 0x01C 0x020 I2C Slave I2CSOAR R/W 0x0000.0000 I2C Slave Own Address 401 I2CMSA I2CMCS I2CMDR I2CMTPR I2CMIMR I2CMRIS I2CMMIS I2CMICR I2CMCR R/W R/W R/W R/W R/W RO RO WO R/W 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0001 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 I2C Master Slave Address I2C Master Control/Status I2C Master Data I2C Master Timer Period I2C Master Interrupt Mask I2C Master Raw Interrupt Status I2C Master Masked Interrupt Status I2C Master Interrupt Clear I2C Master Configuration 388 389 393 394 395 396 397 398 399 Name Type Reset Description See page 0x000 386 Preliminary November 30, 2007 LM3S6965 Microcontroller Offset 0x004 0x008 0x00C 0x010 0x014 0x018 Name I2CSCSR I2CSDR I2CSIMR I2CSRIS I2CSMIS I2CSICR Type RO R/W R/W RO RO WO Reset 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 Description I2C Slave Control/Status I2C Slave Data I2C Slave Interrupt Mask I2C Slave Raw Interrupt Status I2C Slave Masked Interrupt Status I2C Slave Interrupt Clear See page 402 404 405 406 407 408 15.5 Register Descriptions (I2C Master) The remainder of this section lists and describes the I2C master registers, in numerical order by address offset. See also “Register Descriptions (I2C Slave)” on page 400. November 30, 2007 Preliminary 387 Inter-Integrated Circuit (I2C) Interface Register 1: I2C Master Slave Address (I2CMSA), offset 0x000 This register consists of eight bits: seven address bits (A6-A0), and a Receive/Send bit, which determines if the next operation is a Receive (High), or Send (Low). I2C Master Slave Address (I2CMSA) I2C Master 0 base: 0x4002.0000 I2C Master 1 base: 0x4002.1000 Offset 0x000 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 SA RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 RO 0 3 RO 0 2 RO 0 1 RO 0 0 R/S R/W 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. I2C Slave Address This field specifies bits A6 through A0 of the slave address. 7:1 SA R/W 0 0 R/S R/W 0 Receive/Send The R/S bit specifies if the next operation is a Receive (High) or Send (Low). Value Description 0 1 Send. Receive. 388 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 2: I2C Master Control/Status (I2CMCS), offset 0x004 This register accesses four control bits when written, and accesses seven status bits when read. The status register consists of seven bits, which when read determine the state of the I2C bus controller. The control register consists of four bits: the RUN, START, STOP, and ACK bits. The START bit causes the generation of the START, or REPEATED START condition. The STOP bit determines if the cycle stops at the end of the data cycle, or continues on to a burst. To generate a single send cycle, the I2C Master Slave Address (I2CMSA) register is written with the desired address, the R/S bit is set to 0, and the Control register is written with ACK=X (0 or 1), STOP=1, START=1, and RUN=1 to perform the operation and stop. When the operation is completed (or aborted due an error), the interrupt pin becomes active and the data may be read from the I2CMDR register. When the I2C module operates in Master receiver mode, the ACK bit must be set normally to logic 1. This causes the I2C bus controller to send an acknowledge automatically after each byte. This bit must be reset when the I2C bus controller requires no further data to be sent from the slave transmitter. Read-Only Status Register I2C Master Control/Status (I2CMCS) I2C Master 0 base: 0x4002.0000 I2C Master 1 base: 0x4002.1000 Offset 0x004 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 BUSBSY RO 0 RO 0 5 IDLE RO 0 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 BUSY RO 0 ARBLST DATACK ADRACK ERROR RO 0 RO 0 RO 0 RO 0 Bit/Field 31:7 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Bus Busy This bit specifies the state of the I2C bus. If set, the bus is busy; otherwise, the bus is idle. The bit changes based on the START and STOP conditions. 6 BUSBSY RO 0 5 IDLE RO 0 I2C Idle This bit specifies the I2C controller state. If set, the controller is idle; otherwise the controller is not idle. 4 ARBLST RO 0 Arbitration Lost This bit specifies the result of bus arbitration. If set, the controller lost arbitration; otherwise, the controller won arbitration. November 30, 2007 Preliminary 389 Inter-Integrated Circuit (I2C) Interface Bit/Field 3 Name DATACK Type RO Reset 0 Description Acknowledge Data This bit specifies the result of the last data operation. If set, the transmitted data was not acknowledged; otherwise, the data was acknowledged. 2 ADRACK RO 0 Acknowledge Address This bit specifies the result of the last address operation. If set, the transmitted address was not acknowledged; otherwise, the address was acknowledged. 1 ERROR RO 0 Error This bit specifies the result of the last bus operation. If set, an error occurred on the last operation; otherwise, no error was detected. The error can be from the slave address not being acknowledged, the transmit data not being acknowledged, or because the controller lost arbitration. 0 BUSY RO 0 I2C Busy This bit specifies the state of the controller. If set, the controller is busy; otherwise, the controller is idle. When the BUSY bit is set, the other status bits are not valid. Write-Only Control Register I2C Master Control/Status (I2CMCS) I2C Master 0 base: 0x4002.0000 I2C Master 1 base: 0x4002.1000 Offset 0x004 Type WO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset WO 0 15 WO 0 14 WO 0 13 WO 0 12 WO 0 11 WO 0 10 reserved Type Reset WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 9 WO 0 8 WO 0 7 WO 0 6 WO 0 5 WO 0 4 WO 0 3 ACK WO 0 WO 0 2 STOP WO 0 WO 0 1 START WO 0 WO 0 0 RUN WO 0 Bit/Field 31:4 Name reserved Type WO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Data Acknowledge Enable When set, causes received data byte to be acknowledged automatically by the master. See field decoding in Table 15-3 on page 391. 3 ACK WO 0 2 STOP WO 0 Generate STOP When set, causes the generation of the STOP condition. See field decoding in Table 15-3 on page 391. 390 Preliminary November 30, 2007 LM3S6965 Microcontroller Bit/Field 1 Name START Type WO Reset 0 Description Generate START When set, causes the generation of a START or repeated START condition. See field decoding in Table 15-3 on page 391. 0 RUN WO 0 I2C Master Enable When set, allows the master to send or receive data. See field decoding in Table 15-3 on page 391. Table 15-3. Write Field Decoding for I2CMCS[3:0] Field (Sheet 1 of 3) Current I2CMSA[0] State R/S Idle 0 0 1 1 1 1 I2CMCS[3:0] ACK X a Description RUN 1 1 1 1 1 1 START condition followed by SEND (master goes to the Master Transmit state). START condition followed by a SEND and STOP condition (master remains in Idle state). START condition followed by RECEIVE operation with negative ACK (master goes to the Master Receive state). START condition followed by RECEIVE and STOP condition (master remains in Idle state). START condition followed by RECEIVE (master goes to the Master Receive state). Illegal. STOP 0 1 0 1 0 1 START 1 1 1 1 1 1 X 0 0 1 1 All other combinations not listed are non-operations. NOP. Master Transmit X X X 0 0 1 X X X X X 0 0 1 1 0 1 0 0 0 0 1 1 1 1 0 1 1 1 1 SEND operation (master remains in Master Transmit state). STOP condition (master goes to Idle state). SEND followed by STOP condition (master goes to Idle state). Repeated START condition followed by a SEND (master remains in Master Transmit state). Repeated START condition followed by SEND and STOP condition (master goes to Idle state). Repeated START condition followed by a RECEIVE operation with a negative ACK (master goes to Master Receive state). Repeated START condition followed by a SEND and STOP condition (master goes to Idle state). Repeated START condition followed by RECEIVE (master goes to Master Receive state). Illegal. 1 1 1 0 1 1 1 0 1 1 1 1 1 1 1 All other combinations not listed are non-operations. NOP. November 30, 2007 Preliminary 391 Inter-Integrated Circuit (I2C) Interface Current I2CMSA[0] State R/S Master Receive X X X X X 1 I2CMCS[3:0] ACK 0 X 0 1 1 0 STOP 0 1 1 0 1 0 START 0 0 0 0 0 1 RUN 1 0 1 1 1 1 Description RECEIVE operation with negative ACK (master remains in Master Receive state). STOP condition (master goes to Idle state). b RECEIVE followed by STOP condition (master goes to Idle state). RECEIVE operation (master remains in Master Receive state). Illegal. Repeated START condition followed by RECEIVE operation with a negative ACK (master remains in Master Receive state). Repeated START condition followed by RECEIVE and STOP condition (master goes to Idle state). Repeated START condition followed by RECEIVE (master remains in Master Receive state). Repeated START condition followed by SEND (master goes to Master Transmit state). Repeated START condition followed by SEND and STOP condition (master goes to Idle state). 1 1 0 0 0 1 X X 1 0 0 1 1 1 1 1 1 1 1 1 All other combinations not listed are non-operations. NOP. a. An X in a table cell indicates the bit can be 0 or 1. b. In Master Receive mode, a STOP condition should be generated only after a Data Negative Acknowledge executed by the master or an Address Negative Acknowledge executed by the slave. 392 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 3: I2C Master Data (I2CMDR), offset 0x008 This register contains the data to be transmitted when in the Master Transmit state, and the data received when in the Master Receive state. I2C Master Data (I2CMDR) I2C Master 0 base: 0x4002.0000 I2C Master 1 base: 0x4002.1000 Offset 0x008 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 DATA RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Data Transferred Data transferred during transaction. 7:0 DATA R/W 0x00 November 30, 2007 Preliminary 393 Inter-Integrated Circuit (I2C) Interface Register 4: I2C Master Timer Period (I2CMTPR), offset 0x00C This register specifies the period of the SCL clock. I2C Master Timer Period (I2CMTPR) I2C Master 0 base: 0x4002.0000 I2C Master 1 base: 0x4002.1000 Offset 0x00C Type R/W, reset 0x0000.0001 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 TPR RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 1 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. SCL Clock Period This field specifies the period of the SCL clock. SCL_PRD = 2*(1 + TPR)*(SCL_LP + SCL_HP)*CLK_PRD where: SCL_PRD is the SCL line period (I2C clock). TPR is the Timer Period register value (range of 1 to 255). SCL_LP is the SCL Low period (fixed at 6). SCL_HP is the SCL High period (fixed at 4). 7:0 TPR R/W 0x1 394 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 5: I2C Master Interrupt Mask (I2CMIMR), offset 0x010 This register controls whether a raw interrupt is promoted to a controller interrupt. I2C Master Interrupt Mask (I2CMIMR) I2C Master 0 base: 0x4002.0000 I2C Master 1 base: 0x4002.1000 Offset 0x010 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 IM R/W 0 Bit/Field 31:1 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Interrupt Mask This bit controls whether a raw interrupt is promoted to a controller interrupt. If set, the interrupt is not masked and the interrupt is promoted; otherwise, the interrupt is masked. 0 IM R/W 0 November 30, 2007 Preliminary 395 Inter-Integrated Circuit (I2C) Interface Register 6: I2C Master Raw Interrupt Status (I2CMRIS), offset 0x014 This register specifies whether an interrupt is pending. I2C Master Raw Interrupt Status (I2CMRIS) I2C Master 0 base: 0x4002.0000 I2C Master 1 base: 0x4002.1000 Offset 0x014 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 RIS RO 0 Bit/Field 31:1 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Raw Interrupt Status This bit specifies the raw interrupt state (prior to masking) of the I2C master block. If set, an interrupt is pending; otherwise, an interrupt is not pending. 0 RIS RO 0 396 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 7: I2C Master Masked Interrupt Status (I2CMMIS), offset 0x018 This register specifies whether an interrupt was signaled. I2C Master Masked Interrupt Status (I2CMMIS) I2C Master 0 base: 0x4002.0000 I2C Master 1 base: 0x4002.1000 Offset 0x018 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 MIS RO 0 Bit/Field 31:1 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Masked Interrupt Status This bit specifies the raw interrupt state (after masking) of the I2C master block. If set, an interrupt was signaled; otherwise, an interrupt has not been generated since the bit was last cleared. 0 MIS RO 0 November 30, 2007 Preliminary 397 Inter-Integrated Circuit (I2C) Interface Register 8: I2C Master Interrupt Clear (I2CMICR), offset 0x01C This register clears the raw interrupt. I2C Master Interrupt Clear (I2CMICR) I2C Master 0 base: 0x4002.0000 I2C Master 1 base: 0x4002.1000 Offset 0x01C Type WO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 IC WO 0 Bit/Field 31:1 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Interrupt Clear This bit controls the clearing of the raw interrupt. A write of 1 clears the interrupt; otherwise, a write of 0 has no affect on the interrupt state. A read of this register returns no meaningful data. 0 IC WO 0 398 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 9: I2C Master Configuration (I2CMCR), offset 0x020 This register configures the mode (Master or Slave) and sets the interface for test mode loopback. I2C Master Configuration (I2CMCR) I2C Master 0 base: 0x4002.0000 I2C Master 1 base: 0x4002.1000 Offset 0x020 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 SFE RO 0 RO 0 RO 0 RO 0 R/W 0 RO 0 4 MFE R/W 0 RO 0 RO 0 3 RO 0 2 reserved RO 0 RO 0 RO 0 1 RO 0 0 LPBK R/W 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:6 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. I2C Slave Function Enable This bit specifies whether the interface may operate in Slave mode. If set, Slave mode is enabled; otherwise, Slave mode is disabled. 5 SFE R/W 0 4 MFE R/W 0 I2C Master Function Enable This bit specifies whether the interface may operate in Master mode. If set, Master mode is enabled; otherwise, Master mode is disabled and the interface clock is disabled. 3:1 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. I2C Loopback This bit specifies whether the interface is operating normally or in Loopback mode. If set, the device is put in a test mode loopback configuration; otherwise, the device operates normally. 0 LPBK R/W 0 November 30, 2007 Preliminary 399 Inter-Integrated Circuit (I2C) Interface 15.6 Register Descriptions (I2C Slave) The remainder of this section lists and describes the I2C slave registers, in numerical order by address offset. See also “Register Descriptions (I2C Master)” on page 387. 400 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 10: I2C Slave Own Address (I2CSOAR), offset 0x000 This register consists of seven address bits that identify the Stellaris I2C device on the I2C bus. I2C Slave Own Address (I2CSOAR) I2C Slave 0 base: 0x4002.0800 I2C Slave 1 base: 0x4002.1800 Offset 0x000 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ® reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 OAR R/W 0 R/W 0 R/W 0 R/W 0 RO 0 2 RO 0 1 RO 0 0 Bit/Field 31:7 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. I2C Slave Own Address This field specifies bits A6 through A0 of the slave address. 6:0 OAR R/W 0x00 November 30, 2007 Preliminary 401 Inter-Integrated Circuit (I2C) Interface Register 11: I2C Slave Control/Status (I2CSCSR), offset 0x004 This register accesses one control bit when written, and three status bits when read. The read-only Status register consists of three bits: the FBR, RREQ, and TREQ bits. The First ® Byte Received (FBR) bit is set only after the Stellaris device detects its own slave address and receives the first data byte from the I2C master. The Receive Request (RREQ) bit indicates ® that the Stellaris I2C device has received a data byte from an I2C master. Read one data byte from the I2C Slave Data (I2CSDR) register to clear the RREQ bit. The Transmit Request (TREQ) bit ® indicates that the Stellaris I2C device is addressed as a Slave Transmitter. Write one data byte 2C Slave Data (I2CSDR) register to clear the TREQ bit. into the I The write-only Control register consists of one bit: the DA bit. The DA bit enables and disables the ® Stellaris I2C slave operation. Read-Only Status Register I2C Slave Control/Status (I2CSCSR) I2C Slave 0 base: 0x4002.0800 I2C Slave 1 base: 0x4002.1800 Offset 0x004 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 FBR RO 0 RO 0 1 TREQ RO 0 RO 0 0 RREQ RO 0 Bit/Field 31:3 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. First Byte Received Indicates that the first byte following the slave’s own address is received. This bit is only valid when the RREQ bit is set, and is automatically cleared when data has been read from the I2CSDR register. Note: This bit is not used for slave transmit operations. 2 FBR RO 0 1 TREQ RO 0 Transmit Request This bit specifies the state of the I2C slave with regards to outstanding transmit requests. If set, the I2C unit has been addressed as a slave transmitter and uses clock stretching to delay the master until data has been written to the I2CSDR register. Otherwise, there is no outstanding transmit request. 0 RREQ RO 0 Receive Request This bit specifies the status of the I2C slave with regards to outstanding receive requests. If set, the I2C unit has outstanding receive data from the I2C master and uses clock stretching to delay the master until the data has been read from the I2CSDR register. Otherwise, no receive data is outstanding. 402 Preliminary November 30, 2007 LM3S6965 Microcontroller Write-Only Control Register I2C Slave Control/Status (I2CSCSR) I2C Slave 0 base: 0x4002.0800 I2C Slave 1 base: 0x4002.1800 Offset 0x004 Type WO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 DA WO 0 Bit/Field 31:1 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Device Active Value Description 0 1 Disables the I2C slave operation. Enables the I2C slave operation. 0 DA WO 0 November 30, 2007 Preliminary 403 Inter-Integrated Circuit (I2C) Interface Register 12: I2C Slave Data (I2CSDR), offset 0x008 This register contains the data to be transmitted when in the Slave Transmit state, and the data received when in the Slave Receive state. I2C Slave Data (I2CSDR) I2C Slave 0 base: 0x4002.0800 I2C Slave 1 base: 0x4002.1800 Offset 0x008 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 DATA RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Data for Transfer This field contains the data for transfer during a slave receive or transmit operation. 7:0 DATA R/W 0x0 404 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 13: I2C Slave Interrupt Mask (I2CSIMR), offset 0x00C This register controls whether a raw interrupt is promoted to a controller interrupt. I2C Slave Interrupt Mask (I2CSIMR) I2C Slave 0 base: 0x4002.0800 I2C Slave 1 base: 0x4002.1800 Offset 0x00C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 IM R/W 0 Bit/Field 31:1 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Interrupt Mask This bit controls whether a raw interrupt is promoted to a controller interrupt. If set, the interrupt is not masked and the interrupt is promoted; otherwise, the interrupt is masked. 0 IM R/W 0 November 30, 2007 Preliminary 405 Inter-Integrated Circuit (I2C) Interface Register 14: I2C Slave Raw Interrupt Status (I2CSRIS), offset 0x010 This register specifies whether an interrupt is pending. I2C Slave Raw Interrupt Status (I2CSRIS) I2C Slave 0 base: 0x4002.0800 I2C Slave 1 base: 0x4002.1800 Offset 0x010 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 RIS RO 0 Bit/Field 31:1 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Raw Interrupt Status This bit specifies the raw interrupt state (prior to masking) of the I2C slave block. If set, an interrupt is pending; otherwise, an interrupt is not pending. 0 RIS RO 0 406 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 15: I2C Slave Masked Interrupt Status (I2CSMIS), offset 0x014 This register specifies whether an interrupt was signaled. I2C Slave Masked Interrupt Status (I2CSMIS) I2C Slave 0 base: 0x4002.0800 I2C Slave 1 base: 0x4002.1800 Offset 0x014 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 MIS RO 0 Bit/Field 31:1 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Masked Interrupt Status This bit specifies the raw interrupt state (after masking) of the I2C slave block. If set, an interrupt was signaled; otherwise, an interrupt has not been generated since the bit was last cleared. 0 MIS RO 0 November 30, 2007 Preliminary 407 Inter-Integrated Circuit (I2C) Interface Register 16: I2C Slave Interrupt Clear (I2CSICR), offset 0x018 This register clears the raw interrupt. I2C Slave Interrupt Clear (I2CSICR) I2C Slave 0 base: 0x4002.0800 I2C Slave 1 base: 0x4002.1800 Offset 0x018 Type WO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 IC WO 0 Bit/Field 31:1 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Clear Interrupt This bit controls the clearing of the raw interrupt. A write of 1 clears the interrupt; otherwise a write of 0 has no affect on the interrupt state. A read of this register returns no meaningful data. 0 IC WO 0 408 Preliminary November 30, 2007 LM3S6965 Microcontroller 16 Ethernet Controller The Stellaris Ethernet Controller consists of a fully integrated media access controller (MAC) and network physical (PHY) interface device. The Ethernet Controller conforms to IEEE 802.3 specifications and fully supports 10BASE-T and 100BASE-TX standards. The Ethernet Controller module has the following features: ■ Conforms to the IEEE 802.3-2002 specification – 10BASE-T/100BASE-TX IEEE-802.3 compliant. Requires only a dual 1:1 isolation transformer interface to the line – 10BASE-T/100BASE-TX ENDEC, 100BASE-TX scrambler/descrambler – Full-featured auto-negotiation ■ Multiple operational modes – Full- and half-duplex 100 Mbps – Full- and half-duplex 10 Mbps – Power-saving and power-down modes ■ Highly configurable – Programmable MAC address – LED activity selection – Promiscuous mode support – CRC error-rejection control – User-configurable interrupts ■ Physical media manipulation – Automatic MDI/MDI-X cross-over correction – Register-programmable transmit amplitude – Automatic polarity correction and 10BASE-T signal reception ® November 30, 2007 Preliminary 409 Ethernet Controller 16.1 Block Diagram Figure 16-1. Ethernet Controller Block Diagram Interrupt Control MACISR MACIACK MACIMR Interrupt Receive Control MACRCR MACNPR TXOP Transmit FIFO Transmit Encoding Pulse Shaping TXON System Clock Data Access MACDR Collision Detect Carrier Sense MDIX RXIP Transmit Control MACTCR MACITHR MACTRR Receive FIFO Receive Decoding Clock Recovery RXIN MII Control Individual Address MACIAR0 MACIAR1 MACMCR MACMDVR MACMAR MACMDTX MACMDRX Media Independent Interface Management Register Set MR0 MR1 MR2 MR3 MR4 MR5 MR6 MR16 MR17 MR18 MR19 MR23 MR24 Auto Negotiation XTLP Clock Reference XTLN 16.2 Functional Description As shown in Figure 16-2 on page 410, the Ethernet Controller is functionally divided into two layers or modules: the Media Access Controller (MAC) layer and the Network Physical (PHY) layer. These correspond to the OSI model layers 2 and 1. The primary interface to the Ethernet Controller is a simple bus interface to the MAC layer. The MAC layer provides transmit and receive processing for Ethernet frames. The MAC layer also provides the interface to the PHY module via an internal Media Independent Interface (MII). Figure 16-2. Ethernet Controller Ethernet Controller Media Access Controller MAC (Layer 2) Physical Layer Entity PHY (Layer 1) Cortex M3 Magnetics RJ45 16.2.1 Internal MII Operation For the MII management interface to function properly, the MDIO signal must be connected through a 10k Ω pull-up resistor to the +3.3 V supply. Failure to connect this pull-up resistor will prevent management transactions on this internal MII to function. Note that it is possible for data transmission across the MII to still function since the PHY layer will auto-negotiate the link parameters by default. 410 Preliminary November 30, 2007 LM3S6965 Microcontroller For the MII management interface to function properly, the internal clock must be divided down from the system clock to a frequency no greater than 2.5 MHz. The MACMDV register contains the divider used for scaling down the system clock. See page 430 for more details about the use of this register. 16.2.2 PHY Configuration/Operation The Physical Layer (PHY) in the Ethernet Controller includes integrated ENDECs, scrambler/descrambler, dual-speed clock recovery, and full-featured auto-negotiation functions. The transmitter includes an on-chip pulse shaper and a low-power line driver. The receiver has an adaptive equalizer and a baseline restoration circuit required for accurate clock and data recovery. The transceiver interfaces to Category-5 unshielded twisted pair (Cat-5 UTP) cabling for 100BASE-TX applications, and Category-3 unshielded twisted pair (Cat-3 UTP) for 10BASE-T applications. The Ethernet Controller is connected to the line media via dual 1:1 isolation transformers. No external filter is required. 16.2.2.1 Clock Selection The PHY has an on-chip crystal oscillator which can also be driven by an external oscillator. In this mode of operation, a 25-MHz crystal should be connected between the XTALPPHY and XTALNPHY pins. Alternatively, an external 25-MHz clock input can be connected to the XTALPPHY pin. In this mode of operation, a crystal is not required and the XTALNPHY pin must be tied to ground. 16.2.2.2 Auto-Negotiation The PHY supports the auto-negotiation functions of Clause 28 of the IEEE 802.3 standard for 10/100 Mbps operation over copper wiring. This function can be enabled via register settings. The auto-negotiation function defaults to On and the ANEGEN bit in the MR0 register is High after reset. Software can disable the auto-negotiation function by writing to the ANEGEN bit. The contents of the MR4 register are sent to the PHY’s link partner during auto-negotiation via fast-link pulse coding. Once auto-negotiation is complete, the DPLX and RATE bits in the MR18 register reflect the actual speed and duplex that was chosen. If auto-negotiation fails to establish a link for any reason, the ANEGF bit in the MR18 register reflects this and auto-negotiation restarts from the beginning. Writing a 1 to the RANEG bit in the MR0 register also causes auto-negotiation to restart. 16.2.2.3 Polarity Correction The PHY is capable of either automatic or manual polarity reversal for 10BASE-T and auto-negotiation functions. Bits 4 and 5 (RVSPOL and APOL) in the MR16 register control this feature. The default is automatic mode, where APOL is Low and RVSPOL indicates if the detection circuitry has inverted the input signal. To enter manual mode, APOL should be set High and RVSPOL then controls the signal polarity. 16.2.2.4 MDI/MDI-X Configuration The PHY supports the automatic MDI/MDI-X configuration as defined in IEEE 802.3-2002 specification. This eliminates the need for cross-over cables when connecting to another device, such as a hub. The algorithm is controlled via settings in the MR24 register. Refer to page 452 for additional details about these settings. 16.2.2.5 LED Indicators The PHY supports two LED signals that can be used to indicate various states of operation of the Ethernet Controller. These signals are mapped to the LED0 and LED1 pins. By default, these pins are configured as GPIO signals (PF3 and PF2). For the PHY layer to drive these signals, they must be reconfigured to their hardware function. See “General-Purpose Input/Outputs (GPIOs)” on page November 30, 2007 Preliminary 411 Ethernet Controller 163 for additional details. The function of these pins is programmable via the PHY layer MR23 register. Refer to page 451 for additonal details on how to program these LED functions. 16.2.3 MAC Configuration/Operation 16.2.3.1 Ethernet Frame Format Ethernet data is carried by Ethernet frames. The basic frame format is shown in Figure 16-3 on page 412. Figure 16-3. Ethernet Frame Preamble 7 Bytes SFD Destination Address 1 Byte 6 Bytes Source Address 6 Bytes Length/ Type 2 Bytes Data 46 - 1500 Bytes FCS 4 Bytes The seven fields of the frame are transmitted from left to right. The bits within the frame are transmitted from least to most significant bit. ■ Preamble The Preamble field is used by the physical layer signaling circuitry to synchronize with the received frame’s timing. The preamble is 7 octets long. ■ Start Frame Delimiter (SFD) The SFD field follows the preamble pattern and indicates the start of the frame. Its value is 1010.1011. ■ Destination Address (DA) This field specifies destination addresses for which the frame is intended. The LSB of the DA determines whether the address is an individual (0), or group/multicast (1) address. ■ Source Address (SA) The source address field identifies the station from which the frame was initiated. ■ Length/Type Field The meaning of this field depends on its numeric value. The first of two octets is most significant. This field can be interpreted as length or type code. The maximum length of the data field is 1500 octets. If the value of the Length/Type field is less than or equal to 1500 decimal, it indicates the number of MAC client data octets. If the value of this field is greater than or equal to 1536 decimal, then it is type interpretation. The meaning of the Length/Type field when the value is between 1500 and 1536 decimal is unspecified by the standard. The MAC module assumes type interpretation if the value of the Length/Type field is greater than 1500 decimal. ■ Data The data field is a sequence of 0 to 1500 octets. Full data transparency is provided so any values can appear in this field. A minimum frame size is required to properly meet the IEEE standard. If necessary, the data field is extended by appending extra bits (a pad). The pad field can have a size of 0 to 46 octets. The sum of the data and pad lengths must be a minimum of 46 octets. The MAC module automatically inserts pads if required, though it can be disabled by a register 412 Preliminary November 30, 2007 LM3S6965 Microcontroller write. For the MAC module core, data sent/received can be larger than 1500 bytes, and no Frame Too Long error is reported. Instead, a FIFO Overrun error is reported when the frame received is too large to fit into the Ethernet Controller ’s RAM. ■ Frame Check Sequence (FCS) The frame check sequence carries the cyclic redundancy check (CRC) value. The value of this field is computed over destination address, source address, length/type, data, and pad fields using the CRC-32 algorithm. The MAC module computes the FCS value one nibble at a time. For transmitted frames, this field is automatically inserted by the MAC layer, unless disabled by the CRC bit in the MACTCTL register. For received frames, this field is automatically checked. If the FCS does not pass, the frame will not be placed in the RX FIFO, unless the FCS check is disabled by the BADCRC bit in the MACRCTL register. 16.2.3.2 MAC Layer FIFOs For Ethernet frame transmission, a 2 KB TX FIFO is provided that can be used to store a single frame. While the IEEE 802.3 specification limits the size of an Ethernet frame's payload section to 1500 Bytes, the Ethernet Controller places no such limit. The full buffer can be used, for a payload of up to 2032 bytes. For Ethernet frame reception, a 2-KB RX FIFO is provided that can be used to store multiple frames, up to a maximum of 31 frames. If a frame is received and there is insufficient space in the RX FIFO, an overflow error will be indicated. For details regarding the TX and RX FIFO layout, refer to Table 16-1 on page 413. Please note the following difference between TX and RX FIFO layout. For the TX FIFO, the Data Length field in the first FIFO word refers to the Ethernet frame data payload, as shown in the 5th to nth FIFO positions. For the RX FIFO, the Frame Length field is the total length of the received Ethernet frame, including the FCS and Frame Length bytes. Also note that if FCS generation is disabled with the CRC bit in the MACTCTL register, the last word in the FIFO must be the FCS bytes for the frame that has been written to the FIFO. Also note that if the length of the data payload section is not a multiple of 4, the FCS field will overlap words in the FIFO. However, for the RX FIFO, the beginning of the next frame will always be on a word boundary. Table 16-1. TX & RX FIFO Organization FIFO Word Read/Write Sequence 1st Word Bit Fields 7:0 15:8 23:16 31:24 2nd 7:0 15:8 23:16 31:24 3rd 7:0 15:8 23:16 31:24 TX FIFO (Write) Data Length LSB Data Length MSB RX FIFO (Read) Frame Length LSB Frame Length MSB DA oct 1 DA oct 2 DA oct 3 DA oct 4 DA oct 5 DA oct 6 SA oct 1 SA oct 2 SA oct 3 SA oct 4 November 30, 2007 Preliminary 413 Ethernet Controller FIFO Word Read/Write Sequence 4th Word Bit Fields 7:0 15:8 23:16 31:24 TX FIFO (Write) RX FIFO (Read) SA oct 5 SA oct 6 Len/Type MSB Len/Type LSB data oct n data oct n+1 data oct n+2 data oct n+3 5th to nth 7:0 15:8 23:16 31:24 last 7:0 15:8 23:16 31:24 FCS 1 (if the CRC bit in MACCTL is 0) FCS 2 (if the CRC bit in MACCTL is 0) FCS 3 (if the CRC bit in MACCTL is 0) FCS 4 (if the CRC bit in MACCTL is 0) FCS 1 FCS 2 FCS 3 FCS 4 16.2.3.3 Ethernet Transmission Options The Ethernet Controller can automatically generate and insert the Frame Check Sequence (FCS) at the end of the transmit frame. This is controlled by the CRC bit in the MACTCTL register. For test purposes, in order to generate a frame with an invalid CRC, this feature can be disabled. The IEEE 802.3 specification requires that the Ethernet frame payload section be a minimum of 46 bytes. The Ethernet Controller can be configured to automatically pad the data section if the payload data section loaded into the FIFO is less than the minimum 46 bytes. This feature is controlled by the PADEN bit in the MACTCTL register. At the MAC layer, the transmitter can be configured for both full-duplex and half-duplex operation by using the DUPLEX bit in the MACTCTL register. 16.2.3.4 Ethernet Reception Options Using the BADCRC bit in the MACRCTL register, the Ethernet Controller can be configured to reject incoming Ethernet frames with an invalid FCS field. The Ethernet receiver can also be configured for Promiscuous and Multicast modes using the PRMS and AMUL fields in the MACRCTL register. If these modes are not enabled, only Ethernet frames with a broadcast address, or frames matching the MAC address programmed into the MACIA0 and MACIA1 register will be placed into the RX FIFO. 16.2.4 Interrupts The Ethernet Controller can generate an interrupt for one or more of the following conditions: ■ A frame has been received into an empty RX FIFO ■ A frame transmission error has occurred ■ A frame has been transmitted successfully ■ A frame has been received with no room in the RX FIFO (overrun) 414 Preliminary November 30, 2007 LM3S6965 Microcontroller ■ A frame has been received with one or more error conditions (for example, FCS failed) ■ An MII management transaction between the MAC and PHY layers has completed ■ One or more of the following PHY layer conditions occurs: – Auto-Negotiate Complete – Remote Fault – Link Status Change – Link Partner Acknowledge – Parallel Detect Fault – Page Received – Receive Error – Jabber Event Detected 16.3 Initialization and Configuration To use the Ethernet Controller, the peripheral must be enabled by setting the EPHY0 and EMAC0 bits in the RCGC2 register. The following steps can then be used to configure the Ethernet Controller for basic operation. 1. Program the MACDIV register to obtain a 2.5 MHz clock (or less) on the internal MII. Assuming a 20-MHz system clock, the MACDIV value would be 4. 2. Program the MACIA0 and MACIA1 register for address filtering. 3. Program the MACTCTL register for Auto CRC generation, padding, and full-duplex operation using a value of 0x16. 4. Program the MACRCTL register to reject frames with bad FCS using a value of 0x08. 5. Enable both the Transmitter and Receive by setting the LSB in both the MACTCTL and MACRCTL registers. 6. To transmit a frame, write the frame into the TX FIFO using the MACDATA register. Then set the NEWTX bit in the MACTR register to initiate the transmit process. When the NEWTX bit has been cleared, the TX FIFO will be available for the next transmit frame. 7. To receive a frame, wait for the NPR field in the MACNP register to be non-zero. Then begin reading the frame from the RX FIFO by using the MACDATA register. When the frame (including the FCS field) has been read, the NPR field should decrement by one. When there are no more frames in the RX FIFO, the NPR field will read 0. 16.4 Ethernet Register Map Table 16-2 on page 416 lists the Ethernet MAC registers. All addresses given are relative to the Ethernet MAC base address of 0x4004.8000. November 30, 2007 Preliminary 415 Ethernet Controller The IEEE 802.3 standard specifies a register set for controlling and gathering status from the PHY. The registers are collectively known as the MII Management registers and are detailed in Section 22.2.4 of the IEEE 802.3 specification. Table 16-2 on page 416 also lists these MII Management registers. All addresses given are absolute and are written directly to the REGADR field of the MACMCTL register. The format of registers 0 to 15 are defined by the IEEE specification and are common to all PHY implementations. The only variance allowed is for features that may or may not be supported by a specific PHY. Registers 16 to 31 are vendor-specific registers, used to support features that are specific to a vendors PHY implementation. Vendor-specific registers not listed are reserved. Table 16-2. Ethernet Register Map Offset Name Type Reset Description See page Ethernet MAC 0x000 0x000 0x004 0x008 0x00C 0x010 0x014 0x018 0x01C 0x020 0x024 0x02C 0x030 0x034 0x038 MACRIS MACIACK MACIM MACRCTL MACTCTL MACDATA MACIA0 MACIA1 MACTHR MACMCTL MACMDV MACMTXD MACMRXD MACNP MACTR RO W1C R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W RO R/W 0x0000.0000 0x0000.0000 0x0000.007F 0x0000.0008 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.003F 0x0000.0000 0x0000.0080 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 Ethernet MAC Raw Interrupt Status Ethernet MAC Interrupt Acknowledge Ethernet MAC Interrupt Mask Ethernet MAC Receive Control Ethernet MAC Transmit Control Ethernet MAC Data Ethernet MAC Individual Address 0 Ethernet MAC Individual Address 1 Ethernet MAC Threshold Ethernet MAC Management Control Ethernet MAC Management Divider Ethernet MAC Management Transmit Data Ethernet MAC Management Receive Data Ethernet MAC Number of Packets Ethernet MAC Transmission Request 418 420 421 422 423 424 426 427 428 429 430 431 432 433 434 MII Management MR0 MR1 MR2 R/W RO RO 0x3100 0x7849 0x000E Ethernet PHY Management Register 0 – Control Ethernet PHY Management Register 1 – Status Ethernet PHY Management Register 2 – PHY Identifier 1 Ethernet PHY Management Register 3 – PHY Identifier 2 Ethernet PHY Management Register 4 – Auto-Negotiation Advertisement Ethernet PHY Management Register 5 – Auto-Negotiation Link Partner Base Page Ability 435 437 439 - MR3 RO 0x7237 440 - MR4 R/W 0x01E1 441 - MR5 RO 0x0000 443 416 Preliminary November 30, 2007 LM3S6965 Microcontroller Offset Name Type Reset Description Ethernet PHY Management Register 6 – Auto-Negotiation Expansion Ethernet PHY Management Register 16 – Vendor-Specific Ethernet PHY Management Register 17 – Interrupt Control/Status Ethernet PHY Management Register 18 – Diagnostic Ethernet PHY Management Register 19 – Transceiver Control Ethernet PHY Management Register 23 – LED Configuration Ethernet PHY Management Register 24 –MDI/MDIX Control See page 444 - MR6 RO 0x0000 - MR16 R/W 0x0140 445 - MR17 MR18 MR19 R/W RO R/W 0x0000 0x0000 0x4000 447 449 450 - MR23 R/W 0x0010 451 - MR24 R/W 0x00C0 452 16.5 Ethernet MAC Register Descriptions The remainder of this section lists and describes the Ethernet MAC registers, in numerical order by address offset. Also see “MII Management Register Descriptions” on page 434. November 30, 2007 Preliminary 417 Ethernet Controller Register 1: Ethernet MAC Raw Interrupt Status (MACRIS), offset 0x000 The MACRIS register is the interrupt status register. On a read, this register gives the current status value of the corresponding interrupt prior to masking. Ethernet MAC Raw Interrupt Status (MACRIS) Base 0x4004.8000 Offset 0x000 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 PHYINT RO 0 RO 0 5 MDINT RO 0 RO 0 4 RXER RO 0 RO 0 3 FOV RO 0 RO 0 2 TXEMP RO 0 RO 0 1 TXER RO 0 RO 0 0 RXINT RO 0 Bit/Field 31:7 Name reserved Type RO Reset 0x0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. PHY Interrupt When set, indicates that an enabled interrupt in the PHY layer has occured. MR17 in the PHY must be read to determine the specific PHY event that triggered this interrupt. 6 PHYINT RO 0x0 5 MDINT RO 0x0 MII Transaction Complete When set, indicates that a transaction (read or write) on the MII interface has completed successfully. 4 RXER RO 0x0 Receive Error This bit indicates that an error was encountered on the receiver. The possible errors that can cause this interrupt bit to be set are: ■ A receive error occurs during the reception of a frame (100 Mb/s only). The frame is not an integer number of bytes (dribble bits) due to an alignment error. The CRC of the frame does not pass the FCS check. The length/type field is inconsistent with the frame data size when interpreted as a length field. ■ ■ ■ 3 FOV RO 0x0 FIFO Overrrun When set, indicates that an overrun was encountered on the receive FIFO. 2 TXEMP RO 0x0 Transmit FIFO Empty When set, indicates that the packet was transmitted and that the TX FIFO is empty. 418 Preliminary November 30, 2007 LM3S6965 Microcontroller Bit/Field 1 Name TXER Type RO Reset 0x0 Description Transmit Error When set, indicates that an error was encountered on the transmitter. The possible errors that can cause this interrupt bit to be set are: ■ The data length field stored in the TX FIFO exceeds 2032. The frame is not sent when this error occurs. The retransmission attempts during the backoff process have exceeded the maximum limit of 16. ■ 0 RXINT RO 0x0 Packet Received When set, indicates that at least one packet has been received and is stored in the receiver FIFO. November 30, 2007 Preliminary 419 Ethernet Controller Register 2: Ethernet MAC Interrupt Acknowledge (MACIACK), offset 0x000 A write of a 1 to any bit position of this register clears the corresponding interrupt bit in the Ethernet MAC Raw Interrupt Status (MACRIS) register. Ethernet MAC Interrupt Acknowledge (MACIACK) Base 0x4004.8000 Offset 0x000 Type W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 PHYINT W1C 0 RO 0 5 MDINT W1C 0 RO 0 4 RXER W1C 0 RO 0 3 FOV W1C 0 RO 0 2 TXEMP W1C 0 RO 0 1 TXER W1C 0 RO 0 0 RXINT W1C 0 Bit/Field 31:7 Name reserved Type RO Reset 0x0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Clear PHY Interrupt A write of a 1 clears the PHYINT interrupt read from the MACRIS register. 6 PHYINT W1C 0x0 5 MDINT W1C 0x0 Clear MII Transaction Complete A write of a 1 clears the MDINT interrupt read from the MACRIS register. 4 RXER W1C 0x0 Clear Receive Error A write of a 1 clears the RXER interrupt read from the MACRIS register. 3 FOV W1C 0x0 Clear FIFO Overrun A write of a 1 clears the FOV interrupt read from the MACRIS register. 2 TXEMP W1C 0x0 Clear Transmit FIFO Empty A write of a 1 clears the TXEMP interrupt read from the MACRIS register. 1 TXER W1C 0x0 Clear Transmit Error A write of a 1 clears the TXER interrupt read from the MACRIS register and resets the TX FIFO write pointer. 0 RXINT W1C 0x0 Clear Packet Received A write of a 1 clears the RXINT interrupt read from the MACRIS register. 420 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 3: Ethernet MAC Interrupt Mask (MACIM), offset 0x004 This register allows software to enable/disable Ethernet MAC interrupts. Writing a 0 disables the interrupt, while writing a 1 enables it. Ethernet MAC Interrupt Mask (MACIM) Base 0x4004.8000 Offset 0x004 Type R/W, reset 0x0000.007F 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 FOVM R/W 1 RO 0 2 RO 0 1 RO 0 0 RXINTM R/W 1 PHYINTM MDINTM RXERM R/W 1 R/W 1 R/W 1 TXEMPM TXERM R/W 1 R/W 1 Bit/Field 31:7 Name reserved Type RO Reset 0x0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Mask PHY Interrupt This bit masks the PHYINT bit in the MACRIS register from being asserted. 6 PHYINTM R/W 1 5 MDINTM R/W 1 Mask MII Transaction Complete This bit masks the MDINT bit in the MACRIS register from being asserted. 4 RXERM R/W 1 Mask Receive Error This bit masks the RXER bit in the MACRIS register from being asserted. 3 FOVM R/W 1 Mask FIFO Overrrun This bit masks the FOV bit in the MACRIS register from being asserted. 2 TXEMPM R/W 1 Mask Transmit FIFO Empty This bit masks the TXEMP bit in the MACRIS register from being asserted. 1 TXERM R/W 1 Mask Transmit Error This bit masks the TXER bit in the MACRIS register from being asserted. 0 RXINTM R/W 1 Mask Packet Received This bit masks the RXINT bit in the MACRIS register from being asserted. November 30, 2007 Preliminary 421 Ethernet Controller Register 4: Ethernet MAC Receive Control (MACRCTL), offset 0x008 This register enables software to configure the receive module and control the types of frames that are received from the physical medium. It is important to note that when the receive module is enabled, all valid frames with a broadcast address of FF-FF-FF-FF-FF-FF in the Destination Address field will be received and stored in the RX FIFO, even if the AMUL bit is not set. Ethernet MAC Receive Control (MACRCTL) Base 0x4004.8000 Offset 0x008 Type R/W, reset 0x0000.0008 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 PRMS R/W 0 RO 0 1 AMUL R/W 0 RO 0 0 RXEN R/W 0 RSTFIFO BADCRC R/W 0 R/W 1 Bit/Field 31:5 Name reserved Type RO Reset 0x0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Clear Receive FIFO When set, clears the receive FIFO. This should be done when software initialization is performed. It is recommended that the receiver be disabled (RXEN = 0), and then the reset initiated (RSTFIFO = 1). This sequence will flush and reset the RX FIFO. 4 RSTFIFO R/W 0x0 3 BADCRC R/W 0x1 Enable Reject Bad CRC The BADCRC bit enables the rejection of frames with an incorrectly calculated CRC. 2 PRMS R/W 0x0 Enable Promiscuous Mode The PRMS bit enables Promiscuous mode, which accepts all valid frames, regardless of the Destination Address. 1 AMUL R/W 0x0 Enable Multicast Frames The AMUL bit enables the reception of multicast frames from the physical medium. 0 RXEN R/W 0x0 Enable Receiver The RXEN bit enables the Ethernet receiver. When this bit is Low, the receiver is disabled and all frames on the physical medium are ignored. 422 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 5: Ethernet MAC Transmit Control (MACTCTL), offset 0x00C This register enables software to configure the transmit module, and control frames are placed onto the physical medium. Ethernet MAC Transmit Control (MACTCTL) Base 0x4004.8000 Offset 0x00C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 CRC R/W 0 RO 0 1 PADEN R/W 0 RO 0 0 TXEN R/W 0 DUPLEX reserved R/W 0 RO 0 Bit/Field 31:5 Name reserved Type RO Reset 0x0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Enable Duplex Mode When set, enables Duplex mode, allowing simultaneous transmission and reception. 4 DUPLEX R/W 0x0 3 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Enable CRC Generation When set, enables the automatic generation of the CRC and the placement at the end of the packet. If this bit is not set, the frames placed in the TX FIFO will be sent exactly as they are written into the FIFO. 2 CRC R/W 0x0 1 PADEN R/W 0x0 Enable Packet Padding When set, enables the automatic padding of packets that do not meet the minimum frame size. 0 TXEN R/W 0x0 Enable Transmitter When set, enables the transmitter. When this bit is 0, the transmitter is disabled. November 30, 2007 Preliminary 423 Ethernet Controller Register 6: Ethernet MAC Data (MACDATA), offset 0x010 This register enables software to access the TX and RX FIFOs. Reads from this register return the data stored in the RX FIFO from the location indicated by the read pointer. Writes to this register store the data in the TX FIFO at the location indicated by the write pointer. The write pointer is then auto-incremented to the next TX FIFO location. There is no mechanism for randomly accessing bytes in either the RX or TX FIFOs. Data must be read from the RX FIFO sequentially and stored in a buffer for further processing. Once a read has been performed, the data in the FIFO cannot be re-read. Data must be written to the TX FIFO sequentially. If an error is made in placing the frame into the TX FIFO, the write pointer can be reset to the start of the TX FIFO by writing the TXER bit of the MACIACK register and then the data re-written. Read-Only Register Ethernet MAC Data (MACDATA) Base 0x4004.8000 Offset 0x010 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RXDATA Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RXDATA Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 Bit/Field 31:0 Name RXDATA Type RO Reset 0x0 Description Receive FIFO Data The RXDATA bits represent the next four bytes of data stored in the RX FIFO. Write-Only Register Ethernet MAC Data (MACDATA) Base 0x4004.8000 Offset 0x010 Type WO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TXDATA Type Reset WO 0 15 WO 0 14 WO 0 13 WO 0 12 WO 0 11 WO 0 10 WO 0 9 WO 0 8 TXDATA Type Reset WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 7 WO 0 6 WO 0 5 WO 0 4 WO 0 3 WO 0 2 WO 0 1 WO 0 0 424 Preliminary November 30, 2007 LM3S6965 Microcontroller Bit/Field 31:0 Name TXDATA Type WO Reset 0x0 Description Transmit FIFO Data The TXDATA bits represent the next four bytes of data to place in the TX FIFO for transmission. November 30, 2007 Preliminary 425 Ethernet Controller Register 7: Ethernet MAC Individual Address 0 (MACIA0), offset 0x014 This register enables software to program the first four bytes of the hardware MAC address of the Network Interface Card (NIC). (The last two bytes are in MACIA1). The 6-byte IAR is compared against the incoming Destination Address fields to determine whether the frame should be received. Ethernet MAC Individual Address 0 (MACIA0) Base 0x4004.8000 Offset 0x014 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 MACOCT4 Type Reset R/W 0 15 R/W 0 14 R/W 0 13 R/W 0 12 R/W 0 11 R/W 0 10 R/W 0 9 R/W 0 8 R/W 0 7 R/W 0 6 R/W 0 5 MACOCT3 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 MACOCT2 Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 MACOCT1 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field 31:24 Name MACOCT4 Type R/W Reset 0x0 Description MAC Address Octet 4 The MACOCT4 bits represent the fourth octet of the MAC address used to uniquely identify each Ethernet Controller. 23:16 MACOCT3 R/W 0x0 MAC Address Octet 3 The MACOCT3 bits represent the third octet of the MAC address used to uniquely identify each Ethernet Controller. 15:8 MACOCT2 R/W 0x0 MAC Address Octet 2 The MACOCT2 bits represent the second octet of the MAC address used to uniquely identify each Ethernet Controller. 7:0 MACOCT1 R/W 0x0 MAC Address Octet 1 The MACOCT1 bits represent the first octet of the MAC address used to uniquely identify each Ethernet Controller. 426 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 8: Ethernet MAC Individual Address 1 (MACIA1), offset 0x018 This register enables software to program the last two bytes of the hardware MAC address of the Network Interface Card (NIC). (The first four bytes are in MACIA0). The 6-byte IAR is compared against the incoming Destination Address fields to determine whether the frame should be received. Ethernet MAC Individual Address 1 (MACIA1) Base 0x4004.8000 Offset 0x018 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 MACOCT6 Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 MACOCT5 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field 31:16 Name reserved Type RO Reset 0x0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. MAC Address Octet 6 The MACOCT6 bits represent the sixth octet of the MAC address used to uniquely identify each Ethernet Controller. 15:8 MACOCT6 R/W 0x0 7:0 MACOCT5 R/W 0x0 MAC Address Octet 5 The MACOCT5 bits represent the fifth octet of the MAC address used to uniquely identify each Ethernet Controller. November 30, 2007 Preliminary 427 Ethernet Controller Register 9: Ethernet MAC Threshold (MACTHR), offset 0x01C This register enables software to set the threshold level at which the transmission of the frame begins. If the THRESH bits are set to 0x3F, which is the reset value, transmission does not start until the NEWTX bit is set in the MACTR register. This effectively disables the early transmission feature. Writing the THRESH bits to any value besides all 1s enables the early transmission feature. Once the byte count of data in the TX FIFO reaches this level, transmission of the frame begins. When THRESH is set to all 0s, transmission of the frame begins after 4 bytes (a single write) are stored in the TX FIFO. Each increment of the THRESH bit field waits for an additional 32 bytes of data (eight writes) to be stored in the TX FIFO. Therefore, a value of 0x01 would wait for 36 bytes of data to be written while a value of 0x02 would wait for 68 bytes to be written. In general, early transmission starts when: Number of Bytes >= 4 (THRESH x 8 + 1) Reaching the threshold level has the same effect as setting the NEWTX bit in the MACTR register. Transmission of the frame begins and then the number of bytes indicated by the Data Length field is sent out on the physical medium. Because under-run checking is not performed, it is possible that the tail pointer may reach and pass the write pointer in the TX FIFO. This causes indeterminate values to be written to the physical medium rather than the end of the frame. Therefore, sufficient bus bandwidth for writing to the TX FIFO must be guaranteed by the software. If a frame smaller than the threshold level needs to be sent, the NEWTX bit in the MACTR register must be set with an explicit write. This initiates the transmission of the frame even though the threshold limit has not been reached. If the threshold level is set too small, it is possible for the transmitter to underrun. If this occurs, the transmit frame is aborted, and a transmit error occurs. Ethernet MAC Threshold (MACTHR) Base 0x4004.8000 Offset 0x01C Type R/W, reset 0x0000.003F 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 THRESH RO 0 RO 0 RO 0 RO 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:6 Name reserved Type RO Reset 0x0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Threshold Value The THRESH bits represent the early transmit threshold. Once the amount of data in the TX FIFO exceeds this value, transmission of the packet begins. 5:0 THRESH R/W 0x3F 428 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 10: Ethernet MAC Management Control (MACMCTL), offset 0x020 This register enables software to control the transfer of data to and from the MII Management registers in the Ethernet PHY. The address, name, type, reset configuration, and functional description of each of these registers can be found in Table 16-2 on page 416 and in “MII Management Register Descriptions” on page 434. In order to initiate a read transaction from the MII Management registers, the WRITE bit must be written with a 0 during the same cycle that the START bit is written with a 1. In order to initiate a write transaction to the MII Management registers, the WRITE bit must be written with a 1 during the same cycle that the START bit is written with a 1. Ethernet MAC Management Control (MACMCTL) Base 0x4004.8000 Offset 0x020 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 REGADR RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 RO 0 4 RO 0 3 RO 0 2 reserved RO 0 RO 0 1 WRITE R/W 0 RO 0 0 START R/W 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. MII Register Address The REGADR bit field represents the MII Management register address for the next MII management interface transaction. 7:3 REGADR R/W 0x0 2 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. MII Register Transaction Type The WRITE bit represents the operation of the next MII management interface transaction. If WRITE is set, the next operation will be a write; otherwise, it will be a read. 1 WRITE R/W 0x0 0 START R/W 0x0 MII Register Transaction Enable The START bit represents the initiation of the next MII management interface transaction. When a 1 is written to this bit, the MII register located at REGADR will be read (WRITE=0) or written (WRITE=1). November 30, 2007 Preliminary 429 Ethernet Controller Register 11: Ethernet MAC Management Divider (MACMDV), offset 0x024 This register enables software to set the clock divider for the Management Data Clock (MDC). This clock is used to synchronize read and write transactions between the system and the MII Management registers. The frequency of the MDC clock can be calculated from the following formula: Fmdc = Fipclk / (2 * (MACMDVR + 1 )) The clock divider must be written with a value that ensures that the MDC clock will not exceed a frequency of 2.5 MHz. Ethernet MAC Management Divider (MACMDV) Base 0x4004.8000 Offset 0x024 Type R/W, reset 0x0000.0080 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 DIV RO 0 RO 0 RO 0 R/W 1 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:8 Name reserved Type RO Reset 0x0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Clock Divider The DIV bits are used to set the clock divider for the MDC clock used to transmit data between the MAC and PHY over the serial MII interface. 7:0 DIV R/W 0x80 430 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 12: Ethernet MAC Management Transmit Data (MACMTXD), offset 0x02C This register holds the next value to be written to the MII Management registers. Ethernet MAC Management Transmit Data (MACMTXD) Base 0x4004.8000 Offset 0x02C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 MDTX Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 Bit/Field 31:16 Name reserved Type RO Reset 0x0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. MII Register Transmit Data The MDTX bits represent the data that will be written in the next MII management transaction. 15:0 MDTX R/W 0x0 November 30, 2007 Preliminary 431 Ethernet Controller Register 13: Ethernet MAC Management Receive Data (MACMRXD), offset 0x030 This register holds the last value read from the MII Management registers. Ethernet MAC Management Receive Data (MACMRXD) Base 0x4004.8000 Offset 0x030 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 MDRX Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 Bit/Field 31:16 Name reserved Type RO Reset 0x0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. MII Register Receive Data The MDRX bits represent the data that was read in the previous MII management transaction. 15:0 MDRX R/W 0x0 432 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 14: Ethernet MAC Number of Packets (MACNP), offset 0x034 This register holds the number of frames that are currently in the RX FIFO. When NPR is 0, there are no frames in the RX FIFO and the RXINT bit is not set. When NPR is any other value, there is at least one frame in the RX FIFO and the RXINT bit in the MACRIS register is set. Ethernet MAC Number of Packets (MACNP) Base 0x4004.8000 Offset 0x034 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 NPR RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:6 Name reserved Type RO Reset 0x0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Number of Packets in Receive FIFO The NPR bits represent the number of packets stored in the RX FIFO. While the NPR field is greater than 0, the RXINT interrupt in the MACRIS register will be asserted. 5:0 NPR RO 0x0 November 30, 2007 Preliminary 433 Ethernet Controller Register 15: Ethernet MAC Transmission Request (MACTR), offset 0x038 This register enables software to initiate the transmission of the frame currently located in the TX FIFO to the physical medium. Once the frame has been transmitted to the medium from the TX FIFO or a transmission error has been encountered, the NEWTX bit is auto-cleared by the hardware. Ethernet MAC Transmission Request (MACTR) Base 0x4004.8000 Offset 0x038 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 NEWTX R/W 0 Bit/Field 31:1 Name reserved Type RO Reset 0x0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. New Transmission When set, the NEWTX bit initiates an Ethernet transmission once the packet has been placed in the TX FIFO. This bit is cleared once the transmission has been completed. If early transmission is being used (see the MACTHR register), this bit does not need to be set. 0 NEWTX R/W 0x0 16.6 MII Management Register Descriptions The IEEE 802.3 standard specifies a register set for controlling and gathering status from the PHY. The registers are collectively known as the MII Management registers. All addresses given are absolute. Addresses not listed are reserved. Also see “Ethernet MAC Register Descriptions” on page 417. 434 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 16: Ethernet PHY Management Register 0 – Control (MR0), address 0x00 This register enables software to configure the operation of the PHY. The default settings of these registers are designed to initialize the PHY to a normal operational mode without configuration. Ethernet PHY Management Register 0 – Control (MR0) Base 0x4004.8000 Address 0x00 Type R/W, reset 0x3100 15 RESET Type Reset R/W 0 14 13 12 11 10 ISO R/W 0 9 8 7 COLT R/W 0 R/W 0 R/W 0 R/W 0 6 5 4 3 reserved R/W 0 R/W 0 R/W 0 R/W 0 2 1 0 LOOPBK SPEEDSL ANEGEN PWRDN R/W 0 R/W 1 R/W 1 R/W 0 RANEG DUPLEX R/W 0 R/W 1 Bit/Field 15 Name RESET Type R/W Reset 0 Description Reset Registers When set, resets the registers to their default state and reinitializes internal state machines. Once the reset operation has completed, this bit is cleared by hardware. 14 LOOPBK R/W 0 Loopback Mode When set, enables the Loopback mode of operation. The receive circuitry is isolated from the physical medium and transmissions are sent back through the receive circuitry instead of the medium. 13 SPEEDSL R/W 1 Speed Select 1: Enables the 100 Mb/s mode of operation (100BASE-TX). 0: Enables the 10 Mb/s mode of operation (10BASE-T). 12 ANEGEN R/W 1 Auto-Negotiation Enable When set, enables the Auto-Negotiation process. 11 PWRDN R/W 0 Power Down When set, places the PHY into a low-power consuming state. 10 ISO R/W 0 Isolate When set, isolates transmit and receive data paths and ignores all signaling on these buses. 9 RANEG R/W 0 Restart Auto-Negotiation When set, restarts the Auto-Negotiation process. Once the restart has initiated, this bit is cleared by hardware. 8 DUPLEX R/W 1 Set Duplex Mode 1: Enables the Full-Duplex mode of operation. This bit can be set by software in a manual configuration process or by the Auto-Negotiation process. 0: Enables the Half-Duplex mode of operation. November 30, 2007 Preliminary 435 Ethernet Controller Bit/Field 7 Name COLT Type R/W Reset 0 Description Collision Test When set, enables the Collision Test mode of operation. The COLT bit asserts after the initiation of a transmission and de-asserts once the transmission is halted. 6:0 reserved R/W 0x00 Write as 0, ignore on read. 436 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 17: Ethernet PHY Management Register 1 – Status (MR1), address 0x01 This register enables software to determine the capabilities of the PHY and perform its initialization and operation appropriately. Ethernet PHY Management Register 1 – Status (MR1) Base 0x4004.8000 Address 0x01 Type RO, reset 0x7849 15 reserved Type Reset RO 0 14 100X_F RO 1 13 100X_H RO 1 12 10T_F RO 1 11 10T_H RO 1 RO 0 10 9 reserved RO 0 RO 0 RO 0 8 7 6 MFPS RO 1 5 ANEGC RO 0 4 RFAULT RC 0 3 ANEGA RO 1 2 LINK RO 0 1 JAB RC 0 0 EXTD RO 1 Bit/Field 15 Name reserved Type RO Reset 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 100BASE-TX Full-Duplex Mode When set, indicates that the PHY is capable of supporting 100BASE-TX Full-Duplex mode. 14 100X_F RO 1 13 100X_H RO 1 100BASE-TX Half-Duplex Mode When set, indicates that the PHY is capable of supporting 100BASE-TX Half-Duplex mode. 12 10T_F RO 1 10BASE-T Full-Duplex Mode When set, indicates that the PHY is capable of 10BASE-T Full-Duplex mode. 11 10T_H RO 1 10BASE-T Half-Duplex Mode When set, indicates that the PHY is capable of supporting 10BASE-T Half-Duplex mode. 10:7 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Management Frames with Preamble Suppressed When set, indicates that the Management Interface is capable of receiving management frames with the preamble suppressed. 6 MFPS RO 1 5 ANEGC RO 0 Auto-Negotiation Complete When set, indicates that the Auto-Negotiation process has been completed and that the extended registers defined by the Auto-Negotiation protocol are valid. 4 RFAULT RC 0 Remote Fault When set, indicates that a remote fault condition has been detected. This bit remains set until it is read, even if the condition no longer exists. November 30, 2007 Preliminary 437 Ethernet Controller Bit/Field 3 Name ANEGA Type RO Reset 1 Description Auto-Negotiation When set, indicates that the PHY has the ability to perform Auto-Negotiation. 2 LINK RO 0 Link Made When set, indicates that a valid link has been established by the PHY. 1 JAB RC 0 Jabber Condition When set, indicates that a jabber condition has been detected by the PHY. This bit remains set until it is read, even if the jabber condition no longer exists. 0 EXTD RO 1 Extended Capabilities When set, indicates that the PHY provides an extended set of capabilities that can be accessed through the extended register set. 438 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 18: Ethernet PHY Management Register 2 – PHY Identifier 1 (MR2), address 0x02 This register, along with MR3, provides a 32-bit value indicating the manufacturer, model, and revision information. Ethernet PHY Management Register 2 – PHY Identifier 1 (MR2) Base 0x4004.8000 Address 0x02 Type RO, reset 0x000E 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OUI[21:6] Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 1 RO 1 RO 1 RO 0 Bit/Field 15:0 Name OUI[21:6] Type RO Reset 0x000E Description Organizationally Unique Identifier[21:6] This field, along with the OUI[5:0] field in MR3, makes up the Organizationally Unique Identifier indicating the PHY manufacturer. November 30, 2007 Preliminary 439 Ethernet Controller Register 19: Ethernet PHY Management Register 3 – PHY Identifier 2 (MR3), address 0x03 This register, along with MR2, provides a 32-bit value indicating the manufacturer, model, and revision information. Ethernet PHY Management Register 3 – PHY Identifier 2 (MR3) Base 0x4004.8000 Address 0x03 Type RO, reset 0x7237 15 14 13 12 11 10 9 8 7 MN RO 0 RO 0 RO 1 RO 0 RO 0 RO 0 RO 1 RO 1 RO 0 RO 1 6 5 4 3 2 RN RO 1 RO 1 1 0 OUI[5:0] Type Reset RO 0 RO 1 RO 1 RO 1 Bit/Field 15:10 Name OUI[5:0] Type RO Reset 0x1C Description Organizationally Unique Identifier[5:0] This field, along with the OUI[21:6] field in MR2, makes up the Organizationally Unique Identifier indicating the PHY manufacturer. 9:4 MN RO 0x23 Model Number The MN field represents the Model Number of the PHY. 3:0 RN RO 0x7 Revision Number The RN field represents the Revision Number of the PHY. 440 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 20: Ethernet PHY Management Register 4 – Auto-Negotiation Advertisement (MR4), address 0x04 This register provides the advertised abilities of the PHY used during Auto-Negotiation. Bits 8:5 represent the Technology Ability Field bits. This field can be overwritten by software to Auto-Negotiate to an alternate common technology. Writing to this register has no effect until Auto-Negotiation is re-initiated. Ethernet PHY Management Register 4 – Auto-Negotiation Advertisement (MR4) Base 0x4004.8000 Address 0x04 Type R/W, reset 0x01E1 15 NP Type Reset RO 0 14 reserved RO 0 13 RF R/W 0 RO 0 12 11 10 9 8 A3 RO 0 R/W 1 7 A2 R/W 1 6 A1 R/W 1 5 A0 R/W 1 RO 0 RO 0 4 3 2 S[4:0] RO 0 RO 0 RO 1 1 0 reserved RO 0 RO 0 Bit/Field 15 Name NP Type RO Reset 0 Description Next Page When set, indicates the PHY is capable of Next Page exchanges to provide more detailed information on the PHY’s capabilities. 14 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Remote Fault When set, indicates to the link partner that a Remote Fault condition has been encountered. 13 RF R/W 0 12:9 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Technology Ability Field[3] When set, indicates that the PHY supports the 100Base-TX full-duplex signaling protocol. If software wants to ensure that this mode is not used, this bit can be written to 0 and Auto-Negotiation re-initiated with the RANEG bit in the MR0 register. 8 A3 R/W 1 7 A2 R/W 1 Technology Ability Field[2] When set, indicates that the PHY supports the 100Base-T half-duplex signaling protocol. If software wants to ensure that this mode is not used, this bit can be written to 0 and Auto-Negotiation re-initiated. 6 A1 R/W 1 Technology Ability Field[1] When set, indicates that the PHY supports the 10Base-T full-duplex signaling protocol. If software wants to ensure that this mode is not used, this bit can be written to 0 and Auto-Negotiation re-initiated. 5 A0 R/W 1 Technology Ability Field[0] When set, indicates that the PHY supports the 10Base-T half-duplex signaling protocol. If software wants to ensure that this mode is not used, this bit can be written to 0 and Auto-Negotiation re-initiated. November 30, 2007 Preliminary 441 Ethernet Controller Bit/Field 4:0 Name S[4:0] Type RO Reset 0x01 Description Selector Field The S[4:0] field encodes 32 possible messages for communicating between PHYs. This field is hard-coded to 0x01, indicating that the ® Stellaris PHY is IEEE 802.3 compliant. 442 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 21: Ethernet PHY Management Register 5 – Auto-Negotiation Link Partner Base Page Ability (MR5), address 0x05 This register provides the advertised abilities of the link partner ’s PHY that are received and stored during Auto-Negotiation. Ethernet PHY Management Register 5 – Auto-Negotiation Link Partner Base Page Ability (MR5) Base 0x4004.8000 Address 0x05 Type RO, reset 0x0000 15 NP Type Reset RO 0 14 ACK RO 0 13 RF RO 0 RO 0 RO 0 RO 0 RO 0 12 11 10 9 A[7:0] RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 7 6 5 4 3 2 S[4:0] RO 0 RO 0 RO 0 1 0 Bit/Field 15 Name NP Type RO Reset 0 Description Next Page When set, indicates that the link partner ’s PHY is capable of Next page exchanges to provide more detailed information on the PHY’s capabilities. 14 ACK RO 0 Acknowledge When set, indicates that the device has successfully received the link partner ’s advertised abilities during Auto-Negotiation. 13 RF RO 0 Remote Fault Used as a standard transport mechanism for transmitting simple fault information. 12:5 A[7:0] RO 0x00 Technology Ability Field The A[7:0] field encodes individual technologies that are supported by the PHY. See the MR4 register. 4:0 S[4:0] RO 0x00 Selector Field The S[4:0] field encodes possible messages for communicating between PHYs. Value 0x00 0x01 0x02 0x03 0x04 Description Reserved IEEE Std 802.3 IEEE Std 802.9 ISLAN-16T IEEE Std 802.5 IEEE Std 1394 0x05–0x1F Reserved November 30, 2007 Preliminary 443 Ethernet Controller Register 22: Ethernet PHY Management Register 6 – Auto-Negotiation Expansion (MR6), address 0x06 This register enables software to determine the Auto-Negotiation and Next Page capabilities of the PHY and the link partner after Auto-Negotiation. Ethernet PHY Management Register 6 – Auto-Negotiation Expansion (MR6) Base 0x4004.8000 Address 0x06 Type RO, reset 0x0000 15 14 13 12 11 10 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 9 8 7 6 5 4 PDF RC 0 3 LPNPA RO 0 2 reserved RO 0 1 PRX RC 0 0 LPANEGA RO 0 Bit/Field 15:5 Name reserved Type RO Reset 0x000 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Parallel Detection Fault When set, indicates that more than one technology has been detected at link up. This bit is cleared when read. 4 PDF RC 0 3 LPNPA RO 0 Link Partner is Next Page Able When set, indicates that the link partner is Next Page Able. 2 reserved RO 0x000 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. New Page Received When set, indicates that a New Page has been received from the link partner and stored in the appropriate location. This bit remains set until the register is read. 1 PRX RC 0 0 LPANEGA RO 0 Link Partner is Auto-Negotiation Able When set, indicates that the Link partner is Auto-Negotiation Able. 444 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 23: Ethernet PHY Management Register 16 – Vendor-Specific (MR16), address 0x10 This register enables software to configure the operation of vendor-specific modes of the PHY. Ethernet PHY Management Register 16 – Vendor-Specific (MR16) Base 0x4004.8000 Address 0x10 Type R/W, reset 0x0140 15 RPTR Type Reset R/W 0 14 INPOL R/W 0 13 reserved RO 0 12 TXHIM R/W 0 11 SQEI R/W 0 10 NL10 R/W 0 RO 0 9 8 reserved RO 1 RO 0 RO 1 7 6 5 APOL R/W 0 4 RVSPOL R/W 0 3 reserved RO 0 RO 0 2 1 PCSBP R/W 0 0 RXCC R/W 0 Bit/Field 15 Name RPTR Type R/W Reset 0 Description Repeater Mode When set, enables the repeater mode of operation. In this mode, full-duplex is not allowed and the Carrier Sense signal only responds to receive activity. If the PHY is configured to 10Base-T mode, the SQE test function is disabled. 14 INPOL R/W 0 Interrupt Polarity 1: Sets the polarity of the PHY interrupt to be active High. 0: Sets the polarity of the PHY interrupt to active Low. Important: Because the Media Access Controller expects active Low interrupts from the PHY, this bit must always be written with a 0 to ensure proper operation. 13 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Transmit High Impedance Mode When set, enables the transmitter High Impedance mode. In this mode, the TXOP and TXON transmitter pins are put into a high impedance state. The RXIP and RXIN pins remain fully functional. 12 TXHIM R/W 0 11 SQEI R/W 0 SQE Inhibit Testing When set, prohibits 10Base-T SQE testing. When 0, the SQE testing is performed by generating a Collision pulse following the completion of the transmission of a frame. 10 NL10 R/W 0 Natural Loopback Mode When set, enables the 10Base-T Natural Loopback mode. This causes the transmission data received by the PHY to be looped back onto the receive data path when 10Base-T mode is enabled. 9:6 reserved RO 0x05 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. November 30, 2007 Preliminary 445 Ethernet Controller Bit/Field 5 Name APOL Type R/W Reset 0 Description Auto-Polarity Disable When set, disables the PHY’s auto-polarity function. If this bit is 0, the PHY automatically inverts the received signal due to a wrong polarity connection during Auto-Negotiation if the PHY is in 10Base-T mode. 4 RVSPOL R/W 0 Receive Data Polarity This bit indicates whether the receive data pulses are being inverted. If the APOL bit is 0, then the RVSPOL bit is read-only and indicates whether the auto-polarity circuitry is reversing the polarity. In this case, a 1 in the RVSPOL bit indicates that the receive data is inverted while a 0 indicates that the receive data is not inverted. If the APOL bit is 1, then the RVSPOL bit is writable and software can force the receive data to be inverted. Setting RVSPOL to 1 forces the receive data to be inverted while a 0 does not invert the receive data. 3:2 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. PCS Bypass When set, enables the bypass of the PCS and scrambling/descrambling functions in 100Base-TX mode. This mode is only valid when Auto-Negotiation is disabled and 100Base-T mode is enabled. 1 PCSBP R/W 0 0 RXCC R/W 0 Receive Clock Control When set, enables the Receive Clock Control power saving mode if the PHY is configured in 100Base-TX mode. This mode shuts down the receive clock when no data is being received from the physical medium to save power. This mode should not be used when PCSBP is enabled and is automatically disabled when the LOOPBK bit in the MR0 register is set. 446 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 24: Ethernet PHY Management Register 17 – Interrupt Control/Status (MR17), address 0x11 This register provides the means for controlling and observing the events, which trigger a PHY interrupt in the MACRIS register. This register can also be used in a polling mode via the MII Serial Interface as a means to observe key events within the PHY via one register address. Bits 0 through 7 are status bits, which are each set to logic 1 based on an event. These bits are cleared after the register is read. Bits 8 through 15 of this register, when set to logic 1, enable their corresponding bit in the lower byte to signal a PHY interrupt in the MACRIS register. Ethernet PHY Management Register 17 – Interrupt Control/Status (MR17) Base 0x4004.8000 Address 0x11 Type R/W, reset 0x0000 15 JABBER_IE 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RXER_IE PRX_IE R/W 0 R/W 0 PDF_IE LPACK_IE LSCHG_IE RFAULT_IE ANEGCOMP_IE JABBER_INT RXER_INT PRX_INT PDF_INT LPACK_INT LSCHG_INT RFAULT_INT ANEGCOMP_INT R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 RC 0 RC 0 RC 0 RC 0 RC 0 RC 0 RC 0 RC 0 Type Reset R/W 0 Bit/Field 15 Name JABBER_IE Type R/W Reset 0 Description Jabber Interrupt Enable When set, enables system interrupts when a Jabber condition is detected by the PHY. 14 RXER_IE R/W 0 Receive Error Interrupt Enable When set, enables system interrupts when a receive error is detected by the PHY. 13 PRX_IE R/W 0 Page Received Interrupt Enable When set, enables system interrupts when a new page is received by the PHY. 12 PDF_IE R/W 0 Parallel Detection Fault Interrupt Enable When set, enables system interrupts when a Parallel Detection Fault is detected by the PHY. 11 LPACK_IE R/W 0 LP Acknowledge Interrupt Enable When set, enables system interrupts when FLP bursts are received with the Acknowledge bit during Auto-Negotiation. 10 LSCHG_IE R/W 0 Link Status Change Interrupt Enable When set, enables system interrupts when the Link Status changes from OK to FAIL. 9 RFAULT_IE R/W 0 Remote Fault Interrupt Enable When set, enables system interrupts when a Remote Fault condition is signaled by the link partner. 8 ANEGCOMP_IE R/W 0 Auto-Negotiation Complete Interrupt Enable When set, enables system interrupts when the Auto-Negotiation sequence has completed successfully. November 30, 2007 Preliminary 447 Ethernet Controller Bit/Field 7 Name JABBER_INT Type RC Reset 0 Description Jabber Event Interrupt When set, indicates that a Jabber event has been detected by the 10Base-T circuitry. 6 RXER_INT RC 0 Receive Error Interrupt When set, indicates that a receive error has been detected by the PHY. 5 PRX_INT RC 0 Page Receive Interrupt When set, indicates that a new page has been received from the link partner during Auto-Negotiation. 4 PDF_INT RC 0 Parallel Detection Fault Interrupt When set, indicates that a Parallel Detection Fault has been detected by the PHY during the Auto-Negotiation process. 3 LPACK_INT RC 0 LP Acknowledge Interrupt When set, indicates that an FLP burst has been received with the Acknowledge bit set during Auto-Negotiation. 2 LSCHG_INT RC 0 Link Status Change Interrupt When set, indicates that the link status has changed from OK to FAIL. 1 RFAULT_INT RC 0 Remote Fault Interrupt When set, indicates that a Remote Fault condition has been signaled by the link partner. 0 ANEGCOMP_INT RC 0 Auto-Negotiation Complete Interrupt When set, indicates that the Auto-Negotiation sequence has completed successfully. 448 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 25: Ethernet PHY Management Register 18 – Diagnostic (MR18), address 0x12 This register enables software to diagnose the results of the previous Auto-Negotiation. Ethernet PHY Management Register 18 – Diagnostic (MR18) Base 0x4004.8000 Address 0x12 Type RO, reset 0x0000 15 14 reserved Type Reset RO 0 RO 0 RO 0 13 12 ANEGF RC 0 11 DPLX RO 0 10 RATE RO 0 9 RXSD RO 0 8 RX_LOCK RO 0 RO 0 RO 0 RO 0 7 6 5 4 reserved RO 0 RO 0 RO 0 RO 0 RO 0 3 2 1 0 Bit/Field 15:13 Name reserved Type RO Reset 0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Auto-Negotiation Failure When set, indicates that no common technology was found during Auto-Negotiation and has failed. This bit remains set until read. 12 ANEGF RC 0 11 DPLX RO 0 Duplex Mode When set, indicates that Full-Duplex was the highest common denominator found during the Auto-Negotiation process. Otherwise, Half-Duplex was the highest common denominator found. 10 RATE RO 0 Rate When set, indicates that 100Base-TX was the highest common denominator found during the Auto-Negotiation process. Otherwise, 10Base-TX was the highest common denominator found. 9 RXSD RO 0 Receive Detection When set, indicates that receive signal detection has occurred (in 100Base-TX mode) or that Manchester-encoded data has been detected (in 10Base-T mode). 8 RX_LOCK RO 0 Receive PLL Lock When set, indicates that the Receive PLL has locked onto the receive signal for the selected speed of operation (10Base-T or 100Base-TX). 7:0 reserved RO 00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. November 30, 2007 Preliminary 449 Ethernet Controller Register 26: Ethernet PHY Management Register 19 – Transceiver Control (MR19), address 0x13 This register enables software to set the gain of the transmit output to compensate for transformer loss. Ethernet PHY Management Register 19 – Transceiver Control (MR19) Base 0x4004.8000 Address 0x13 Type R/W, reset 0x4000 15 14 13 12 11 10 9 8 7 reserved RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 6 5 4 3 2 1 0 TXO[1:0] Type Reset R/W 0 R/W 1 Bit/Field 15:14 Name TXO[1:0] Type R/W Reset 1 Description Transmit Amplitude Selection The TXO[1:0] field sets the transmit output amplitude to account for transmit transformer insertion loss. Value Description 0x0 0x1 0x2 0x3 Gain set for 0.0dB of insertion loss Gain set for 0.4dB of insertion loss Gain set for 0.8dB of insertion loss Gain set for 1.2dB of insertion loss 13:0 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 450 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 27: Ethernet PHY Management Register 23 – LED Configuration (MR23), address 0x17 This register enables software to select the source that will cause the LEDs to toggle. Ethernet PHY Management Register 23 – LED Configuration (MR23) Base 0x4004.8000 Address 0x17 Type R/W, reset 0x0010 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 R/W 0 LED1[3:0] R/W 0 R/W 0 R/W 1 R/W 0 LED0[3:0] R/W 0 R/W 0 R/W 0 Bit/Field 15:8 Name reserved Type RO Reset 0x0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. LED1 Source The LED1 field selects the source that will toggle the LED1 signal. Value Description 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 Link OK RX or TX Activity (Default LED1) TX Activity RX Activity Collision 100BASE-TX mode 10BASE-T mode Full-Duplex Link OK & Blink=RX or TX Activity 7:4 LED1[3:0] R/W 1 3:0 LED0[3:0] R/W 0 LED0 Source The LED0 field selects the source that will toggle the LED0 signal. Value Description 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 Link OK (Default LED0) RX or TX Activity TX Activity RX Activity Collision 100BASE-TX mode 10BASE-T mode Full-Duplex Link OK & Blink=RX or TX Activity November 30, 2007 Preliminary 451 Ethernet Controller Register 28: Ethernet PHY Management Register 24 –MDI/MDIX Control (MR24), address 0x18 This register enables software to control the behavior of the MDI/MDIX mux and its switching capabilities. Ethernet PHY Management Register 24 –MDI/MDIX Control (MR24) Base 0x4004.8000 Address 0x18 Type R/W, reset 0x00C0 15 14 13 12 11 10 9 8 7 6 5 MDIX R/W 0 4 MDIX_CM RO 0 R/W 0 3 2 1 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 PD_MODE AUTO_SW R/W 0 R/W 0 MDIX_SD R/W 0 R/W 0 R/W 0 Bit/Field 15:8 Name reserved Type RO Reset 0x0 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Parallel Detection Mode When set, enables the Parallel Detection mode and allows auto-switching to work when Auto-Negotiation is not enabled. 7 PD_MODE R/W 0 6 AUTO_SW R/W 0 Auto-Switching Enable When set, enables Auto-Switching of the MDI/MDIX mux. 5 MDIX R/W 0 Auto-Switching Configuration When set, indicates that the MDI/MDIX mux is in the crossover (MDIX) configuration. When 0, it indicates that the mux is in the pass-through (MDI) configuration. When the AUTO_SW bit is 1, the MDIX bit is read-only. When the AUTO_SW bit is 0, the MDIX bit is read/write and can be configured manually. 4 MDIX_CM RO 0 Auto-Switching Complete When set, indicates that the auto-switching sequence has completed. If 0, it indicates that the sequence has not completed or that auto-switching is disabled. 3:0 MDIX_SD R/W 0 Auto-Switching Seed This field provides the initial seed for the switching algorithm. This seed directly affects the number of attempts [5,4] respectively to write bits [3:0]. A 0 sets the seed to 0x5. 452 Preliminary November 30, 2007 LM3S6965 Microcontroller 17 Analog Comparators An analog comparator is a peripheral that compares two analog voltages, and provides a logical output that signals the comparison result. The LM3S6965 controller provides two independent integrated analog comparators that can be configured to drive an output or generate an interrupt or ADC event. Note: Not all comparators have the option to drive an output pin. See the Comparator Operating Mode tables for more information. A comparator can compare a test voltage against any one of these voltages: ■ An individual external reference voltage ■ A shared single external reference voltage ■ A shared internal reference voltage The comparator can provide its output to a device pin, acting as a replacement for an analog comparator on the board, or it can be used to signal the application via interrupts or triggers to the ADC to cause it to start capturing a sample sequence. The interrupt generation and ADC triggering logic is separate. This means, for example, that an interrupt can be generated on a rising edge and the ADC triggered on a falling edge. 17.1 Block Diagram Figure 17-1. Analog Comparator Module Block Diagram C1C1+ -ve input +ve input Comparator 1 output trigger trigger interrupt +ve input (alternate) ACCTL1 ACSTAT1 interrupt reference input C0C0+ -ve input +ve input Comparator 0 output C0o trigger interrupt +ve input (alternate) ACCTL0 trigger ACSTAT0 interrupt reference input Voltage Ref internal bus ACREFCTL November 30, 2007 Preliminary 453 Analog Comparators 17.2 Functional Description Important: It is recommended that the Digital-Input enable (the GPIODEN bit in the GPIO module) for the analog input pin be disabled to prevent excessive current draw from the I/O pads. The comparator compares the VIN- and VIN+ inputs to produce an output, VOUT. VIN- < VIN+, VOUT = 1 VIN- > VIN+, VOUT = 0 As shown in Figure 17-2 on page 454, the input source for VIN- is an external input. In addition to an external input, input sources for VIN+ can be the +ve input of comparator 0 or an internal reference. Figure 17-2. Structure of Comparator Unit -ve input +ve input 0 output CINV IntGen TrigGen +ve input (alternate) 1 reference input 2 ACCTL ACSTAT internal bus A comparator is configured through two status/control registers (ACCTL and ACSTAT ). The internal reference is configured through one control register (ACREFCTL). Interrupt status and control is configured through three registers (ACMIS, ACRIS, and ACINTEN). The operating modes of the comparators are shown in the Comparator Operating Mode tables. Typically, the comparator output is used internally to generate controller interrupts. It may also be used to drive an external pin or generate an analog-to-digital converter (ADC) trigger. Important: Certain register bit values must be set before using the analog comparators. The proper pad configuration for the comparator input and output pins are described in the Comparator Operating Mode tables. Table 17-1. Comparator 0 Operating Modes ACCNTL0 Comparator 0 ASRCP 00 01 VIN- VIN+ C0C0C0+ C0+ Output C0o/C1+ C0o/C1+ Interrupt ADC Trigger yes yes yes yes 454 Preliminary interrupt trigger November 30, 2007 LM3S6965 Microcontroller ACCNTL0 Comparator 0 ASRCP 10 11 VIN- VIN+ C0Vref Output C0o/C1+ Interrupt ADC Trigger yes yes yes yes C0- reserved C0o/C1+ Table 17-2. Comparator 1 Operating Modes ACCNTL1 Comparator 1 ASRCP 00 01 10 11 VIN- VIN+ C1- C0o/C1+ C1C1C0+ Vref a Output Interrupt ADC Trigger n/a n/a n/a n/a yes yes yes yes yes yes yes yes C1- reserved a. C0o and C1+ signals share a single pin and may only be used as one or the other. 17.2.1 Internal Reference Programming The structure of the internal reference is shown in Figure 17-3 on page 455. This is controlled by a single configuration register (ACREFCTL). Table 17-3 on page 455 shows the programming options to develop specific internal reference values, to compare an external voltage against a particular voltage generated internally. Figure 17-3. Comparator Internal Reference Structure AVDD 8R R R ••• EN 15 VREF RNG 14 ••• Decoder 1 0 internal reference R R 8R Table 17-3. Internal Reference Voltage and ACREFCTL Field Values ACREFCTL Register EN Bit Value RNG Bit Value EN=0 RNG=X 0 V (GND) for any value of VREF; however, it is recommended that RNG=1 and VREF=0 for the least noisy ground reference. Output Reference Voltage Based on VREF Field Value November 30, 2007 Preliminary 455 Analog Comparators ACREFCTL Register EN Bit Value RNG Bit Value EN=1 RNG=0 Output Reference Voltage Based on VREF Field Value Total resistance in ladder is 32 R. V RE F = AV DD R --- -- --F - -E × ---V-R--R T V V RE F = AV DD V F + 8) (---RE---------× ---------------32 R EF = 0 .8 25 + 0 .10 3 V R E F The range of internal reference in this mode is 0.825-2.37 V. RNG=1 Total resistance in ladder is 24 R. V RE F = AV DD R --- -- --F - -E × ---V-R--R T V RE F = AV DD V (---RE-F-) --- × ----------24 VREF = 0.1375 x VREF The range of internal reference for this mode is 0.0-2.0625 V. 17.3 Initialization and Configuration The following example shows how to configure an analog comparator to read back its output value from an internal register. 1. Enable the analog comparator 0 clock by writing a value of 0x0010.0000 to the RCGC1 register in the System Control module. 2. In the GPIO module, enable the GPIO port/pin associated with C0- as a GPIO input. 3. Configure the internal voltage reference to 1.65 V by writing the ACREFCTL register with the value 0x0000.030C. 4. Configure comparator 0 to use the internal voltage reference and to not invert the output on the C0o pin by writing the ACCTL0 register with the value of 0x0000.040C. 5. Delay for some time. 6. Read the comparator output value by reading the ACSTAT0 register ’s OVAL value. Change the level of the signal input on C0- to see the OVAL value change. 17.4 Register Map Table 17-4 on page 457 lists the comparator registers. The offset listed is a hexadecimal increment to the register ’s address, relative to the Analog Comparator base address of 0x4003.C000. 456 Preliminary November 30, 2007 LM3S6965 Microcontroller Table 17-4. Analog Comparators Register Map Offset 0x00 0x04 0x08 0x10 0x20 0x24 0x40 0x44 Name ACMIS ACRIS ACINTEN ACREFCTL ACSTAT0 ACCTL0 ACSTAT1 ACCTL1 Type R/W1C RO R/W R/W RO R/W RO R/W Reset 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 Description Analog Comparator Masked Interrupt Status Analog Comparator Raw Interrupt Status Analog Comparator Interrupt Enable Analog Comparator Reference Voltage Control Analog Comparator Status 0 Analog Comparator Control 0 Analog Comparator Status 1 Analog Comparator Control 1 See page 458 459 460 461 462 463 462 463 17.5 Register Descriptions The remainder of this section lists and describes the Analog Comparator registers, in numerical order by address offset. November 30, 2007 Preliminary 457 Analog Comparators Register 1: Analog Comparator Masked Interrupt Status (ACMIS), offset 0x00 This register provides a summary of the interrupt status (masked) of the comparators. Analog Comparator Masked Interrupt Status (ACMIS) Base 0x4003.C000 Offset 0x00 Type R/W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 IN1 R/W1C 0 RO 0 0 IN0 R/W1C 0 Bit/Field 31:2 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Comparator 1 Masked Interrupt Status Gives the masked interrupt state of this interrupt. Write 1 to this bit to clear the pending interrupt. 1 IN1 R/W1C 0 0 IN0 R/W1C 0 Comparator 0 Masked Interrupt Status Gives the masked interrupt state of this interrupt. Write 1 to this bit to clear the pending interrupt. 458 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 2: Analog Comparator Raw Interrupt Status (ACRIS), offset 0x04 This register provides a summary of the interrupt status (raw) of the comparators. Analog Comparator Raw Interrupt Status (ACRIS) Base 0x4003.C000 Offset 0x04 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 IN1 RO 0 RO 0 0 IN0 RO 0 Bit/Field 31:2 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Comparator 1 Interrupt Status When set, indicates that an interrupt has been generated by comparator 1. 1 IN1 RO 0 0 IN0 RO 0 Comparator 0 Interrupt Status When set, indicates that an interrupt has been generated by comparator 0. November 30, 2007 Preliminary 459 Analog Comparators Register 3: Analog Comparator Interrupt Enable (ACINTEN), offset 0x08 This register provides the interrupt enable for the comparators. Analog Comparator Interrupt Enable (ACINTEN) Base 0x4003.C000 Offset 0x08 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 IN1 R/W 0 RO 0 0 IN0 R/W 0 Bit/Field 31:2 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Comparator 1 Interrupt Enable When set, enables the controller interrupt from the comparator 1 output. 1 IN1 R/W 0 0 IN0 R/W 0 Comparator 0 Interrupt Enable When set, enables the controller interrupt from the comparator 0 output. 460 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 4: Analog Comparator Reference Voltage Control (ACREFCTL), offset 0x10 This register specifies whether the resistor ladder is powered on as well as the range and tap. Analog Comparator Reference Voltage Control (ACREFCTL) Base 0x4003.C000 Offset 0x10 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 EN RO 0 RO 0 R/W 0 RO 0 8 RNG R/W 0 RO 0 RO 0 7 RO 0 6 reserved RO 0 RO 0 RO 0 R/W 0 R/W 0 RO 0 5 RO 0 4 RO 0 3 RO 0 2 VREF R/W 0 R/W 0 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 Bit/Field 31:10 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Resistor Ladder Enable The EN bit specifies whether the resistor ladder is powered on. If 0, the resistor ladder is unpowered. If 1, the resistor ladder is connected to the analog VDD. This bit is reset to 0 so that the internal reference consumes the least amount of power if not used and programmed. 9 EN R/W 0 8 RNG R/W 0 Resistor Ladder Range The RNG bit specifies the range of the resistor ladder. If 0, the resistor ladder has a total resistance of 32 R. If 1, the resistor ladder has a total resistance of 24 R. 7:4 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Resistor Ladder Voltage Ref The VREF bit field specifies the resistor ladder tap that is passed through an analog multiplexer. The voltage corresponding to the tap position is the internal reference voltage available for comparison. See Table 17-3 on page 455 for some output reference voltage examples. 3:0 VREF R/W 0x00 November 30, 2007 Preliminary 461 Analog Comparators Register 5: Analog Comparator Status 0 (ACSTAT0), offset 0x20 Register 6: Analog Comparator Status 1 (ACSTAT1), offset 0x40 These registers specify the current output value of the comparator. Analog Comparator Status 0 (ACSTAT0) Base 0x4003.C000 Offset 0x20 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 OVAL RO 0 RO 0 0 reserved RO 0 Bit/Field 31:2 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Comparator Output Value The OVAL bit specifies the current output value of the comparator. 1 OVAL RO 0 0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 462 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 7: Analog Comparator Control 0 (ACCTL0), offset 0x24 Register 8: Analog Comparator Control 1 (ACCTL1), offset 0x44 These registers configure the comparator ’s input and output. Analog Comparator Control 0 (ACCTL0) Base 0x4003.C000 Offset 0x24 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 TOEN RO 0 R/W 0 RO 0 10 ASRCP R/W 0 R/W 0 RO 0 9 RO 0 8 reserved RO 0 RO 0 7 TSLVAL R/W 0 R/W 0 RO 0 6 TSEN R/W 0 RO 0 5 RO 0 4 ISLVAL R/W 0 R/W 0 RO 0 3 ISEN R/W 0 RO 0 2 RO 0 1 CINV R/W 0 RO 0 0 reserved RO 0 reserved Type Reset RO 0 RO 0 RO 0 Bit/Field 31:12 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Trigger Output Enable The TOEN bit enables the ADC event transmission to the ADC. If 0, the event is suppressed and not sent to the ADC. If 1, the event is transmitted to the ADC. 11 TOEN R/W 0 10:9 ASRCP R/W 0x00 Analog Source Positive The ASRCP field specifies the source of input voltage to the VIN+ terminal of the comparator. The encodings for this field are as follows: Value Function 0x0 0x1 0x2 0x3 Pin value Pin value of C0+ Internal voltage reference Reserved 8 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Trigger Sense Level Value The TSLVAL bit specifies the sense value of the input that generates an ADC event if in Level Sense mode. If 0, an ADC event is generated if the comparator output is Low. Otherwise, an ADC event is generated if the comparator output is High. 7 TSLVAL R/W 0 November 30, 2007 Preliminary 463 Analog Comparators Bit/Field 6:5 Name TSEN Type R/W Reset 0x0 Description Trigger Sense The TSEN field specifies the sense of the comparator output that generates an ADC event. The sense conditioning is as follows: Value Function 0x0 0x1 0x2 0x3 Level sense, see TSLVAL Falling edge Rising edge Either edge 4 ISLVAL R/W 0 Interrupt Sense Level Value The ISLVAL bit specifies the sense value of the input that generates an interrupt if in Level Sense mode. If 0, an interrupt is generated if the comparator output is Low. Otherwise, an interrupt is generated if the comparator output is High. 3:2 ISEN R/W 0x0 Interrupt Sense The ISEN field specifies the sense of the comparator output that generates an interrupt. The sense conditioning is as follows: Value Function 0x0 0x1 0x2 0x3 Level sense, see ISLVAL Falling edge Rising edge Either edge 1 CINV R/W 0 Comparator Output Invert The CINV bit conditionally inverts the output of the comparator. If 0, the output of the comparator is unchanged. If 1, the output of the comparator is inverted prior to being processed by hardware. 0 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 464 Preliminary November 30, 2007 LM3S6965 Microcontroller 18 Pulse Width Modulator (PWM) Pulse width modulation (PWM) is a powerful technique for digitally encoding analog signal levels. High-resolution counters are used to generate a square wave, and the duty cycle of the square wave is modulated to encode an analog signal. Typical applications include switching power supplies and motor control. The Stellaris PWM module consists of three PWM generator blocks and a control block. Each PWM generator block contains one timer (16-bit down or up/down counter), two PWM comparators, a PWM signal generator, a dead-band generator, and an interrupt/ADC-trigger selector. The control block determines the polarity of the PWM signals, and which signals are passed through to the pins. Each PWM generator block produces two PWM signals that can either be independent signals (other than being based on the same timer and therefore having the same frequency) or a single pair of complementary signals with dead-band delays inserted. The output of the PWM generation blocks are managed by the output control block before being passed to the device pins. The Stellaris PWM module provides a great deal of flexibility. It can generate simple PWM signals, such as those required by a simple charge pump. It can also generate paired PWM signals with dead-band delays, such as those required by a half-H bridge driver. The three generator blocks can also generate the full six channels of gate controls required by a 3-phase inverter bridge. ® ® 18.1 Block Diagram Figure 18-1 on page 465 provides a block diagram of a Stellaris PWM module. The LM3S6965 controller contains three generator blocks (PWM0, PWM1, and PWM2) and generates six independent PWM signals or three paired PWM signals with dead-band delays inserted. Figure 18-1. PWM Module Block Diagram PWMnLOAD ® zero load dir PWM Generator Block PWMnGENA PWMnGENB PWM Clock Timer PWMnCOUNT 16 Fault PWMnCMPA cmpA Comparator A PWMnCMPB PWM Generator pwma pwmb PWMnDBCTL PWMnDBRISE PWMnDBFALL PWMENABLE PWMINVERT PWMFAULT cmpB Comparator B PWMnINTEN Dead-Band Generator PWM Output Control Interrupt and Trigger Generate PWMnRIS PWMnISC Interrupt 18.2 18.2.1 Functional Description PWM Timer The timer in each PWM generator runs in one of two modes: Count-Down mode or Count-Up/Down mode. In Count-Down mode, the timer counts from the load value to zero, goes back to the load value, and continues counting down. In Count-Up/Down mode, the timer counts from zero up to the November 30, 2007 Preliminary 465 Pulse Width Modulator (PWM) load value, back down to zero, back up to the load value, and so on. Generally, Count-Down mode is used for generating left- or right-aligned PWM signals, while the Count-Up/Down mode is used for generating center-aligned PWM signals. The timers output three signals that are used in the PWM generation process: the direction signal (this is always Low in Count-Down mode, but alternates between Low and High in Count-Up/Down mode), a single-clock-cycle-width High pulse when the counter is zero, and a single-clock-cycle-width High pulse when the counter is equal to the load value. Note that in Count-Down mode, the zero pulse is immediately followed by the load pulse. 18.2.2 PWM Comparators There are two comparators in each PWM generator that monitor the value of the counter; when either match the counter, they output a single-clock-cycle-width High pulse. When in Count-Up/Down mode, these comparators match both when counting up and when counting down; they are therefore qualified by the counter direction signal. These qualified pulses are used in the PWM generation process. If either comparator match value is greater than the counter load value, then that comparator never outputs a High pulse. Figure 18-2 on page 466 shows the behavior of the counter and the relationship of these pulses when the counter is in Count-Down mode. Figure 18-3 on page 467 shows the behavior of the counter and the relationship of these pulses when the counter is in Count-Up/Down mode. Figure 18-2. PWM Count-Down Mode Load CompA CompB Zero Load Zero A B Dir BDown ADown 466 Preliminary November 30, 2007 LM3S6965 Microcontroller Figure 18-3. PWM Count-Up/Down Mode Load CompA CompB Zero Load Zero A B Dir BUp AUp BDown ADown 18.2.3 PWM Signal Generator The PWM generator takes these pulses (qualified by the direction signal), and generates two PWM signals. In Count-Down mode, there are four events that can affect the PWM signal: zero, load, match A down, and match B down. In Count-Up/Down mode, there are six events that can affect the PWM signal: zero, load, match A down, match A up, match B down, and match B up. The match A or match B events are ignored when they coincide with the zero or load events. If the match A and match B events coincide, the first signal, PWMA, is generated based only on the match A event, and the second signal, PWMB, is generated based only on the match B event. For each event, the effect on each output PWM signal is programmable: it can be left alone (ignoring the event), it can be toggled, it can be driven Low, or it can be driven High. These actions can be used to generate a pair of PWM signals of various positions and duty cycles, which do or do not overlap. Figure 18-4 on page 467 shows the use of Count-Up/Down mode to generate a pair of center-aligned, overlapped PWM signals that have different duty cycles. Figure 18-4. PWM Generation Example In Count-Up/Down Mode Load CompA CompB Zero PWMA PWMB In this example, the first generator is set to drive High on match A up, drive Low on match A down, and ignore the other four events. The second generator is set to drive High on match B up, drive Low on match B down, and ignore the other four events. Changing the value of comparator A November 30, 2007 Preliminary 467 Pulse Width Modulator (PWM) changes the duty cycle of the PWMA signal, and changing the value of comparator B changes the duty cycle of the PWMB signal. 18.2.4 Dead-Band Generator The two PWM signals produced by the PWM generator are passed to the dead-band generator. If disabled, the PWM signals simply pass through unmodified. If enabled, the second PWM signal is lost and two PWM signals are generated based on the first PWM signal. The first output PWM signal is the input signal with the rising edge delayed by a programmable amount. The second output PWM signal is the inversion of the input signal with a programmable delay added between the falling edge of the input signal and the rising edge of this new signal. This is therefore a pair of active High signals where one is always High, except for a programmable amount of time at transitions where both are Low. These signals are therefore suitable for driving a half-H bridge, with the dead-band delays preventing shoot-through current from damaging the power electronics. Figure 18-5 on page 468 shows the effect of the dead-band generator on an input PWM signal. Figure 18-5. PWM Dead-Band Generator Input PWMA PWMB Rising Edge Delay Falling Edge Delay 18.2.5 Interrupt/ADC-Trigger Selector The PWM generator also takes the same four (or six) counter events and uses them to generate an interrupt or an ADC trigger. Any of these events or a set of these events can be selected as a source for an interrupt; when any of the selected events occur, an interrupt is generated. Additionally, the same event, a different event, the same set of events, or a different set of events can be selected as a source for an ADC trigger; when any of these selected events occur, an ADC trigger pulse is generated. The selection of events allows the interrupt or ADC trigger to occur at a specific position within the PWM signal. Note that interrupts and ADC triggers are based on the raw events; delays in the PWM signal edges caused by the dead-band generator are not taken into account. 18.2.6 Synchronization Methods There is a global reset capability that can synchronously reset any or all of the counters in the PWM generators. If multiple PWM generators are configured with the same counter load value, this can be used to guarantee that they also have the same count value (this does imply that the PWM generators must be configured before they are synchronized). With this, more than two PWM signals can be produced with a known relationship between the edges of those signals since the counters always have the same values. The counter load values and comparator match values of the PWM generator can be updated in two ways. The first is immediate update mode, where a new value is used as soon as the counter reaches zero. By waiting for the counter to reach zero, a guaranteed behavior is defined, and overly short or overly long output PWM pulses are prevented. The other update method is synchronous, where the new value is not used until a global synchronized update signal is asserted, at which point the new value is used as soon as the counter reaches zero. This second mode allows multiple items in multiple PWM generators to be updated 468 Preliminary November 30, 2007 LM3S6965 Microcontroller simultaneously without odd effects during the update; everything runs from the old values until a point at which they all run from the new values. The Update mode of the load and comparator match values can be individually configured in each PWM generator block. It typically makes sense to use the synchronous update mechanism across PWM generator blocks when the timers in those blocks are synchronized, though this is not required in order for this mechanism to function properly. 18.2.7 Fault Conditions There are two external conditions that affect the PWM block; the signal input on the Fault pin and the stalling of the controller by a debugger. There are two mechanisms available to handle such conditions: the output signals can be forced into an inactive state and/or the PWM timers can be stopped. Each output signal has a fault bit. If set, a fault input signal causes the corresponding output signal to go into the inactive state. If the inactive state is a safe condition for the signal to be in for an extended period of time, this keeps the output signal from driving the outside world in a dangerous manner during the fault condition. A fault condition can also generate a controller interrupt. Each PWM generator can also be configured to stop counting during a stall condition. The user can select for the counters to run until they reach zero then stop, or to continue counting and reloading. A stall condition does not generate a controller interrupt. 18.2.8 Output Control Block With each PWM generator block producing two raw PWM signals, the output control block takes care of the final conditioning of the PWM signals before they go to the pins. Via a single register, the set of PWM signals that are actually enabled to the pins can be modified; this can be used, for example, to perform commutation of a brushless DC motor with a single register write (and without modifying the individual PWM generators, which are modified by the feedback control loop). Similarly, fault control can disable any of the PWM signals as well. A final inversion can be applied to any of the PWM signals, making them active Low instead of the default active High. 18.3 Initialization and Configuration The following example shows how to initialize the PWM Generator 0 with a 25-KHz frequency, and with a 25% duty cycle on the PWM0 pin and a 75% duty cycle on the PWM1 pin. This example assumes the system clock is 20 MHz. 1. Enable the PWM clock by writing a value of 0x0010.0000 to the RCGC0 register in the System Control module. 2. Enable the clock to the appropriate GPIO module via the RCGC2 register in the System Control module. 3. In the GPIO module, enable the appropriate pins for their alternate function using the GPIOAFSEL register. 4. Configure the Run-Mode Clock Configuration (RCC) register in the System Control module to use the PWM divide (USEPWMDIV) and set the divider (PWMDIV) to divide by 2 (000). 5. Configure the PWM generator for countdown mode with immediate updates to the parameters. ■ Write the PWM0CTL register with a value of 0x0000.0000. ■ Write the PWM0GENA register with a value of 0x0000.008C. November 30, 2007 Preliminary 469 Pulse Width Modulator (PWM) ■ Write the PWM0GENB register with a value of 0x0000.080C. 6. Set the period. For a 25-KHz frequency, the period = 1/25,000, or 40 microseconds. The PWM clock source is 10 MHz; the system clock divided by 2. This translates to 400 clock ticks per period. Use this value to set the PWM0LOAD register. In Count-Down mode, set the Load field in the PWM0LOAD register to the requested period minus one. ■ Write the PWM0LOAD register with a value of 0x0000.018F. 7. Set the pulse width of the PWM0 pin for a 25% duty cycle. ■ Write the PWM0CMPA register with a value of 0x0000.012B. 8. Set the pulse width of the PWM1 pin for a 75% duty cycle. ■ Write the PWM0CMPB register with a value of 0x0000.0063. 9. Start the timers in PWM generator 0. ■ Write the PWM0CTL register with a value of 0x0000.0001. 10. Enable PWM outputs. ■ Write the PWMENABLE register with a value of 0x0000.0003. 18.4 Register Map Table 18-1 on page 470 lists the PWM registers. The offset listed is a hexadecimal increment to the register ’s address, relative to the PWM base address of 0x4002.8000. Table 18-1. PWM Register Map Offset 0x000 0x004 0x008 0x00C 0x010 0x014 0x018 0x01C 0x020 0x040 0x044 0x048 0x04C Name PWMCTL PWMSYNC PWMENABLE PWMINVERT PWMFAULT PWMINTEN PWMRIS PWMISC PWMSTATUS PWM0CTL PWM0INTEN PWM0RIS PWM0ISC Type R/W R/W R/W R/W R/W R/W RO R/W1C RO R/W R/W RO R/W1C Reset 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 Description PWM Master Control PWM Time Base Sync PWM Output Enable PWM Output Inversion PWM Output Fault PWM Interrupt Enable PWM Raw Interrupt Status PWM Interrupt Status and Clear PWM Status PWM0 Control PWM0 Interrupt and Trigger Enable PWM0 Raw Interrupt Status PWM0 Interrupt Status and Clear See page 473 474 475 476 477 478 479 480 481 482 484 486 487 470 Preliminary November 30, 2007 LM3S6965 Microcontroller Offset 0x050 0x054 0x058 0x05C 0x060 0x064 0x068 0x06C 0x070 0x080 0x084 0x088 0x08C 0x090 0x094 0x098 0x09C 0x0A0 0x0A4 0x0A8 0x0AC 0x0B0 0x0C0 0x0C4 0x0C8 0x0CC 0x0D0 0x0D4 0x0D8 0x0DC 0x0E0 0x0E4 0x0E8 Name PWM0LOAD PWM0COUNT PWM0CMPA PWM0CMPB PWM0GENA PWM0GENB PWM0DBCTL PWM0DBRISE PWM0DBFALL PWM1CTL PWM1INTEN PWM1RIS PWM1ISC PWM1LOAD PWM1COUNT PWM1CMPA PWM1CMPB PWM1GENA PWM1GENB PWM1DBCTL PWM1DBRISE PWM1DBFALL PWM2CTL PWM2INTEN PWM2RIS PWM2ISC PWM2LOAD PWM2COUNT PWM2CMPA PWM2CMPB PWM2GENA PWM2GENB PWM2DBCTL Type R/W RO R/W R/W R/W R/W R/W R/W R/W R/W R/W RO R/W1C R/W RO R/W R/W R/W R/W R/W R/W R/W R/W R/W RO R/W1C R/W RO R/W R/W R/W R/W R/W Reset 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 Description PWM0 Load PWM0 Counter PWM0 Compare A PWM0 Compare B PWM0 Generator A Control PWM0 Generator B Control PWM0 Dead-Band Control PWM0 Dead-Band Rising-Edge Delay PWM0 Dead-Band Falling-Edge-Delay PWM1 Control PWM1 Interrupt and Trigger Enable PWM1 Raw Interrupt Status PWM1 Interrupt Status and Clear PWM1 Load PWM1 Counter PWM1 Compare A PWM1 Compare B PWM1 Generator A Control PWM1 Generator B Control PWM1 Dead-Band Control PWM1 Dead-Band Rising-Edge Delay PWM1 Dead-Band Falling-Edge-Delay PWM2 Control PWM2 Interrupt and Trigger Enable PWM2 Raw Interrupt Status PWM2 Interrupt Status and Clear PWM2 Load PWM2 Counter PWM2 Compare A PWM2 Compare B PWM2 Generator A Control PWM2 Generator B Control PWM2 Dead-Band Control See page 488 489 490 491 492 495 498 499 500 482 484 486 487 488 489 490 491 492 495 498 499 500 482 484 486 487 488 489 490 491 492 495 498 November 30, 2007 Preliminary 471 Pulse Width Modulator (PWM) Offset 0x0EC 0x0F0 Name PWM2DBRISE PWM2DBFALL Type R/W R/W Reset 0x0000.0000 0x0000.0000 Description PWM2 Dead-Band Rising-Edge Delay PWM2 Dead-Band Falling-Edge-Delay See page 499 500 18.5 Register Descriptions The remainder of this section lists and describes the PWM registers, in numerical order by address offset. 472 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 1: PWM Master Control (PWMCTL), offset 0x000 This register provides master control over the PWM generation blocks. PWM Master Control (PWMCTL) Base 0x4002.8000 Offset 0x000 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 GlobalSync2 GlobalSync1 GlobalSync0 R/W 0 R/W 0 R/W 0 Bit/Field 31:3 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Update PWM Generator 2 Same as GlobalSync0 but for PWM generator 2. 2 GlobalSync2 R/W 0 1 GlobalSync1 R/W 0 Update PWM Generator 1 Same as GlobalSync0 but for PWM generator 1. 0 GlobalSync0 R/W 0 Update PWM Generator 0 Setting this bit causes any queued update to a load or comparator register in PWM generator 0 to be applied the next time the corresponding counter becomes zero. This bit automatically clears when the updates have completed; it cannot be cleared by software. November 30, 2007 Preliminary 473 Pulse Width Modulator (PWM) Register 2: PWM Time Base Sync (PWMSYNC), offset 0x004 This register provides a method to perform synchronization of the counters in the PWM generation blocks. Writing a bit in this register to 1 causes the specified counter to reset back to 0; writing multiple bits resets multiple counters simultaneously. The bits auto-clear after the reset has occurred; reading them back as zero indicates that the synchronization has completed. PWM Time Base Sync (PWMSYNC) Base 0x4002.8000 Offset 0x004 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 Sync2 R/W 0 RO 0 1 Sync1 R/W 0 RO 0 0 Sync0 R/W 0 Bit/Field 31:3 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Reset Generator 2 Counter Performs a reset of the PWM generator 2 counter. 2 Sync2 R/W 0 1 Sync1 R/W 0 Reset Generator 1 Counter Performs a reset of the PWM generator 1 counter. 0 Sync0 R/W 0 Reset Generator 0 Counter Performs a reset of the PWM generator 0 counter. 474 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 3: PWM Output Enable (PWMENABLE), offset 0x008 This register provides a master control of which generated PWM signals are output to device pins. By disabling a PWM output, the generation process can continue (for example, when the time bases are synchronized) without driving PWM signals to the pins. When bits in this register are set, the corresponding PWM signal is passed through to the output stage, which is controlled by the PWMINVERT register. When bits are not set, the PWM signal is replaced by a zero value which is also passed to the output stage. PWM Output Enable (PWMENABLE) Base 0x4002.8000 Offset 0x008 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 PWM5En PWM4En PWM3En PWM2En PWM1En PWM0En R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field 31:6 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. PWM5 Output Enable When set, allows the generated PWM5 signal to be passed to the device pin. 5 PWM5En R/W 0 4 PWM4En R/W 0 PWM4 Output Enable When set, allows the generated PWM4 signal to be passed to the device pin. 3 PWM3En R/W 0 PWM3 Output Enable When set, allows the generated PWM3 signal to be passed to the device pin. 2 PWM2En R/W 0 PWM2 Output Enable When set, allows the generated PWM2 signal to be passed to the device pin. 1 PWM1En R/W 0 PWM1 Output Enable When set, allows the generated PWM1 signal to be passed to the device pin. 0 PWM0En R/W 0 PWM0 Output Enable When set, allows the generated PWM0 signal to be passed to the device pin. November 30, 2007 Preliminary 475 Pulse Width Modulator (PWM) Register 4: PWM Output Inversion (PWMINVERT), offset 0x00C This register provides a master control of the polarity of the PWM signals on the device pins. The PWM signals generated by the PWM generator are active High; they can optionally be made active Low via this register. Disabled PWM channels are also passed through the output inverter (if so configured) so that inactive channels maintain the correct polarity. PWM Output Inversion (PWMINVERT) Base 0x4002.8000 Offset 0x00C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 PWM5Inv PWM4Inv PWM3Inv PWM2Inv PWM1Inv PWM0Inv R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field 31:6 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Invert PWM5 Signal When set, the generated PWM5 signal is inverted. 5 PWM5Inv R/W 0 4 PWM4Inv R/W 0 Invert PWM4 Signal When set, the generated PWM4 signal is inverted. 3 PWM3Inv R/W 0 Invert PWM3 Signal When set, the generated PWM3 signal is inverted. 2 PWM2Inv R/W 0 Invert PWM2 Signal When set, the generated PWM2 signal is inverted. 1 PWM1Inv R/W 0 Invert PWM1 Signal When set, the generated PWM1 signal is inverted. 0 PWM0Inv R/W 0 Invert PWM0 Signal When set, the generated PWM0 signal is inverted. 476 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 5: PWM Output Fault (PWMFAULT), offset 0x010 This register controls the behavior of the PWM outputs in the presence of fault conditions. Both the fault input and debug events are considered fault conditions. On a fault condition, each PWM signal can either be passed through unmodified or driven Low. For outputs that are configured for pass-through, the debug event handling on the corresponding PWM generator also determines if the PWM signal continues to be generated. Fault condition control happens before the output inverter, so PWM signals driven Low on fault are inverted if the channel is configured for inversion (therefore, the pin is driven High on a fault condition). PWM Output Fault (PWMFAULT) Base 0x4002.8000 Offset 0x010 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 Fault5 RO 0 RO 0 RO 0 RO 0 R/W 0 RO 0 4 Fault4 R/W 0 RO 0 3 Fault3 R/W 0 RO 0 2 Fault2 R/W 0 RO 0 1 Fault1 R/W 0 RO 0 0 Fault0 R/W 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:6 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. PWM5 Driven Low on Fault When set, the PWM5 output signal is driven Low on a fault condition. 5 Fault5 R/W 0 4 Fault4 R/W 0 PWM4 Driven Low on Fault When set, the PWM4 output signal is driven Low on a fault condition. 3 Fault3 R/W 0 PWM3 Driven Low on Fault When set, the PWM3 output signal is driven Low on a fault condition. 2 Fault2 R/W 0 PWM2 Driven Low on Fault When set, the PWM2 output signal is driven Low on a fault condition. 1 Fault1 R/W 0 PWM1 Driven Low on Fault When set, the PWM1 output signal is driven Low on a fault condition. 0 Fault0 R/W 0 PWM0 Driven Low on Fault When set, the PWM0 output signal is driven Low on a fault condition. November 30, 2007 Preliminary 477 Pulse Width Modulator (PWM) Register 6: PWM Interrupt Enable (PWMINTEN), offset 0x014 This register controls the global interrupt generation capabilities of the PWM module. The events that can cause an interrupt are the fault input and the individual interrupts from the PWM generators. PWM Interrupt Enable (PWMINTEN) Base 0x4002.8000 Offset 0x014 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 23 22 21 20 19 18 17 16 IntFault R/W 0 0 IntPWM2 IntPWM1 IntPWM0 R/W 0 R/W 0 R/W 0 Bit/Field 31:17 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Fault Interrupt Enable When 1, an interrupt occurs when the fault input is asserted. 16 IntFault R/W 0 15:3 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. PWM2 Interrupt Enable When 1, an interrupt occurs when the PWM generator 2 block asserts an interrupt. 2 IntPWM2 R/W 0 1 IntPWM1 R/W 0 PWM1 Interrupt Enable When 1, an interrupt occurs when the PWM generator 1 block asserts an interrupt. 0 IntPWM0 R/W 0 PWM0 Interrupt Enable When 1, an interrupt occurs when the PWM generator 0 block asserts an interrupt. 478 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 7: PWM Raw Interrupt Status (PWMRIS), offset 0x018 This register provides the current set of interrupt sources that are asserted, regardless of whether they cause an interrupt to be asserted to the controller. The fault interrupt is latched on detection; it must be cleared through the PWM Interrupt Status and Clear (PWMISC) register (see page 480). The PWM generator interrupts simply reflect the status of the PWM generators; they are cleared via the interrupt status register in the PWM generator blocks. Bits set to 1 indicate the events that are active; a zero bit indicates that the event in question is not active. PWM Raw Interrupt Status (PWMRIS) Base 0x4002.8000 Offset 0x018 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 23 22 21 20 19 18 17 16 IntFault RO 0 0 IntPWM2 IntPWM1 IntPWM0 RO 0 RO 0 RO 0 Bit/Field 31:17 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Fault Interrupt Asserted Indicates that the fault input has been asserted. 16 IntFault RO 0 15:3 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. PWM2 Interrupt Asserted Indicates that the PWM generator 2 block is asserting its interrupt. 2 IntPWM2 RO 0 1 IntPWM1 RO 0 PWM1 Interrupt Asserted Indicates that the PWM generator 1 block is asserting its interrupt. 0 IntPWM0 RO 0 PWM0 Interrupt Asserted Indicates that the PWM generator 0 block is asserting its interrupt. November 30, 2007 Preliminary 479 Pulse Width Modulator (PWM) Register 8: PWM Interrupt Status and Clear (PWMISC), offset 0x01C This register provides a summary of the interrupt status of the individual PWM generator blocks. A bit set to 1 indicates that the corresponding generator block is asserting an interrupt. The individual interrupt status registers in each block must be consulted to determine the reason for the interrupt, and used to clear the interrupt. For the fault interrupt, a write of 1 to that bit position clears the latched interrupt status. PWM Interrupt Status and Clear (PWMISC) Base 0x4002.8000 Offset 0x01C Type R/W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 23 22 21 20 19 18 17 16 IntFault R/W1C 0 0 IntPWM2 IntPWM1 IntPWM0 RO 0 RO 0 RO 0 Bit/Field 31:17 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Fault Interrupt Asserted Indicates if the fault input is asserting an interrupt. 16 IntFault R/W1C 0 15:3 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. PWM2 Interrupt Status Indicates if the PWM generator 2 block is asserting an interrupt. 2 IntPWM2 RO 0 1 IntPWM1 RO 0 PWM1 Interrupt Status Indicates if the PWM generator 1 block is asserting an interrupt. 0 IntPWM0 RO 0 PWM0 Interrupt Status Indicates if the PWM generator 0 block is asserting an interrupt. 480 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 9: PWM Status (PWMSTATUS), offset 0x020 This register provides the status of the Fault input signal. PWM Status (PWMSTATUS) Base 0x4002.8000 Offset 0x020 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 Fault RO 0 Bit/Field 31:1 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Fault Interrupt Status When set to 1, indicates the fault input is asserted. 0 Fault RO 0 November 30, 2007 Preliminary 481 Pulse Width Modulator (PWM) Register 10: PWM0 Control (PWM0CTL), offset 0x040 Register 11: PWM1 Control (PWM1CTL), offset 0x080 Register 12: PWM2 Control (PWM2CTL), offset 0x0C0 These registers configure the PWM signal generation blocks (PWM0CTL controls the PWM generator 0 block, and so on). The Register Update mode, Debug mode, Counting mode, and Block Enable mode are all controlled via these registers. The blocks produce the PWM signals, which can be either two independent PWM signals (from the same counter), or a paired set of PWM signals with dead-band delays added. The PWM0 block produces the PWM0 and PWM1 outputs, the PWM1 block produces the PWM2 and PWM3 outputs, and the PWM2 block produces the PWM4 and PWM5 outputs. PWM0 Control (PWM0CTL) Base 0x4002.8000 Offset 0x040 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 Debug R/W 0 RO 0 1 Mode R/W 0 RO 0 0 Enable R/W 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 CmpBUpd CmpAUpd LoadUpd R/W 0 R/W 0 R/W 0 Bit/Field 31:6 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Comparator B Update Mode Same as CmpAUpd but for the comparator B register. 5 CmpBUpd R/W 0 4 CmpAUpd R/W 0 Comparator A Update Mode The Update mode for the comparator A register. If 0, updates to the register are reflected to the comparator the next time the counter is 0. If 1, updates to the register are delayed until the next time the counter is 0 after a synchronous update has been requested through the PWM Master Control (PWMCTL) register (see page 473). 3 LoadUpd R/W 0 Load Register Update Mode The Update mode for the load register. If 0, updates to the register are reflected to the counter the next time the counter is 0. If 1, updates to the register are delayed until the next time the counter is 0 after a synchronous update has been requested through the PWM Master Control (PWMCTL) register. 2 Debug R/W 0 Debug Mode The behavior of the counter in Debug mode. If 0, the counter stops running when it next reaches 0, and continues running again when no longer in Debug mode. If 1, the counter always runs. 482 Preliminary November 30, 2007 LM3S6965 Microcontroller Bit/Field 1 Name Mode Type R/W Reset 0 Description Counter Mode The mode for the counter. If 0, the counter counts down from the load value to 0 and then wraps back to the load value (Count-Down mode). If 1, the counter counts up from 0 to the load value, back down to 0, and then repeats (Count-Up/Down mode). 0 Enable R/W 0 PWM Block Enable Master enable for the PWM generation block. If 0, the entire block is disabled and not clocked. If 1, the block is enabled and produces PWM signals. November 30, 2007 Preliminary 483 Pulse Width Modulator (PWM) Register 13: PWM0 Interrupt and Trigger Enable (PWM0INTEN), offset 0x044 Register 14: PWM1 Interrupt and Trigger Enable (PWM1INTEN), offset 0x084 Register 15: PWM2 Interrupt and Trigger Enable (PWM2INTEN), offset 0x0C4 These registers control the interrupt and ADC trigger generation capabilities of the PWM generators (PWM0INTEN controls the PWM generator 0 block, and so on). The events that can cause an interrupt or an ADC trigger are: ■ The counter being equal to the load register ■ The counter being equal to zero ■ The counter being equal to the comparator A register while counting up ■ The counter being equal to the comparator A register while counting down ■ The counter being equal to the comparator B register while counting up ■ The counter being equal to the comparator B register while counting down Any combination of these events can generate either an interruptor an ADC trigger, though no determination can be made as to the actual event that caused an ADC trigger if more than one is specified. PWM0 Interrupt and Trigger Enable (PWM0INTEN) Base 0x4002.8000 Offset 0x044 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 reserved RO 0 RO 0 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 TrCmpBD TrCmpBU TrCmpAD TrCmpAU TrCntLoad TrCntZero R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 IntCmpBD IntCmpBU IntCmpAD IntCmpAU IntCntLoad IntCntZero R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field 31:14 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Trigger for Counter=Comparator B Down When 1, a trigger pulse is output when the counter matches the comparator B value and the counter is counting down. 13 TrCmpBD R/W 0 12 TrCmpBU R/W 0 Trigger for Counter=Comparator B Up When 1, a trigger pulse is output when the counter matches the comparator B value and the counter is counting up. 11 TrCmpAD R/W 0 Trigger for Counter=Comparator A Down When 1, a trigger pulse is output when the counter matches the comparator A value and the counter is counting down. 484 Preliminary November 30, 2007 LM3S6965 Microcontroller Bit/Field 10 Name TrCmpAU Type R/W Reset 0 Description Trigger for Counter=Comparator A Up When 1, a trigger pulse is output when the counter matches the comparator A value and the counter is counting up. 9 TrCntLoad R/W 0 Trigger for Counter=Load When 1, a trigger pulse is output when the counter matches the PWMnLOAD register. 8 TrCntZero R/W 0 Trigger for Counter=0 When 1, a trigger pulse is output when the counter is 0. 7:6 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Interrupt for Counter=Comparator B Down When 1, an interrupt occurs when the counter matches the comparator B value and the counter is counting down. 5 IntCmpBD R/W 0 4 IntCmpBU R/W 0 Interrupt for Counter=Comparator B Up When 1, an interrupt occurs when the counter matches the comparator B value and the counter is counting up. 3 IntCmpAD R/W 0 Interrupt for Counter=Comparator A Down When 1, an interrupt occurs when the counter matches the comparator A value and the counter is counting down. 2 IntCmpAU R/W 0 Interrupt for Counter=Comparator A Up When 1, an interrupt occurs when the counter matches the comparator A value and the counter is counting up. 1 IntCntLoad R/W 0 Interrupt for Counter=Load When 1, an interrupt occurs when the counter matches the PWMnLOAD register. 0 IntCntZero R/W 0 Interrupt for Counter=0 When 1, an interrupt occurs when the counter is 0. November 30, 2007 Preliminary 485 Pulse Width Modulator (PWM) Register 16: PWM0 Raw Interrupt Status (PWM0RIS), offset 0x048 Register 17: PWM1 Raw Interrupt Status (PWM1RIS), offset 0x088 Register 18: PWM2 Raw Interrupt Status (PWM2RIS), offset 0x0C8 These registers provide the current set of interrupt sources that are asserted, regardless of whether they cause an interrupt to be asserted to the controller (PWM0RIS controls the PWM generator 0 block, and so on). Bits set to 1 indicate the latched events that have occurred; a 0 bit indicates that the event in question has not occurred. PWM0 Raw Interrupt Status (PWM0RIS) Base 0x4002.8000 Offset 0x048 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 IntCmpBD IntCmpBU IntCmpAD IntCmpAU IntCntLoad IntCntZero RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 Bit/Field 31:6 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Comparator B Down Interrupt Status Indicates that the counter has matched the comparator B value while counting down. 5 IntCmpBD RO 0 4 IntCmpBU RO 0 Comparator B Up Interrupt Status Indicates that the counter has matched the comparator B value while counting up. 3 IntCmpAD RO 0 Comparator A Down Interrupt Status Indicates that the counter has matched the comparator A value while counting down. 2 IntCmpAU RO 0 Comparator A Up Interrupt Status Indicates that the counter has matched the comparator A value while counting up. 1 IntCntLoad RO 0 Counter=Load Interrupt Status Indicates that the counter has matched the PWMnLOAD register. 0 IntCntZero RO 0 Counter=0 Interrupt Status Indicates that the counter has matched 0. 486 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 19: PWM0 Interrupt Status and Clear (PWM0ISC), offset 0x04C Register 20: PWM1 Interrupt Status and Clear (PWM1ISC), offset 0x08C Register 21: PWM2 Interrupt Status and Clear (PWM2ISC), offset 0x0CC These registers provide the current set of interrupt sources that are asserted to the controller (PWM0ISC controls the PWM generator 0 block, and so on). Bits set to 1 indicate the latched events that have occurred; a 0 bit indicates that the event in question has not occurred. These are R/W1C registers; writing a 1 to a bit position clears the corresponding interrupt reason. PWM0 Interrupt Status and Clear (PWM0ISC) Base 0x4002.8000 Offset 0x04C Type R/W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 IntCmpBD IntCmpBU IntCmpAD IntCmpAU IntCntLoad IntCntZero R/W1C 0 R/W1C 0 R/W1C 0 R/W1C 0 R/W1C 0 R/W1C 0 Bit/Field 31:6 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Comparator B Down Interrupt Indicates that the counter has matched the comparator B value while counting down. 5 IntCmpBD R/W1C 0 4 IntCmpBU R/W1C 0 Comparator B Up Interrupt Indicates that the counter has matched the comparator B value while counting up. 3 IntCmpAD R/W1C 0 Comparator A Down Interrupt Indicates that the counter has matched the comparator A value while counting down. 2 IntCmpAU R/W1C 0 Comparator A Up Interrupt Indicates that the counter has matched the comparator A value while counting up. 1 IntCntLoad R/W1C 0 Counter=Load Interrupt Indicates that the counter has matched the PWMnLOAD register. 0 IntCntZero R/W1C 0 Counter=0 Interrupt Indicates that the counter has matched 0. November 30, 2007 Preliminary 487 Pulse Width Modulator (PWM) Register 22: PWM0 Load (PWM0LOAD), offset 0x050 Register 23: PWM1 Load (PWM1LOAD), offset 0x090 Register 24: PWM2 Load (PWM2LOAD), offset 0x0D0 These registers contain the load value for the PWM counter (PWM0LOAD controls the PWM generator 0 block, and so on). Based on the counter mode, either this value is loaded into the counter after it reaches zero, or it is the limit of up-counting after which the counter decrements back to zero. If the Load Value Update mode is immediate, this value is used the next time the counter reaches zero; if the mode is synchronous, it is used the next time the counter reaches zero after a synchronous update has been requested through the PWM Master Control (PWMCTL) register (see page 473). If this register is re-written before the actual update occurs, the previous value is never used and is lost. PWM0 Load (PWM0LOAD) Base 0x4002.8000 Offset 0x050 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 Load Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 Bit/Field 31:16 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Counter Load Value The counter load value. 15:0 Load R/W 0 488 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 25: PWM0 Counter (PWM0COUNT), offset 0x054 Register 26: PWM1 Counter (PWM1COUNT), offset 0x094 Register 27: PWM2 Counter (PWM2COUNT), offset 0x0D4 These registers contain the current value of the PWM counter (PWM0COUNT is the value of the PWM generator 0 block, and so on). When this value matches the load register, a pulse is output; this can drive the generation of a PWM signal (via the PWMnGENA/PWMnGENB registers, see page 492 and page 495) or drive an interrupt or ADC trigger (via the PWMnINTEN register, see page 484). A pulse with the same capabilities is generated when this value is zero. PWM0 Counter (PWM0COUNT) Base 0x4002.8000 Offset 0x054 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 Count Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 Bit/Field 31:16 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Counter Value The current value of the counter. 15:0 Count RO 0x00 November 30, 2007 Preliminary 489 Pulse Width Modulator (PWM) Register 28: PWM0 Compare A (PWM0CMPA), offset 0x058 Register 29: PWM1 Compare A (PWM1CMPA), offset 0x098 Register 30: PWM2 Compare A (PWM2CMPA), offset 0x0D8 These registers contain a value to be compared against the counter (PWM0CMPA controls the PWM generator 0 block, and so on). When this value matches the counter, a pulse is output; this can drive the generation of a PWM signal (via the PWMnGENA/PWMnGENB registers) or drive an interrupt or ADC trigger (via the PWMnINTEN register). If the value of this register is greater than the PWMnLOAD register (see page 488), then no pulse is ever output. If the comparator A update mode is immediate (based on the CmpAUpd bit in the PWMnCTL register), then this 16-bit CompA value is used the next time the counter reaches zero. If the update mode is synchronous, it is used the next time the counter reaches zero after a synchronous update has been requested through the PWM Master Control (PWMCTL) register (see page 473). If this register is rewritten before the actual update occurs, the previous value is never used and is lost. PWM0 Compare A (PWM0CMPA) Base 0x4002.8000 Offset 0x058 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 CompA Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 Bit/Field 31:16 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Comparator A Value The value to be compared against the counter. 15:0 CompA R/W 0x00 490 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 31: PWM0 Compare B (PWM0CMPB), offset 0x05C Register 32: PWM1 Compare B (PWM1CMPB), offset 0x09C Register 33: PWM2 Compare B (PWM2CMPB), offset 0x0DC These registers contain a value to be compared against the counter (PWM0CMPB controls the PWM generator 0 block, and so on). When this value matches the counter, a pulse is output; this can drive the generation of a PWM signal (via the PWMnGENA/PWMnGENB registers) or drive an interrupt or ADC trigger (via the PWMnINTEN register). If the value of this register is greater than the PWMnLOAD register, then no pulse is ever output. IF the comparator B update mode is immediate (based on the CmpBUpd bit in the PWMnCTL register), then this 16-bit CompB value is used the next time the counter reaches zero. If the update mode is synchronous, it is used the next time the counter reaches zero after a synchronous update has been requested through the PWM Master Control (PWMCTL) register (see page 473). If this register is rewritten before the actual update occurs, the previous value is never used and is lost. PWM0 Compare B (PWM0CMPB) Base 0x4002.8000 Offset 0x05C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 CompB Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 Bit/Field 31:16 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Comparator B Value The value to be compared against the counter. 15:0 CompB R/W 0x00 November 30, 2007 Preliminary 491 Pulse Width Modulator (PWM) Register 34: PWM0 Generator A Control (PWM0GENA), offset 0x060 Register 35: PWM1 Generator A Control (PWM1GENA), offset 0x0A0 Register 36: PWM2 Generator A Control (PWM2GENA), offset 0x0E0 These registers control the generation of the PWMnA signal based on the load and zero output pulses from the counter, as well as the compare A and compare B pulses from the comparators (PWM0GENA controls the PWM generator 0 block, and so on). When the counter is running in Count-Down mode, only four of these events occur; when running in Count-Up/Down mode, all six occur. These events provide great flexibility in the positioning and duty cycle of the PWM signal that is produced. The PWM0GENA register controls generation of the PWM0A signal; PWM1GENA, the PWM1A signal; and PWM2GENA, the PWM2A signal. If a zero or load event coincides with a compare A or compare B event, the zero or load action is taken and the compare A or compare B action is ignored. If a compare A event coincides with a compare B event, the compare A action is taken and the compare B action is ignored. PWM0 Generator A Control (PWM0GENA) Base 0x4002.8000 Offset 0x060 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 ActLoad R/W 0 R/W 0 RO 0 2 RO 0 1 ActZero R/W 0 R/W 0 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 ActCmpBD R/W 0 R/W 0 ActCmpBU R/W 0 R/W 0 ActCmpAD R/W 0 R/W 0 ActCmpAU R/W 0 R/W 0 Bit/Field 31:12 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Action for Comparator B Down The action to be taken when the counter matches comparator B while counting down. The table below defines the effect of the event on the output signal. Value Description 0x0 Do nothing. 0x1 Invert the output signal. 0x2 Set the output signal to 0. 0x3 Set the output signal to 1. 11:10 ActCmpBD R/W 0x0 492 Preliminary November 30, 2007 LM3S6965 Microcontroller Bit/Field 9:8 Name ActCmpBU Type R/W Reset 0x0 Description Action for Comparator B Up The action to be taken when the counter matches comparator B while counting up. Occurs only when the Mode bit in the PWMnCTL register (see page 482) is set to 1. The table below defines the effect of the event on the output signal. Value Description 0x0 Do nothing. 0x1 Invert the output signal. 0x2 Set the output signal to 0. 0x3 Set the output signal to 1. 7:6 ActCmpAD R/W 0x0 Action for Comparator A Down The action to be taken when the counter matches comparator A while counting down. The table below defines the effect of the event on the output signal. Value Description 0x0 Do nothing. 0x1 Invert the output signal. 0x2 Set the output signal to 0. 0x3 Set the output signal to 1. 5:4 ActCmpAU R/W 0x0 Action for Comparator A Up The action to be taken when the counter matches comparator A while counting up. Occurs only when the Mode bit in the PWMnCTL register is set to 1. The table below defines the effect of the event on the output signal. Value Description 0x0 Do nothing. 0x1 Invert the output signal. 0x2 Set the output signal to 0. 0x3 Set the output signal to 1. 3:2 ActLoad R/W 0x0 Action for Counter=Load The action to be taken when the counter matches the load value. The table below defines the effect of the event on the output signal. Value Description 0x0 Do nothing. 0x1 Invert the output signal. 0x2 Set the output signal to 0. 0x3 Set the output signal to 1. November 30, 2007 Preliminary 493 Pulse Width Modulator (PWM) Bit/Field 1:0 Name ActZero Type R/W Reset 0x0 Description Action for Counter=0 The action to be taken when the counter is zero. The table below defines the effect of the event on the output signal. Value Description 0x0 Do nothing. 0x1 Invert the output signal. 0x2 Set the output signal to 0. 0x3 Set the output signal to 1. 494 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 37: PWM0 Generator B Control (PWM0GENB), offset 0x064 Register 38: PWM1 Generator B Control (PWM1GENB), offset 0x0A4 Register 39: PWM2 Generator B Control (PWM2GENB), offset 0x0E4 These registers control the generation of the PWMnB signal based on the load and zero output pulses from the counter, as well as the compare A and compare B pulses from the comparators (PWM0GENB controls the PWM generator 0 block, and so on). When the counter is running in Down mode, only four of these events occur; when running in Up/Down mode, all six occur. These events provide great flexibility in the positioning and duty cycle of the PWM signal that is produced. The PWM0GENB register controls generation of the PWM0B signal; PWM1GENB, the PWM1B signal; and PWM2GENB, the PWM2B signal. If a zero or load event coincides with a compare A or compare B event, the zero or load action is taken and the compare A or compare B action is ignored. If a compare A event coincides with a compare B event, the compare B action is taken and the compare A action is ignored. PWM0 Generator B Control (PWM0GENB) Base 0x4002.8000 Offset 0x064 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 ActLoad R/W 0 R/W 0 RO 0 2 RO 0 1 ActZero R/W 0 R/W 0 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 ActCmpBD R/W 0 R/W 0 ActCmpBU R/W 0 R/W 0 ActCmpAD R/W 0 R/W 0 ActCmpAU R/W 0 R/W 0 Bit/Field 31:12 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Action for Comparator B Down The action to be taken when the counter matches comparator B while counting down. The table below defines the effect of the event on the output signal. Value Description 0x0 Do nothing. 0x1 Invert the output signal. 0x2 Set the output signal to 0. 0x3 Set the output signal to 1. 11:10 ActCmpBD R/W 0x0 November 30, 2007 Preliminary 495 Pulse Width Modulator (PWM) Bit/Field 9:8 Name ActCmpBU Type R/W Reset 0x0 Description Action for Comparator B Up The action to be taken when the counter matches comparator B while counting up. Occurs only when the Mode bit in the PWMnCTL register is set to 1. The table below defines the effect of the event on the output signal. Value Description 0x0 Do nothing. 0x1 Invert the output signal. 0x2 Set the output signal to 0. 0x3 Set the output signal to 1. 7:6 ActCmpAD R/W 0x0 Action for Comparator A Down The action to be taken when the counter matches comparator A while counting down. The table below defines the effect of the event on the output signal. Value Description 0x0 Do nothing. 0x1 Invert the output signal. 0x2 Set the output signal to 0. 0x3 Set the output signal to 1. 5:4 ActCmpAU R/W 0x0 Action for Comparator A Up The action to be taken when the counter matches comparator A while counting up. Occurs only when the Mode bit in the PWMnCTL register is set to 1. The table below defines the effect of the event on the output signal. Value Description 0x0 Do nothing. 0x1 Invert the output signal. 0x2 Set the output signal to 0. 0x3 Set the output signal to 1. 3:2 ActLoad R/W 0x0 Action for Counter=Load The action to be taken when the counter matches the load value. The table below defines the effect of the event on the output signal. Value Description 0x0 Do nothing. 0x1 Invert the output signal. 0x2 Set the output signal to 0. 0x3 Set the output signal to 1. 496 Preliminary November 30, 2007 LM3S6965 Microcontroller Bit/Field 1:0 Name ActZero Type R/W Reset 0x0 Description Action for Counter=0 The action to be taken when the counter is 0. The table below defines the effect of the event on the output signal. Value Description 0x0 Do nothing. 0x1 Invert the output signal. 0x2 Set the output signal to 0. 0x3 Set the output signal to 1. November 30, 2007 Preliminary 497 Pulse Width Modulator (PWM) Register 40: PWM0 Dead-Band Control (PWM0DBCTL), offset 0x068 Register 41: PWM1 Dead-Band Control (PWM1DBCTL), offset 0x0A8 Register 42: PWM2 Dead-Band Control (PWM2DBCTL), offset 0x0E8 The PWM0DBCTL register controls the dead-band generator, which produces the PWM0 and PWM1 signals based on the PWM0A and PWM0B signals. When disabled, the PWM0A signal passes through to the PWM0 signal and the PWM0B signal passes through to the PWM1 signal. When enabled and inverting the resulting waveform, the PWM0B signal is ignored; the PWM0 signal is generated by delaying the rising edge(s) of the PWM0A signal by the value in the PWM0DBRISE register (see page 499), and the PWM1 signal is generated by delaying the falling edge(s) of the PWM0A signal by the value in the PWM0DBFALL register (see page 500). In a similar manner, PWM2 and PWM3 are produced from the PWM1A and PWM1B signals, and PWM4 and PWM5 are produced from the PWM2A and PWM2B signals. PWM0 Dead-Band Control (PWM0DBCTL) Base 0x4002.8000 Offset 0x068 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 Enable R/W 0 Bit/Field 31:1 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Dead-Band Generator Enable When set, the dead-band generator inserts dead bands into the output signals; when clear, it simply passes the PWM signals through. 0 Enable R/W 0 498 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 43: PWM0 Dead-Band Rising-Edge Delay (PWM0DBRISE), offset 0x06C Register 44: PWM1 Dead-Band Rising-Edge Delay (PWM1DBRISE), offset 0x0AC Register 45: PWM2 Dead-Band Rising-Edge Delay (PWM2DBRISE), offset 0x0EC The PWM0DBRISE register contains the number of clock ticks to delay the rising edge of the PWM0A signal when generating the PWM0 signal. If the dead-band generator is disabled through the PWMnDBCTL register, the PWM0DBRISE register is ignored. If the value of this register is larger than the width of a High pulse on the input PWM signal, the rising-edge delay consumes the entire High time of the signal, resulting in no High time on the output. Care must be taken to ensure that the input High time always exceeds the rising-edge delay. In a similar manner, PWM2 is generated from PWM1A with its rising edge delayed and PWM4 is produced from PWM2A with its rising edge delayed. PWM0 Dead-Band Rising-Edge Delay (PWM0DBRISE) Base 0x4002.8000 Offset 0x06C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 RiseDelay R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 Bit/Field 31:12 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Dead-Band Rise Delay The number of clock ticks to delay the rising edge. 11:0 RiseDelay R/W 0 November 30, 2007 Preliminary 499 Pulse Width Modulator (PWM) Register 46: PWM0 Dead-Band Falling-Edge-Delay (PWM0DBFALL), offset 0x070 Register 47: PWM1 Dead-Band Falling-Edge-Delay (PWM1DBFALL), offset 0x0B0 Register 48: PWM2 Dead-Band Falling-Edge-Delay (PWM2DBFALL), offset 0x0F0 The PWM0DBFALL register contains the number of clock ticks to delay the falling edge of the PWM0A signal when generating the PWM1 signal. If the dead-band generator is disabled, this register is ignored. If the value of this register is larger than the width of a Low pulse on the input PWM signal, the falling-edge delay consumes the entire Low time of the signal, resulting in no Low time on the output. Care must be taken to ensure that the input Low time always exceeds the falling-edge delay. In a similar manner, PWM3 is generated from PWM1A with its falling edge delayed and PWM5 is produced from PWM2A with its falling edge delayed. PWM0 Dead-Band Falling-Edge-Delay (PWM0DBFALL) Base 0x4002.8000 Offset 0x070 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 RO 0 7 RO 0 6 FallDelay RO 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 reserved Type Reset RO 0 RO 0 RO 0 Bit/Field 31:12 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Dead-Band Fall Delay The number of clock ticks to delay the falling edge. 11:0 FallDelay R/W 0x00 500 Preliminary November 30, 2007 LM3S6965 Microcontroller 19 Quadrature Encoder Interface (QEI) A quadrature encoder, also known as a 2-channel incremental encoder, converts linear displacement into a pulse signal. By monitoring both the number of pulses and the relative phase of the two signals, you can track the position, direction of rotation, and speed. In addition, a third channel, or index signal, can be used to reset the position counter. The LM3S6965 microcontroller includes two quadrature encoder interface (QEI) modules. Each QEI module interprets the code produced by a quadrature encoder wheel to integrate position over time and determine direction of rotation. In addition, it can capture a running estimate of the velocity of the encoder wheel. Each Stellaris quadrature encoder has the following features: ■ Position integrator that tracks the encoder position ■ Velocity capture using built-in timer ■ Interrupt generation on: – Index pulse – Velocity-timer expiration – Direction change – Quadrature error detection ® 19.1 Block Diagram Figure 19-1 on page 502 provides a block diagram of a Stellaris QEI module. ® November 30, 2007 Preliminary 501 Quadrature Encoder Interface (QEI) Figure 19-1. QEI Block Diagram QEILOAD Control & Status QEICTL QEISTAT Velocity Timer QEITIME Velocity Accumulator Velocity Predivider PhA PhB IDX QEIINTEN QEICOUNT QEISPEED clk QEIMAXPOS Quadrature Encoder dir Position Integrator QEIPOS Interrupt Control QEIRIS QEIISC Interrupt 19.2 Functional Description The QEI module interprets the two-bit gray code produced by a quadrature encoder wheel to integrate position over time and determine direction of rotation. In addition, it can capture a running estimate of the velocity of the encoder wheel. The position integrator and velocity capture can be independently enabled, though the position integrator must be enabled before the velocity capture can be enabled. The two phase signals, PhA and PhB, can be swapped before being interpreted by the QEI module to change the meaning of forward and backward, and to correct for miswiring of the system. Alternatively, the phase signals can be interpreted as a clock and direction signal as output by some encoders. The QEI module supports two modes of signal operation: quadrature phase mode and clock/direction mode. In quadrature phase mode, the encoder produces two clocks that are 90 degrees out of phase; the edge relationship is used to determine the direction of rotation. In clock/direction mode, the encoder produces a clock signal to indicate steps and a direction signal to indicate the direction of rotation. This mode is determined by the SigMode bit of the QEI Control (QEICTL) register (see page 506). When the QEI module is set to use the quadrature phase mode (SigMode bit equals zero), the capture mode for the position integrator can be set to update the position counter on every edge of the PhA signal or to update on every edge of both PhA and PhB. Updating the position counter on every PhA and PhB provides more positional resolution at the cost of less range in the positional counter. When edges on PhA lead edges on PhB , the position counter is incremented. When edges on PhB lead edges on PhA , the position counter is decremented. When a rising and falling edge pair is seen on one of the phases without any edges on the other, the direction of rotation has changed. 502 Preliminary November 30, 2007 LM3S6965 Microcontroller The positional counter is automatically reset on one of two conditions: sensing the index pulse or reaching the maximum position value. Which mode is determined by the ResMode bit of the QEI Control (QEICTL) register. When ResMode is 0, the positional counter is reset when the index pulse is sensed. This limits the positional counter to the values [0:N-1], where N is the number of phase edges in a full revolution of the encoder wheel. The QEIMAXPOS register must be programmed with N-1 so that the reverse direction from position 0 can move the position counter to N-1. In this mode, the position register contains the absolute position of the encoder relative to the index (or home) position once an index pulse has been seen. When ResMode is 1, the positional counter is constrained to the range [0:M], where M is the programmable maximum value. The index pulse is ignored by the positional counter in this mode. The velocity capture has a configurable timer and a count register. It counts the number of phase edges (using the same configuration as for the position integrator) in a given time period. The edge count from the previous time period is available to the controller via the QEISPEED register, while the edge count for the current time period is being accumulated in the QEICOUNT register. As soon as the current time period is complete, the total number of edges counted in that time period is made available in the QEISPEED register (losing the previous value), the QEICOUNT is reset to 0, and counting commences on a new time period. The number of edges counted in a given time period is directly proportional to the velocity of the encoder. Figure 19-2 on page 503 shows how the Stellaris quadrature encoder converts the phase input signals into clock pulses, the direction signal, and how the velocity predivider operates (in Divide by 4 mode). Figure 19-2. Quadrature Encoder and Velocity Predivider Operation PhA PhB clk clkdiv dir pos rel -1 -1 -1 -1 -1 -1 -1 -1 -1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 +1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +1 +1 +1 ® The period of the timer is configurable by specifying the load value for the timer in the QEILOAD register. When the timer reaches zero, an interrupt can be triggered, and the hardware reloads the timer with the QEILOAD value and continues to count down. At lower encoder speeds, a longer timer period is needed to be able to capture enough edges to have a meaningful result. At higher encoder speeds, both a shorter timer period and/or the velocity predivider can be used. The following equation converts the velocity counter value into an rpm value: rpm = (clock * (2 ^ VelDiv) * Speed * 60) ÷ (Load * ppr * edges) where: clock is the controller clock rate ppr is the number of pulses per revolution of the physical encoder edges is 2 or 4, based on the capture mode set in the QEICTL register (2 for CapMode set to 0 and 4 for CapMode set to 1) For example, consider a motor running at 600 rpm. A 2048 pulse per revolution quadrature encoder is attached to the motor, producing 8192 phase edges per revolution. With a velocity predivider of November 30, 2007 Preliminary 503 Quadrature Encoder Interface (QEI) ÷1 (VelDiv set to 0) and clocking on both PhA and PhB edges, this results in 81,920 pulses per second (the motor turns 10 times per second). If the timer were clocked at 10,000 Hz, and the load value was 2,500 (¼ of a second), it would count 20,480 pulses per update. Using the above equation: rpm = (10000 * 1 * 20480 * 60) ÷ (2500 * 2048 * 4) = 600 rpm Now, consider that the motor is sped up to 3000 rpm. This results in 409,600 pulses per second, or 102,400 every ¼ of a second. Again, the above equation gives: rpm = (10000 * 1 * 102400 * 60) ÷ (2500 * 2048 * 4) = 3000 rpm Care must be taken when evaluating this equation since intermediate values may exceed the capacity of a 32-bit integer. In the above examples, the clock is 10,000 and the divider is 2,500; both could be predivided by 100 (at compile time if they are constants) and therefore be 100 and 25. In fact, if they were compile-time constants, they could also be reduced to a simple multiply by 4, cancelled by the ÷4 for the edge-count factor. Important: Reducing constant factors at compile time is the best way to control the intermediate values of this equation, as well as reducing the processing requirement of computing this equation. The division can be avoided by selecting a timer load value such that the divisor is a power of 2; a simple shift can therefore be done in place of the division. For encoders with a power of 2 pulses per revolution, this is a simple matter of selecting a power of 2 load value. For other encoders, a load value must be selected such that the product is very close to a power of two. For example, a 100 pulse per revolution encoder could use a load value of 82, resulting in 32,800 as the divisor, which is 0.09% above 214; in this case a shift by 15 would be an adequate approximation of the divide in most cases. If absolute accuracy were required, the controller ’s divide instruction could be used. The QEI module can produce a controller interrupt on several events: phase error, direction change, reception of the index pulse, and expiration of the velocity timer. Standard masking, raw interrupt status, interrupt status, and interrupt clear capabilities are provided. 19.3 Initialization and Configuration The following example shows how to configure the Quadrature Encoder module to read back an absolute position: 1. Enable the QEI clock by writing a value of 0x0000.0100 to the RCGC1 register in the System Control module. 2. Enable the clock to the appropriate GPIO module via the RCGC2 register in the System Control module. 3. In the GPIO module, enable the appropriate pins for their alternate function using the GPIOAFSEL register. 4. Configure the quadrature encoder to capture edges on both signals and maintain an absolute position by resetting on index pulses. Using a 1000-line encoder at four edges per line, there are 4000 pulses per revolution; therefore, set the maximum position to 3999 (0xF9F) since the count is zero-based. ■ Write the QEICTL register with the value of 0x0000.0018. 504 Preliminary November 30, 2007 LM3S6965 Microcontroller ■ Write the QEIMAXPOS register with the value of 0x0000.0F9F. 5. Enable the quadrature encoder by setting bit 0 of the QEICTL register. 6. Delay for some time. 7. Read the encoder position by reading the QEIPOS register value. 19.4 Register Map Table 19-1 on page 505 lists the QEI registers. The offset listed is a hexadecimal increment to the register ’s address, relative to the module’s base address: ■ QEI0: 0x4002.C000 ■ QEI1: 0x4002.D000 Table 19-1. QEI Register Map Offset 0x000 0x004 0x008 0x00C 0x010 0x014 0x018 0x01C 0x020 0x024 0x028 Name QEICTL QEISTAT QEIPOS QEIMAXPOS QEILOAD QEITIME QEICOUNT QEISPEED QEIINTEN QEIRIS QEIISC Type R/W RO R/W R/W R/W RO RO RO R/W RO R/W1C Reset 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 0x0000.0000 Description QEI Control QEI Status QEI Position QEI Maximum Position QEI Timer Load QEI Timer QEI Velocity Counter QEI Velocity QEI Interrupt Enable QEI Raw Interrupt Status QEI Interrupt Status and Clear See page 506 508 509 510 511 512 513 514 515 516 517 19.5 Register Descriptions The remainder of this section lists and describes the QEI registers, in numerical order by address offset. November 30, 2007 Preliminary 505 Quadrature Encoder Interface (QEI) Register 1: QEI Control (QEICTL), offset 0x000 This register contains the configuration of the QEI module. Separate enables are provided for the quadrature encoder and the velocity capture blocks; the quadrature encoder must be enabled in order to capture the velocity, but the velocity does not need to be captured in applications that do not need it. The phase signal interpretation, phase swap, Position Update mode, Position Reset mode, and velocity predivider are all set via this register. QEI Control (QEICTL) QEI0 base: 0x4002.C000 QEI1 base: 0x4002.D000 Offset 0x000 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 reserved Type Reset RO 0 RO 0 RO 0 RO 0 13 RO 0 12 STALLEN R/W 0 RO 0 11 INVI R/W 0 RO 0 10 INVB R/W 0 RO 0 9 INVA R/W 0 R/W 0 RO 0 8 RO 0 7 VelDiv R/W 0 R/W 0 RO 0 6 RO 0 5 VelEn R/W 0 RO 0 4 RO 0 3 RO 0 2 RO 0 1 Swap R/W 0 RO 0 0 Enable R/W 0 ResMode CapMode SigMode R/W 0 R/W 0 R/W 0 Bit/Field 31:13 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Stall QEI When set, the QEI stalls when the microcontroller asserts Halt. 12 STALLEN R/W 0 11 INVI R/W 0 Invert Index Pulse When set , the input Index Pulse is inverted. 10 INVB R/W 0 Invert PhB When set, the PhB input is inverted. 9 INVA R/W 0 Invert PhA When set, the PhA input is inverted. 8:6 VelDiv R/W 0x0 Predivide Velocity A predivider of the input quadrature pulses before being applied to the QEICOUNT accumulator. This field can be set to the following values: Value Predivider 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 ÷1 ÷2 ÷4 ÷8 ÷16 ÷32 ÷64 ÷128 506 Preliminary November 30, 2007 LM3S6965 Microcontroller Bit/Field 5 Name VelEn Type R/W Reset 0 Description Capture Velocity When set, enables capture of the velocity of the quadrature encoder. 4 ResMode R/W 0 Reset Mode The Reset mode for the position counter. When 0, the position counter is reset when it reaches the maximum; when 1, the position counter is reset when the index pulse is captured. 3 CapMode R/W 0 Capture Mode The Capture mode defines the phase edges that are counted in the position. When 0, only the PhA edges are counted; when 1, the PhA and PhB edges are counted, providing twice the positional resolution but half the range. 2 SigMode R/W 0 Signal Mode When 1, the PhA and PhB signals are clock and direction; when 0, they are quadrature phase signals. 1 Swap R/W 0 Swap Signals Swaps the PhA and PhB signals. 0 Enable R/W 0 Enable QEI Enables the quadrature encoder module. November 30, 2007 Preliminary 507 Quadrature Encoder Interface (QEI) Register 2: QEI Status (QEISTAT), offset 0x004 This register provides status about the operation of the QEI module. QEI Status (QEISTAT) QEI0 base: 0x4002.C000 QEI1 base: 0x4002.D000 Offset 0x004 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 Direction RO 0 0 Error RO 0 RO 0 Bit/Field 31:2 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Direction of Rotation Indicates the direction the encoder is rotating. The Direction values are defined as follows: Value Description 0 1 Forward rotation Reverse rotation 1 Direction RO 0 0 Error RO 0 Error Detected Indicates that an error was detected in the gray code sequence (that is, both signals changing at the same time). 508 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 3: QEI Position (QEIPOS), offset 0x008 This register contains the current value of the position integrator. Its value is updated by inputs on the QEI phase inputs, and can be set to a specific value by writing to it. QEI Position (QEIPOS) QEI0 base: 0x4002.C000 QEI1 base: 0x4002.D000 Offset 0x008 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 Position Type Reset R/W 0 15 R/W 0 14 R/W 0 13 R/W 0 12 R/W 0 11 R/W 0 10 R/W 0 9 R/W 0 8 Position Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 23 22 21 20 19 18 17 16 Bit/Field 31:0 Name Position Type R/W Reset 0x00 Description Current Position Integrator Value The current value of the position integrator. November 30, 2007 Preliminary 509 Quadrature Encoder Interface (QEI) Register 4: QEI Maximum Position (QEIMAXPOS), offset 0x00C This register contains the maximum value of the position integrator. When moving forward, the position register resets to zero when it increments past this value. When moving backward, the position register resets to this value when it decrements from zero. QEI Maximum Position (QEIMAXPOS) QEI0 base: 0x4002.C000 QEI1 base: 0x4002.D000 Offset 0x00C Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 MaxPos Type Reset R/W 0 15 R/W 0 14 R/W 0 13 R/W 0 12 R/W 0 11 R/W 0 10 R/W 0 9 R/W 0 8 MaxPos Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 23 22 21 20 19 18 17 16 Bit/Field 31:0 Name MaxPos Type R/W Reset 0x00 Description Maximum Position Integrator Value The maximum value of the position integrator. 510 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 5: QEI Timer Load (QEILOAD), offset 0x010 This register contains the load value for the velocity timer. Since this value is loaded into the timer the clock cycle after the timer is zero, this value should be one less than the number of clocks in the desired period. So, for example, to have 2000 clocks per timer period, this register should contain 1999. QEI Timer Load (QEILOAD) QEI0 base: 0x4002.C000 QEI1 base: 0x4002.D000 Offset 0x010 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 Load Type Reset R/W 0 15 R/W 0 14 R/W 0 13 R/W 0 12 R/W 0 11 R/W 0 10 R/W 0 9 R/W 0 8 Load Type Reset R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 23 22 21 20 19 18 17 16 Bit/Field 31:0 Name Load Type R/W Reset 0x00 Description Velocity Timer Load Value The load value for the velocity timer. November 30, 2007 Preliminary 511 Quadrature Encoder Interface (QEI) Register 6: QEI Timer (QEITIME), offset 0x014 This register contains the current value of the velocity timer. This counter does not increment when VelEn in QEICTL is 0. QEI Timer (QEITIME) QEI0 base: 0x4002.C000 QEI1 base: 0x4002.D000 Offset 0x014 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 Time Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 Time Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 23 22 21 20 19 18 17 16 Bit/Field 31:0 Name Time Type RO Reset 0x00 Description Velocity Timer Current Value The current value of the velocity timer. 512 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 7: QEI Velocity Counter (QEICOUNT), offset 0x018 This register contains the running count of velocity pulses for the current time period. Since this is a running total, the time period to which it applies cannot be known with precision (that is, a read of this register does not necessarily correspond to the time returned by the QEITIME register since there is a small window of time between the two reads, during which time either value may have changed). The QEISPEED register should be used to determine the actual encoder velocity; this register is provided for information purposes only. This counter does not increment when VelEn in QEICTL is 0. QEI Velocity Counter (QEICOUNT) QEI0 base: 0x4002.C000 QEI1 base: 0x4002.D000 Offset 0x018 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 Count Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 Count Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 23 22 21 20 19 18 17 16 Bit/Field 31:0 Name Count Type RO Reset 0x00 Description Velocity Pulse Count The running total of encoder pulses during this velocity timer period. November 30, 2007 Preliminary 513 Quadrature Encoder Interface (QEI) Register 8: QEI Velocity (QEISPEED), offset 0x01C This register contains the most recently measured velocity of the quadrature encoder. This corresponds to the number of velocity pulses counted in the previous velocity timer period. This register does not update when VelEn in QEICTL is 0. QEI Velocity (QEISPEED) QEI0 base: 0x4002.C000 QEI1 base: 0x4002.D000 Offset 0x01C Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 Speed Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 RO 0 8 Speed Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 RO 0 0 23 22 21 20 19 18 17 16 Bit/Field 31:0 Name Speed Type RO Reset 0x00 Description Velocity The measured speed of the quadrature encoder in pulses per period. 514 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 9: QEI Interrupt Enable (QEIINTEN), offset 0x020 This register contains enables for each of the QEI module’s interrupts. An interrupt is asserted to the controller if its corresponding bit in this register is set to 1. QEI Interrupt Enable (QEIINTEN) QEI0 base: 0x4002.C000 QEI1 base: 0x4002.D000 Offset 0x020 Type R/W, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 IntError R/W 0 RO 0 2 IntDir R/W 0 RO 0 1 IntTimer R/W 0 RO 0 0 IntIndex R/W 0 Bit/Field 31:4 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Phase Error Interrupt Enable When 1, an interrupt occurs when a phase error is detected. 3 IntError R/W 0 2 IntDir R/W 0 Direction Change Interrupt Enable When 1, an interrupt occurs when the direction changes. 1 IntTimer R/W 0 Timer Expires Interrupt Enable When 1, an interrupt occurs when the velocity timer expires. 0 IntIndex R/W 0 Index Pulse Detected Interrupt Enable When 1, an interrupt occurs when the index pulse is detected. November 30, 2007 Preliminary 515 Quadrature Encoder Interface (QEI) Register 10: QEI Raw Interrupt Status (QEIRIS), offset 0x024 This register provides the current set of interrupt sources that are asserted, regardless of whether they cause an interrupt to be asserted to the controller (this is set through the QEIINTEN register). Bits set to 1 indicate the latched events that have occurred; a zero bit indicates that the event in question has not occurred. QEI Raw Interrupt Status (QEIRIS) QEI0 base: 0x4002.C000 QEI1 base: 0x4002.D000 Offset 0x024 Type RO, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 IntError RO 0 RO 0 2 IntDir RO 0 RO 0 1 IntTimer RO 0 RO 0 0 IntIndex RO 0 Bit/Field 31:4 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Phase Error Detected Indicates that a phase error was detected. 3 IntError RO 0 2 IntDir RO 0 Direction Change Detected Indicates that the direction has changed. 1 IntTimer RO 0 Velocity Timer Expired Indicates that the velocity timer has expired. 0 IntIndex RO 0 Index Pulse Asserted Indicates that the index pulse has occurred. 516 Preliminary November 30, 2007 LM3S6965 Microcontroller Register 11: QEI Interrupt Status and Clear (QEIISC), offset 0x028 This register provides the current set of interrupt sources that are asserted to the controller. Bits set to 1 indicate the latched events that have occurred; a zero bit indicates that the event in question has not occurred. This is a R/W1C register; writing a 1 to a bit position clears the corresponding interrupt reason. QEI Interrupt Status and Clear (QEIISC) QEI0 base: 0x4002.C000 QEI1 base: 0x4002.D000 Offset 0x028 Type R/W1C, reset 0x0000.0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 9 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 IntError R/W1C 0 RO 0 2 IntDir R/W1C 0 RO 0 1 IntTimer R/W1C 0 RO 0 0 IntIndex R/W1C 0 Bit/Field 31:4 Name reserved Type RO Reset 0x00 Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Phase Error Interrupt Indicates that a phase error was detected. 3 IntError R/W1C 0 2 IntDir R/W1C 0 Direction Change Interrupt Indicates that the direction has changed. 1 IntTimer R/W1C 0 Velocity Timer Expired Interrupt Indicates that the velocity timer has expired. 0 IntIndex R/W1C 0 Index Pulse Interrupt Indicates that the index pulse has occurred. November 30, 2007 Preliminary 517 Pin Diagram 20 Pin Diagram Figure 20-1 on page 518 shows the pin diagram and pin-to-signal-name mapping. Figure 20-1. Pin Connection Diagram PA0/U0Rx PA1/U0Tx PA2/SSI0Clk PA3/SSI0Fss PA4/SSI0Rx PA5/SSI0Tx VDD GND PA6/I2C1SCL PA7/I2C1SDA VCCPHY RXIN VDD25 GND RXIP GNDPHY GNDPHY TXOP VDD GND LM3S6965 518 Preliminary TXON PF0/PWM0 OSC0 OSC1 WAKE 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 ADC0 ADC1 VDDA GNDA ADC2 ADC3 LDO VDD GND PD0/IDX0 PD1/PWM1 PD2/U1Rx PD3/U1Tx VDD25 GND XTALPPHY XTALNPHY PG1/U2Tx PG0/U2Rx VDD GND PC7/PhB0 PC6/CCP3 PC5/C1+/C0o PC4/PhA0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 VCCPHY VCCPHY GND VDD PC0/TCK/SWCLK PC1/TMS/SWDIO PC2/TDI PC3/TDO/SWO CMOD1 PD7/CCP1 PD6/Fault VDDA GNDA PD5/CCP2 PD4/CCP0 GND VDD PB4/C0PB5/C1PB6/C0+ PB7/TRST VDD25 GND GNDPHY GNDPHY 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 PE3/PhA1 PE2/PhB1 PE1/PWM5 PE0/PWM4 PB3/I2C0SDA PB2/I2C0SCL GND VDD PB1/PWM3 PB0/PWM2 CMOD0 RST GND VDD25 PF1/IDX1 PF2/LED1 PF3/LED0 MDIO GND VDD VBAT GND XOSC1 XOSC0 HIB November 30, 2007 LM3S6965 Microcontroller 21 Signal Tables The following tables list the signals available for each pin. Functionality is enabled by software with the GPIOAFSEL register. Important: All multiplexed pins are GPIOs by default, with the exception of the five JTAG pins (PB7 and PC[3:0]) which default to the JTAG functionality. Table 21-1 on page 519 shows the pin-to-signal-name mapping, including functional characteristics of the signals. Table 21-2 on page 523 lists the signals in alphabetical order by signal name. Table 21-3 on page 528 groups the signals by functionality, except for GPIOs. Table 21-4 on page 532 lists the GPIO pins and their alternate functionality. Table 21-1. Signals by Pin Number Pin Number 1 2 3 Pin Name ADC0 ADC1 VDDA Pin Type I I Buffer Type Description Analog Analog Power Analog-to-digital converter input 0. Analog-to-digital converter input 1. The positive supply (3.3 V) for the analog circuits (ADC, Analog Comparators, etc.). These are separated from VDD to minimize the electrical noise contained on VDD from affecting the analog functions. The ground reference for the analog circuits (ADC, Analog Comparators, etc.). These are separated from GND to minimize the electrical noise contained on VDD from affecting the analog functions. Analog-to-digital converter input 2. Analog-to-digital converter input 3. Low drop-out regulator output voltage. This pin requires an external capacitor between the pin and GND of 1 µF or greater. When the on-chip LDO is used to provide power to the logic, the LDO pin must also be connected to the VDD25 pins at the board level in addition to the decoupling capacitor(s). Positive supply for I/O and some logic. Ground reference for logic and I/O pins. GPIO port D bit 0 QEI module 0 index GPIO port D bit 1 PWM 1 GPIO port D bit 2 UART module 1 receive. When in IrDA mode, this signal has IrDA modulation. GPIO port D bit 3 UART module 1 transmit. When in IrDA mode, this signal has IrDA modulation. 4 GNDA - Power 5 6 7 ADC2 ADC3 LDO I I - Analog Analog Power 8 9 10 VDD GND PD0 IDX0 I/O I I/O O I/O I I/O O Power Power TTL TTL TTL TTL TTL TTL TTL TTL 11 PD1 PWM1 12 PD2 U1Rx 13 PD3 U1Tx November 30, 2007 Preliminary 519 Signal Tables Pin Number 14 Pin Name VDD25 Pin Type - Buffer Type Description Power Positive supply for most of the logic function, including the processor core and most peripherals. Ground reference for logic and I/O pins. XTALP of the Ethernet PHY XTALN of the Ethernet PHY GPIO port G bit 1 UART 2 Transmit. When in IrDA mode, this signal has IrDA modulation. GPIO port G bit 0 UART 2 Receive. When in IrDA mode, this signal has IrDA modulation. Positive supply for I/O and some logic. Ground reference for logic and I/O pins. GPIO port C bit 7 QEI module 0 Phase B GPIO port C bit 6 Capture/Compare/PWM 3 GPIO port C bit 5 Analog comparator positive input Analog comparator 0 output GPIO port C bit 4 QEI module 0 Phase A GPIO port A bit 0 UART module 0 receive. When in IrDA mode, this signal has IrDA modulation. GPIO port A bit 1 UART module 0 transmit. When in IrDA mode, this signal has IrDA modulation. GPIO port A bit 2 SSI module 0 clock GPIO port A bit 3 SSI module 0 frame GPIO port A bit 4 SSI module 0 receive GPIO port A bit 5 SSI module 0 transmit Positive supply for I/O and some logic. Ground reference for logic and I/O pins. GPIO port A bit 6 I2C module 1 clock GPIO port A bit 7 I2C module 1 data VCC of the Ethernet PHY 15 16 17 18 GND XTALPPHY XTALNPHY PG1 U2Tx O I I/O O I/O I I/O I I/O I/O I/O I O I/O I I/O I I/O O I/O I/O I/O I/O I/O I I/O O I/O I/O I/O I/O I Power TTL TTL TTL TTL TTL TTL Power Power TTL TTL TTL TTL TTL Analog TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL Power Power TTL OD TTL OD TTL 19 PG0 U2Rx 20 21 22 VDD GND PC7 PhB0 23 PC6 CCP3 24 PC5 C1+ C0o 25 PC4 PhA0 26 PA0 U0Rx 27 PA1 U0Tx 28 PA2 SSI0Clk 29 PA3 SSI0Fss 30 PA4 SSI0Rx 31 PA5 SSI0Tx 32 33 34 VDD GND PA6 I2C1SCL 35 PA7 I2C1SDA 36 VCCPHY 520 Preliminary November 30, 2007 LM3S6965 Microcontroller Pin Number 37 38 Pin Name RXIN VDD25 Pin Type I - Buffer Type Description Analog Power RXIN of the Ethernet PHY Positive supply for most of the logic function, including the processor core and most peripherals. Ground reference for logic and I/O pins. RXIP of the Ethernet PHY GND of the Ethernet PHY GND of the Ethernet PHY TXOP of the Ethernet PHY Positive supply for I/O and some logic. Ground reference for logic and I/O pins. TXON of the Ethernet PHY GPIO port F bit 0 PWM 0 Main oscillator crystal input or an external clock reference input. Main oscillator crystal output. An external input that brings the processor out of hibernate mode when asserted. An output that indicates the processor is in hibernate mode. Hibernation Module oscillator crystal input or an external clock reference input. Note that this is either a 4.19-MHz crystal or a 32.768-kHz oscillator for the Hibernation Module RTC. See the CLKSEL bit in the HIBCTL register. Hibernation Module oscillator crystal output. Ground reference for logic and I/O pins. Power source for the Hibernation Module. It is normally connected to the positive terminal of a battery and serves as the battery backup/Hibernation Module power-source supply. Positive supply for I/O and some logic. Ground reference for logic and I/O pins. MDIO of the Ethernet PHY GPIO port F bit 3 MII LED 0 GPIO port F bit 2 MII LED 1 GPIO port F bit 1 QEI module 1 index Positive supply for most of the logic function, including the processor core and most peripherals. Ground reference for logic and I/O pins. 39 40 41 42 43 44 45 46 47 GND RXIP GNDPHY GNDPHY TXOP VDD GND TXON PF0 PWM0 I I I O O I/O O I I I O I Power Analog TTL TTL Analog Power Power Analog TTL TTL Analog Analog OD TTL Analog 48 49 50 51 52 OSC0 OSC1 WAKE HIB XOSC0 53 54 55 XOSC1 GND VBAT I - Analog Power Power 56 57 58 59 VDD GND MDIO PF3 LED0 I/O I/O O I/O O I/O I - Power Power TTL TTL TTL TTL TTL TTL TTL Power 60 PF2 LED1 61 PF1 IDX1 62 VDD25 63 GND - Power November 30, 2007 Preliminary 521 Signal Tables Pin Number 64 65 66 Pin Name RST CMOD0 PB0 PWM2 Pin Type I I/O I/O O I/O O I/O I/O I/O I/O I/O O I/O O I/O I I/O I I/O I/O O O I/O I I/O I/O I/O I/O I I I I I I - Buffer Type Description TTL TTL TTL TTL TTL TTL Power Power TTL OD TTL OD TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL Power Power TTL TTL TTL TTL Power Power System reset input. CPU Mode bit 0. Input must be set to logic 0 (grounded); other encodings reserved. GPIO port B bit 0 PWM 2 GPIO port B bit 1 PWM 3 Positive supply for I/O and some logic. Ground reference for logic and I/O pins. GPIO port B bit 2 I2C module 0 clock GPIO port B bit 3 I2C module 0 data GPIO port E bit 0 PWM 4 GPIO port E bit 1 PWM 5 GPIO port E bit 2 QEI module 1 Phase B GPIO port E bit 3 QEI module 1 Phase A CPU Mode bit 1. Input must be set to logic 0 (grounded); other encodings reserved. GPIO port C bit 3 JTAG TDO and SWO JTAG TDO and SWO GPIO port C bit 2 JTAG TDI GPIO port C bit 1 JTAG TMS and SWDIO JTAG TMS and SWDIO GPIO port C bit 0 JTAG/SWD CLK JTAG/SWD CLK Positive supply for I/O and some logic. Ground reference for logic and I/O pins. VCC of the Ethernet PHY VCC of the Ethernet PHY GND of the Ethernet PHY GND of the Ethernet PHY Ground reference for logic and I/O pins. Positive supply for most of the logic function, including the processor core and most peripherals. 67 PB1 PWM3 68 69 70 VDD GND PB2 I2C0SCL 71 PB3 I2C0SDA 72 PE0 PWM4 73 PE1 PWM5 74 PE2 PhB1 75 PE3 PhA1 76 77 CMOD1 PC3 TDO SWO 78 PC2 TDI 79 PC1 TMS SWDIO 80 PC0 TCK SWCLK 81 82 83 84 85 86 87 88 VDD GND VCCPHY VCCPHY GNDPHY GNDPHY GND VDD25 522 Preliminary November 30, 2007 LM3S6965 Microcontroller Pin Number 89 Pin Name PB7 TRST Pin Type I/O I I/O I I/O I I/O I I/O I/O I/O I/O - Buffer Type Description TTL TTL TTL Analog TTL Analog TTL Analog Power Power TTL TTL TTL TTL Power GPIO port B bit 7 JTAG TRSTn GPIO port B bit 6 Analog comparator 0 positive input GPIO port B bit 5 Analog comparator 1 negative input GPIO port B bit 4 Analog comparator 0 negative input Positive supply for I/O and some logic. Ground reference for logic and I/O pins. GPIO port D bit 4 Capture/Compare/PWM 0 GPIO port D bit 5 Capture/Compare/PWM 2 The ground reference for the analog circuits (ADC, Analog Comparators, etc.). These are separated from GND to minimize the electrical noise contained on VDD from affecting the analog functions. The positive supply (3.3 V) for the analog circuits (ADC, Analog Comparators, etc.). These are separated from VDD to minimize the electrical noise contained on VDD from affecting the analog functions. GPIO port D bit 6 PWM Fault GPIO port D bit 7 Capture/Compare/PWM 1 90 PB6 C0+ 91 PB5 C1- 92 PB4 C0- 93 94 95 VDD GND PD4 CCP0 96 PD5 CCP2 97 GNDA 98 VDDA - Power 99 PD6 Fault I/O I I/O I/O TTL TTL TTL TTL 100 PD7 CCP1 Table 21-2. Signals by Signal Name Pin Name ADC0 ADC1 ADC2 ADC3 C0+ C0C0o C1+ C1CCP0 CCP1 CCP2 CCP3 Pin Number 1 2 5 6 90 92 24 24 91 95 100 96 23 Pin Type I I I I I I O I I I/O I/O I/O I/O Buffer Type Description Analog Analog Analog Analog Analog Analog TTL Analog Analog TTL TTL TTL TTL Analog-to-digital converter input 0. Analog-to-digital converter input 1. Analog-to-digital converter input 2. Analog-to-digital converter input 3. Analog comparator 0 positive input Analog comparator 0 negative input Analog comparator 0 output Analog comparator positive input Analog comparator 1 negative input Capture/Compare/PWM 0 Capture/Compare/PWM 1 Capture/Compare/PWM 2 Capture/Compare/PWM 3 November 30, 2007 Preliminary 523 Signal Tables Pin Name CMOD0 CMOD1 Fault GND GND GND GND GND GND GND GND GND GND GND GND GND GNDA Pin Number 65 76 99 9 15 21 33 39 45 54 57 63 69 82 87 94 4 Pin Type I/O I/O I - Buffer Type Description TTL TTL TTL Power Power Power Power Power Power Power Power Power Power Power Power Power Power CPU Mode bit 0. Input must be set to logic 0 (grounded); other encodings reserved. CPU Mode bit 1. Input must be set to logic 0 (grounded); other encodings reserved. PWM Fault Ground reference for logic and I/O pins. Ground reference for logic and I/O pins. Ground reference for logic and I/O pins. Ground reference for logic and I/O pins. Ground reference for logic and I/O pins. Ground reference for logic and I/O pins. Ground reference for logic and I/O pins. Ground reference for logic and I/O pins. Ground reference for logic and I/O pins. Ground reference for logic and I/O pins. Ground reference for logic and I/O pins. Ground reference for logic and I/O pins. Ground reference for logic and I/O pins. The ground reference for the analog circuits (ADC, Analog Comparators, etc.). These are separated from GND to minimize the electrical noise contained on VDD from affecting the analog functions. The ground reference for the analog circuits (ADC, Analog Comparators, etc.). These are separated from GND to minimize the electrical noise contained on VDD from affecting the analog functions. GND of the Ethernet PHY GND of the Ethernet PHY GND of the Ethernet PHY GND of the Ethernet PHY An output that indicates the processor is in hibernate mode. I2C module 0 clock I2C module 0 data I2C module 1 clock I2C module 1 data QEI module 0 index QEI module 1 index Low drop-out regulator output voltage. This pin requires an external capacitor between the pin and GND of 1 µF or greater. When the on-chip LDO is used to provide power to the logic, the LDO pin must also be connected to the VDD25 pins at the board level in addition to the decoupling capacitor(s). MII LED 0 GNDA 97 - Power GNDPHY GNDPHY GNDPHY GNDPHY HIB I2C0SCL I2C0SDA I2C1SCL I2C1SDA IDX0 IDX1 LDO 41 42 85 86 51 70 71 34 35 10 61 7 I I I I O I/O I/O I/O I/O I I - TTL TTL TTL TTL TTL OD OD OD OD TTL TTL Power LED0 59 O TTL 524 Preliminary November 30, 2007 LM3S6965 Microcontroller Pin Name LED1 MDIO OSC0 OSC1 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PE0 PE1 PE2 PE3 PF0 PF1 Pin Number 60 58 48 49 26 27 28 29 30 31 34 35 66 67 70 71 92 91 90 89 80 79 78 77 25 24 23 22 10 11 12 13 95 96 99 100 72 73 74 75 47 61 Pin Type O I/O I I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Buffer Type Description TTL TTL Analog Analog TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL MII LED 1 MDIO of the Ethernet PHY Main oscillator crystal input or an external clock reference input. Main oscillator crystal output. GPIO port A bit 0 GPIO port A bit 1 GPIO port A bit 2 GPIO port A bit 3 GPIO port A bit 4 GPIO port A bit 5 GPIO port A bit 6 GPIO port A bit 7 GPIO port B bit 0 GPIO port B bit 1 GPIO port B bit 2 GPIO port B bit 3 GPIO port B bit 4 GPIO port B bit 5 GPIO port B bit 6 GPIO port B bit 7 GPIO port C bit 0 GPIO port C bit 1 GPIO port C bit 2 GPIO port C bit 3 GPIO port C bit 4 GPIO port C bit 5 GPIO port C bit 6 GPIO port C bit 7 GPIO port D bit 0 GPIO port D bit 1 GPIO port D bit 2 GPIO port D bit 3 GPIO port D bit 4 GPIO port D bit 5 GPIO port D bit 6 GPIO port D bit 7 GPIO port E bit 0 GPIO port E bit 1 GPIO port E bit 2 GPIO port E bit 3 GPIO port F bit 0 GPIO port F bit 1 November 30, 2007 Preliminary 525 Signal Tables Pin Name PF2 PF3 PG0 PG1 PhA0 PhA1 PhB0 PhB1 PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 RST RXIN RXIP SSI0Clk SSI0Fss SSI0Rx SSI0Tx SWCLK SWDIO SWO TCK TDI TDO TMS TRST TXON TXOP U0Rx U0Tx U1Rx U1Tx U2Rx U2Tx Pin Number 60 59 19 18 25 75 22 74 47 11 66 67 72 73 64 37 40 28 29 30 31 80 79 77 80 78 77 79 89 46 43 26 27 12 13 19 18 Pin Type I/O I/O I/O I/O I I I I O O O O O O I I I I/O I/O I O I I/O O I I O I/O I O O I O I O I O Buffer Type Description TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL Analog Analog TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL Analog Analog TTL TTL TTL TTL TTL TTL GPIO port F bit 2 GPIO port F bit 3 GPIO port G bit 0 GPIO port G bit 1 QEI module 0 Phase A QEI module 1 Phase A QEI module 0 Phase B QEI module 1 Phase B PWM 0 PWM 1 PWM 2 PWM 3 PWM 4 PWM 5 System reset input. RXIN of the Ethernet PHY RXIP of the Ethernet PHY SSI module 0 clock SSI module 0 frame SSI module 0 receive SSI module 0 transmit JTAG/SWD CLK JTAG TMS and SWDIO JTAG TDO and SWO JTAG/SWD CLK JTAG TDI JTAG TDO and SWO JTAG TMS and SWDIO JTAG TRSTn TXON of the Ethernet PHY TXOP of the Ethernet PHY UART module 0 receive. When in IrDA mode, this signal has IrDA modulation. UART module 0 transmit. When in IrDA mode, this signal has IrDA modulation. UART module 1 receive. When in IrDA mode, this signal has IrDA modulation. UART module 1 transmit. When in IrDA mode, this signal has IrDA modulation. UART 2 Receive. When in IrDA mode, this signal has IrDA modulation. UART 2 Transmit. When in IrDA mode, this signal has IrDA modulation. 526 Preliminary November 30, 2007 LM3S6965 Microcontroller Pin Name VBAT Pin Number 55 Pin Type - Buffer Type Description Power Power source for the Hibernation Module. It is normally connected to the positive terminal of a battery and serves as the battery backup/Hibernation Module power-source supply. VCC of the Ethernet PHY VCC of the Ethernet PHY VCC of the Ethernet PHY Positive supply for I/O and some logic. Positive supply for I/O and some logic. Positive supply for I/O and some logic. Positive supply for I/O and some logic. Positive supply for I/O and some logic. Positive supply for I/O and some logic. Positive supply for I/O and some logic. Positive supply for I/O and some logic. Positive supply for most of the logic function, including the processor core and most peripherals. Positive supply for most of the logic function, including the processor core and most peripherals. Positive supply for most of the logic function, including the processor core and most peripherals. Positive supply for most of the logic function, including the processor core and most peripherals. The positive supply (3.3 V) for the analog circuits (ADC, Analog Comparators, etc.). These are separated from VDD to minimize the electrical noise contained on VDD from affecting the analog functions. The positive supply (3.3 V) for the analog circuits (ADC, Analog Comparators, etc.). These are separated from VDD to minimize the electrical noise contained on VDD from affecting the analog functions. An external input that brings the processor out of hibernate mode when asserted. Hibernation Module oscillator crystal input or an external clock reference input. Note that this is either a 4.19-MHz crystal or a 32.768-kHz oscillator for the Hibernation Module RTC. See the CLKSEL bit in the HIBCTL register. Hibernation Module oscillator crystal output. XTALN of the Ethernet PHY XTALP of the Ethernet PHY VCCPHY VCCPHY VCCPHY VDD VDD VDD VDD VDD VDD VDD VDD VDD25 36 83 84 8 20 32 44 56 68 81 93 14 I I I - TTL TTL TTL Power Power Power Power Power Power Power Power Power VDD25 38 - Power VDD25 62 - Power VDD25 88 - Power VDDA 3 - Power VDDA 98 - Power WAKE XOSC0 50 52 I I OD Analog XOSC1 XTALNPHY XTALPPHY 53 17 16 I I O Analog TTL TTL November 30, 2007 Preliminary 527 Signal Tables Table 21-3. Signals by Function, Except for GPIO Function ADC Pin Name ADC0 ADC1 ADC2 ADC3 Analog Comparators C0+ C0C0o C1+ C1Ethernet PHY GNDPHY GNDPHY GNDPHY GNDPHY LED0 LED1 MDIO RXIN RXIP TXON TXOP VCCPHY VCCPHY VCCPHY XTALNPHY XTALPPHY General-Purpose CCP0 Timers CCP1 CCP2 CCP3 I2C I2C0SCL I2C0SDA I2C1SCL I2C1SDA JTAG/SWD/SWO SWCLK SWDIO SWO TCK TDI TDO TMS Pin Number 1 2 5 6 90 92 24 24 91 41 42 85 86 59 60 58 37 40 46 43 36 83 84 17 16 95 100 96 23 70 71 34 35 80 79 77 80 78 77 79 Pin Type I I I I I I O I I I I I I O O I/O I I O O I I I I O I/O I/O I/O I/O I/O I/O I/O I/O I I/O O I I O I/O Buffer Type Analog Analog Analog Analog Analog Analog TTL Analog Analog TTL TTL TTL TTL TTL TTL TTL Analog Analog Analog Analog TTL TTL TTL TTL TTL TTL TTL TTL TTL OD OD OD OD TTL TTL TTL TTL TTL TTL TTL Description Analog-to-digital converter input 0. Analog-to-digital converter input 1. Analog-to-digital converter input 2. Analog-to-digital converter input 3. Analog comparator 0 positive input Analog comparator 0 negative input Analog comparator 0 output Analog comparator positive input Analog comparator 1 negative input GND of the Ethernet PHY GND of the Ethernet PHY GND of the Ethernet PHY GND of the Ethernet PHY MII LED 0 MII LED 1 MDIO of the Ethernet PHY RXIN of the Ethernet PHY RXIP of the Ethernet PHY TXON of the Ethernet PHY TXOP of the Ethernet PHY VCC of the Ethernet PHY VCC of the Ethernet PHY VCC of the Ethernet PHY XTALN of the Ethernet PHY XTALP of the Ethernet PHY Capture/Compare/PWM 0 Capture/Compare/PWM 1 Capture/Compare/PWM 2 Capture/Compare/PWM 3 I2C module 0 clock I2C module 0 data I2C module 1 clock I2C module 1 data JTAG/SWD CLK JTAG TMS and SWDIO JTAG TDO and SWO JTAG/SWD CLK JTAG TDI JTAG TDO and SWO JTAG TMS and SWDIO 528 Preliminary November 30, 2007 LM3S6965 Microcontroller Function PWM Pin Name Fault PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 Pin Number 99 47 11 66 67 72 73 Pin Type I O O O O O O Buffer Type TTL TTL TTL TTL TTL TTL TTL PWM Fault PWM 0 PWM 1 PWM 2 PWM 3 PWM 4 PWM 5 Description November 30, 2007 Preliminary 529 Signal Tables Function Power Pin Name GND GND GND GND GND GND GND GND GND GND GND GND GND GNDA Pin Number 9 15 21 33 39 45 54 57 63 69 82 87 94 4 Pin Type - Buffer Type Power Power Power Power Power Power Power Power Power Power Power Power Power Power Description Ground reference for logic and I/O pins. Ground reference for logic and I/O pins. Ground reference for logic and I/O pins. Ground reference for logic and I/O pins. Ground reference for logic and I/O pins. Ground reference for logic and I/O pins. Ground reference for logic and I/O pins. Ground reference for logic and I/O pins. Ground reference for logic and I/O pins. Ground reference for logic and I/O pins. Ground reference for logic and I/O pins. Ground reference for logic and I/O pins. Ground reference for logic and I/O pins. The ground reference for the analog circuits (ADC, Analog Comparators, etc.). These are separated from GND to minimize the electrical noise contained on VDD from affecting the analog functions. The ground reference for the analog circuits (ADC, Analog Comparators, etc.). These are separated from GND to minimize the electrical noise contained on VDD from affecting the analog functions. An output that indicates the processor is in hibernate mode. Low drop-out regulator output voltage. This pin requires an external capacitor between the pin and GND of 1 µF or greater. When the on-chip LDO is used to provide power to the logic, the LDO pin must also be connected to the VDD25 pins at the board level in addition to the decoupling capacitor(s). Power source for the Hibernation Module. It is normally connected to the positive terminal of a battery and serves as the battery backup/Hibernation Module power-source supply. Positive supply for I/O and some logic. Positive supply for I/O and some logic. Positive supply for I/O and some logic. Positive supply for I/O and some logic. Positive supply for I/O and some logic. Positive supply for I/O and some logic. Positive supply for I/O and some logic. Positive supply for I/O and some logic. Positive supply for most of the logic function, including the processor core and most peripherals. Positive supply for most of the logic function, including the processor core and most peripherals. Positive supply for most of the logic function, including the processor core and most peripherals. GNDA 97 - Power HIB LDO 51 7 O - TTL Power VBAT 55 - Power VDD VDD VDD VDD VDD VDD VDD VDD VDD25 VDD25 VDD25 8 20 32 44 56 68 81 93 14 38 62 - Power Power Power Power Power Power Power Power Power Power Power 530 Preliminary November 30, 2007 LM3S6965 Microcontroller Function Pin Name VDD25 VDDA Pin Number 88 3 Pin Type - Buffer Type Power Power Description Positive supply for most of the logic function, including the processor core and most peripherals. The positive supply (3.3 V) for the analog circuits (ADC, Analog Comparators, etc.). These are separated from VDD to minimize the electrical noise contained on VDD from affecting the analog functions. The positive supply (3.3 V) for the analog circuits (ADC, Analog Comparators, etc.). These are separated from VDD to minimize the electrical noise contained on VDD from affecting the analog functions. An external input that brings the processor out of hibernate mode when asserted. QEI module 0 index QEI module 1 index QEI module 0 Phase A QEI module 1 Phase A QEI module 0 Phase B QEI module 1 Phase B SSI module 0 clock SSI module 0 frame SSI module 0 receive SSI module 0 transmit CPU Mode bit 0. Input must be set to logic 0 (grounded); other encodings reserved. CPU Mode bit 1. Input must be set to logic 0 (grounded); other encodings reserved. Main oscillator crystal input or an external clock reference input. Main oscillator crystal output. System reset input. JTAG TRSTn Hibernation Module oscillator crystal input or an external clock reference input. Note that this is either a 4.19-MHz crystal or a 32.768-kHz oscillator for the Hibernation Module RTC. See the CLKSEL bit in the HIBCTL register. Hibernation Module oscillator crystal output. VDDA 98 - Power WAKE QEI IDX0 IDX1 PhA0 PhA1 PhB0 PhB1 SSI SSI0Clk SSI0Fss SSI0Rx SSI0Tx System Control & CMOD0 Clocks CMOD1 OSC0 OSC1 RST TRST XOSC0 50 10 61 25 75 22 74 28 29 30 31 65 76 48 49 64 89 52 I I I I I I I I/O I/O I O I/O I/O I I I I I OD TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL Analog Analog TTL TTL Analog XOSC1 53 I Analog November 30, 2007 Preliminary 531 Signal Tables Function UART Pin Name U0Rx U0Tx U1Rx U1Tx U2Rx U2Tx Pin Number 26 27 12 13 19 18 Pin Type I O I O I O Buffer Type TTL TTL TTL TTL TTL TTL Description UART module 0 receive. When in IrDA mode, this signal has IrDA modulation. UART module 0 transmit. When in IrDA mode, this signal has IrDA modulation. UART module 1 receive. When in IrDA mode, this signal has IrDA modulation. UART module 1 transmit. When in IrDA mode, this signal has IrDA modulation. UART 2 Receive. When in IrDA mode, this signal has IrDA modulation. UART 2 Transmit. When in IrDA mode, this signal has IrDA modulation. Table 21-4. GPIO Pins and Alternate Functions GPIO Pin PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PD0 PD1 PD2 PD3 PD4 Pin Number 26 27 28 29 30 31 34 35 66 67 70 71 92 91 90 89 80 79 78 77 25 24 23 22 10 11 12 13 95 Multiplexed Function U0Rx U0Tx SSI0Clk SSI0Fss SSI0Rx SSI0Tx I2C1SCL I2C1SDA PWM2 PWM3 I2C0SCL I2C0SDA C0C1C0+ TRST TCK TMS TDI TDO PhA0 C1+ CCP3 PhB0 IDX0 PWM1 U1Rx U1Tx CCP0 C0o SWO SWCLK SWDIO Multiplexed Function 532 Preliminary November 30, 2007 LM3S6965 Microcontroller GPIO Pin PD5 PD6 PD7 PE0 PE1 PE2 PE3 PF0 PF1 PF2 PF3 PG0 PG1 Pin Number 96 99 100 72 73 74 75 47 61 60 59 19 18 Multiplexed Function CCP2 Fault CCP1 PWM4 PWM5 PhB1 PhA1 PWM0 IDX1 LED1 LED0 U2Rx U2Tx Multiplexed Function November 30, 2007 Preliminary 533 Operating Characteristics 22 Operating Characteristics Table 22-1. Temperature Characteristics Characteristic a Symbol Value -40 to +85 Unit °C Operating temperature range TA a. Maximum storage temperature is 150°C. Table 22-2. Thermal Characteristics Characteristic a b Symbol Value 55.3 TA + (PAVG • ΘJA) Unit °C/W °C Thermal resistance (junction to ambient) ΘJA Average junction temperature TJ a. Junction to ambient thermal resistance θJA numbers are determined by a package simulator. b. Power dissipation is a function of temperature. 534 Preliminary November 30, 2007 LM3S6965 Microcontroller 23 23.1 23.1.1 Electrical Characteristics DC Characteristics Maximum Ratings The maximum ratings are the limits to which the device can be subjected without permanently damaging the device. Note: The device is not guaranteed to operate properly at the maximum ratings. Table 23-1. Maximum Ratings Characteristic a Symbol Value Min Max Unit I/O supply voltage (VDD) Core supply voltage (VDD25) Analog supply voltage (VDDA) Battery supply voltage (VBAT) VDD VDD25 VDDA VBAT 0 0 0 0 0 4 4 4 4 4 V V V V V V mA Ethernet PHY supply voltage (VCCPHY) VCCPHY Input voltage Maximum current per output pins VIN I -0.3 5.5 25 a. Voltages are measured with respect to GND. Important: This device contains circuitry to protect the inputs against damage due to high-static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (for example, either GND or VDD). 23.1.2 Recommended DC Operating Conditions Table 23-2. Recommended DC Operating Conditions Parameter Parameter Name VDD VDD25 VDDA VBAT VCCPHY VIH VIL VSIH VSIL VOH VOL I/O supply voltage Core supply voltage Analog supply voltage Battery supply voltage Ethernet PHY supply voltage High-level input voltage Low-level input voltage Min 3.0 2.25 3.0 2.3 3.0 2.0 -0.3 Nom 3.3 2.5 3.3 3.0 3.3 Max 3.6 2.75 3.6 3.6 3.6 5.0 1.3 VDD 0.2 * VDD 0.4 Unit V V V V V V V V V V V High-level input voltage for Schmitt trigger inputs 0.8 * VDD Low-level input voltage for Schmitt trigger inputs High-level output voltage Low-level output voltage 0 2.4 - November 30, 2007 Preliminary 535 Electrical Characteristics Parameter Parameter Name IOH High-level source current, VOH=2.4 V 2-mA Drive 4-mA Drive 8-mA Drive IOL Low-level sink current, VOL=0.4 V 2-mA Drive 4-mA Drive 8-mA Drive Min Nom Max Unit 2.0 4.0 8.0 - - mA mA mA 2.0 4.0 8.0 - - mA mA mA 23.1.3 On-Chip Low Drop-Out (LDO) Regulator Characteristics Table 23-3. LDO Regulator Characteristics Parameter Parameter Name VLDOOUT tPON tON tOFF VSTEP CLDO Min Nom Max Unit V % µs µs µs mV µF Programmable internal (logic) power supply output value 2.25 2.5 2.75 Output voltage accuracy Power-on time Time on Time off Step programming incremental voltage External filter capacitor size for internal power supply 1.0 2% 50 100 200 100 3.0 23.1.4 Power Specifications The power measurements specified in the tables that follow are run on the core processor using SRAM with the following specifications (except as noted): ■ VDD = 3.3 V ■ VDD25 = 2.50 V ■ VBAT = 3.0 V ■ VDDA = 3.3 V ■ VDDPHY = 3.3 V ■ Temperature = 25°C ■ Clock Source (MOSC) =3.579545 MHz Crystal Oscillator ■ Main oscillator (MOSC) = enabled ■ Internal oscillator (IOSC) = disabled 536 Preliminary November 30, 2007 LM3S6965 Microcontroller Table 23-4. Detailed Power Specifications Parameter Parameter Name Conditions 3.3 V VDD, VDDA, VDDPHY Nom IDD_RUN Run mode 1 (Flash loop) VDD25 = 2.50 V Code= while(1){} executed in Flash Peripherals = All ON System Clock = 50 MHz (with PLL) Run mode 2 (Flash loop) VDD25 = 2.50 V Code= while(1){} executed in Flash Peripherals = All OFF System Clock = 50 MHz (with PLL) Run mode 1 (SRAM loop) VDD25 = 2.50 V Code= while(1){} executed in SRAM Peripherals = All ON System Clock = 50 MHz (with PLL) Run mode 2 (SRAM loop) VDD25 = 2.50 V Code= while(1){} executed in SRAM Peripherals = All OFF System Clock = 50 MHz (with PLL) IDD_SLEEP Sleep mode VDD25 = 2.50 V Peripherals = All OFF System Clock = 50 MHz (with PLL) IDD_DEEPSLEEP Deep-Sleep mode LDO = 2.25 V Peripherals = All OFF System Clock = IOSC30KHZ/64 IDD_HIBERNATE Hibernate mode VBAT = 3.0 V VDD = 0 V VDD25 = 0 V VDDA = 0 V VDDPHY = 0 V Peripherals = All OFF System Clock = OFF Hibernate Module = 32 kHz a. Pending characterization completion. 0 pendinga 0 pendinga 16 pendinga µA 4.6 pendinga 0.21 pendinga 0 pendinga mA 5 pendinga 16 pendinga 0 pendinga mA 5 pendinga 45 pendinga 0 pendinga mA 48 pendinga 100 pendinga 0 pendinga mA 5 pendinga 52 pendinga 0 pendinga mA 48 Max pending a 2.5 V VDD25 Nom 108 Max pendinga 3.0 V VBAT Nom 0 Max Unit pendinga mA November 30, 2007 Preliminary 537 Electrical Characteristics 23.1.5 Flash Memory Characteristics Table 23-5. Flash Memory Characteristics Parameter Parameter Name PECYC TRET TPROG TERASE TME a Min Nom Max Unit cycles years µs ms ms Number of guaranteed program/erase cycles before failure 10,000 100,000 Data retention at average operating temperature of 85˚C Word program time Page erase time Mass erase time 10 20 20 200 - a. A program/erase cycle is defined as switching the bits from 1-> 0 -> 1. 23.2 23.2.1 AC Characteristics Load Conditions Unless otherwise specified, the following conditions are true for all timing measurements. Timing measurements are for 4-mA drive strength. Figure 23-1. Load Conditions pin CL = 50 pF GND 23.2.2 Clocks Table 23-6. Phase Locked Loop (PLL) Characteristics Parameter Parameter Name fref_crystal fref_ext fpll TREADY Crystal reference External clock PLL frequency PLL lock time b a Min 3.579545 3.579545 - Nom Max Unit 400 8.192 MHz 8.192 MHz 0.5 MHz ms referencea a. The exact value is determined by the crystal value programmed into the XTAL field of the Run-Mode Clock Configuration (RCC) register. b. PLL frequency is automatically calculated by the hardware based on the XTAL field of the RCC register. Table 23-7. Clock Characteristics Parameter fIOSC fIOSC30KHZ fXOSC fXOSC_XTAL fXOSC_EXT Parameter Name Internal 12 MHz oscillator frequency Internal 30 KHz oscillator frequency Hibernation module oscillator frequency Crystal reference for hibernation oscillator External clock reference for hibernation module Min 8.4 21 Nom 12 30 4.194304 4.194304 32.768 Max Unit 15.6 MHz 39 KHz MHz MHz KHz 538 Preliminary November 30, 2007 LM3S6965 Microcontroller Parameter fMOSC tMOSC_per Parameter Name Main oscillator frequency Main oscillator period a Min 1 125 1 0 0 Nom - Max Unit 8 1000 8 50 50 MHz ns MHz MHz MHz fref_crystal_bypass Crystal reference using the main oscillator (PLL in BYPASS mode) fref_ext_bypass fsystem_clock External clock reference (PLL in BYPASS mode) System clock a a. The ADC must be clocked from the PLL or directly from a 14-MHz to 18-MHz clock source to operate properly. Table 23-8. Crystal Characteristics Parameter Name Frequency Frequency tolerance Aging Oscillation mode Temperature stability (0 - 85 °C) Motional capacitance (typ) Motional inductance (typ) Equivalent series resistance (max) Shunt capacitance (max) Load capacitance (typ) Drive level (typ) 8 ±50 ±5 6 ±50 ±5 Value 4 ±50 ±5 3.5 ±50 ±5 Units MHz ppm ppm/yr Parallel Parallel Parallel Parallel ±25 27.8 14.3 120 10 16 100 ±25 37.0 19.1 160 10 16 100 ±25 55.6 28.6 200 10 16 100 ±25 63.5 32.7 220 10 16 100 ppm pF mH Ω pF pF µW 23.2.3 Analog-to-Digital Converter Table 23-9. ADC Characteristics Parameter Parameter Name VADCIN Maximum single-ended, full-scale analog input voltage Minimum single-ended, full-scale analog input voltage Maximum differential, full-scale analog input voltage Minimum differential, full-scale analog input voltage CADCIN N fADC tADCCONV f ADCCONV INL DNL OFF GAIN Equivalent input capacitance Resolution ADC internal clock frequency Conversion time Conversion rate Integral nonlinearity Differential nonlinearity Offset Gain Min Nom Max 14 1 10 16 3.0 V 0 V Unit 1.5 V -1.5 V 18 16 pF bits MHz tADCcycles a 875 1000 1125 k samples/s ±1 ±1 ±1 ±1 LSB LSB LSB LSB a. tADC= 1/fADC clock November 30, 2007 Preliminary 539 Electrical Characteristics 23.2.4 Analog Comparator Table 23-10. Analog Comparator Characteristics Parameter Parameter Name VOS VCM CMRR TRT TMC Input offset voltage Input common mode voltage range Common mode rejection ratio Response time Comparator mode change to Output Valid Min Nom 0 50 ±10 Max ±25 VDD-1.5 1 10 Unit mV V dB µs µs Table 23-11. Analog Comparator Voltage Reference Characteristics Parameter Parameter Name RHR RLR AHR ALR Resolution high range Resolution low range Absolute accuracy high range Absolute accuracy low range Min Nom Max Unit VDD/32 VDD/24 LSB LSB ±1/2 LSB ±1/4 LSB 23.2.5 I2C Table 23-12. I2C Characteristics Parameter No. Parameter Parameter Name I1 I2 I3 I4 a a b a c Min Nom 36 36 2 24 18 9 - Max (see note b) 10 - Unit system clocks system clocks ns system clocks ns system clocks system clocks system clocks system clocks tSCH tLP tSRT tDH tSFT tHT tDS tSCSR tSCS Start condition hold time Clock Low period I2CSCL/I2CSDA rise time (VIL =0.5 V to V IH =2.4 V) Data hold time I2CSCL/I2CSDA fall time (VIH =2.4 V to V IL =0.5 V) Clock High time Data setup time I5 I6 I7 I8 I9 a a a Start condition setup time (for repeated start condition 36 only) Stop condition setup time I2C 24 a a. Values depend on the value programmed into the TPR bit in the Master Timer Period (I2CMTPR) register; a TPR programmed for the maximum I2CSCL frequency (TPR=0x2) results in a minimum output timing as shown in the table above. The I 2C interface is designed to scale the actual data transition time to move it to the middle of the I2CSCL Low period. The actual position is affected by the value programmed into the TPR; however, the numbers given in the above values are minimum values. b. Because I2CSCL and I2CSDA are open-drain-type outputs, which the controller can only actively drive Low, the time I2CSCL or I2CSDA takes to reach a high level depends on external signal capacitance and pull-up resistor values. c. Specified at a nominal 50 pF load. 540 Preliminary November 30, 2007 LM3S6965 Microcontroller Figure 23-2. I2C Timing I2 I6 I5 I2CSCL I1 I4 I7 I8 I3 I9 I2CSDA 23.2.6 Ethernet Controller Table 23-13. 100BASE-TX Transmitter Characteristics Parameter Name Peak output amplitude Min Nom Max Unit 950 1050 mVpk 1.02 mVpk 5 5 500 1.4 % ns ps ps ns a Output amplitude symmetry 0.98 Output overshoot Rise/Fall time Rise/Fall time imbalance Duty cycle distortion Jitter 3 - a. Measured at the line side of the transformer. Table 23-14. 100BASE-TX Transmitter Characteristics (informative) Parameter Name Return loss Min Nom Max Unit 16 dB µs a Open-circuit inductance 350 a. The specifications in this table are included for information only. They are mainly a function of the external transformer and termination resistors used for measurements. Table 23-15. 100BASE-TX Receiver Characteristics Parameter Name Signal detect assertion threshold Min Nom Max 600 700 +75 1000 4 Unit mVppd mVppd kΩ ns % µs µs a Signal detect de-assertion threshold 350 425 Differential input resistance Jitter tolerance (pk-pk) Baseline wander tracking Signal detect assertion time Signal detect de-assertion time 20 4 -75 - Table 23-16. 10BASE-T Transmitter Characteristics Parameter Name Min Nom Max Unit 100 2.8 V dB ns Peak differential output signal 2.2 Harmonic content Link pulse width 27 - November 30, 2007 Preliminary 541 Electrical Characteristics Parameter Name Start-of-idle pulse width Min Nom Max Unit 300 350 ns a. The Manchester-encoded data pulses, the link pulse and the start-of-idle pulse are tested against the templates and using the procedures found in Clause 14 of IEEE 802.3. Table 23-17. 10BASE-T Transmitter Characteristics (informative) Parameter Name Output return loss Output impedance balance Peak common-mode output voltage Common-mode rejection Common-mode rejection jitter Min 15 29-17log(f/10) Nom Max Unit 50 dB dB mV a 100 mV 1 ns a. The specifications in this table are included for information only. They are mainly a function of the external transformer and termination resistors used for measurements. Table 23-18. 10BASE-T Receiver Characteristics Parameter Name DLL phase acquisition time Jitter tolerance (pk-pk) Input squelched threshold Min Nom Max 30 10 Unit BT ns 500 600 700 mVppd Input unsquelched threshold 275 350 425 mVppd Differential input resistance Bit error ratio Common-mode rejection 25 20 10-10 a kΩ V Table 23-19. Isolation Transformers Name Turns ratio Open-circuit inductance Leakage inductance Inter-winding capacitance DC resistance Insertion loss HIPOT Value 1 CT : 1 CT 350 uH (min) 0.40 uH (max) 25 pF (max) 0.9 Ohm (max) 0.4 dB (typ) 1500 Condition +/- 5% @ 10 mV, 10 kHz @ 1 MHz (min) 0-65 MHz Vrms a. Two simple 1:1 isolation transformers are required at the line interface. Transformers with integrated common-mode chokes are recommended for exceeding FCC requirements. This table gives the recommended line transformer characteristics. Note: The 100Base-TX amplitude specifications assume a transformer loss of 0.4 dB. For the transmit line transformer with higher insertion losses, up to 1.2 dB of insertion loss can be compensated by selecting the appropriate setting in the Transmit Amplitude Selection (TXO) bits in the MR19 register. 542 Preliminary November 30, 2007 LM3S6965 Microcontroller Table 23-20. Ethernet Reference Crystal Name Frequency Load capacitance b a Value 25.00000 4 c Condition MHz pF PPM PPM/yr PPM Frequency tolerance Aging Temperature stability (0° to 70°) Oscillation mode Parameters at 25° C ±2° C; Drive level = 0.5 mW Drive level (typ) Shunt capacitance (max) Motional capacitance (min) Serious resistance (max) Spurious response (max) ±50 ±2 ±5 Parallel resonance, fundamental mode 50-100 10 10 60 > 5 dB below main within 500 kHz µW pF fF Ω a. If the internal crystal oscillator is used, select a crystal with the following characteristics. b. Equivalent differential capacitance across XTLP/XTLN. c. If crystal with a larger load is used, external shunt capacitors to ground should be added to make up the equivalent capacitance difference. Figure 23-3. External XTLP Oscillator Characteristics Tr Tf Tclkhi Tclkper Tclklo Table 23-21. External XTLP Oscillator Characteristics Parameter Name a Symbol Min Nom Max Unit 40 40 25.0 40 0.8 60 60 4.0 0.1 ns ns % XTLN Input Low Voltage XTLNILV XTLP Frequency XTLP Period b XTLPf Tclkper XTLPDC XTLP Duty Cycle Rise/Fall Time Absolute Jitter Tr , Tf - a. IEEE 802.3 frequency tolerance ±50 ppm. November 30, 2007 Preliminary 543 Electrical Characteristics b. IEEE 802.3 frequency tolerance ±50 ppm. 23.2.7 Hibernation Module The Hibernation Module requires special system implementation considerations since it is intended to power-down all other sections of its host device. The system power-supply distribution and interfaces of the system must be driven to 0 VDC or powered down with the same regulator controlled by HIB. The regulators controlled by HIB are expected to have a settling time of 250 μs or less. Table 23-22. Hibernation Module Characteristics Parameter No H1 H2 H3 H4 H5 H6 H7 Parameter tHIB_LOW tHIB_HIGH Parameter Name Internal 32.768 KHz clock reference rising edge to /HIB asserted Internal 32.768 KHz clock reference rising edge to /HIB deasserted Min Nom Max Unit 62 62 20 200 30 124 250 μs μs μs μs ms μs μs tWAKE_ASSERT /WAKE assertion time tWAKETOHIB /WAKE assert to /HIB desassert a tXOSC_SETTLE XOSC settling time tHIB_REG_WRITE Time for a write to non-volatile registers in HIB module to complete 92 tHIB_TO_VDD HIB deassert to VDD and VDD25 at minimum operational level - a. This parameter is highly sensitive to PCB layout and trace lengths, which may make this parameter time longer. Care must be taken in PCB design to minimize trace lengths and RLC (resistance, inductance, capacitance). Figure 23-4. Hibernation Module Timing 32.768 KHz (internal) H1 H2 /HIB H4 /WAKE H3 23.2.8 Synchronous Serial Interface (SSI) Table 23-23. SSI Characteristics Parameter No. Parameter Parameter Name S1 S2 S3 S4 S5 S6 S7 tclk_per tclk_high tclk_low tclkrf tDMd tDMs tDMh SSIClk cycle time SSIClk high time SSIClk low time SSIClk rise/fall time Data from master valid delay time Data from master setup time Data from master hold time Min Nom Max 2 0 20 40 1/2 1/2 7.4 Unit 65024 system clocks 26 20 t clk_per t clk_per ns ns ns ns 544 Preliminary November 30, 2007 LM3S6965 Microcontroller Parameter No. Parameter Parameter Name S8 S9 tDSs tDSh Data from slave setup time Data from slave hold time Min Nom Max 20 40 - Unit ns ns Figure 23-5. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement S1 S2 S4 SSIClk S3 SSIFss SSITx SSIRx MSB 4 to 16 bits LSB Figure 23-6. SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer S2 S1 SSIClk S3 SSIFss SSITx MSB 8-bit control LSB SSIRx 0 MSB 4 to 16 bits output data LSB November 30, 2007 Preliminary 545 Electrical Characteristics Figure 23-7. SSI Timing for SPI Frame Format (FRF=00), with SPH=1 S1 S4 S2 SSIClk (SPO=0) S3 SSIClk (SPO=1) S6 S7 SSITx (master) S5 MSB S8 S9 LSB SSIRx (slave) MSB LSB SSIFss 23.2.9 JTAG and Boundary Scan Table 23-24. JTAG Characteristics Parameter No. J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 t TDO_ZDV Parameter fTCK tTCK tTCK_LOW tTCK_HIGH tTCK_R tTCK_F tTMS_SU tTMS_HLD tTDI_SU tTDI_HLD TCK fall to Data Valid from High-Z Parameter Name TCK operational clock frequency TCK operational clock period TCK clock Low time TCK clock High time TCK rise time TCK fall time TMS setup time to TCK rise TMS hold time from TCK rise TDI setup time to TCK rise TDI hold time from TCK rise 2-mA drive 4-mA drive 8-mA drive 8-mA drive with slew rate control J12 t TDO_DV TCK fall to Data Valid from Data Valid 2-mA drive 4-mA drive 8-mA drive 8-mA drive with slew rate control Min Nom Max Unit 0 100 0 0 20 20 25 25 tTCK tTCK 23 15 14 18 21 14 13 18 10 MHz 10 10 35 26 25 29 35 25 24 28 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 546 Preliminary November 30, 2007 LM3S6965 Microcontroller Parameter No. J13 t TDO_DVZ Parameter TCK fall to High-Z from Data Valid Parameter Name 2-mA drive 4-mA drive 8-mA drive 8-mA drive with slew rate control Min Nom Max Unit 9 7 6 7 100 10 11 9 8 9 ns ns ns ns ns ns J14 J15 tTRST tTRST_SU TRST assertion time TRST setup time to TCK rise Figure 23-8. JTAG Test Clock Input Timing J2 J3 J4 TCK J6 J5 Figure 23-9. JTAG Test Access Port (TAP) Timing TCK J7 J8 J7 J8 TMS TMS Input Valid J9 J10 TMS Input Valid J9 J10 TDI J11 TDI Input Valid J12 TDO Output Valid TDI Input Valid J13 TDO Output Valid TDO Figure 23-10. JTAG TRST Timing TCK J14 J15 TRST 23.2.10 General-Purpose I/O Note: All GPIOs are 5 V-tolerant. November 30, 2007 Preliminary 547 Electrical Characteristics Table 23-25. GPIO Characteristics Parameter Parameter Name tGPIOR GPIO Rise Time (from 20% to 80% of VDD) Condition 2-mA drive 4-mA drive 8-mA drive 8-mA drive with slew rate control tGPIOF GPIO Fall Time (from 80% to 20% of VDD) 2-mA drive 4-mA drive 8-mA drive 8-mA drive with slew rate control Min Nom Max Unit 17 9 6 10 17 8 6 11 26 13 9 12 25 12 10 13 ns ns ns ns ns ns ns ns 23.2.11 Reset Table 23-26. Reset Characteristics Parameter No. Parameter Parameter Name R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 a. 20 * t MOSC_per VTH VBTH TPOR TBOR TIRPOR TIRBOR TIRHWR TIRSWR TIRWDR TVDDRISE TMIN Reset threshold Brown-Out threshold Power-On Reset timeout Brown-Out timeout Internal reset timeout after POR Internal reset timeout after BOR a Min Nom Max Unit 2.0 V V ms µs ms µs ms µs µs 2.85 2.9 2.95 6 0 0 reset a 2.5 2.5 2 10 500 11 1 1 20 20 Internal reset timeout after hardware reset (RST pin) Internal reset timeout after software-initiated system Internal reset timeout after watchdog reseta Supply voltage (VDD) rise time (0V-3.3V) Minimum RST pulse width 100 ms µs Figure 23-11. External Reset Timing (RST) RST R11 R7 /Reset (Internal) 548 Preliminary November 30, 2007 LM3S6965 Microcontroller Figure 23-12. Power-On Reset Timing R1 VDD R3 /POR (Internal) R5 /Reset (Internal) Figure 23-13. Brown-Out Reset Timing R2 VDD R4 /BOR (Internal) R6 /Reset (Internal) Figure 23-14. Software Reset Timing SW Reset R8 /Reset (Internal) Figure 23-15. Watchdog Reset Timing WDOG Reset (Internal) R9 /Reset (Internal) November 30, 2007 Preliminary 549 Package Information 24 Package Information Figure 24-1. 100-Pin LQFP Package Note: The following notes apply to the package drawing. 1. All dimensions shown in mm. 2. Dimensions shown are nominal with tolerances indicated. 3. Foot length 'L' is measured at gage plane 0.25 mm above seating plane. 550 Preliminary November 30, 2007 LM3S6965 Microcontroller Body +2.00 mm Footprint, 1.4 mm package thickness Symbols A A1 A2 D D1 E E1 L e b θ ddd ccc ±0.05 ±0.20 ±0.05 ±0.20 ±0.05 ±0.15/-0.10 BASIC ±0.05 === Max. Max. Leads Max. 100L 1.60 0.05 Min./0.15 Max. 1.40 16.00 14.00 16.00 14.00 0.60 0.50 0.22 0˚~7˚ 0.08 0.08 MS-026 BED JEDEC Reference Drawing Variation Designator November 30, 2007 Preliminary 551 Serial Flash Loader A A.1 Serial Flash Loader Serial Flash Loader The Stellaris serial flash loader is a preprogrammed flash-resident utility used to download code to the flash memory of a device without the use of a debug interface. The serial flash loader uses a simple packet interface to provide synchronous communication with the device. The flash loader runs off the crystal and does not enable the PLL, so its speed is determined by the crystal used. The two serial interfaces that can be used are the UART0 and SSI0 interfaces. For simplicity, both the data format and communication protocol are identical for both serial interfaces. ® A.2 Interfaces Once communication with the flash loader is established via one of the serial interfaces, that interface is used until the flash loader is reset or new code takes over. For example, once you start communicating using the SSI port, communications with the flash loader via the UART are disabled until the device is reset. A.2.1 UART The Universal Asynchronous Receivers/Transmitters (UART) communication uses a fixed serial format of 8 bits of data, no parity, and 1 stop bit. The baud rate used for communication is automatically detected by the flash loader and can be any valid baud rate supported by the host and the device. The auto detection sequence requires that the baud rate should be no more than 1/32 the crystal frequency of the board that is running the serial flash loader. This is actually the ® same as the hardware limitation for the maximum baud rate for any UART on a Stellaris device which is calculated as follows: Max Baud Rate = System Clock Frequency / 16 In order to determine the baud rate, the serial flash loader needs to determine the relationship between its own crystal frequency and the baud rate. This is enough information for the flash loader to configure its UART to the same baud rate as the host. This automatic baud-rate detection allows the host to use any valid baud rate that it wants to communicate with the device. The method used to perform this automatic synchronization relies on the host sending the flash loader two bytes that are both 0x55. This generates a series of pulses to the flash loader that it can use to calculate the ratios needed to program the UART to match the host’s baud rate. After the host sends the pattern, it attempts to read back one byte of data from the UART. The flash loader returns the value of 0xCC to indicate successful detection of the baud rate. If this byte is not received after at least twice the time required to transfer the two bytes, the host can resend another pattern of 0x55, 0x55, and wait for the 0xCC byte again until the flash loader acknowledges that it has received a synchronization pattern correctly. For example, the time to wait for data back from the flash loader should be calculated as at least 2*(20(bits/sync)/baud rate (bits/sec)). For a baud rate of 115200, this time is 2*(20/115200) or 0.35 ms. A.2.2 SSI The Synchronous Serial Interface (SSI) port also uses a fixed serial format for communications, with the framing defined as Motorola format with SPH set to 1 and SPO set to 1. See “Frame Formats” on page 339 in the SSI chapter for more information on formats for this transfer protocol. Like the UART, this interface has hardware requirements that limit the maximum speed that the SSI clock can run. This allows the SSI clock to be at most 1/12 the crystal frequency of the board running 552 Preliminary November 30, 2007 LM3S6965 Microcontroller the flash loader. Since the host device is the master, the SSI on the flash loader device does not need to determine the clock as it is provided directly by the host. A.3 Packet Handling All communications, with the exception of the UART auto-baud, are done via defined packets that are acknowledged (ACK) or not acknowledged (NAK) by the devices. The packets use the same format for receiving and sending packets, including the method used to acknowledge successful or unsuccessful reception of a packet. A.3.1 Packet Format All packets sent and received from the device use the following byte-packed format. struct { unsigned char ucSize; unsigned char ucCheckSum; unsigned char Data[]; }; ucSize ucChecksum Data The first byte received holds the total size of the transfer including the size and checksum bytes. This holds a simple checksum of the bytes in the data buffer only. The algorithm is Data[0]+Data[1]+…+ Data[ucSize-3]. This is the raw data intended for the device, which is formatted in some form of command interface. There should be ucSize–2 bytes of data provided in this buffer to or from the device. A.3.2 Sending Packets The actual bytes of the packet can be sent individually or all at once; the only limitation is that commands that cause flash memory access should limit the download sizes to prevent losing bytes during flash programming. This limitation is discussed further in the section that describes the serial flash loader command, COMMAND_SEND_DATA (see “COMMAND_SEND_DATA (0x24)” on page 555). Once the packet has been formatted correctly by the host, it should be sent out over the UART or SSI interface. Then the host should poll the UART or SSI interface for the first non-zero data returned from the device. The first non-zero byte will either be an ACK (0xCC) or a NAK (0x33) byte from the device indicating the packet was received successfully (ACK) or unsuccessfully (NAK). This does not indicate that the actual contents of the command issued in the data portion of the packet were valid, just that the packet was received correctly. A.3.3 Receiving Packets The flash loader sends a packet of data in the same format that it receives a packet. The flash loader may transfer leading zero data before the first actual byte of data is sent out. The first non-zero byte is the size of the packet followed by a checksum byte, and finally followed by the data itself. There is no break in the data after the first non-zero byte is sent from the flash loader. Once the device communicating with the flash loader receives all the bytes, it must either ACK or NAK the packet to indicate that the transmission was successful. The appropriate response after sending a NAK to the flash loader is to resend the command that failed and request the data again. If needed, the host may send leading zeros before sending down the ACK/NAK signal to the flash loader, as the November 30, 2007 Preliminary 553 Serial Flash Loader flash loader only accepts the first non-zero data as a valid response. This zero padding is needed by the SSI interface in order to receive data to or from the flash loader. A.4 Commands The next section defines the list of commands that can be sent to the flash loader. The first byte of the data should always be one of the defined commands, followed by data or parameters as determined by the command that is sent. A.4.1 COMMAND_PING (0X20) This command simply accepts the command and sets the global status to success. The format of the packet is as follows: Byte[0] = 0x03; Byte[1] = checksum(Byte[2]); Byte[2] = COMMAND_PING; The ping command has 3 bytes and the value for COMMAND_PING is 0x20 and the checksum of one byte is that same byte, making Byte[1] also 0x20. Since the ping command has no real return status, the receipt of an ACK can be interpreted as a successful ping to the flash loader. A.4.2 COMMAND_GET_STATUS (0x23) This command returns the status of the last command that was issued. Typically, this command should be sent after every command to ensure that the previous command was successful or to properly respond to a failure. The command requires one byte in the data of the packet and should be followed by reading a packet with one byte of data that contains a status code. The last step is to ACK or NAK the received data so the flash loader knows that the data has been read. Byte[0] = 0x03 Byte[1] = checksum(Byte[2]) Byte[2] = COMMAND_GET_STATUS A.4.3 COMMAND_DOWNLOAD (0x21) This command is sent to the flash loader to indicate where to store data and how many bytes will be sent by the COMMAND_SEND_DATA commands that follow. The command consists of two 32-bit values that are both transferred MSB first. The first 32-bit value is the address to start programming data into, while the second is the 32-bit size of the data that will be sent. This command also triggers an erase of the full area to be programmed so this command takes longer than other commands. This results in a longer time to receive the ACK/NAK back from the board. This command should be followed by a COMMAND_GET_STATUS to ensure that the Program Address and Program size are valid for the device running the flash loader. The format of the packet to send this command is a follows: Byte[0] Byte[1] Byte[2] Byte[3] Byte[4] Byte[5] Byte[6] Byte[7] = = = = = = = = 11 checksum(Bytes[2:10]) COMMAND_DOWNLOAD Program Address [31:24] Program Address [23:16] Program Address [15:8] Program Address [7:0] Program Size [31:24] 554 Preliminary November 30, 2007 LM3S6965 Microcontroller Byte[8] = Program Size [23:16] Byte[9] = Program Size [15:8] Byte[10] = Program Size [7:0] A.4.4 COMMAND_SEND_DATA (0x24) This command should only follow a COMMAND_DOWNLOAD command or another COMMAND_SEND_DATA command if more data is needed. Consecutive send data commands automatically increment address and continue programming from the previous location. The caller should limit transfers of data to a maximum 8 bytes of packet data to allow the flash to program successfully and not overflow input buffers of the serial interfaces. The command terminates programming once the number of bytes indicated by the COMMAND_DOWNLOAD command has been received. Each time this function is called it should be followed by a COMMAND_GET_STATUS to ensure that the data was successfully programmed into the flash. If the flash loader sends a NAK to this command, the flash loader does not increment the current address to allow retransmission of the previous data. Byte[0] = 11 Byte[1] = checksum(Bytes[2:10]) Byte[2] = COMMAND_SEND_DATA Byte[3] = Data[0] Byte[4] = Data[1] Byte[5] = Data[2] Byte[6] = Data[3] Byte[7] = Data[4] Byte[8] = Data[5] Byte[9] = Data[6] Byte[10] = Data[7] A.4.5 COMMAND_RUN (0x22) This command is used to tell the flash loader to execute from the address passed as the parameter in this command. This command consists of a single 32-bit value that is interpreted as the address to execute. The 32-bit value is transmitted MSB first and the flash loader responds with an ACK signal back to the host device before actually executing the code at the given address. This allows the host to know that the command was received successfully and the code is now running. Byte[0] Byte[1] Byte[2] Byte[3] Byte[4] Byte[5] Byte[6] = = = = = = = 7 checksum(Bytes[2:6]) COMMAND_RUN Execute Address[31:24] Execute Address[23:16] Execute Address[15:8] Execute Address[7:0] A.4.6 COMMAND_RESET (0x25) This command is used to tell the flash loader device to reset. This is useful when downloading a new image that overwrote the flash loader and wants to start from a full reset. Unlike the COMMAND_RUN command, this allows the initial stack pointer to be read by the hardware and set up for the new code. It can also be used to reset the flash loader if a critical error occurs and the host device wants to restart communication with the flash loader. November 30, 2007 Preliminary 555 Serial Flash Loader Byte[0] = 3 Byte[1] = checksum(Byte[2]) Byte[2] = COMMAND_RESET The flash loader responds with an ACK signal back to the host device before actually executing the software reset to the device running the flash loader. This allows the host to know that the command was received successfully and the part will be reset. 556 Preliminary November 30, 2007 LM3S6965 Microcontroller B 31 15 30 14 Register Quick Reference 29 13 28 12 27 11 26 10 25 9 24 8 23 7 22 6 21 5 20 4 19 3 18 2 17 1 16 0 System Control Base 0x400F.E000 DID0, type RO, offset 0x000, reset VER MAJOR PBORCTL, type R/W, offset 0x030, reset 0x0000.7FFD CLASS MINOR BORIOR LDOPCTL, type R/W, offset 0x034, reset 0x0000.0000 VADJ RIS, type RO, offset 0x050, reset 0x0000.0000 PLLLRIS IMC, type R/W, offset 0x054, reset 0x0000.0000 BORRIS PLLLIM MISC, type R/W1C, offset 0x058, reset 0x0000.0000 BORIM PLLLMIS RESC, type R/W, offset 0x05C, reset - BORMIS LDO RCC, type R/W, offset 0x060, reset 0x07AE.3AD1 ACG PWRDN PLLCFG, type RO, offset 0x064, reset BYPASS SYSDIV XTAL USESYSDIV SW WDT BOR POR EXT USEPWMDIV PWMDIV IOSCDIS MOSCDIS OSCSRC F RCC2, type R/W, offset 0x070, reset 0x0780.2800 USERCC2 PWRDN2 BYPASS2 SYSDIV2 OSCSRC2 R DSLPCLKCFG, type R/W, offset 0x144, reset 0x0780.0000 DSDIVORIDE DSOSCSRC DID1, type RO, offset 0x004, reset VER PINCOUNT DC0, type RO, offset 0x008, reset 0x00FF.007F SRAMSZ FLASHSZ DC1, type RO, offset 0x010, reset 0x0011.33FF PWM MINSYSDIV DC2, type RO, offset 0x014, reset 0x030F.5317 COMP1 I2C1 I2C0 QEI1 COMP0 QEI0 SSI0 TIMER3 TIMER2 UART2 TIMER1 UART1 TIMER0 UART0 MAXADCSPD MPU HIB TEMPSNS PLL WDT SWO SWD ADC JTAG FAM TEMP PARTNO PKG ROHS QUAL DC3, type RO, offset 0x018, reset 0x0F0F.87FF CCP3 PWMF T AUL CCP2 CCP1 CCP0 C0O C0PLUS C0MINUS PWM5 PWM4 ADC3 PWM3 ADC2 PWM2 ADC1 PWM1 ADC0 PWM0 C1PLUS C1MINUS November 30, 2007 Preliminary 557 Register Quick Reference 31 15 30 14 29 13 28 12 27 11 26 10 25 9 24 8 23 7 22 6 21 5 20 4 19 3 18 2 17 1 16 0 DC4, type RO, offset 0x01C, reset 0x5000.007F EPHY0 EMAC0 GPIOG RCGC0, type R/W, offset 0x100, reset 0x00000040 PWM MAXADCSPD SCGC0, type R/W, offset 0x110, reset 0x00000040 PWM MAXADCSPD DCGC0, type R/W, offset 0x120, reset 0x00000040 PWM MAXADCSPD RCGC1, type R/W, offset 0x104, reset 0x00000000 COMP1 I2C1 I2C0 QEI1 COMP0 QEI0 SSI0 TIMER3 TIMER2 UART2 TIMER1 UART1 TIMER0 UART0 HIB WDT ADC HIB WDT ADC HIB WDT ADC GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA SCGC1, type R/W, offset 0x114, reset 0x00000000 COMP1 I2C1 I2C0 QEI1 COMP0 QEI0 SSI0 TIMER3 TIMER2 UART2 TIMER1 UART1 TIMER0 UART0 DCGC1, type R/W, offset 0x124, reset 0x00000000 COMP1 I2C1 I2C0 QEI1 COMP0 QEI0 SSI0 TIMER3 TIMER2 UART2 TIMER1 UART1 TIMER0 UART0 RCGC2, type R/W, offset 0x108, reset 0x00000000 EPHY0 EMAC0 GPIOG SCGC2, type R/W, offset 0x118, reset 0x00000000 EPHY0 EMAC0 GPIOG DCGC2, type R/W, offset 0x128, reset 0x00000000 EPHY0 EMAC0 GPIOG SRCR0, type R/W, offset 0x040, reset 0x00000000 PWM HIB SRCR1, type R/W, offset 0x044, reset 0x00000000 COMP1 I2C1 I2C0 QEI1 COMP0 QEI0 SSI0 TIMER3 TIMER2 UART2 TIMER1 UART1 TIMER0 UART0 WDT ADC GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA SRCR2, type R/W, offset 0x048, reset 0x00000000 EPHY0 EMAC0 GPIOG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA Hibernation Module Base 0x400F.C000 HIBRTCC, type RO, offset 0x000, reset 0x0000.0000 RTCC RTCC HIBRTCM0, type R/W, offset 0x004, reset 0xFFFF.FFFF RTCM0 RTCM0 HIBRTCM1, type R/W, offset 0x008, reset 0xFFFF.FFFF RTCM1 RTCM1 HIBRTCLD, type R/W, offset 0x00C, reset 0xFFFF.FFFF RTCLD RTCLD 558 Preliminary November 30, 2007 LM3S6965 Microcontroller 31 15 30 14 29 13 28 12 27 11 26 10 25 9 24 8 23 7 22 6 21 5 20 4 19 3 18 2 17 1 16 0 HIBCTL, type R/W, offset 0x010, reset 0x0000.0000 VABORT CLK32EN LOWBA TEN PINWEN RTCWEN CLKSEL HIBIM, type R/W, offset 0x014, reset 0x0000.0000 HIBREQ RTCEN EXTW HIBRIS, type RO, offset 0x018, reset 0x0000.0000 LOWBAT RTCALT1 RTCALT0 EXTW HIBMIS, type RO, offset 0x01C, reset 0x0000.0000 LOWBAT RTCALT1 RTCALT0 EXTW HIBIC, type R/W1C, offset 0x020, reset 0x0000.0000 LOWBAT RTCALT1 RTCALT0 EXTW HIBRTCT, type R/W, offset 0x024, reset 0x0000.7FFF LOWBAT RTCALT1 RTCALT0 TRIM HIBDATA, type R/W, offset 0x030-0x12C, reset 0x0000.0000 RTD RTD Internal Memory Flash Control Offset Base 0x400F.D000 FMA, type R/W, offset 0x000, reset 0x0000.0000 OFFSET OFFSET FMD, type R/W, offset 0x004, reset 0x0000.0000 DATA DATA FMC, type R/W, offset 0x008, reset 0x0000.0000 WRKEY COMT FCRIS, type RO, offset 0x00C, reset 0x0000.0000 MERASE ERASE WRITE PRIS FCIM, type R/W, offset 0x010, reset 0x0000.0000 ARIS PMASK FCMISC, type R/W1C, offset 0x014, reset 0x0000.0000 AMASK PMISC AMISC Internal Memory System Control Offset Base 0x400F.E000 USECRL, type R/W, offset 0x140, reset 0x31 USEC FMPRE0, type R/W, offset 0x130 and 0x200, reset 0xFFFF.FFFF READ_ENABLE READ_ENABLE November 30, 2007 Preliminary 559 Register Quick Reference 31 15 30 14 29 13 28 12 27 11 26 10 25 9 24 8 23 7 22 6 21 5 20 4 19 3 18 2 17 1 16 0 FMPPE0, type R/W, offset 0x134 and 0x400, reset 0xFFFF.FFFF PROG_ENABLE PROG_ENABLE USER_DBG, type R/W, offset 0x1D0, reset 0xFFFF.FFFE NW DATA USER_REG0, type R/W, offset 0x1E0, reset 0xFFFF.FFFF NW DATA USER_REG1, type R/W, offset 0x1E4, reset 0xFFFF.FFFF NW DATA FMPRE1, type R/W, offset 0x204, reset 0xFFFF.FFFF READ_ENABLE READ_ENABLE FMPRE2, type R/W, offset 0x208, reset 0xFFFF.FFFF READ_ENABLE READ_ENABLE FMPRE3, type R/W, offset 0x20C, reset 0xFFFF.FFFF READ_ENABLE READ_ENABLE FMPPE1, type R/W, offset 0x404, reset 0xFFFF.FFFF PROG_ENABLE PROG_ENABLE FMPPE2, type R/W, offset 0x408, reset 0xFFFF.FFFF PROG_ENABLE PROG_ENABLE FMPPE3, type R/W, offset 0x40C, reset 0xFFFF.FFFF PROG_ENABLE PROG_ENABLE DATA DATA DATA DBG1 DBG0 General-Purpose Input/Outputs (GPIOs) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.5000 GPIO Port G base: 0x4002.6000 GPIODATA, type R/W, offset 0x000, reset 0x0000.0000 DATA GPIODIR, type R/W, offset 0x400, reset 0x0000.0000 DIR GPIOIS, type R/W, offset 0x404, reset 0x0000.0000 IS GPIOIBE, type R/W, offset 0x408, reset 0x0000.0000 IBE GPIOIEV, type R/W, offset 0x40C, reset 0x0000.0000 IEV 560 Preliminary November 30, 2007 LM3S6965 Microcontroller 31 15 30 14 29 13 28 12 27 11 26 10 25 9 24 8 23 7 22 6 21 5 20 4 19 3 18 2 17 1 16 0 GPIOIM, type R/W, offset 0x410, reset 0x0000.0000 IME GPIORIS, type RO, offset 0x414, reset 0x0000.0000 RIS GPIOMIS, type RO, offset 0x418, reset 0x0000.0000 MIS GPIOICR, type W1C, offset 0x41C, reset 0x0000.0000 IC GPIOAFSEL, type R/W, offset 0x420, reset - AFSEL GPIODR2R, type R/W, offset 0x500, reset 0x0000.00FF DRV2 GPIODR4R, type R/W, offset 0x504, reset 0x0000.0000 DRV4 GPIODR8R, type R/W, offset 0x508, reset 0x0000.0000 DRV8 GPIOODR, type R/W, offset 0x50C, reset 0x0000.0000 ODE GPIOPUR, type R/W, offset 0x510, reset - PUE GPIOPDR, type R/W, offset 0x514, reset 0x0000.0000 PDE GPIOSLR, type R/W, offset 0x518, reset 0x0000.0000 SRL GPIODEN, type R/W, offset 0x51C, reset - DEN GPIOLOCK, type R/W, offset 0x520, reset 0x0000.0001 LOCK LOCK GPIOCR, type -, offset 0x524, reset - CR GPIOPeriphID4, type RO, offset 0xFD0, reset 0x0000.0000 PID4 GPIOPeriphID5, type RO, offset 0xFD4, reset 0x0000.0000 PID5 November 30, 2007 Preliminary 561 Register Quick Reference 31 15 30 14 29 13 28 12 27 11 26 10 25 9 24 8 23 7 22 6 21 5 20 4 19 3 18 2 17 1 16 0 GPIOPeriphID6, type RO, offset 0xFD8, reset 0x0000.0000 PID6 GPIOPeriphID7, type RO, offset 0xFDC, reset 0x0000.0000 PID7 GPIOPeriphID0, type RO, offset 0xFE0, reset 0x0000.0061 PID0 GPIOPeriphID1, type RO, offset 0xFE4, reset 0x0000.0000 PID1 GPIOPeriphID2, type RO, offset 0xFE8, reset 0x0000.0018 PID2 GPIOPeriphID3, type RO, offset 0xFEC, reset 0x0000.0001 PID3 GPIOPCellID0, type RO, offset 0xFF0, reset 0x0000.000D CID0 GPIOPCellID1, type RO, offset 0xFF4, reset 0x0000.00F0 CID1 GPIOPCellID2, type RO, offset 0xFF8, reset 0x0000.0005 CID2 GPIOPCellID3, type RO, offset 0xFFC, reset 0x0000.00B1 CID3 General-Purpose Timers Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Timer3 base: 0x4003.3000 GPTMCFG, type R/W, offset 0x000, reset 0x0000.0000 GPTMCFG GPTMTAMR, type R/W, offset 0x004, reset 0x0000.0000 TAAMS GPTMTBMR, type R/W, offset 0x008, reset 0x0000.0000 TACMR TAMR TBAMS GPTMCTL, type R/W, offset 0x00C, reset 0x0000.0000 TBCMR TBMR TBPWML TBOTE TBEVENT TBSTALL TBEN TAPWML TAOTE RTCEN TAEVENT TASTALL TAEN GPTMIMR, type R/W, offset 0x018, reset 0x0000.0000 CBEIM GPTMRIS, type RO, offset 0x01C, reset 0x0000.0000 CBMIM TBTOIM RTCIM CAEIM CAMIM TATOIM CBERIS CBMRIS TBTORIS RTCRIS CAERIS CAMRIS TATORIS 562 Preliminary November 30, 2007 LM3S6965 Microcontroller 31 15 30 14 29 13 28 12 27 11 26 10 25 9 24 8 23 7 22 6 21 5 20 4 19 3 18 2 17 1 16 0 GPTMMIS, type RO, offset 0x020, reset 0x0000.0000 CBEMIS GPTMICR, type W1C, offset 0x024, reset 0x0000.0000 CBMMIS TBTOMIS RTCMIS CAEMIS CAMMIS TATOMIS CBECINT CBMCINT TBTOCINT GPTMTAILR, type R/W, offset 0x028, reset 0x0000.FFFF (16-bit mode) and 0xFFFF.FFFF (32-bit mode) TAILRH TAILRL GPTMTBILR, type R/W, offset 0x02C, reset 0x0000.FFFF RTCCINT CAECINT CAMCINT TATOCINT TBILRL GPTMTAMATCHR, type R/W, offset 0x030, reset 0x0000.FFFF (16-bit mode) and 0xFFFF.FFFF (32-bit mode) TAMRH TAMRL GPTMTBMATCHR, type R/W, offset 0x034, reset 0x0000.FFFF TBMRL GPTMTAPR, type R/W, offset 0x038, reset 0x0000.0000 TAPSR GPTMTBPR, type R/W, offset 0x03C, reset 0x0000.0000 TBPSR GPTMTAPMR, type R/W, offset 0x040, reset 0x0000.0000 TAPSMR GPTMTBPMR, type R/W, offset 0x044, reset 0x0000.0000 TBPSMR GPTMTAR, type RO, offset 0x048, reset 0x0000.FFFF (16-bit mode) and 0xFFFF.FFFF (32-bit mode) TARH TARL GPTMTBR, type RO, offset 0x04C, reset 0x0000.FFFF TBRL Watchdog Timer Base 0x4000.0000 WDTLOAD, type R/W, offset 0x000, reset 0xFFFF.FFFF WDTLoad WDTLoad WDTVALUE, type RO, offset 0x004, reset 0xFFFF.FFFF WDTValue WDTValue WDTCTL, type R/W, offset 0x008, reset 0x0000.0000 RESEN WDTICR, type WO, offset 0x00C, reset WDTIntClr WDTIntClr WDTRIS, type RO, offset 0x010, reset 0x0000.0000 INTEN WDTRIS November 30, 2007 Preliminary 563 Register Quick Reference 31 15 30 14 29 13 28 12 27 11 26 10 25 9 24 8 23 7 22 6 21 5 20 4 19 3 18 2 17 1 16 0 WDTMIS, type RO, offset 0x014, reset 0x0000.0000 WDTMIS WDTTEST, type R/W, offset 0x418, reset 0x0000.0000 STALL WDTLOCK, type R/W, offset 0xC00, reset 0x0000.0000 WDTLock WDTLock WDTPeriphID4, type RO, offset 0xFD0, reset 0x0000.0000 PID4 WDTPeriphID5, type RO, offset 0xFD4, reset 0x0000.0000 PID5 WDTPeriphID6, type RO, offset 0xFD8, reset 0x0000.0000 PID6 WDTPeriphID7, type RO, offset 0xFDC, reset 0x0000.0000 PID7 WDTPeriphID0, type RO, offset 0xFE0, reset 0x0000.0005 PID0 WDTPeriphID1, type RO, offset 0xFE4, reset 0x0000.0018 PID1 WDTPeriphID2, type RO, offset 0xFE8, reset 0x0000.0018 PID2 WDTPeriphID3, type RO, offset 0xFEC, reset 0x0000.0001 PID3 WDTPCellID0, type RO, offset 0xFF0, reset 0x0000.000D CID0 WDTPCellID1, type RO, offset 0xFF4, reset 0x0000.00F0 CID1 WDTPCellID2, type RO, offset 0xFF8, reset 0x0000.0005 CID2 WDTPCellID3, type RO, offset 0xFFC, reset 0x0000.00B1 CID3 Analog-to-Digital Converter (ADC) Base 0x4003.8000 ADCACTSS, type R/W, offset 0x000, reset 0x0000.0000 ASEN3 ADCRIS, type RO, offset 0x004, reset 0x0000.0000 ASEN2 ASEN1 ASEN0 INR3 INR2 INR1 INR0 564 Preliminary November 30, 2007 LM3S6965 Microcontroller 31 15 30 14 29 13 28 12 27 11 26 10 25 9 24 8 23 7 22 6 21 5 20 4 19 3 18 2 17 1 16 0 ADCIM, type R/W, offset 0x008, reset 0x0000.0000 MASK3 ADCISC, type R/W1C, offset 0x00C, reset 0x0000.0000 MASK2 MASK1 MASK0 IN3 ADCOSTAT, type R/W1C, offset 0x010, reset 0x0000.0000 IN2 IN1 IN0 OV3 ADCEMUX, type R/W, offset 0x014, reset 0x0000.0000 OV2 OV1 OV0 EM3 ADCUSTAT, type R/W1C, offset 0x018, reset 0x0000.0000 EM2 EM1 EM0 UV3 ADCSSPRI, type R/W, offset 0x020, reset 0x0000.3210 UV2 UV1 UV0 SS3 ADCPSSI, type WO, offset 0x028, reset - SS2 SS1 SS0 SS3 ADCSAC, type R/W, offset 0x030, reset 0x0000.0000 SS2 SS1 SS0 AVG ADCSSMUX0, type R/W, offset 0x040, reset 0x0000.0000 MUX7 MUX3 ADCSSCTL0, type R/W, offset 0x044, reset 0x0000.0000 TS7 TS3 IE7 IE3 END7 END3 D7 D3 TS6 TS2 IE6 IE2 END6 END2 D6 D2 TS5 TS1 IE5 IE1 END5 END1 D5 D1 TS4 TS0 IE4 IE0 END4 END0 D4 D0 MUX6 MUX2 MUX5 MUX1 MUX4 MUX0 ADCSSFIFO0, type RO, offset 0x048, reset 0x0000.0000 DATA ADCSSFIFO1, type RO, offset 0x068, reset 0x0000.0000 DATA ADCSSFIFO2, type RO, offset 0x088, reset 0x0000.0000 DATA ADCSSFIFO3, type RO, offset 0x0A8, reset 0x0000.0000 DATA ADCSSFSTAT0, type RO, offset 0x04C, reset 0x0000.0100 FULL ADCSSFSTAT1, type RO, offset 0x06C, reset 0x0000.0100 EMPTY HPTR TPTR FULL ADCSSFSTAT2, type RO, offset 0x08C, reset 0x0000.0100 EMPTY HPTR TPTR FULL EMPTY HPTR TPTR November 30, 2007 Preliminary 565 Register Quick Reference 31 15 30 14 29 13 28 12 27 11 26 10 25 9 24 8 23 7 22 6 21 5 20 4 19 3 18 2 17 1 16 0 ADCSSFSTAT3, type RO, offset 0x0AC, reset 0x0000.0100 FULL ADCSSMUX1, type RO, offset 0x060, reset 0x0000.0000 EMPTY HPTR TPTR MUX3 ADCSSMUX2, type RO, offset 0x080, reset 0x0000.0000 MUX2 MUX1 MUX0 MUX3 ADCSSCTL1, type RO, offset 0x064, reset 0x0000.0000 MUX2 MUX1 MUX0 TS3 IE3 END3 D3 TS2 IE2 END2 D2 TS1 IE1 END1 D1 TS0 IE0 END0 D0 ADCSSCTL2, type RO, offset 0x084, reset 0x0000.0000 TS3 IE3 END3 D3 TS2 IE2 END2 D2 TS1 IE1 END1 D1 TS0 IE0 END0 D0 ADCSSMUX3, type R/W, offset 0x0A0, reset 0x0000.0000 MUX0 ADCSSCTL3, type R/W, offset 0x0A4, reset 0x0000.0002 TS0 ADCTMLB, type RO, offset 0x100, reset 0x0000.0000 IE0 END0 D0 CNT ADCTMLB, type WO, offset 0x100, reset 0x0000.0000 CONT DIFF TS MUX LB Universal Asynchronous Receivers/Transmitters (UARTs) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UART2 base: 0x4000.E000 UARTDR, type R/W, offset 0x000, reset 0x0000.0000 OE BE PE FE DATA UARTRSR/UARTECR, type RO, offset 0x004, reset 0x0000.0000 OE UARTRSR/UARTECR, type WO, offset 0x004, reset 0x0000.0000 BE PE FE DATA UARTFR, type RO, offset 0x018, reset 0x0000.0090 TXFE UARTILPR, type R/W, offset 0x020, reset 0x0000.0000 RXFF TXFF RXFE BUSY ILPDVSR UARTIBRD, type R/W, offset 0x024, reset 0x0000.0000 DIVINT UARTFBRD, type R/W, offset 0x028, reset 0x0000.0000 DIVFRAC 566 Preliminary November 30, 2007 LM3S6965 Microcontroller 31 15 30 14 29 13 28 12 27 11 26 10 25 9 24 8 23 7 22 6 21 5 20 4 19 3 18 2 17 1 16 0 UARTLCRH, type R/W, offset 0x02C, reset 0x0000.0000 SPS UARTCTL, type R/W, offset 0x030, reset 0x0000.0300 WLEN FEN STP2 EPS PEN BRK RXE UARTIFLS, type R/W, offset 0x034, reset 0x0000.0012 TXE LBE SIRLP SIREN UARTEN RXIFLSEL UARTIM, type R/W, offset 0x038, reset 0x0000.0000 TXIFLSEL OEIM UARTRIS, type RO, offset 0x03C, reset 0x0000.000F BEIM PEIM FEIM RTIM TXIM RXIM OERIS UARTMIS, type RO, offset 0x040, reset 0x0000.0000 BERIS PERIS FERIS RTRIS TXRIS RXRIS OEMIS UARTICR, type W1C, offset 0x044, reset 0x0000.0000 BEMIS PEMIS FEMIS RTMIS TXMIS RXMIS OEIC UARTPeriphID4, type RO, offset 0xFD0, reset 0x0000.0000 BEIC PEIC FEIC RTIC TXIC RXIC PID4 UARTPeriphID5, type RO, offset 0xFD4, reset 0x0000.0000 PID5 UARTPeriphID6, type RO, offset 0xFD8, reset 0x0000.0000 PID6 UARTPeriphID7, type RO, offset 0xFDC, reset 0x0000.0000 PID7 UARTPeriphID0, type RO, offset 0xFE0, reset 0x0000.0011 PID0 UARTPeriphID1, type RO, offset 0xFE4, reset 0x0000.0000 PID1 UARTPeriphID2, type RO, offset 0xFE8, reset 0x0000.0018 PID2 UARTPeriphID3, type RO, offset 0xFEC, reset 0x0000.0001 PID3 UARTPCellID0, type RO, offset 0xFF0, reset 0x0000.000D CID0 UARTPCellID1, type RO, offset 0xFF4, reset 0x0000.00F0 CID1 November 30, 2007 Preliminary 567 Register Quick Reference 31 15 30 14 29 13 28 12 27 11 26 10 25 9 24 8 23 7 22 6 21 5 20 4 19 3 18 2 17 1 16 0 UARTPCellID2, type RO, offset 0xFF8, reset 0x0000.0005 CID2 UARTPCellID3, type RO, offset 0xFFC, reset 0x0000.00B1 CID3 Synchronous Serial Interface (SSI) SSI0 base: 0x4000.8000 SSICR0, type R/W, offset 0x000, reset 0x0000.0000 SCR SSICR1, type R/W, offset 0x004, reset 0x0000.0000 SPH SPO FRF DSS SOD SSIDR, type R/W, offset 0x008, reset 0x0000.0000 MS SSE LBM DATA SSISR, type RO, offset 0x00C, reset 0x0000.0003 BSY SSICPSR, type R/W, offset 0x010, reset 0x0000.0000 RFF RNE TNF TFE CPSDVSR SSIIM, type R/W, offset 0x014, reset 0x0000.0000 TXIM SSIRIS, type RO, offset 0x018, reset 0x0000.0008 RXIM RTIM RORIM TXRIS SSIMIS, type RO, offset 0x01C, reset 0x0000.0000 RXRIS RTRIS RORRIS TXMIS SSIICR, type W1C, offset 0x020, reset 0x0000.0000 RXMIS RTMIS RORMIS RTIC SSIPeriphID4, type RO, offset 0xFD0, reset 0x0000.0000 RORIC PID4 SSIPeriphID5, type RO, offset 0xFD4, reset 0x0000.0000 PID5 SSIPeriphID6, type RO, offset 0xFD8, reset 0x0000.0000 PID6 SSIPeriphID7, type RO, offset 0xFDC, reset 0x0000.0000 PID7 SSIPeriphID0, type RO, offset 0xFE0, reset 0x0000.0022 PID0 SSIPeriphID1, type RO, offset 0xFE4, reset 0x0000.0000 PID1 568 Preliminary November 30, 2007 LM3S6965 Microcontroller 31 15 30 14 29 13 28 12 27 11 26 10 25 9 24 8 23 7 22 6 21 5 20 4 19 3 18 2 17 1 16 0 SSIPeriphID2, type RO, offset 0xFE8, reset 0x0000.0018 PID2 SSIPeriphID3, type RO, offset 0xFEC, reset 0x0000.0001 PID3 SSIPCellID0, type RO, offset 0xFF0, reset 0x0000.000D CID0 SSIPCellID1, type RO, offset 0xFF4, reset 0x0000.00F0 CID1 SSIPCellID2, type RO, offset 0xFF8, reset 0x0000.0005 CID2 SSIPCellID3, type RO, offset 0xFFC, reset 0x0000.00B1 CID3 Inter-Integrated Circuit (I2C) Interface I2C Master I2C Master 0 base: 0x4002.0000 I2C Master 1 base: 0x4002.1000 I2CMSA, type R/W, offset 0x000, reset 0x0000.0000 SA I2CMCS, type RO, offset 0x004, reset 0x0000.0000 R/S BUSBSY I2CMCS, type WO, offset 0x004, reset 0x0000.0000 IDLE ARBLST DATACK ADRACK ERROR BUSY ACK I2CMDR, type R/W, offset 0x008, reset 0x0000.0000 STOP START RUN DATA I2CMTPR, type R/W, offset 0x00C, reset 0x0000.0001 TPR I2CMIMR, type R/W, offset 0x010, reset 0x0000.0000 IM I2CMRIS, type RO, offset 0x014, reset 0x0000.0000 RIS I2CMMIS, type RO, offset 0x018, reset 0x0000.0000 MIS I2CMICR, type WO, offset 0x01C, reset 0x0000.0000 IC I2CMCR, type R/W, offset 0x020, reset 0x0000.0000 SFE MFE LPBK November 30, 2007 Preliminary 569 Register Quick Reference 31 15 30 14 29 13 28 12 27 11 26 10 25 9 24 8 23 7 22 6 21 5 20 4 19 3 18 2 17 1 16 0 Inter-Integrated Circuit I2C Slave (I2C) Interface I2C Slave 0 base: 0x4002.0800 I2C Slave 1 base: 0x4002.1800 I2CSOAR, type R/W, offset 0x000, reset 0x0000.0000 OAR I2CSCSR, type RO, offset 0x004, reset 0x0000.0000 FBR I2CSCSR, type WO, offset 0x004, reset 0x0000.0000 TREQ RREQ DA I2CSDR, type R/W, offset 0x008, reset 0x0000.0000 DATA I2CSIMR, type R/W, offset 0x00C, reset 0x0000.0000 IM I2CSRIS, type RO, offset 0x010, reset 0x0000.0000 RIS I2CSMIS, type RO, offset 0x014, reset 0x0000.0000 MIS I2CSICR, type WO, offset 0x018, reset 0x0000.0000 IC Ethernet Controller Ethernet MAC Base 0x4004.8000 MACRIS, type RO, offset 0x000, reset 0x0000.0000 PHYINT MACIACK, type W1C, offset 0x000, reset 0x0000.0000 MDINT RXER FOV TXEMP TXER RXINT PHYINT MACIM, type R/W, offset 0x004, reset 0x0000.007F MDINT RXER FOV TXEMP TXER RXINT PHYINTM MDINTM MACRCTL, type R/W, offset 0x008, reset 0x0000.0008 RXERM FOVM TXEMPM TXERM RXINTM RSTFIFO BADCRC MACTCTL, type R/W, offset 0x00C, reset 0x0000.0000 PRMS AMUL RXEN DUPLEX MACDATA, type RO, offset 0x010, reset 0x0000.0000 RXDATA RXDATA MACDATA, type WO, offset 0x010, reset 0x0000.0000 TXDATA TXDATA CRC PADEN TXEN 570 Preliminary November 30, 2007 LM3S6965 Microcontroller 31 15 30 14 29 13 28 12 27 11 26 10 25 9 24 8 23 7 22 6 21 5 20 4 19 3 18 2 17 1 16 0 MACIA0, type R/W, offset 0x014, reset 0x0000.0000 MACOCT4 MACOCT2 MACIA1, type R/W, offset 0x018, reset 0x0000.0000 MACOCT3 MACOCT1 MACOCT6 MACTHR, type R/W, offset 0x01C, reset 0x0000.003F MACOCT5 THRESH MACMCTL, type R/W, offset 0x020, reset 0x0000.0000 REGADR MACMDV, type R/W, offset 0x024, reset 0x0000.0080 WRITE START DIV MACMTXD, type R/W, offset 0x02C, reset 0x0000.0000 MDTX MACMRXD, type R/W, offset 0x030, reset 0x0000.0000 MDRX MACNP, type RO, offset 0x034, reset 0x0000.0000 NPR MACTR, type R/W, offset 0x038, reset 0x0000.0000 NEWTX Ethernet Controller MII Management Base 0x4004.8000 MR0, type R/W, address 0x00, reset 0x3100 RESET LOOPBK SPEEDSL ANEGEN PWRDN ISO RANEG DUPLEX COLT MR1, type RO, address 0x01, reset 0x7849 100X_F 100X_H 10T_F 10T_H MFPS ANEGC RFAULT ANEGA LINK JAB EXTD MR2, type RO, address 0x02, reset 0x000E OUI[21:6] MR3, type RO, address 0x03, reset 0x7237 OUI[5:0] MR4, type R/W, address 0x04, reset 0x01E1 NP RF A3 A2 A1 A0 S[4:0] MN RN MR5, type RO, address 0x05, reset 0x0000 NP ACK RF A[7:0] S[4:0] MR6, type RO, address 0x06, reset 0x0000 PDF MR16, type R/W, address 0x10, reset 0x0140 RPTR INPOL TXHIM SQEI NL10 APOL RVSPOL PCSBP RXCC LPNPA PRX LPANEGA MR17, type R/W, address 0x11, reset 0x0000 JABBER_IE RXER_IE PRX_IE PDF_IE N G O PI T LPACK_IE LSCHG_IE RFAULT_IE ANEGCOMP_IE JABBER_INT RXER_INT PRX_INT PDF_INT LPACK_INT LSCHG_INT RFAULT_INT A E C M _N MR18, type RO, address 0x12, reset 0x0000 ANEGF MR19, type R/W, address 0x13, reset 0x4000 TXO[1:0] DPLX RATE RXSD RX_LOCK November 30, 2007 Preliminary 571 Register Quick Reference 31 15 30 14 29 13 28 12 27 11 26 10 25 9 24 8 23 7 22 6 21 5 20 4 19 3 18 2 17 1 16 0 MR23, type R/W, address 0x17, reset 0x0010 LED1[3:0] MR24, type R/W, address 0x18, reset 0x00C0 PD_MODE AUTO_SW MDIX MDIX_CM MDIX_SD LED0[3:0] Analog Comparators Base 0x4003.C000 ACMIS, type R/W1C, offset 0x00, reset 0x0000.0000 IN1 ACRIS, type RO, offset 0x04, reset 0x0000.0000 IN0 IN1 ACINTEN, type R/W, offset 0x08, reset 0x0000.0000 IN0 IN1 ACREFCTL, type R/W, offset 0x10, reset 0x0000.0000 IN0 EN ACSTAT0, type RO, offset 0x20, reset 0x0000.0000 RNG VREF OVAL ACSTAT1, type RO, offset 0x40, reset 0x0000.0000 OVAL ACCTL0, type RO, offset 0x24, reset 0x0000.0000 TOEN ACCTL1, type RO, offset 0x44, reset 0x0000.0000 ASRCP TSLVAL TSEN ISLVAL ISEN CINV TOEN ASRCP TSLVAL TSEN ISLVAL ISEN CINV Pulse Width Modulator (PWM) Base 0x4002.8000 PWMCTL, type R/W, offset 0x000, reset 0x0000.0000 GlobalSync2 GlobalSync1 GlobalSync0 PWMSYNC, type R/W, offset 0x004, reset 0x0000.0000 Sync2 PWMENABLE, type R/W, offset 0x008, reset 0x0000.0000 Sync1 Sync0 PWM5En PWM4En PWM3En PWM2En PWM1En PWM0En PWMINVERT, type R/W, offset 0x00C, reset 0x0000.0000 PWM5Inv PWM4Inv PWM3Inv PWM2Inv PWM1Inv PWM0Inv PWMFAULT, type R/W, offset 0x010, reset 0x0000.0000 Fault5 PWMINTEN, type R/W, offset 0x014, reset 0x0000.0000 Fault4 Fault3 Fault2 Fault1 Fault0 IntFault IntPWM2 IntPWM1 IntPWM0 572 Preliminary November 30, 2007 LM3S6965 Microcontroller 31 15 30 14 29 13 28 12 27 11 26 10 25 9 24 8 23 7 22 6 21 5 20 4 19 3 18 2 17 1 16 0 PWMRIS, type RO, offset 0x018, reset 0x0000.0000 IntFault IntPWM2 IntPWM1 IntPWM0 PWMISC, type R/W1C, offset 0x01C, reset 0x0000.0000 IntFault IntPWM2 IntPWM1 IntPWM0 PWMSTATUS, type RO, offset 0x020, reset 0x0000.0000 Fault PWM0CTL, type R/W, offset 0x040, reset 0x0000.0000 CmpBUpd CmpAUpd LoadUpd PWM1CTL, type R/W, offset 0x080, reset 0x0000.0000 Debug Mode Enable CmpBUpd CmpAUpd LoadUpd PWM2CTL, type R/W, offset 0x0C0, reset 0x0000.0000 Debug Mode Enable CmpBUpd CmpAUpd LoadUpd PWM0INTEN, type R/W, offset 0x044, reset 0x0000.0000 Debug Mode Enable TrCmpBD TrCmpBU TrCmpAD TrCmpAU TrCntLoad PWM1INTEN, type R/W, offset 0x084, reset 0x0000.0000 TrCntZero IntCmpBD IntCmpBU IntCmpAD IntCmpAU IntCntLoad IntCntZero TrCmpBD TrCmpBU TrCmpAD TrCmpAU TrCntLoad PWM2INTEN, type R/W, offset 0x0C4, reset 0x0000.0000 TrCntZero IntCmpBD IntCmpBU IntCmpAD IntCmpAU IntCntLoad IntCntZero TrCmpBD TrCmpBU TrCmpAD TrCmpAU TrCntLoad PWM0RIS, type RO, offset 0x048, reset 0x0000.0000 TrCntZero IntCmpBD IntCmpBU IntCmpAD IntCmpAU IntCntLoad IntCntZero IntCmpBD IntCmpBU IntCmpAD IntCmpAU IntCntLoad PWM1RIS, type RO, offset 0x088, reset 0x0000.0000 IntCntZero IntCmpBD IntCmpBU IntCmpAD IntCmpAU IntCntLoad PWM2RIS, type RO, offset 0x0C8, reset 0x0000.0000 IntCntZero IntCmpBD IntCmpBU IntCmpAD IntCmpAU IntCntLoad PWM0ISC, type R/W1C, offset 0x04C, reset 0x0000.0000 IntCntZero IntCmpBD IntCmpBU IntCmpAD IntCmpAU IntCntLoad PWM1ISC, type R/W1C, offset 0x08C, reset 0x0000.0000 IntCntZero IntCmpBD IntCmpBU IntCmpAD IntCmpAU IntCntLoad PWM2ISC, type R/W1C, offset 0x0CC, reset 0x0000.0000 IntCntZero IntCmpBD IntCmpBU IntCmpAD IntCmpAU IntCntLoad PWM0LOAD, type R/W, offset 0x050, reset 0x0000.0000 IntCntZero Load PWM1LOAD, type R/W, offset 0x090, reset 0x0000.0000 Load November 30, 2007 Preliminary 573 Register Quick Reference 31 15 30 14 29 13 28 12 27 11 26 10 25 9 24 8 23 7 22 6 21 5 20 4 19 3 18 2 17 1 16 0 PWM2LOAD, type R/W, offset 0x0D0, reset 0x0000.0000 Load PWM0COUNT, type RO, offset 0x054, reset 0x0000.0000 Count PWM1COUNT, type RO, offset 0x094, reset 0x0000.0000 Count PWM2COUNT, type RO, offset 0x0D4, reset 0x0000.0000 Count PWM0CMPA, type R/W, offset 0x058, reset 0x0000.0000 CompA PWM1CMPA, type R/W, offset 0x098, reset 0x0000.0000 CompA PWM2CMPA, type R/W, offset 0x0D8, reset 0x0000.0000 CompA PWM0CMPB, type R/W, offset 0x05C, reset 0x0000.0000 CompB PWM1CMPB, type R/W, offset 0x09C, reset 0x0000.0000 CompB PWM2CMPB, type R/W, offset 0x0DC, reset 0x0000.0000 CompB PWM0GENA, type R/W, offset 0x060, reset 0x0000.0000 ActCmpBD PWM1GENA, type R/W, offset 0x0A0, reset 0x0000.0000 ActCmpBU ActCmpAD ActCmpAU ActLoad ActZero ActCmpBD PWM2GENA, type R/W, offset 0x0E0, reset 0x0000.0000 ActCmpBU ActCmpAD ActCmpAU ActLoad ActZero ActCmpBD PWM0GENB, type R/W, offset 0x064, reset 0x0000.0000 ActCmpBU ActCmpAD ActCmpAU ActLoad ActZero ActCmpBD PWM1GENB, type R/W, offset 0x0A4, reset 0x0000.0000 ActCmpBU ActCmpAD ActCmpAU ActLoad ActZero ActCmpBD PWM2GENB, type R/W, offset 0x0E4, reset 0x0000.0000 ActCmpBU ActCmpAD ActCmpAU ActLoad ActZero ActCmpBD PWM0DBCTL, type R/W, offset 0x068, reset 0x0000.0000 ActCmpBU ActCmpAD ActCmpAU ActLoad ActZero Enable 574 Preliminary November 30, 2007 LM3S6965 Microcontroller 31 15 30 14 29 13 28 12 27 11 26 10 25 9 24 8 23 7 22 6 21 5 20 4 19 3 18 2 17 1 16 0 PWM1DBCTL, type R/W, offset 0x0A8, reset 0x0000.0000 Enable PWM2DBCTL, type R/W, offset 0x0E8, reset 0x0000.0000 Enable PWM0DBRISE, type R/W, offset 0x06C, reset 0x0000.0000 RiseDelay PWM1DBRISE, type R/W, offset 0x0AC, reset 0x0000.0000 RiseDelay PWM2DBRISE, type R/W, offset 0x0EC, reset 0x0000.0000 RiseDelay PWM0DBFALL, type R/W, offset 0x070, reset 0x0000.0000 FallDelay PWM1DBFALL, type R/W, offset 0x0B0, reset 0x0000.0000 FallDelay PWM2DBFALL, type R/W, offset 0x0F0, reset 0x0000.0000 FallDelay Quadrature Encoder Interface (QEI) QEI0 base: 0x4002.C000 QEI1 base: 0x4002.D000 QEICTL, type R/W, offset 0x000, reset 0x0000.0000 STALLEN INVI INVB INVA VelDiv VelEn ResMode CapMode SigMode Swap Enable QEISTAT, type RO, offset 0x004, reset 0x0000.0000 Direction Error QEIPOS, type R/W, offset 0x008, reset 0x0000.0000 Position Position QEIMAXPOS, type R/W, offset 0x00C, reset 0x0000.0000 MaxPos MaxPos QEILOAD, type R/W, offset 0x010, reset 0x0000.0000 Load Load QEITIME, type RO, offset 0x014, reset 0x0000.0000 Time Time QEICOUNT, type RO, offset 0x018, reset 0x0000.0000 Count Count QEISPEED, type RO, offset 0x01C, reset 0x0000.0000 Speed Speed November 30, 2007 Preliminary 575 Register Quick Reference 31 15 30 14 29 13 28 12 27 11 26 10 25 9 24 8 23 7 22 6 21 5 20 4 19 3 18 2 17 1 16 0 QEIINTEN, type R/W, offset 0x020, reset 0x0000.0000 IntError QEIRIS, type RO, offset 0x024, reset 0x0000.0000 IntDir IntTimer IntIndex IntError QEIISC, type R/W1C, offset 0x028, reset 0x0000.0000 IntDir IntTimer IntIndex IntError IntDir IntTimer IntIndex 576 Preliminary November 30, 2007 LM3S6965 Microcontroller C C.1 Ordering and Contact Information Ordering Information LM3Snnnn–gppss–rrm Part Number Temperature I = -40 C to 85 C Package RN = 28-pin SOIC QN = 48-pin LQFP QC = 100-pin LQFP Speed 20 = 20 MHz 25 = 25 MHz 50 = 50 MHz Shipping Medium T = Tape-and-reel Omitted = Default shipping (tray or tube) Revision Omitted = Default to current shipping revision A0 = First all-layer mask A1 = Metal layers update to A0 A2 = Metal layers update to A1 B0 = Second all-layer mask revision Table C-1. Part Ordering Information Orderable Part Number Description LM3S6965-IQC50 LM3S6965-IQC50(T) Stellaris LM3S6965 Microcontroller Stellaris LM3S6965 Microcontroller ® ® C.2 Kits The Luminary Micro Stellaris Family provides the hardware and software tools that engineers need to begin development quickly. ■ Reference Design Kits accelerate product development by providing ready-to-run hardware, and comprehensive documentation including hardware design files: http://www.luminarymicro.com/products/reference_design_kits/ ■ Evaluation Kits provide a low-cost and effective means of evaluating Stellaris microcontrollers before purchase: http://www.luminarymicro.com/products/evaluation_kits/ ■ Development Kits provide you with all the tools you need to develop and prototype embedded applications right out of the box: http://www.luminarymicro.com/products/boards.html See the Luminary Micro website for the latest tools available or ask your Luminary Micro distributor. ® ® C.3 Company Information Luminary Micro, Inc. designs, markets, and sells ARM Cortex-M3-based microcontrollers (MCUs). Austin, Texas-based Luminary Micro is the lead partner for the Cortex-M3 processor, delivering the world's first silicon implementation of the Cortex-M3 processor. Luminary Micro's introduction of the November 30, 2007 Preliminary 577 Ordering and Contact Information Stellaris® family of products provides 32-bit performance for the same price as current 8- and 16-bit microcontroller designs. With entry-level pricing at $1.00 for an ARM technology-based MCU, Luminary Micro's Stellaris product line allows for standardization that eliminates future architectural upgrades or software tool changes. Luminary Micro, Inc. 108 Wild Basin, Suite 350 Austin, TX 78746 Main: +1-512-279-8800 Fax: +1-512-279-8879 http://www.luminarymicro.com sales@luminarymicro.com C.4 Support Information For support on Luminary Micro products, contact: support@luminarymicro.com +1-512-279-8800, ext. 3 578 Preliminary November 30, 2007