P3057LCG

NIKO-SEM N-Channel Logic Level Enhancement Mode Field Effect Transistor P3057LCG SOT-89 Lead-Free D PRODUCT SUMMARY V(BR)DSS 25 RDS(ON) 50mΩ ID 6A 3 G S 1 1. GATE 2. DRAIN 3. SOURCE ABSOLUTE MAXIMUM RATINGS (TC = 25 °C Unless Otherwise Noted) PARAMETERS/TEST CONDITIONS Gate-Source Voltage Continuous Drain Current Pulsed Drain Current Power Dissipation 1 SYMBOL VGS 2 LIMITS ±20 6 4 20 3 1.2 -55 to 150 275 UNITS V TC = 25 °C TC = 100 °C TC = 25 °C TC = 100 °C ID IDM PD Tj, Tstg TL A W Operating Junction & Storage Temperature Range Lead Temperature ( /16” from case for 10 sec.) THERMAL RESISTANCE RATINGS THERMAL RESISTANCE Junction-to-Case Junction-to-Ambient 1 2 1 °C SYMBOL RθJC RθJA TYPICAL MAXIMUM 18 160 UNITS °C / W Pulse width limited by maximum junction temperature. Duty cycle ≤ 1% ELECTRICAL CHARACTERISTICS (TC = 25 °C, Unless Otherwise Noted) PARAMETER SYMBOL TEST CONDITIONS STATIC Drain-Source Breakdown Voltage Gate Threshold Voltage Gate-Body Leakage Zero Gate Voltage Drain Current On-State Drain Current1 Drain-Source On-State Resistance1 Forward Transconductance1 V(BR)DSS VGS(th) IGSS IDSS ID(ON) RDS(ON) gfs VGS = 0V, ID = 250µA VDS = VGS, ID = 250µA VDS = 0V, VGS = ±20V VDS = 20V, VGS = 0V VDS = 20V, VGS = 0V, TJ = 125 °C VDS = 10V, VGS = 10V VGS = 4.5V, ID = 3A VGS = 10V, ID = 6A VDS = 15V, ID = 6A 6 70 48 16 115 85 25 0.8 1.2 2.5 V LIMITS UNIT MIN TYP MAX ±250 nA 25 250 µA A mΩ S 1 Jun-29-2004 NIKO-SEM N-Channel Logic Level Enhancement Mode Field Effect Transistor DYNAMIC P3057LCG SOT-89 Lead-Free Input Capacitance Output Capacitance Reverse Transfer Capacitance Total Gate Charge 2 2 Ciss Coss Crss Qg Qgs Qgd 2 450 VGS = 0V, VDS = 15V, f = 1MHz 200 60 15 VDS = 0.5V(BR)DSS, VGS = 10V, ID = 6A 2.0 7.0 6.0 VDS = 15V, RL = 1Ω ID ≅ 12A, VGS = 10V, RGS = 2.5Ω 6.0 20 5.0 nS nC pF Gate-Source Charge Gate-Drain Charge Rise Time2 2 Turn-On Delay Time td(on) tr td(off) tf Turn-Off Delay Time2 Fall Time2 SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS (TC = 25 °C) Continuous Current Pulsed Current3 Forward Voltage1 1 2 IS ISM VSD IF = IS, VGS = 0V 2.3 4 1.5 A V Pulse test : Pulse Width ≤ 300 µsec, Duty Cycle ≤ 2%. Independent of operating temperature. 3 Pulse width limited by maximum junction temperature. REMARK: THE PRODUCT MARKED WITH “P3057G”, DATE CODE or LOT # Orders for parts with Lead-Free plating can be placed using the PXXXXXXG parts name. 2 Jun-29-2004 NIKO-SEM N-Channel Logic Level Enhancement Mode Field Effect Transistor P3057LCG SOT-89 Lead-Free 3 Jun-29-2004 NIKO-SEM N-Channel Logic Level Enhancement Mode Field Effect Transistor P3057LCG SOT-89 Lead-Free SOT-89 MECHANICAL DATA mm Min. 4.3 1.6 0.4 2.4 0.8 0.4 0.4 Typ. 4.5 1.7 0.5 2.5 1.2 0.45 0.5 Max. 4.7 1.8 0.6 2.6 1.4 0.5 0.6 mm Min. 1.4 2.8 1.3 3.8 0.3 Typ. 1.5 3.0 1.5 4.2 0.4 Max. 1.6 3.2 1.7 4.6 0.5 Dimension A B C D E F G Dimension H I J K L M N 4 Jun-29-2004