P3503EVG

NIKO-SEM P3503EVG P-Channel Logic Level Enhancement Mode Field Effect Transistor D SOP-8 Lead-Free PRODUCT SUMMARY V(BR)DSS -30 RDS(ON) 35mΩ ID -8A G S 4 :GATE 5,6,7,8 :DRAIN 1,2,3 :SOURCE ABSOLUTE MAXIMUM RATINGS (TC = 25 °C Unless Otherwise Noted) PARAMETERS/TEST CONDITIONS Drain-Source Voltage Gate-Source Voltage Continuous Drain Current Pulsed Drain Current Power Dissipation 1 SYMBOL VDS VGS LIMITS -30 ± 20 -8 -7 UNITS V V TC = 25 °C TC = 70 °C ID IDM A -30 2.5 1.3 W TC = 25 °C TC = 70 °C PD Tj, Tstg Operating Junction & Storage Temperature Range THERMAL RESISTANCE RATINGS THERMAL RESISTANCE Junction-to-Case Junction-to-Ambient 1 2 -55 to 150 °C UNITS °C / W °C / W SYMBOL RθJc RθJA TYPICAL MAXIMUM 25 50 Pulse width limited by maximum junction temperature. Duty cycle ≤ 1% ELECTRICAL CHARACTERISTICS (TC = 25 °C, Unless Otherwise Noted) PARAMETER SYMBOL TEST CONDITIONS STATIC Drain-Source Breakdown Voltage Gate Threshold Voltage Gate-Body Leakage Zero Gate Voltage Drain Current On-State Drain Current 1 Drain-Source On-State Resistance1 Forward Transconductance1 V(BR)DSS VGS(th) IGSS IDSS ID(ON) RDS(ON) gfs VGS = 0V, ID = -250µA VDS = VGS, ID = -250µA VDS = 0V, VGS = ± 20V VDS = -24V, VGS = 0V VDS = -20V, VGS = 0V, TJ = 125 °C VDS = -5V, VGS = -10V VGS = -4.5V, ID = -6A VGS = -10V, ID = -8A VDS = -10V, ID = -6A -30 44 28 7 60 35 S -30 -0.8 -1.5 -2.5 ±100 -1 -10 A mΩ nA µA V LIMITS UNIT MIN TYP MAX Jan-06-2005 1 NIKO-SEM P3503EVG P-Channel Logic Level Enhancement Mode Field Effect Transistor DYNAMIC SOP-8 Lead-Free Input Capacitance Output Capacitance Reverse Transfer Capacitance Total Gate Charge 2 Ciss Coss Crss Qg Qgs Qgd 2 970 VGS = 0V, VDS = -10V, f = 1MHz 370 180 28 VDS = 0.5V (BR)DSS, VGS = -10V, ID = -8A 6 12 20 VDS = -15V, RL = 1Ω ID ≅ -1A, VGS = -10V, RGS = 6Ω 17 180 75 nS nC pF Gate-Source Charge2 Gate-Drain Charge2 Turn-On Delay Time Rise Time2 Turn-Off Delay Time2 Fall Time2 td(on) tr td(off) tf SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS (TC = 25 °C) Continuous Current Pulsed Current 3 Forward Voltage1 Reverse Recovery Charge 1 2 IS ISM VSD Qrr IF = -1A, VGS = 0V 7.9 -3 -6 -1 A V nC Pulse test : Pulse Width ≤ 300 µsec, Duty Cycle ≤ 2％ . Independent of operating temperature. 3 Pulse width limited by maximum junction temperature. REMARK: THE PRODUCT MARKED WITH “P3503EVG”, DATE CODE or LOT # Orders for parts with Lead-Free plating can be placed using the PXXXXXXG parts name. Jan-06-2005 2 NIKO-SEM P3503EVG P-Channel Logic Level Enhancement Mode Field Effect Transistor SOP-8 Lead-Free Jan-06-2005 3 NIKO-SEM P3503EVG P-Channel Logic Level Enhancement Mode Field Effect Transistor SOP-8 Lead-Free Jan-06-2005 4 NIKO-SEM P3503EVG P-Channel Logic Level Enhancement Mode Field Effect Transistor SOP-8 Lead-Free SOIC-8(D) MECHANICAL DATA mm Dimension Min. A B C D E F G mm Dimension Max. 5.0 4.0 6.2 0.51 H I J K L 1.75 0.25 Typ. 4.9 3.9 6.0 0.445 1.27 Min. 0.5 0.18 Typ. 0.715 0.254 0.22 Max. 0.83 0.25 4.8 3.8 5.8 0.38 0° 4° 8° 1.35 0.1 1.55 0.175 M N Jan-06-2005 5