P4404EDG

P4404EDG

  • 厂商:

    ETC2

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  • 描述:

    P4404EDG - P-Channel Logic Level Enhancement Mode Field Effect Transistor ( Preliminary ) - List of ...

  • 数据手册
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P4404EDG 数据手册
NIKO-SEM P-Channel Logic Level Enhancement Mode Field Effect Transistor ( Preliminary ) P4404EDG TO-252(DPAK) Lead-Free D PRODUCT SUMMARY V(BR)DSS -40V RDS(ON) 44mΩ ID -10A G S 1. GATE 2. DRAIN 3. SOURCE ABSOLUTE MAXIMUM RATINGS (TC = 25 °C Unless Otherwise Noted) PARAMETERS/TEST CONDITIONS Drain-Source Voltage Gate-Source Voltage Continuous Drain Current Pulsed Drain Current Power Dissipation 1 SYMBOL VDS VGS LIMITS -40 ± 20 -10 -8 UNITS V V TC = 25 °C TC = 70 °C ID IDM A -32 30 20 W TC = 25 °C TC = 70 °C PD Tj, Tstg TL Operating Junction & Storage Temperature Range Lead Temperature (1/16” from case for 10 sec.) THERMAL RESISTANCE RATINGS THERMAL RESISTANCE Junction-to-Case Junction-to-Ambient 1 2 -55 to 150 275 MAXIMUM 4.1 80 °C SYMBOL RθJc RθJA TYPICAL UNITS °C / W °C / W Pulse width limited by maximum junction temperature. Duty cycle ≤ 1% ELECTRICAL CHARACTERISTICS (TC = 25 °C, Unless Otherwise Noted) PARAMETER SYMBOL TEST CONDITIONS STATIC Drain-Source Breakdown Voltage Gate Threshold Voltage Gate-Body Leakage Zero Gate Voltage Drain Current On-State Drain Current 1 Drain-Source On-State Resistance1 V(BR)DSS VGS(th) IGSS IDSS ID(ON) RDS(ON) VGS = 0V, ID = -250µA VDS = VGS, ID = -250µA VDS = 0V, VGS = ± 20V VDS = -32V, VGS = 0V VDS = -30V, VGS = 0V, TJ = 125 °C VDS = -5V, VGS = -10V VGS = -4.5V, ID = -8A VGS = -10V, ID = -10A -32 57 38 68 44 -40 -1 -1.8 -3.0 ±250 1 10 A mΩ nA µA V LIMITS UNIT MIN TYP MAX JAN-17-2005 1 NIKO-SEM P-Channel Logic Level Enhancement Mode Field Effect Transistor ( Preliminary ) P4404EDG TO-252(DPAK) Lead-Free 11 S Forward Transconductance1 gfs VDS = -10V, ID = -10A DYNAMIC Input Capacitance Output Capacitance Reverse Transfer Capacitance Total Gate Charge 2 Ciss Coss Crss Qg Qgs Qgd 2 660 VGS = 0V, VDS = -10V, f = 1MHz 300 70 14 VDS = 0.5V (BR)DSS, VGS = -10V, ID = -10A 2.2 1.9 6.0 VDS = -20V, RL = 1Ω ID ≅ -1A, VGS = -10V, RGS = 6Ω 9.2 19.2 11.8 12.8 18.6 34.8 21.6 nS nC pF Gate-Source Charge2 Gate-Drain Charge2 Turn-On Delay Time Rise Time2 Turn-Off Delay Time2 Fall Time2 td(on) tr td(off) tf SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS (TC = 25 °C) Continuous Current Pulsed Current 3 IS ISM VSD trr Qrr IF = IS, VGS = 0V IF = -5 A, dlF/dt = 100A / µS 15.5 7.9 -10 -30 -1 A V nS nC Forward Voltage1 Reverse Recovery Time Reverse Recovery Charge 1 2 Pulse test : Pulse Width ≤ 300 µsec, Duty Cycle ≤ 2% . Independent of operating temperature. 3 Pulse width limited by maximum junction temperature. REMARK: THE PRODUCT MARKED WITH “P4404EDG”, DATE CODE or LOT # Orders for parts with Lead-Free plating can be placed using the PXXXXXXG parts name. JAN-17-2005 2 NIKO-SEM P-Channel Logic Level Enhancement Mode Field Effect Transistor ( Preliminary ) P4404EDG TO-252(DPAK) Lead-Free TYPICAL PERFORMANCE CHARACTERISTICS Body Diode Forward Voltage Variation with Source Current and Temperature 100 -Is - Reverse Drain Current(A) V GS = 0V 10 T A = 125°C 1 0.1 25°C -55°C 0.01 0.001 0 0.2 0.4 0.6 0.8 1.0 1.2 -VSD - Body Diode Forward Voltage(V) 1.4 JAN-17-2005 3 NIKO-SEM P-Channel Logic Level Enhancement Mode Field Effect Transistor ( Preliminary ) P4404EDG TO-252(DPAK) Lead-Free JAN-17-2005 4 NIKO-SEM P-Channel Logic Level Enhancement Mode Field Effect Transistor ( Preliminary ) P4404EDG TO-252(DPAK) Lead-Free TO-252 (DPAK) MECHANICAL DATA mm Dimension Min. A B C D E F G mm Dimension Max. 10.1 2.4 0.6 1.5 0.6 0.23 6.2 Typ. Min. H I J K L M N Typ. 0.8 Max. 9.35 2.2 0.48 0.89 0.45 0.03 6 6.4 5.2 0.6 0.64 4.4 6.6 5.4 1 0.9 4.6 A B C F H G L XXXXXXXXX NIKOS K M J I D E JAN-17-2005 5
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