RTD2513

Realtek RTD2523/2513 RTD2523/2513 Flat Panel Display Controller www.DataSheet4U.com Confidential Revision 0.18 March 19, 2004 Realtek Revision History Rev. 0.18 l l RTD2523/2513 Description Date March 2004 Pin-Description modification of TCON function in TTL output interface Explanation for register DV_Total www.DataSheet4U.com 2 Realtek 1. Features General l l l l l l l l Embedded dual DDC support DDC1, DDC2B, DDC/CI Zoom scaling up and down Embedded Pattern Generator No external memory required. Require only one crystal to generate all timing Embedded reset control output Embedded crystal output to MICROP 3 channels 8 bits PWM output, and selectable PWM clock frequency. RTD2523/2513 Color Processor l l l l Digital brightness and contrast adjustments sRGB compliance Gamma correction Dithering logic for 18-bit panel color depth enhancement Output Interface l l l l l l l l l Built-in display timing generator and fully programmable (RTD2523) 1 and 2-pixel/clock panel support and up to 140MHz (RTD2513) 1 and 2-pixel/clock panel support and up to 95MHz Scaler internal LSB/MSB swap, odd/even swap and red/blue group swap. Programmable TCON function support RSDS (Reduced Swing Differential Signaling) data bus type 1~3. Dual/Single LVDS interface output Reduced EMI and power saving feature Integrated Spread-Spectrum DCLK PLL. Analog RGB Input Interface l l l l l l Integrated 8-bit triple-channel 140MHz ADC/PLL Support up to 140MHz (SXGA@ 75Hz) Embedded programmable Schmitt trigger of HSYNC Support Sync On Green (SOG) and de-composite sync modes On-chip high-performance PLLs 32 phase APLL Digital Input Interface www.DataSheet4U.com Host Interface l l Support MCU serial bus interface Support MCU parallel bus interface l l Support 8-bit video (ITU 656) format input Built-in YUV to RGB color space converter & de-interlace DVI Compliant Digital Input Interface l l l Single link on-chip TMDS receiver Operation up to 165Mhz Direct connect to DVI compliant TMDS transmitter Embedded OSD l l l l l l l l l Embedded 11.25K SRAM dynamically stores OSD command and fonts Support multi-color RAM font, 1, 2 and 4-bit per pixel 16 color palette with 24bit true color selection Maximum 8 window with alpha-blending/ gradient/dynamic fade-in/fade-out, bordering/ shadow/3D window type Every window can place anywhere on the screen Rotary 90,180,270 degree Independent row shadowing/bordering Programmable blinking effects for each character OSD-made internal pattern generator for factory mode Support 12x18~4x18 proportional font Auto Detection /Auto Calibration l l l Input format detection Compatibility with standard VESA mode and support user-defined mode Smart engine for Phase and Image position calibration Scaling l l l l Fully programmable zoom ratios Independent horizontal/vertical scaling Advanced zoom algorithm provides high image quality Sharpness/Smooth filter enhancement l l l Power & Technology 2.5V/3.3V power supplier 0.25um CMOS process; 128-pin QFP package. 3 Realtek 2. RTD2523/2513 Pin-Out Diagram GNDK VC C K DDCSCL2 / TCON[5] DDCSDA2 / TCON[7] TCON[0] / VCLK / DCLK TCON[1] / V[7] /DENA TCON[5] / V[6] / DVS VCCIO GNDIO TCON[6] / V[5] DHS TCON[7] / V[4] TCON[8] / V[3] TCON[9] / V[2] TCON[10] / V[1] TCON[11] / V[0] TCON[12]/COUT/PW M2 REFCLK / PW M0 SC SB PVC C PGND A R 1N A R 1P A R 2N A R 2P A R 3N A R 3P RTD2523/2513 www.DataSheet4U.com ■:LVDS+RSDS+TTLO ■:RSDS+TTLO ■:TTLO (TCON) ADC_GND ADC_GND A D C _V D D AH S AVS GNDK VC C K DDCSCL / TCON[0] DDCSDA/TCON[1]/PW M1 GNDIO VCCIO S C LK TCON[2] /SDIO[3] / PW M2 TCON[3] / SDIO[2] TCON[4] / SDIO[1] SDIO[0] TCON[13] / COUT / PW M2 R ESET PGND PVC C B B 3P B B 3N B B 2P B B 2N B B 1P B B 1N 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 XO XI DPLL_GND DPLL_VDD APLL_VDD PLL_TST1 PLL_TST2 APLL_GND TMDS_TST/PWM1 TMDS_GND TMDS_VDD REXT TMDS_VDD RX2P RX2N TMDS_GND RX1P RX1N TMDS_VDD RX0P RX0N TMDS_GND RXCP RXCN TMDS_GND TMDS_VDD ADC_GND ADC_REFIO ADC_VDD B+ BADC_GND SOG G+ GADC_VDD R+ R- 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 RTD2523 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 AG1N AG1P AG2N AG2P VCCK GNDK PGND PVCC AG3N AG3P ACLKN ACLKP AB1N AB1P AB2N AB2P AB3N AB3P PGND PVCC BR1N BR1P BR2N BR2P BR3N BR3P BG1N BG1P BG2N BG2P PGND PVCC GNDK VCCK BG3N BG3P BCLKN BCLKP ■:TTLIO (TCON / VIDEO) ■:TTLIO (DDC / TCON) Figure 1 Pin-Out Diagram ( 6-bit Dual RSDS ) 4 Realtek (I/O Legend: A = Analog, I = Input, O = Output, P = Power, G = Ground) n ADC: 15 pins Name ADC_GND ADC_REFIO ADC_VDD BLUE+ BLUEADC_GND SOG/ADC_TEST GREEN+ GREENADCB_VDD RED+ REDADC_GND ADC_GND ADC_VDD AHS AVS I/O AG AP AP AI AI AG AIO AI AI AP AI AI AG AG AP AI AI Pin No 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 Description ADC ground ADC band-gap voltage de-coupling Analog power Analog input from BLUE channel Analog input ground from BLUE channel ADC ground SOG in/ADC test pin Analog input from GREEN channel Analog input ground from GREEN channel Analog power Analog input from RED channel Analog input ground from RED channel Analog ground Analog ground Analog power Analog HS input Analog VS input RTD2523/2513 Note 1.20V (3.3V) (3.3V) (3.3V) (10), (4), (5) (2), (4), (5) n www.DataSheet4U.com PLL: 8 pins Name XO XI DPLL_GND DPLL_VDD APLL_VDD PLL_TEST1 PLL_TEST2 APLL_GND I/O AI AO AG AP AP AIO AIO AG Pin No 1 2 3 4 5 6 7 8 Description Reference clock output Reference clock input Ground for digital PLL Power for digital PLL Power for multi-phase PLL Test Pin 1 / IRQ# Test Pin 2/Power-on-latch for crystal out Frequency Ground for multi-phase PLL Note (3.3V) (3.3V) 3.3V tolerance n Control Interface: 7 pins Name SDIO [0] SDIO [1] / TCON [4] / BBLU [0] SDIO [2] / TCON [3] / BBLU [1] SDIO [3] / PWM2 / TCON [2] SCLK SCSB RESET I/O IO IO IO IO I I O Pin No 54 53 52 51 50 111 56 Description Serial control I/F data in / Parallel port data [0] Parallel port data [1] / TCON [4] / TTL BBLU [0] Parallel port data [2] / TCON [3] / TTL BBLU [1] Parallel port data [1] / TCON [4] / PWM2 Serial control I/F clock Serial control I/F chip select RESET output for Micron Note (2), (3), / 2mA (1), (2), (3), / 2mA (1), (2), (3), / 2mA (1), (2), (3), / 2mA (2), (3), (5) (2), (3), (5) (2), (5), (6) / 2mA 5 Realtek n Pin NO . 51 6-bits Dual RSDS S[3] / TCON[2] / PWM2 S[2] / TCON[3] S[1] / TCON[4] PWM2 / COUT / TCON[13] BB3P BB3N BB2P BB2N BB1P BB1N BCLKP BCLKN BG3P BG3N BG2P BG2N BG1P BG1N BR3P BR3N BR2P BR2N BR1P BR1N AB3P AB3N 6 bits Single RSDS S[3] / TCON[2] / PWM2 S[2] / TCON[3] S[1] / TCON[4] PWM2 / COUT / TCON[13] BB3P BB3N BB2P BB2N BB1P BB1N BCLKP BCLKN BG3P BG3N RTD2523/2513 Display & TCON/VIDEO-8 Port: 54 pins ■ :LVDS+RSDS+TTLO ■:RSDS+TTLO ■:RSDS+TTLIO■:TTLO ■:TTLIO 8/6 bits Dual/Single LVDS S[3] / TCON[2] / PWM2 S[2] / TCON[3] S[1] / TCON[4] PWM2 / COUT / TCON[13] NC NC NC NC NC NC NC NC NC NC TODP TODN TOCLKP TOCLKN TOCP TOCN TOBP TOBP TOAP TOAP TEDP TEDN 8 bits Dual/Single TTL S[3] / TCON[2] / PWM2 S[2] /BBLU[1] / TCON[3] S[1]/ BBLU[0] / TCON[4] PWM2 / COUT / TCON[13] BBLU [7] BBLU [6] BBLU [5] BBLU [4] BBLU [3]/T0 BBLU [2] / T1 BGRN [1] / T2 BGRN [0] / T3 BGRN[7] BGRN[6] BGRN [5] / T4 BGRN [4] / T5 BGRN [3] / T6 BGRN [2] / T7 BRED [7] / T8 BRED [6] / T9 BRED [5] / T10 BRED [4] / T11 BRED [3] / T12 BRED [2] / T13 ABLU [7] / T14 ABLU [6] / T15 6 bits Dual TTL S[3] / TCON[2] / PWM2 S[2] / TCON[3] S[1] / TCON[4] PWM2 / COUT / TCON[13] BBLU [7] BBLU [6] BBLU [5] BBLU [4] BBLU [3] BBLU [2] TCON [6] TCON [5] BGRN [7] BGRN [6] BGRN [5] BGRN [4] BGRN [3] BGRN [2] BRED [7] BRED [6] BRED [5] BRED [4] BRED [3] BRED [2] ABLU [7] ABLU [6] 6 bits Single TTL S[3] / TCON[2] / PWM2 S[2] / TCON[3] S[1] / TCON[4] PWM2 / COUT / TCON[13] BBLU [7] BBLU [6] BBLU [5] BBLU [4] BBLU [3] BBLU [2] TCON [6] TCON [5] BGRN [7] BGRN [6] BGRN [5] BGRN [4] BGRN [3] BGRN [2] BRED [7] BRED [6] BRED [5] BRED [4] BRED [3] BRED [2] ABLU [7] ABLU [6] Note (1), (2), (3)/ 2mA (1), (2), (3)/ 2mA (1), (2), (3)/ 2mA (1), (2), (3)/ 2mA 52 53 55 59 60 61 62 63 64 65 www.DataSheet4U.com 66 67 68 73 74 75 76 77 78 79 80 81 82 85 86 BG2P BG2N BG1P BG1N BR3P BR3N BR2P BR2N BR1P BR1N NC NC 6 Realtek 87 88 89 90 91 92 93 94 99 100 101 102 103 104 www.DataSheet4U.com RTD2523/2513 NC NC NC NC NC NC NC NC TCON [11] TCON [10] TCON [9] TCON [8] TCON [7] TCON [6] TCON [5] TCON [1] TCON [0] NC PWM2 / COUT / TCON[12] V [0] V [1] V [2] V [3] V [4] V [5] V [6] V [7] VCLK TECLKP TECLKN TECP TECN TEBP TEBN TEAP TEAN NC NC NC NC NC NC NC NC NC NC PWM2 / COUT / TCON[12] V [0] V [1] V [2] V [3] V [4] V [5] V [6] V [7] VCLK ABLU [5] / T16 ABLU [4] / T17 ABLU [3] / T18 ABLU [2] / T19 ABLU [1] / T20 ABLU [0] / T21 AGRN [7] / T22 AGRN [6] / T23 AGRN [5] / T24 AGRN [4] / T25 AGRN [3] / T26 AGRN [2] / T27 ARED [7] / T28 ARED [6] / T29 ARED [5] / TH ARED [4] / TV ARED [3] / TE ARED [2] / TK ARED [1] ABLU [5] ABLU [4] ABLU [3] ABLU [2] TCON [1] TCON [0] AGRN [7] AGRN [6] AGRN [5] AGRN [4] AGRN [3] AGRN [2] ARED [7] ARED [6] ARED [5] ARED [4] ARED [3] ARED [2] COUT ABLU [5] ABLU [4] ABLU [3] ABLU [2] TCON [1] TCON [0] AGRN [7] AGRN [6] AGRN [5] AGRN [4] AGRN [3] AGRN [2] ARED [7] ARED [6] ARED [5] ARED [4] ARED [3] ARED [2] PWM2 / COUT / TCON[12] TCON [11] TCON [10] TCON [9] TCON [8] TCON [7] DHS DVS DENA DCLK DHS DVS DENA DCLK (9) AB2P AB2N AB1P AB1N ACLKP ACLKN AG3P AG3N AG2P AG2N AG1P AG1N AR3P AR3N AR2P AR2N AR1P AR1N PWM2 / COUT / TCON[12] TCON [11] /V[0] TCON [10] /V[1] TCON [9] / V[2] TCON [8] / V[3] TCON [7] / V[4] TCON [6] / V[5] TCON [5] / V[6] TCON [1] / V[7] TCON [0] / VCLK 105 106 107 108 113 114 115 116 117 118 119 122 123 124 ARED [0] BRED [1] BRED [0] AGRN [1] AGRN [0] DHS DVS DENA DCLK (1), (7), (8) (1), (7), (8) (1), (7), (8) (1), (7), (8) (1), (7), (8) (1), (7), (8) (1), (7), (8) (1), (7), (8) (1), (7), (8) 7 Realtek RTD2523/2513 * Single RSDS, even/odd swap, data(59~82) output to pin85~108, TCON(99~108) output to pin59~68. * In 6-bit dual TTL output mode, Video8 cannot output TCON7~TCON11; while video8 can output TCON in 6-bit single TTL mode. n TMDS: 18 pins Name TMDS_TST/ PWM1 TMDS_GND TMDS_VDD EXT_RES TMDS_VDD RX2P RX2N TMDS_GND RX1P RX1N TMDS_VDD RX0P RX0N TMDS_GND RXCP RXCN TMDS_GND TMDS_VDD I/O AIO G P A P I I G I I P I I G I I G P Pin No 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Description TMDS_TEST Pin / PWM1 / Power-on-latch for serial / parallel port Note (3.3V) Impedance Match Reference. (3.3V) Differential Data Input Differential Data Input Differential Data Input Differential Data Input (3.3V) Differential Data Input Differential Data Input Differential Data Input Differential Data Input (3.3V) www.DataSheet4U.com n PWM Interface: (PWM1, PWM2 can be selected from 1 of 3 possible pins.) Name PWM2 / TCON [2] / S [3] PWM2 / TCON [13] / COUT PWM2 / TCON [12] / COUT PWM1 / TMDS_TST PWM1 / DDCSDA / TCON [1] / BBLU [0] PWM1 / DDCSDA2 / TCON [7] PWM0 / REFCLK I/O O O O Pin No 51 55 113 Description PWM2 / TCON [2] / SDIO [3] PWM2 / TCON [13] / Crystal out PWM2 / TCON [12] / Crystal out Note (1), (2), (3), (5), (8), (2), (8), (9) (2), (8), (9) 6bit dual TTL cannot support (2), (7), (8) (1), (2), (3), (5), (8), (1), (2), (3), (5), (8), (2), (9) AIO IO IO IO 9 47 125 112 PWM1/ TMDS_TEST Pin / Power-on-latch for serial / parallel port PWM1 / DDC serial control I/F data input / output / TCON [4] PWM1 / DDC serial control I/F data input / output / TCON [7] PWM0 / (In / out) test pin for DCLK / Video8 even-odd signal n DDC Channel: 4 pins Name DDCSCL / TCON [0] / BBLU [1] DDCSDA / TCON [1] / PWM1 / BBLU [0] DDCSCL2 / TCON [5] DDCSDA2 / TCON [7] /PWM1 I/O I IO I IO Pin No 46 47 126 125 Description DDC serial control I/F clock / TCON [0] / TTL BBLU [1] DDC serial control I/F data input / output / TCON [1] / PWM1 / TTL BBLU [0] DDC serial control I/F clock / TCON [5] DDC serial control I/F data input / output / TCON [7] / PWM1 Note (2), (3), (5) (1), (2), (3), (5), (6), (8)/ 8mA /no slew (2), (3), (5) (1), (2), (3), (5), (6), (8)/ 8mA /no slew 8 Realtek n Power & Ground: 22 pins Name I/O Pin No 3.3V Power P 49,121 VCCIO: 2 G 3.3V Ground 48,120 GNDIO: 2 P 3.3V Power 58,71,83,95,110 PVCC: 5 G 3.3V Ground 57,72,84,96,109 PGND: 5 2.5V Power P 45,69,98,127 VCCK: 4 G 2.5V Ground 44,70,97,128 GNDK: 4 Note: (1) TTL compatible CMOS Input (Vt=1.7V); VCC=3.3V; (2) 5V tolerance pad; (3) Internal 75K Ohms pull high resistor. (4) Internal 75K Ohms pull low resistor. (5) Schmitt trigger CMOS Input (Vt=1.4-~2.2V); (6) Open-Drain, Output Drive low & Pull-high. (7) Bi-directional input/output (8) Programmable driving current (2~10mA) (9) TTL output 5V & 3.3V (10) 4V tolerance pad RTD2523/2513 Description www.DataSheet4U.com 9 Realtek 3. General Description DDC TCON 5C 48D RTD2523 Flat Panel Display RTD2523/2513 VS HS R/G/B Rx0~2 RxC Video Decoder 1C 8D 24.576MHz Parallel Port LCD Panel Row/Column Driver 5C 48D TTL Signal LCD Panel 48D 5C 20 RSDS Signal LCD Panel Reset 24.576MHz IIC MCU LVDS Signal LCD Panel Figure 2 Application System Block Diagram www.DataSheet4U.com Analog RGB Digital DVI ITU-656 Triple-ADC FIFO TMDS/ HDCP Color Conversion Timing Control Panel Driver HS & VS Sync Processor Control Register Scaling Up Build-In OSD PLL 24.576MHz Color Processing OSD MUX Panel MCU Figure 3 Chip Functional Block Diagram 10 Realtek 4. Functional Description 4.1 Input RTD2523/2513 Digital Input (ITU 656) RTD is designed to connect the interface of digital signal from video decoder. Input data is latched within a capture window defined in registers. The timing scheme designed for input devices are showed in the following diagram. There are not H sync 、 V sync signals provided by the video decoder with ITU BT.656, these synchronal signals have to be generated by decoding the EAV & SAV timing reference signals. VGBCLK VGB_R(Byte) xxx U0 Y0 V0 Y1 U2 Figure 4 Input YUV 4:2:2(8-bits) Timing Only 254 of possible 256 8-bit words may be used to express a signal value, 0 and 255 are reserved for data identification purposes. Video 8 data stream is as below: Blanking Timing reference 720 pixels YUV 422 DATA period code … 80 10 FF 00 00 SAV Cb0 Y0 Cr0 Y1 Cb2 Y2 … Cbn: U(B-Y) colour difference component Yn : luminance component Crn: V(R-Y) colour difference component Timing reference Blanking code period Cr718 Y719 FF 00 00 EAV 80 10 … www.DataSheet4U.com SAV/EAV format Bit 7 Bit 6(F) 1 Field bit 1st field F=0 2nd field F=1 Bit 5(V) Bit 4(H) Bit 3(P3) Bit 2(P2) Bit 1(P1) Bit 0(P0) Vertical blanking bit V=1 H=0 in SAV Protection bits Active video V=0 H=1 in EAV Hardware can recognize the occurrence of EAV & SAV by detecting the 0xff , 0x00 , 0x00 data sequence, and then generate the Hsync、Vsync、Field signals internally by decoding the fourth word of the timing reference signal(EAV、SAV). F & V change state synchronously with the EAV(End of active video) reference code at the beginning of the digital line. Bits P0, P1, P2, P3, have states dependent on the states of the bits F, V and H as shown below. At the receiver this permits one-bit errors to be corrected and two-bits errors to be detected. 11 Realtek RTD2523/2513 Error correction A = P1 xor F xor V B = P2 xor F xor H C = P3 xor V xor H D = F xor V xor H xor P3 xor P2 xor P1 xor P0 F’ = F xor (D．A ．B．C# ) V’ = V xor (D．A．B#．C) H’ = H xor (D．A#．B．C) SAV/EAV one-bit error occurs when D．(A + B + C) SAV/EAV two-bit error occurs when D#．(A + B + C) www.DataSheet4U.com Analog Input RTD integrates three ADC’ (analog-to-digital converters), one for each color (red, green, and blue). s The sync-processor can deal with Separate-Sync, Composite-Sync, and Sync-On-Green. And the PLL can generate very low jitter clock from HS to sample the analog signal to digital data. Input data is latched within a capture window defined in registers refer to VS and HS leading edge. TMDS Input RTD integrates high-speed single link receiver. It can operate up to 165Mhz. Input Capture Window Inside RTD, there are four registers IPH_ACT_STA, IPH_ACT_WID, IPV_ACT_STA & IPV_ACT_LEN to define input capture window for the selected input video on either A or B input port while programmed analog input mode. The horizontal sync (IHS) & vertical sync (IVS) signals are used from the selected port to determine the capture window region. 12 Realtek IHS IVS RTD2523/2513 Vertical blanking region (back porch) IPV_ACT_STA IPV_ACT_LEN Input Capture Window Horizontal blanking region (back porch) Horizontal blanking region (front porch) Vertical blanking region (front porch) www.DataSheet4U.com IPH_ACT_STA IPH_ACT_WID Figure 5 Input Capture Window 13 Realtek 4.2 Output Timing RTD2523/2513 Display Output Timing The display output port sends single/double pixel data transfer and synchronized display timing to an external device. The display port also support display panel with 6-bit per color, turn on the dithering function to enhance color depth. In single pixel output mode, single pixel data (24-bit RGB) is transferred to display port A on each active edge of DCLK, the rate of DCLK is also equal to display pixel clock. The sync & enable signals are also sent to display port on each active edge of DCLK. Seeing figure13 as below In double pixel output mode, double pixel data (48-bit RGB) is transferred to display port A & B on each active edge of DCLK and the rate of DCLK is equal to half display pixel clock at this moment. The sync & enable signals are also sent to display port on each active edge of DCLK. Seeing figure14 as below. DCLK DEN DA/RGB www.DataSheet4U.com xxx rgb0 rgb1 rgb2 rgb3 rgb4 rgb5 DB/RGB xxx Figure 6 Single Pixel Mode Display Data Timing DHCLK DEN DA/RGB DB/RGB xxx rgb0 rgb2 rgb4 rgb6 rgb8 rgb10 xxx rgb1 rgb3 rgb5 rgb7 rgb9 rgb11 Figure 7 Double Pixel Mode Display Data Timing 14 Realtek RTD2523/2513 Display Active Window These registers to define the display active window are showed us below in application with frame buffer. In the case of without frame buffer that means frame sync mode, the definitions of these registers are quiet different from the description below. There are two frame sync modes applied to RTD chip for various applications. Refer to the register description for detailed. DHS DEN DVS DV_VS_END Vertical blanking region (back porch) DV_BKGD_STA Background Region DV_ACT_STA www.DataSheet4U.com Display Active Window Horizontal blanking region (back porch) DV_ACT_END DV_BKGD_END Vertical blanking region (front porch) Horizontal blanking region (front porch) DV_TOTAL DH_HS_END DH_BKGD_STA DH_ACT_STA DH_ACT_END DH_BKGD_END DH_TOTAL Figure 8 Display Active Window Diagram 15 Realtek 4.3 Color Processing RTD2523/2513 Digital color R & G & B independent channel contrast & brightness controls are built in RTD. The contrast control is performed a multiply value from 0/128, 1/128, 2/128… to 255/128 for each R/G/B channel. The brightness control is used to set an offset value from –128 to +127 also for each R/G/B channel. Scaled RGB X + Gamma Correction To Dithering Contrast (0~2) Brightness (-128~127) Figure 9 Brightness, Contrast & Gamma Correction block diagram 4.4 OSD & Color LUT Build-In OSD The detailed function-description of build-in OSD, please refer to the application note for RTD embedded OSD. www.DataSheet4U.com Color LUT & Overlay Port The following diagram presents the data flow among the gamma correction, dithering, overlay MUX, OSD LUT and output format conversion blocks. 24 Gamma Correction 24 Dithering 24 Output Format Conversion Internal OSD Background Color 4 24/48 MUX 4 4 16x24 color look-up table 24 CR38 Figure 10 OSD color look-up table data path diagram 16 Realtek 4.5 Auto-Adjustment RTD2523/2513 There are two main independent auto-adjustment functions supported by RTD, including auto-position & auto-tracking. The operation procedure is as following; Auto-Position 1. Define the RGB color noise margin (7B,7C,7D): When the value of color channel R or G or B is greater than these noise margins, a valid pixel is found. 2. Define the threshold-pixel for vertical boundary search (7C[1:0]). 3. Define the boundary window of searching (75 ~ 7A) for horizontal boundary search. 4. Start auto-function (7F[0]) . 5. The result can be read from register (80 ~ 87). Auto-Tracking 1. Setting the control-registers (7F) for the function (auto-phase, auto-balance) according to the Control-Table. 2. Define the Diff-Threshold (7E). 3. Define the boundary window of searching (75 ~ 7A) for tracking window. 4. Start auto-function (7F[0]) . 5. The result can be read from register (88 ~ 8B). 4.6 PLL System Inside the RTD, there are three PLL systems for display clock and ADC sample clock. www.DataSheet4U.com DCLK PLL PLL provides a wide range of user-programmable frequency synthesis options, and the formula as following; The frequency before VCO_Divide must be 50MHz~450MHz. DCLK = Fin * DPM / DPN / VCO_Divide, Meanwhile, Fin = 24.576MHz, the DPLL_M[7:0] & DPLL_N[5:0] are the 8-bit M & 6-bit N value of DCLK. DPM=DPLL_M[7:0]+2, DPN=DPLL_N[5:0]+2. Of course, you can force this clock from external oscillators through pins REFCLK for your own applications. Control Bit1 REFCLK1 Internal CLK CLK PLL Control Bit0 Figure 11 PLL System Control Diagram Spread-Spectrum function is also build in DCLK to reduce EMI while using TCON. You can control the SSP_I, SSP_W, and FMDIV to fine-tune the EMI. 17 Realtek 4.7 Host Interface RTD2523/2513 Serial Port: Any transaction should start from asserted the SCS# and stop after de-asserted the SCS#. Within this period, any data are driving by clock rising edge and latched by clock falling edge. The detailed timing diagrams are as following; R/W : 0 - Write INC : 0 - Address Auto-Inc A0 ~ A7 SCLK SCSB SDIO D0 ~ D7 STOP A A A A A A A A R IN D D D D D D D D D D D D D D D D D D D D D D D D 0 1 2 3 4 5 6 7 WC 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 Address www.DataSheet4U.com Data0 Data1 Data2 Address: A0~A7 R/W: Read/Write Mode for Data Phase, 0 -- Write, 1 -- Read INC: Address Auto-Increasing Mode, 0 -- enable auto-increasing, 1 -- disable Figure 12 Serial Port Write Timing & Data Format R/W : 1 - Read INC : 1 - Non-Address Auto-Inc A0 ~ A7 SCLK SCSB SDIO STOP D0 ~ D7 Figure 13 Serial Port Read Timing 18 Realtek Parallel Port: RTD2523/2513 After RESET end, the status of pin 9 (TMDS_TST) can be sensed to determine the interface mode: highà parallel port, lowà serial port. Reset end 3.3V SENSE RESET_IN 3.3V TMDS_TST 0V SENSE Figure 15 Serial Port / Parallel Port Select Serial port Parallel port The 4-bit parallel port works just like our serial port. The biggest difference is that the address part needs 3 clocks but data 2. All the other definitions like “R/W”, “INC” and “STOP” are the same with the serial port. The detailed timing diagrams are as following; www.DataSheet4U.com Address SCLK SCSB SDIO [3:0] SDIO [0] SDIO [1] SDIO [2] SDIO [3] Data 0 Data 1 Data 2 A [0] A [4] R/W D0 [0] D0 [4] D1 [0] D1 [4] D2 [0] D2 [4] A [1] A [5] A [2] A [6] A [3] A [7] INC D0 [1] D0 [5] D1 [1] D1 [5] D2 [1] D2 [5] X X D0 [2] D0 [6] D1 [2] D1 [6] D2 [2] D2 [6] D0 [3] D0 [7] D1 [3] D1 [7] D2 [3] D2 [7] 1 1 1 1 Figure 16 Parallel Port Timing 19 Realtek 4.8 Reset Output RTD2523/2513 We have the RESET_OUT function, and also reserve the RESET_IN function. By the bounding of internal pins we can select three kinds of reset function. First of all is only reset-out, we can output the reset signal to microns, and the micron can reset the RTD by firmware. The second choice is only reset-in, the RTD can be reset by input signal or also firmware. The last is RTD output reset and also reset itself. Noticed that the reset output is positive polarity, the reset in is negative polarity. Besides, the reset output is open-drain pin. The reset function operating voltage is determined by ADC_VDD voltage. The negative threshold voltage is 1.8V at power-on status, but it can be programmed by registers to be 1.8V, 2.0V, 2.2V and 2.4V after power on. The registers are 0xEB [7:6] Die RESET_OU T Die RESET_OU T Die RESET_OU T RESETB RESETB RESETB Package RESET_IN Package RESET_IN Package RESET_IN Figure 17 Three kinds of RESET function www.DataSheet4U.com For the reset-out function, the characteristics are below: Parameter Symbol Min. Typ. Detection Voltage -Vdet 1.8 2.4 Release Voltage +Vdet 2.6 Delay Time td 50 +3.3V +Vdet -Vdet Max. Unit V V ms +5V td RESET_OUT Figure 18 The RESET_OUT Timing Diagram 20 Realtek 4.9 The Programmable Schmitt Trigger of HSYNC RTD2523/2513 To get better waveform of the input HSYNC, we have a programmable Schmitt Trigger circuit. For different HSYNC amplitude and polarity, we can select different setting of the threshold voltage. The Vt+ and the Vt- can be selected by register 0xED. We can select the old mode or the new mode. When using the new mode we can directly determine the positive threshold voltage (1.4V, 1.6V… 2.6V), and we can choose the distance from the Vt+ to determine the Vt- (0.6V, 0.8V, 1.0V, 1.2V). We also can finely tune the voltage by minus 0.1V. For application, we can select different threshold voltage by the polarity of the HSYNC. The control register is 0xED. Input HSYNC Vt + Vt- Output HSYNC www.DataSheet4U.com Figure 18 The Schmitt Trigger Behavior Diagram 4.10 Crystal Frequency Output RTD can output crystal frequency or half crystal frequency to external MCU to save a crystal device. After power on, RTD latch the state of PLL_TEST2 pin to determine which frequency to output, and the result shows in TCON register address 0x00[0]. 0 is for half of crystal frequency and 1 is for crystal frequency. When power on, crystal frequency output to TCON12 and TCON13. Hence, crystal-in pin of external MCU can connect to TCON12 or TCON13. Firmware can turn off the signal output of other pin, and the control register is in TCON register 0x00[1] and 0x00[2]. 4.11 Pin Out Configuration RTD supports TTL, LVDS and RSDS output interface. After power on, display port is high impedance. Firmware can set its control register in TCON address 0x03[7:6] to select output interface. Refer to Pin Out Diagram for output pin definition. RSDS interface 21 Realtek RTD2523/2513 For dual RSDS output interface, set 2’b11 to “Display Port Configuration” in TCON 0x03[7:6], 1’b1 to “Display 18 bit RGB Mode Enable” in 0x20[4], and 1’b1 to “Display Output Double-Width Pixel Enable” in 0x20[2]. “Display Even/Odd Data Swap” in 0x21[7] can swap even pixel and odd pixel output to RSDS A Port and RSDS B Port. “Display Red/Blue Data Swap” in 0x21[6] can swap red-channel data and blue-channel data. “Display MSB/LSB Data Swap” in 0x21[5] can swap bit order between “bit7, 6, 5, 4, 3, 2” and “bit2, 3, 4, 5, 6, 7”. “RSDS Green / Clock Pair Swap” in TCON 0x03[5] can swap three green pair and clock pair order between “G1, G2, G3, CLOCK” and “CLOCK, G1, G2, G3”. “RSDS High/Low Bit Swap (data)” in TCON 0x03[1] can swap bit order in one data pair. “RSDS Differential pair PN swap (data)” in TCON 0x03[0] can swap differential positive and negative pin. TCON signal shares pin with parallel access port, PWM, crystal frequency output, video port and DDC channel. www.DataSheet4U.com For single RSDS output interface, set 2’b11 to “Display Port Configuration” in TCON 0x03[7:6], 1’b1 to “Display 18 bit RGB Mode Enable” in 0x20[4], and 1’b0 to “Display Output Double-Width Pixel Enable” in 0x20[2]. “Display Red/Blue Data Swap” in 0x21[6] can swap red-channel data and blue-channel data. “Display MSB/LSB Data Swap” in 0x21[5] can swap bit order between “bit7, 6, 5, 4, 3, 2” and “bit2, 3, 4, 5, 6, 7”. “RSDS Green / Clock Pair Swap” in TCON 0x03[5] can swap three green pair and clock pair order between “G1, G2, G3, CLOCK” and “CLOCK, G1, G2, G3”. “RSDS High/Low Bit Swap (data)” in TCON 0x03[1] can swap bit order in one data pair. “RSDS Differential pair PN swap (data)” in TCON 0x03[0] can swap differential positive and negative pin. TCON11, 10, 9, 8, 7, 6, 5, 1, 0 use dedicated pin and output to pin 99~107. Video input port also has dedicated pin. LVDS interface For single/dual LVDS output interface, set 2’b10 to “Display Port Configuration” in TCON 0x03[7:6]. “Display 18 bit RGB Mode Enable” in 0x20[4] determines 6bits or 8bits data output per channel. “Display Output Double-Width Pixel Enable” in 0x20[2] determines one pixel or two pixels output per display clock. “Display Even/Odd Data Swap” in 0x21[7] swap Even port and Odd port data when output double-width pixel enable, and determine output to Even port or Odd port in output single-width pixel mode. “Display Red/Blue Data Swap” in 0x21[6] can swap red-channel data and blue-channel data. Set “Bit-Mapping Table Select” in 0xC2[0] 0 for 8bit LVDS output interface and 1 for 6bit LVDS output interface. TTL interface For 8bit TTL output interface, set 2’b10 to “Display Port Configuration” in TCON 0x03[7:6], 1’b0 to “Display 18 bit RGB Mode Enable” in 0x20[4]. “Display Output Double-Width Pixel Enable” in 0x20[2] determines one pixel or two pixels output per display clock. “Display Even/Odd Data Swap” in 0x21[7] swaps A port and B port data when output double-width pixel enable, and determine output to A port or B port in output single-width pixel mode. “Display Red/Blue Data Swap” in 0x21[6] can swap red-channel data and blue-channel data. “Display MSB/LSB Data Swap” in 0x21[5] can swap bit order between “bit7, 6, 5, 4, 3, 2, 1, 0” and “bit0, 1, 2, 3, 4, 5, 6, 7”. “TTL Display B port Blue [1:0] Location” in TCON register 0x04[4] select where B port 22 Realtek RTD2523/2513 Blue[1:0] output to. If Blue[1:0] output to pin 52&53, RTD must work on serial port access mode. If Blue[1:0] output to pin 46&47, ADC_DDC must be disabled. For 6bit TTL output interface, LSB 2bit of TTL 8bit output is not necessary, and it is used as TCON signal. TCON Due to the limitation of pin count, TCON shares pins with other signals. Refer to “Display & TCON / Video-8 Port” in the pin definition for TCON configuration. The configuration is in TCON Control Register. 4.12 Display Clock DPLL DPLL frequency = F_IN * DPM / DPN * Divider. F_IN is input crystal frequency. DPM and DPN is in 0xD1[7:0] and 0xD2[3:0]. Divider is in 0xD2[7:6], and it divide PLL frequency by 1, 2, 4 or 8. According to parameter DPN, you must set LPF Mode in 0xD3[2]. If LPF Mode is 1, the charge pump current, Ich, must be DPM/17.6, while Ich must be DPM/1.67 if LPF Mode is 0. The charge pump current Ich is in 0xD0[0,7:3]. www.DataSheet4U.com Offset Frequency The resolution of DPLL frequency from DPM and DPN factor might be not fine enough. Setting DCLK Offset[11:0] can fine tune DPLL close to target frequency. Employing spread spectrum can fine tune DPLL frequency. “Enable DDS Spread Spectrum Output Enable” in register 0x5A[3] allows DDS to output spread spectrum control signal, and “DPLL Spread Spectrum Enable” in 0xD2[5] allows DPLL to receive control signal. “Offset Frequency Direction Induced by Spread Spectrum” in 0xD2[4] controls the direction of offset frequency. “DCLK Offset[11:0]” in 0x9A and 0x9B[3:0] determines the magnitude of offset frequency. Every step of offset frequency is DCLK*2^(-15). In interlaced mode, odd field and even field have different period. Setting 0x9B[6] and 0x9B[4] can enable offset frequency function only in even filed or odd field. Spread Spectrum Spread spectrum can distribute the radiation energy to a band and reduce EMI. “DCLK Spreading Range” in 0x99[7:4] control spread spectrum range of 0~7.5% (peak-to-peak). “Spread Spectrum FMDIV” in 0x99[3] control spreading frequency 33k or 66kHz. Fixed the Number of DCLK in a Frame “Enable the Fixed DVTOTAL & Last Line Length” in 0x5A[4] makes there are fixed DVTOTAL and Last Line Length in every frame. Fixed Last Line Length[10:0] is in 0x59 and 23 Realtek RTD2523/2513 0x5A[2:0], and DVTOTAL[10:0] is in register 0x97 and 0x98[2:0]. Output frame is synchronized with input frame by selecting higher-frequency DCLK and lower-frequency DCLK – N*dF according to the position of Display VS leading edge. N is controlled in register 0x99[1:0] and dF is DCLK*2^(-15). www.DataSheet4U.com 24 Realtek Registers Description Reading unimplemented registers will return 0. Address: 00 ID_REG Bit Mode 7:0 R MSB 4 bits: 1000 product code LSB 4 bits: 0001 rev. code RTD2523/2513 Default: 81h Function www.DataSheet4U.com Address: 01 STATUS (Status Register) Default: 00h Function Bit Mode 7 R ADC_PLL Non-Lock: If the ADC_PLL non-lock occurs, this bit is set to “1”. 6 R Input VSYNC Error If the input vertical sync occurs within the programmed active period, this bit is set to “1”. 5 R Input HSYNC Error If the input horizontal sync occurs within the programmed active period, this bit is set to “1”. 4 R Input ODD Toggle Occur If the ODD signal(from SAV/EAV) toggle occurs, this bit is set to “1”. 3 R Video-8 Input Vertical Sync Occurs If the YUV input vertical sync edge occurs, this bit is set to “1”. 2 R ADC Input Vertical Sync Occurs If the RGB input vertical sync edge occurs, this bit is set to “1”. 1 R Input Overflow Status (Frame Sync Mode) If an overflow in the input data capture buffer occurs, this bit is set to “1”. 0 R Line Buffer Underflow status (Frame Sync Mode) If an underflow in the line-buffer occurs, this bit is set to “1”. Write to clear status. 25 Realtek Address: 02 HOSTCTRL Bit Mode Function 7 R Display Support 0: XGA (RTD2513/2013) 1: SXGA (RTD2523/2023) 6:5 --Reserved 4 R/W SOG_Mode 0: DC-offset, using POLY R 1: DC-offset, using MOS R 3 --Reserved 2 R/W Power Down Mode Enable 0: Normal 1: Enable power down mode 1 R/W Power Saving Mode Enable (except sync processor & serial port): 0: Normal 1: Enable power saving mode 0 R/W Reset Whole Chip (Low pulse at least 8ms): 0: Normal 1: Enable reset Address: 03 IRQ_CTRL0 (IRQ Control Register 0) Function Bit Mode 7 R/W IRQ (ADC_PLL Non-Lock) 0: Disable the ADC_PLL non-lock error event as an interrupt source 1: Enable the ADC_PLL non-lock error event as an interrupt source 6 R/W IRQ (Input VSYNC Error) 0: Disable the Input VSYNC error event as an interrupt source 1: Enable the Input VSYNC error event as an interrupt source 5 R/W IRQ (Input HSYNC Error) 0: Disable the Input HSYNC error event as an interrupt source 1: Enable the Input HSYNC error event as an interrupt source 4 R/W IRQ (Input ODD Toggle Occur) 0: Disable the Input ODD toggle event as an interrupt source 1: Enable the Input ODD toggle event as an interrupt source 3 R/W IRQ (Video-8 Input Vertical Sync Occurs) 0: Disable the B-port (VGB) Input VSync event as an interrupt source 1: Enable the B-port (VGB) Input VSync event as an interrupt source 2 R/W IRQ (ADC Input Vertical Sync Occurs) 0: Disable the A-port (VGA) Input VSync event as an interrupt source 1: Enable the A-port (VGA) Input VSync event as an interrupt source 1 R/W IRQ (Input Overflow Status) 0: Disable the Input Buffer overflow event as an interrupt source 1: Enable the Input Buffer overflow event as an interrupt source 0 R/W IRQ (Line Buffer Underflow status) 0: Disable the Line Buffer underflow event as an interrupt source 1: Enable the Line Buffer underflow event as an interrupt source RTD2523/2513 Default: 02h Default: 00h www.DataSheet4U.com 26 Realtek Input Video Capture a. Capture Format RTD2523/2513 www.DataSheet4U.com Address: 04 VGIP_CTRL (Video Graphic Input Control Register) Default: 00h Bit Mode Function 7 R/W Vertical Scale-Down Compensation 0: disable 1: enable 6 R/W Horizontal Scale-Down Compensation 0: disable 1: enable 5 R/W Input Test Mode: 0: Normal 1: Video8 input will go through RGB channel, AVS=>IVS, AHS=>IHS, VCLK=>ICLK 4:2 R/W Input Pixel Format 000: From Embedded ADC 001: Reserved 010: Low Speed Input (00=>11(from fastest to slowest) 00: defalut, each stage=>~0.25ns Address: 3A DIS_TIMING (Display Clock Fine Tuning Register) Bit Mode Function 7 R/W YUV-to-RGB Color Space Conversion Test Mode: 0: Normal 1: Direct output conversion result to display port 6 R/W Internal OSD Port Latch Clock Delay 0: normal 1: 1ns delay 5 R/W Force Display Timing Generator Enable: 0: wait for input VS trigger 1: force enable 4 --Reserved 3 R/W Display Output Clock Coarse Tuning Control: 0: Disable 1: 8ns delay 2:0 R/W Display Output Clock Fine Tuning Control: 000: DCLK rising edge correspondents with output display data 001: 1ns delay 010: 2ns delay 011: 3ns delay 100: 4ns delay 101: 5ns delay 110: 6ns delay 111: 7ns delay RTD2523/2513 Default: 00h Default: 00h www.DataSheet4U.com Address: 3B DIS_TIMING (Display Clock Fine Tuning Register) Default: 00h Bit Mode Function 7 --Reserved 6 R/W PLL_TEST1 input crystal clock (reference to table2. test-pin pair setting) 0: Disable 1: Enable 5:4 R/W DPLL Output Select 00: Select the internal PLL clock source as DPLL output (PWM0 output to REFCLK) 01: Select the external REFCLK clock source as DPLL output 10: Select the internal PLL clock source as DPLL & REFCLK output 11: Select the internal PLL clock source as DPLL output (Video odd/even from EAV output to REFCLK) 37 Realtek 3 R/W REFCLK) DCLK Polarity Inverted 0: Non-Inverted 1: Inverted DCLK Output Enable 0: Disable 1: Enable DCLK (on REFCLK pin) Polarity Inverted 0: Non-Inverted 1: Inverted DCLK (on REFCLK pin) Enable 0: Disable 1: Enable RTD2523/2513 2 R/W 1 R/W 0 R/W Address: 3C PE_CTRL Bit Mode Function 7 R/W DDS Tracking Edge 0: HS positive edge 1: HS negative edge 6 R/W PE Measure Enable 0: Disable 1: Enable PE Measurement, clear after finish. 5 R/W FCROM Static Pull-High Control 0: Disable 1: Enable 4:0 R PE Value Default: 00h www.DataSheet4U.com Address: 3D Status Default: 00h Function Bit Mode 7 R The line number of Display HS is equal to Display Vertical Total, this bit is set to “1”. Write to clear status. 6 W PE Max. Measure Clear 0: clear after finish 1: write ‘1’ to clear PE Max. Value 5 R/W PE Max. Measure Enable 0: Disable 1: Enable PE Max. Measurement 4:0 R PE Max Value 38 Realtek RTD2523/2513 Address: 3E DUTY_FINE_TUNE Bit Mode Function 7:4 R/W Internal Display Clock (IDCLK) Duty Fine-tune: (3F_bit1 to enable) 1111 (min fine-tune) à 1110 à 1100 à 1000 à 0000 (max fine-tune) 3:0 R/W Color Processing Clock (CPCLK) Duty Fine-tune: (3F_bit2 to enable) 1111 (min fine-tune) à 1110 à 1100 à1000 à0000 (max fine-tune) Address: 3F DUTY_FINE_TUNE_CTRL Bit Mode Function 7 R/W RSDS data latch Inverted 0: Non-Inverted 1: Inverted 6:4 R/W RSDS data latch Delay 000: 0ns delay 001: 0.5ns delay 010: 1ns delay 011: 1.5ns delay 100: 2ns delay 101: 2.5ns delay 110: 3ns delay 111: 3.5ns delay 3 R/W Internal Display Clock (IDCLK) Delay Enable: 0: Disable. 1: Enable IDCLK delay. 2 R/W Color Processing Clock (CPCLK) Duty Fine-tune Enable: 0: Disable. 1: Enable CPCLK duty fine-tune (setting in 3E_bit3:0) 1 R/W Internal Display Clock (IDCLK) Duty Fine-tune Enable: 0: Disable. 1: Enable IDCLK duty fine-tuner (setting in 3E_bit7:4) 0 R/W Internal Display Clock (IDCLK) Invert. 0: Disable 1: IDCLK invert enable. Default:00h www.DataSheet4U.com 39 Realtek FIFO Display Window Address: 40 DRWL_BSU (Display Read Pixel Low Byte Before Scaling-Up) Bit Mode Function 7:0 R/W Display window read width before scaling up: Low Byte [7:0] Address: 41 DRWH_BSU (Display Read Pixel High Byte Before Scaling-Up) Bit Mode Function 2:0 R/W Display window read width before scaling up: High Byte [10:8] Address: 42 DRLL_BSU (Display Read Length Low Byte Before Scaling-Up) Bit Mode Function 7:0 R/W Display window read length before scaling up: Low Byte [7:0] Address: 43 DRLH_BSU (Display Read Length High Byte Before Scaling-Up) Function Bit Mode 2:0 R/W Display window read length before scaling up: High Byte [10:8] Address: 44 sRGB Function Bit Mode 7:0 W When R-port coefficient: RG0, RB0, RG1, RB1, … RG31, RB31, When G-port coefficient: GR0, GB0, GR1, GB1, … GR31, GB31, When B-port coefficient: BR0, BG0, BR1, BG1, … BR31, BG31 total 64 bytes (2’ complement : -128~127) s Address: 45 sRGB R-Offset Bit Mode 5:0 R/W (2’ complement : -32~31) s www.DataSheet4U.com RTD2523/2513 Function Address: 46 sRGB G-Offset Bit Mode 5:0 R/W (2’ complement : -32~31) s Address: 47 sRGB B-Offset Bit Mode 5:0 R/W (2’ complement : -32~31) s R’ = Rin[7:0] + R-Offset G’ = Gin[7:0] + G-Offset B’ = Bin[7:0] + B-Offset Rout = R’[7:0] + GR( G’[7:3] ) + BR( B’[7:3] ) Gout = RG( R’[7:3] ) + G’[7:0] + BG( B’[7:3] ) Bout = RB( R’[7:3] ) + GB( G’[7:3] ) + B’[7:0] Function Function Address: 48 EVENT_STATUS_CONTROL Bit Mode Function 7 R/W Enable Vertical Line Compare Function 0: Disable 1: Enable 6 R/W Gating Vertical Line Compare Function to IRQ 5 R Vertical Line Compare Status (for Polling). Write to clear 4 R/W Select Compare Source: 0: Input Side 1: Display Side 3 -Reserved Default: 00h 40 Realtek 2:0 R/W Select Vertical Line –Low Byte [2:0] RTD2523/2513 Address: 49 EVENT_LOCATION Bit Mode 7:0 R/W Select Vertical Line --High Byte [11:3] Default: 00h Function www.DataSheet4U.com 41 Realtek SYNC Processor RTD2523/2513 Address: 4A SYNC_CTRL Default: 00h Bit Mode Function 7 R/W IRQ Enable 0: Disable input sync signal edge occurs as an interrupt source 1: Enable input sync signal edge occurs as an interrupt source 6 R SOG Edge Occurs If the SOG edge occurs, this bit is set to “1”. 5 R ADC Input Horizontal Sync Occurs (HS_RAW) If the ADC input horizontal sync edge occurs, this bit is set to “1”. 4 R Video-8 Input Horizontal Sync Occurs If the Video-8 input horizontal sync edge occurs, this bit is set to “1”. 3 R/W Reserved to 0 Measure VSYNC select 0: The VSYNC chosen by 0x4A [1:0] 1: The VSYNC from de -composite 2 R/W Measure VSYNC Timing Delay 2 clock 0: disable 1: enable 1:0 R/W Measure HSYNC/VSYNC Source Select: 00: RTD300x/RTD20xx original configuration 01: HS_RAW / AVS 10: Video-8 HSYNC / Video-8 VSYNC 11: TMDS HSYNC / TMDS VSYNC Write to clear status. Address: 4B SYNC_CTRL (SYNC Control Register) Bit Mode Function 7 R/W COAST Signal Invert Enable: 0: not inverted 1: inverted 6 R/W COAST Signal Output Enable: 0: disable; 1: enable; 5 R/W HS_OUT Signal Invert Enable: 0: not inverted 1: inverted 4 R/W HS_OUT Signal Output Enable: 0: disable; 1: enable; 3 R/W CLAMP Signal Invert Enable: 0: not inverted 1: inverted 2 R/W CLAMP Signal Output Enable: 0: Disable; 1: Enable 1 R/W Sync-On-Green Enable: 0: Disable; 1: Enable (set “1” to Sync-Mode-Select at the same time) 0 R/W Sync Mode Select: 0: Separate H & V; 1: Composite Sync from HSYNC or Green Address: 4C SYNC_POR (H & V SYNC Polarity Measured Result) Bit Mode Function Default: 00h www.DataSheet4U.com Default: 00h 42 Realtek 7 R/W RTD2523/2513 Safe Mode 0: Normal 1: Safe Mode Enable, mask 1 of 2 IVS. Sync Processor Test Mode 0: Normal 1: Enable Test Mode; (switch 70ns-ck to the time-out & polarity counters) Select HS_OUT Source Signal 0: Bypass HS_RAW 1: Select De-Composite HS out (In Composite mode) Input VSYNC Polarity Indicator 0: negative polarity (high period is longer than low one) 1: positive polarity (low period is longer than high one) Input HSYNC Polarity Indicator 0: negative polarity (high period is longer than low one) 1: positive polarity (low period is longer than high one) Start a HS & VS period / H & V resolution & polarity measurement 0: disable to start a measurement 1: enable to start a measurement, cleared after finished HSYNC & VSYNC Measured Mode 0: HS period counted by crystal clock & VS period counted by HS 1: H resolution counted by input clock & V resolution counted by ENA (Get the correct resolution which is triggered by enable signal, ENA) 6 R/W 5 R/W 3 R 2 R 1 R/W 0 R/W www.DataSheet4U.com 43 Realtek RTD2523/2513 Address: 4D MEAS_HS_PER (HSYNC Period Measured Result) Bit Mode Function 7:0 R Input HSYNC Period Measurement Result: Low Byte[7:0] Address: 4E MEAS_HS_PER (HSYNC Period Measured Result) Default: 8’bx000xxxx Bit Mode Function 7 R Input HSYNC Period Measurement Result: Over-flow bit 1: Over-flow occurred 6 R/W ODD invert for ODD-Controlled-IVS_delay. 0: Disable 1: Invert 5 R/W ODD-Controlled-IVS_delay Enable 0: Disable 1: Enable 4 R/W Input HSYNC Synchronize Edge 0: Input HSYNC is synchronized by the positive edge of the input clock 1: Input HSYNC is synchronized by the negative edge of the input clock 3:0 R Input HSYNC Period Measurement Result: High Byte[11:8] This result is expressed in terms of crystal clocks. When measured digitally, the result is expressed as the number of input clocks between 2 input HS signals divided by 2. Address: 4F MEAS_VS_PER (VSYNC Period Measured Result) Function Bit Mode 7:0 R Input VSYNC Period Measurement Result: Low Byte[7:0] Address: 50 MEAS_VS_PER (VSYNC Period Measured Result) Bit Mode Function 7 R Input VSYNC Period Measurement Result: Over-flow bit 1: Over-flow occurred 6 R Internal Field Detection ODD toggle happen 5:4 R The number of input HS between 2 input VS. LSB bit [1:0] 3 --Reserved 2:0 R Input VSYNC Period Measurement Result: High Byte[10:8] This result is expressed in terms of input HS pulses. When measured digitally, the result is expressed as the number of input enable signal within a frame. Address: 51 MEAS_HS_HI (HSYNC High Period Measured Result) Function Bit Mode 7:0 R Input HSYNC Period Measurement Result: Low Byte[7:0] Address: 52 MEAS_HS_HI (HSYNC High Period Measured Result) Default: 8’b00xx_xxxx Bit Mode Function 7 R/W HS Recovery in Coast 0: Disable 1: Enable (can turn on when CS or SOG) 6 R/W HSYNC Synchronize source 0: Input HS 1: Feedback HS 3:0 R Input HSYNC Period Measurement Result: High Byte[11:8] This result is expressed in terms of crystal clocks. When measured digitally, the result is expressed as the number of input clocks inside the input enable signal divided by 2. Address: 53 MEAS_VS_HI (VSYNC High Period Measured Result) Bit Mode Function 7:0 R Input VSYNC Period Measurement Result: Low Byte[7:0] Address: 54 MEAS_VS_HI (VSYNC High Period Measured Result) Bit Mode Function 7 R 6-iclk-delay HS level latched by VS rising edge www.DataSheet4U.com Default: 8’bxxx00xxx 44 Realtek 6 5 4 R R R/W RTD2523/2513 HS level latched by VS rising edge HS level latched by 6-iclk-delay VS rising edge Feedback HSYNC Synchronize Edge 0: Feedback HSYNC is synchronized by the positive edge of the input clock 1: Feedback HSYNC is synchronized by the negative edge of the input clock 3 R/W VSYNC Synchronize Edge 0: latch VS by the positive edge of input HSYNC 1: latch VS by the negative edge of input HSYNC 2:0 R Input VSYNC Period Measurement Result: High Byte[10:8] This result is expressed in terms of input HS pulses www.DataSheet4U.com 45 Realtek Clamping Signal Control RTD2523/2513 Address: 55 CLAMP_START (Clamp Signal Output Start) Function Bit Mode 7:0 R/W Start of Output Clamp Signal Pulse: Determine the number of input double-pixel between the trailing edge of input HSYNC and the start of the output CLAMP signal. Address: 56 CLAMP_END (Clamp Signal Output End) Function Bit Mode 7:0 R/W End of Output Clamp Signal Pulse: Determine the number of input double-pixel between the trailing edge of input HSYNC and the end of the output CLAMP signal. Display Data Bus Control (For RSDS type-3) Address: 57 Display Data Bus Interleaving Line Buffer Length Low Byte Bit Mode Function 7:0 R/W Interleaving Line Buffer Line Bufer: Low Byte [7:0] Address: 58 Display Data Bus Interleaving Line Buffer Length High Byte Bit Mode Function 2 R/W Display Data Bus Interleaving Enable 0: Disable 1: Enable 1:0 R/W Interleaving Line Buffer Line Bufer: High Byte [9:8] Default: 00h Default: 00h www.DataSheet4U.com 46 Realtek RTD2523/2513 www.DataSheet4U.com Fixed Last Line Length Address: 59 FX_LST_LN_LNGTH_LSB Bit Mode 7:0 R/W Fixed Last Line Length [7:0] Function Address: 5A FX_LST_LN_LNGTH_MSB Bit Mode Function 7 R/W New Dithering 0: Disable 1: Enable 6 R/W RSDS_TET_EN 0: Disable 1: Enable 5 R/W SSCG_TST_EN Test Enable 0: Disable 1: Enable(SDMOUT[3:0] will be pass to V8_DATA[3:0]) 4 R/W Enable the Fixed DVTOTAL & Last Line Length Function 0: Disable 1: Enable 3 R/W Enable DDS Spread Spectrum Output Function 0: Disable 1: Enable 2:0 R/W Fixed Last Line Length [10:8] Default: 0000_0xxxb 47 Realtek Anti-Flicker Control Address: 5B Bit Mode 7:0 R/W Address: 5C Bit Mode 7 R/W RTD2523/2513 6 5 4:0 Pixel Threshold Value for Smart Polarity (TH1) Default: 00h Function 2 line Sum of Difference Threshold Value: bit [7:0] Line Threshold Value for Smart Polarity (TH2) Default: 0x000000b Function Measure Dot Pattern over Threshold (depend on 0x00[1]) 1: run. /* Auto: always measure Manual: start to measure, clear after finish */ 0: stop R Dot Pattern Sum of Difference Measure Result 1: over threshold 0: under threshold R/W TCON [7] Polarity one / two Line Toggle Control 1: Auto /* If sum of difference under threshold, TCON [7] will auto switch to “normal ” output. If sum of difference over threshold, TCON [7] will auto switch to “original setting” output */. 0: Manual R/W Over Difference Line Threshold Value: bit [4:0] 動作說明 0x5C[7] & 0x5C[5] 自動 anti-flicker ‘1’ & ‘1’ ‘1’ & ‘0’ 透過 manual 方式,當 0x5C[7]設為’1’,便會自動執行㆒個 frame,做完後 0x5C[7] clear 成’0’ 沒動作 ‘0’ & ‘x’ www.DataSheet4U.com Color Processor Control Address: 5D COLOR_CTRL (Color Control Register) Bit Mode Function 7 R/W Dithering Frame Modulation Vertical Enable 0: disable 1: enable 6 R/W Dithering Frame Modulation Horizontal Enable 0: disable 1: enable 5 R/W Enable Access Channel for Dithering Table: 0: disable this channel 1: enable this channel (address should not auto increase) 4 R/W Enable Access Channels for Gamma Correction Coefficient: 0: disable these channels 1: enable these channels (address should not auto increase) 3 R/W Enable Dithering Function: 0: disable the dithering function 1: enable the dithering function 2 R/W Enable Look-Up Table for Gamma Correction Coefficient: 0: disable the look-up table 1: enable the look-up table coefficient 1 R/W Enable Contrast Control Coefficient: 0: disable the coefficient 1: enable the coefficient 0 R/W Enable Brightness Control Coefficient: 0: disable the coefficient Default: 00h 48 Realtek 1: enable the coefficient RTD2523/2513 Brightness Coefficient: Address: 5E BRI_R_COE (Brightness Red Coefficient) Bit Mode Function 7:0 W Brightness Red Coefficient: Valid range: -128(00h) ~ 0(80h) ~ +127(FFh) Address: 5F BRI_G_COE (Brightness Green Coefficient) Bit Mode Function 7:0 W Brightness Green Coefficient: Valid range: -128(00h) ~ 0(80h) ~ +127(FFh) Address: 60 BRI_B_COE (Brightness Blue Coefficient) Bit Mode Function 7:0 W Brightness Blue Coefficient: Valid range: -128(00h) ~ 0(80h) ~ +127(FFh) Contrast Coefficient: Address: 61 CTS_R_COE (Contrast Red Coefficient) Bit Mode Function 7:0 W Contrast Red Coefficient: Valid range: 0(00h) ~ 1(80h) ~ 2(FFh) Address: 62 CTS_G_COE (Contrast Green Coefficient) Function Bit Mode 7:0 W Contrast Green Coefficient: Valid range: 0(00h) ~ 1(80h) ~ 2(FFh) Address: 63 CTS_B_COE (Contrast Blue Coefficient) Function Bit Mode 7:0 W Contrast Blue Coefficient: Valid range: 0(00h) ~ 1(80h) ~ 2(FFh) www.DataSheet4U.com Gamma Correction : Address: 64 RED_GAMMA_PORT (Red Gamma Table Access Port) Bit Mode Function 7:0 W Access port for red gamma correction table Address: 65 GRN_GAMMA_PORT (Green Gamma Table Access Port) Bit Mode Function 7:0 W Access port for green gamma correction table Address: 66 BLU_GAMMA_PORT (Blue Gamma Table Access Port) Bit Mode Function 7:0 W Access port for blue gamma correction table When enable gamma correction table accessing, total size of coefficient table is 256 bytes for each color respectively. And the input data sequence is c0, c1, c2, … c255. Dithering Coefficient: Address: 67 DITHER_PORT (Dithering Table Access Port) Bit Mode Function 7:0 W Access port for dithering table Old dithering(0x5A[7] = 0): When enable dithering table accessing, total size of coefficient table is 16 * 4 bits for RGB color. And the input data sequence is {c1, c0}, {c3, c2}, … {c15, c14}. C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 49 Realtek RTD2523/2513 New dithering(0x5A[7] = 1): One dithering sequence table contains 32element, s0, s1, … , s31. Each element has 2bit to index one of 4 dithering table. Input data sequence is {s3,s2,s1,s0}, {s7,s6,s5,s4}, … , {s31,s30,s29,s28}. R + (2R+1) * C choose sequence element, where R is Row Number / 2, and C is Column Number / 2. 4 dithering table, 0,1,2,3, is C0 C1 C2 C3 C8 C9 C10 C11 C4 C5 C6 C7 C12 C13 C14 C15 www.DataSheet4U.com 50 Realtek Cyclic-Redundant-Check Address: 68 OP_CRC_CTRL (Output CRC Control Register) Bit Mode Function 7:2 R/W SRAM Control //111111 (F, I, A, M, G, C) F (bit 7): four-line SRAM I (bit 6): input SRAM A (bit 5): OSD attribute SRAM M (bit 4): OSD font map SRAM G (bit 3): Gamma, Dithering table SRAM C (bit 2): filter coefficient SRAM 1 R/W Enable Full Line buffer: 0: Disable 1: Enable 0 R/W Output CRC Control: 0: Stop or finish (Auto-stop after checked a completed display frame) 1: Start CRC function = X^24 + X^7 + X^2 + X + 1. Address: 69 OP_CRC_BYTE_0 (Output CRC Checksum Byte 0) Bit Mode Function 7:0 R Output CRC-24 bit 7~0 Address: 6A OP _CRC_BYTE_1 (Output CRC Checksum Byte 1) Bit Mode Function 7:0 R Output CRC-24 bit 15~8 Address: 6B OP _CRC_BYTE_2 (Output CRC Checksum Byte 2) Bit Mode Function 7:0 R Output CRC-24 bit 23~16 www.DataSheet4U.com RTD2523/2513 Default: FCh 51 Realtek Background color control RTD2523/2513 Address: 6C Background color control Bit Mode Function 7:0 R/W Background color RGB 8-bit value There are 3 bytes color select of background R, G, B, and the writing and reading is selected by 0x6D[7:6]. Overlay Control Address: 6D OVL_CTRL (Overlay Display Control Register) Function Bit Mode 7:6 R/W Background color select (select the writing and reading byte of 0x6c) 00: Red 01: Green 10: Blue 11: X 5:3 R/W Alpha blending level 00:Disable, 001 ~111: 1/8~ 7/8 2 --Reserved 1 R/W Overlay Sampling Mode Select: 0: dual pixels per clock 1: single pixel per clock 0 R/W Overlay Port Enable: 0: Disable 1: Enable Address: 6E OVL_LUT_ADDR (Overlay LUT Address) Function Bit Mode 7 R/W Enable Overlay Color Plate Access: 0: Disable 1: Enable 6 --Reserved 5:0 R/W Overlay 16x24 Look-Up-Table Write Address [5:0] Auto-increment while every accessing “Overlay LUT Access Port”. Default: 00h Default: 00h www.DataSheet4U.com Address: 6F OVL_LUT_PORT (Overlay LUT Access Port) Function Bit Mode 7:0 W Overlay 16x24 Look-Up-Table access port [7:0] Using this port to access overlay color plate which addressing by the above registers. The writing sequence into LUT is {R0, G0, B0, R1, G1, B1, … R15, G15, and B15} and the address counter will be automatic increment and circular from 0 to 47. 52 Realtek Scale Down Control RTD2523/2513 Address: 70 SCALE_DOWN_CTRL (Scale Down Control Register) Default: 00h Bit Mode Function 7 R/W Video 8 Port Input Latch Bus MSB to LSB Swap Control: 0: normal 1: Switched Video8 port MSB to LSB sequence into LSB to MSB 6 R/W Default=’0’. When set to ‘1’, vertical scale down is disable in scale down mode 5 R/W Internal ENA (I_ENA) Delay Control: 0: normal; 1: 2ns delay; 4 R/W Internal VS (I_VS) Delay Control: 0: normal; 1: 2ns delay; 3 R/W Internal HS (I_HS) Delay Control: 0: normal; 1: 2ns delay; 2:1 R/W Input Clock Delay Control: 00: Normal 01: 1ns delay 10: 2ns delay 11: 3ns delay 0 R/W Scale down function enable: 0: disable scale down function 1: enable scale down function Address: 71 H_SCALE_DL (Horizontal scale down factor register) Function Bit Mode 7:0 R/W Horizontal Scale Down Factor: Low Byte [7:0] Address: 72 H_SCALE_DH (Horizontal scale down factor register) Bit Mode Function 7:0 R/W Horizontal Scale Down Factor: High Byte [15:8] Registers { H_SCALE_DH, H_SCALE_DL} = (Xi / Xm) x (2^12) truncate. If not truncate, fill minus 1. Meanwhile, Xi = horizontal input width; Xm = horizontal memory write width Address: 73 V_SCALE_DL (Vertical scale down factor register) Function Bit Mode 7:0 R/W Vertical Scale Down Factor: Low Byte [7:0] Address: 74 V_SCALE_DH (Vertical scale down factor register) Bit Mode Function 7:0 R/W Vertical Scale Down Factor: High Byte [15:8] Registers { V_SCALE_DH, V_SCALE_DL} = (Yi / Ym) x (2^12) truncate. If not truncate, fill minus 1 Meanwhile, Yi = vertical input width; Ym = vertical memory write width www.DataSheet4U.com 53 Realtek Image Auto Function Address: 75 H_BOUNDARY_STA_L Bit Mode Function 7:0 R/W Horizontal Boundary Start: Low Byte [7:0] Address: 76 H_BOUNDARY_END_L Bit Mode Function 7:0 R/W Horizontal Boundary End: Low Byte [7:0] RTD2523/2513 Address: 77 H_BOUNDARY_HIGH Default: 8’b0xxx_xxxx Bit Mode Function 7 R/W Field_Select_Enable: Auto-Function only active when Even or Odd field. 0: Disable 1: Enable 6:4 R/W Horizontal Boundary Start: High Byte [10:8] //11-bit=2048 3:0 R/W Horizontal Boundary End: High Byte [11:8] //12-bit=4096 Address: 78 V_BOUNDARY_STA_L Function Bit Mode 7:0 R/W Vertical Boundary Start: Low Byte [7:0] //(Invalid when Vertical Auto-Boundary) Address: 79 V_BOUNDARY_END_L Bit Mode Function 7:0 R/W Vertical Boundary End: Low Byte [7:0] //(Invalid when Vertical Auto-Boundary) Address: 7A V_BOUNDARY_HIGH Default: 8’b0xxx_xxxx Function Bit Mode 7 R/W Field_Select: Select Even or Odd field. Active when Field_Select_Enable. 0: Active when ODD signal is “0” 1: Active when ODD signal is “1” 6:4 R/W Vertical Boundary Start: High Byte [10:8] //11-bit //(Invalid when Vertical Auto-Boundary) 3:0 R/W Vertical Boundary End: High Byte [11:8] //12-bit //(Invalid when Vertical Auto-Boundary) Address: 7B RED_NOISE_MARGIN (Red Noise Margin Register) Function Bit Mode 7:2 R/W Red pixel noise margin setting register 1 R/W Even or Odd pixel be measured 0: Even 1: Odd 0 R/W Measure only Even or Odd pixel enable 0: Disable 1: Enable Address: 7C GRN_NOISE_MARGIN (Green Noise Margin Register) Bit Mode Function 7:2 R/W Green pixel noise margin setting register 1:0 R/W Vertical boundary search: 00: 1 pixel over threshold; 01: 2 pixel over threshold 10: 4 pixel over threshold; 11: 8 pixel over threshold Address: 7D BLU_NOISE_MARGIN (Blue Noise Margin Register) Bit Mode Function 7:2 R/W Blue pixel noise margin setting register 1:0 R/W Color Source Select for Detection: 00: B color 01: G color 10: R color Address: 7E DIFF_THRESHOLD Bit Mode 7:0 R/W Difference Threshold Default: 8’bxxxxxx00 www.DataSheet4U.com Default: 8’bxxxxxx00 Default: 8’bxxxxxx00 Function 54 Realtek Next Pixel Current Pixel absolute value 1's com 0 0 1 DFF store max pixel of current and next pixel max DFF if "compare" output 0 compare DFF >= RTD2523/2513 >= 0 DFF 1 Enable Substrater Next Pixel Diff_en _ + Current Pixel Inv_en 7F.1 Function Selection 0:Balance / 1:Phase 7F.5 Max/Min Select 0:Min(inv) / 1:Max 7E DifferenceThreshold 7F.6 Diff/Pixel select 0:Pixel-value / 1:Diff 7F.4 Accu/Comp select 0:Comp / 1:Accu Figure 14 Auto-Tracking Control Block Address: 7F AUTO_ADJ_CTRL (Auto adjustment control register ) Default: 00h Bit Mode Function 7 R/W Measure Digital Enable Info when boundary search active 0: Normal Boundary Search 1: Digital Enable Info Boundary Search. (The vertical & horizontal, start & end information of external digital signal can be obtained from CR80~87). 6 R/W Accumulation Type 0: Type1 1: Type2 5 R/W Color Max or Min Measured Select: 0: MIN color measured (Only when Balance-Mode, result must be complemented) 1: MAX color measured 4 R/W Accumulation or Compare Mode 0: Compare Mode 1: Accumulation Mode 3:2 R/W Mode Selection (00 is forbidden) 01: Mode1 10: Mode2 11: Mode3 1 R/W Function (Phase/Balance) Selection 0: Auto-Balance 1: Auto-Phase 0 R/W Start Auto-Function Tracking Function: 0: stop or finished 1: start Control Table/ Function Auto-Balance Auto-Phase Type1 Sub-Function Max pixel Min pixel Mode1 Mode2 Mode3 Mode1 Mode2 Mode3 All pixel 7F.6 X X 0 0 0 1 1 1 1 7F.5 1 0 1 1 1 1 1 1 1 7F.4 0 0 1 1 1 1 1 1 1 7F.3 0 0 0 1 1 0 1 1 0 7F.2 X X 1 0 1 1 0 1 1 7F.1 0 0 1 1 1 1 1 1 0 7E X X Th Th Th Th Th Th 0 www.DataSheet4U.com Auto-Phase Type2 Accumulation Table 1 Auto-Tracking Control Table Address: 80 VER_START_L (Active region vertical start Register) Bit Mode Function 55 Realtek 7:0 R Active region vertical start measurement result: bit[7:0] Address: 81 VER_START_H (Active region vertical start Register) Function Bit Mode 3:0 R Active region vertical start measurement result: bit[11:8] Address: 82 VER_END_L (Active region vertical end Register) Function Bit Mode 7:0 R Active region vertical end measurement result: bit[7:0] Address: 83 VER_END_H (Active region vertical end Register) Function Bit Mode 3:0 R Active region vertical end measurement result: bit[11:8] Address: 84 Bit Mode 7:0 R Address: 85 Bit Mode 3:0 R Address: 86 Bit Mode 7:0 R Address: 87 Bit Mode 3:0 R HOR_START_L (Active region horizontal start Register) Function Active region horizontal start measurement result: bit[7:0] HOR_START_H (Active region horizontal start Register) Function Active region horizontal start measurement result: bit[11:8] HOR_END_L (Active region horizontal end Register) Function Active region horizontal end measurement result: bit[7:0] HOR_END_H (Active region horizontal end Register) Function Active region horizontal end measurement result: bit[11:8] RTD2523/2513 www.DataSheet4U.com Address: 88 AUTO_PHASE_0 (Auto phase result byte0 register) Bit Mode Function 7:0 R Auto phase measurement result: bit[7:0] / The measured value of R or G or B color max or min. (Auto-Balance) Address: 89 AUTO_PHASE_1 (Auto phase result byte1 register) Bit Mode Function 7:0 R Auto phase measurement result: bit[15:8] Address: 8A AUTO_PHASE_2 (Auto phase result byte2 register) Function Bit Mode 7:0 R Auto phase measurement result: bit[23:16] Address: 8B AUTO_PHASE_3 (Auto phase result byte3 register) Bit Mode Function 7:0 R Auto phase measurement result: bit[31:24] Address: 8C IVS_DELAY (Internal Input-VS Delay Control Register) Bit Mode Function 7:0 R/W Input VS delay count by Input HS to reset input data Address: 8D IHS_DELAY (Internal Input-HS Delay Control Register) Bit Mode Function 7:0 R/W Input HS delay count by Input clock Address: 8E ODD_CTRL (ODD Source Control Register) Bit Mode Function 7 R SAV/EAV two-bit error 6 R SAV/EAV one-bit error 5 R/W Auto switch when ADC-PLL non-lock 0: Disable 1: Enable 4 R/W Auto switch when overflow or underflow Default: 00h Default: 00h Default: 00h 56 Realtek RTD2523/2513 0: Disable 1: Enable 3 R/W Decode Video-8 when ADC or TMDS active 0: Disable 1: Enable 2 R/W Input Auto Toggle (TEST) Enable: 0: Disable 1: Enable (DCLK feed to ICLK) (Only works in Video8 port single pixel mode, R & B toggle by ICLK rate, but G toggle by ICLK2 rate) 1 R/W EAV Error Correction Enable in video8 0: Disable 1: Enable 0 R/W 8-bit Random Generator 0: Disable 1: Enable In video8 input format, the bit1 should be the complement of remainder of SAV location clock count/2. www.DataSheet4U.com Address: 8F FCLK (Scale Down Clcok) Fine Tune Bit Mode Function 7:3 -Reserved 3 R/W Select VGIP clock 0: Reference clock 1: DDCSCL 2 R/W Select source of FCLK 0: original setting (default) 1: select ADC_CLK without combinational logic delay 1:0 R/W 0x8F[1] & 0x8F[0] FCLK fine tune 01: slowest 00: typical 1x: fastest Default: 00h 57 Realtek Embedded OSD Address: 90 OSD_ADDR_MSB (OSD Address MSB 8-bit) Bit Mode Function 7:0 R/W OSD MSB 8-bit address Address: 91 OSD _ADDR_LSB (OSD Address LSB 8-bit) Bit Mode Function 7:0 R/W OSD LSB 8-bit address Address: 92 OSD_DATA_PORT (OSD Data Port) Bit Mode 7:0 W Data port for embedded OSD access Refer to the embedded OSD application note for the detailed. Address: 93 OSD_TEST Bit Mode 7:0 R/W Testing Pattern Address: 94 OSD_SCRAMBLE Bit Mode 7 R/W BIST Start 0: stop 1: start (auto clear) 6 R/W BIST Result 0: fail 1: success www.DataSheet4U.com RTD2523/2513 Function Default: 00h Function Default: 00h Function 58 Realtek Embedded Timing Controller Address: 95 TCON_ADDR _PORT Bit Mode 7:0 R/W Address port for embedded TCON access Address: 96 TCON_DATA _PORT Bit Mode 7:0 R/W Data port for embedded TCON access RTD2523/2513 Default: 00h Function Function DCLK Spread Spectrum Address: 97 FIXED_LAST_LINE_MODE_DVTOTAL_LSB Bit Mode Function 7:0 R/W Fixed Last Line Mode DVTOTAL [7:0] Address: 98 FIXED_LAST_LINE_MODE_DVTOTAL_MSB Bit Mode Function 2:0 R/W Fixed Last Line Mode DVTOTAL [10:8] In FreeRun mode, Display Vertical Total is assigned in {0x98[2:0], 0x97[7:0]}. Address: 99 SPREAD_SPECTRUM Function Bit Mode 7:4 R/W DCLK Spreading range (0.0~7.5%) 0000: 0.0% 0001: 0.5% 0010: 1.0% 0011: 1.5% 0100: 2.0% 0101: 2.5% 0110: 3.0% 0111: 3.5% 1000: 4.0% 1001: 4.5% 1010: 5.0% 1011: 5.5% 1100: 6.0% 1101: 6.5% 1110: 7.0% 1111: 7.5% 3 R/W Reserved to 0 Spread Spectrum FMDIV (SSP_FMDIV)//(0) 0: 33K 1: 66K 2 R/W Reserved 1:0 R/W Frequency Synthesis Select (F & F-N*dF) 00~11: N=1~4 df = dclk* 2^(-15) Address: 9A DCLK_FINE_TUNE_OFFSET_ LSB Bit Mode Function 7:0 R/W DCLK Offset [7:0] in Fixed DVTOTAL & Last Line Length Mode Address: 9B DCLK_FINE_TUNE_OFFSET_ MSB Bit Mode Default: 00h www.DataSheet4U.com Default: 00h Default: 00h Function 59 Realtek 7 6 --R/W RTD2523/2513 Reserved Only Even / Odd Field Mode Enable 0: Disable 1: Enable 5 R/W Spread Spectrum Setting Ready for Writing (Auto Clear) 0: Not ready 1: Ready to write 4 R/W Even / Odd Field Select 0: Even 1: Odd 3:0 R/W DCLK Offset [11:8] in Fixed DVTOTAL & Last Line Length Mode The “Spread Spectrum Setting Ready for Writing” (0x9B [5]) means 4 kinds of registers will be set after this bit is set: 1. Spreading range (0x99 [7:4]) 2. Spreading FMDIV (0x99 [3]) 3. DCLK offset setting (0x9A, 0x9B[3:0]) 4. Frequency synthesis select (0x99 [1:0]) Hardware Enhanced Auto Function Address: 9E HARDWARE_AUTO_PHASE Default: 00h Bit Mode Function 7 R HS_ACT_FLAG 2 R/W Hardware / Software Auto Phase Switch 0: Software 1: Hardware 1:0 R/W Hardware Auto Phase Step 00: Step =1 01: Step =2 10: Step =4 11: Step =8 When hardware auto phase enabled, if the 0x7F [0] is set, then the procedure will start. Every frame the 0x89, 0x8A, 0x8B will be updated by auto-increased phase; the phase will be initially 0 and auto-increased by step setting. The Micron have to read 0x89~8B every frame to get the information. Address: 9F Bit Mode 7 R/W 6:3 R/W 2:1 R/W PLLPHASE (Select Phase to A/D) Function X control 16 phases pre-select Reserved to 00 Phase shift 00: Original phase selected by X, Y, and 16 -phase pre-select 01~11: Add 1~3 phase to the Original phase selected by X, Y, and 16 -phase pre-select Y control Phase 32 36 40 44 48 52 56 60 [X ^^^^ Y] [0 1000 1] [0 1001 1] [0 1010 1] [0 1011 1] [0 1100 1] [1 1101 0] [1 1110 0] [1 1111 0] Phase 64 68 72 76 80 84 88 92 [X ^^^^ Y] [1 0000 0] [1 0001 0] [1 0010 0] [1 0011 0] [1 0100 0] [1 0101 0] [0 0110 0] [0 0111 0] Phase 96 100 104 108 112 116 120 124 [X ^^^^ Y] [0 1000 0] [0 1001 0] [0 1010 0] [0 1011 0] [0 1100 0] [1 1101 1] [1 1110 1] [1 1111 1] Default: 00h www.DataSheet4U.com 0 Phase 0 4 8 12 16 20 24 28 R/W [X ^^^^ Y] [1 0000 1] [1 0001 1] [1 0010 1] [1 0011 1] [1 0100 1] [0 0101 1] [0 0110 1] [0 0111 1] 60 Realtek Embedded TMDS RTD2523/2513 www.DataSheet4U.com Address A0: Output Port Enable Default: 6Fh Bit Mode Function 7 R/W Power down TMDS whole function High: Normal Run Low: Power Down 6:5 R/W TMDS_TEST 34 Data Output Select (30 bit over-sampled data, DEN, HS, VS, CLK) 00: Blue channel 01: Green channel 10: Red channel 11: Disable 4 R/W TMDS_TEST 3 DE Output Select 0: Disable 1: 3 channel DE output with CLK (HS, VS be replaced by DE1, DE2) 3 R/W Output control by auto function High: Auto output, Low: Manual. 2:0 R/W Bit 0: Enable Blue output port. Bit 1: Enable Green output port Bit 2: Enable Red output port Address A1: Input Port Enable Default: EFh Bit Mode Function 7 R/W Mcufirst High: disable DDC channel and MCU access only Low: enable DDC channel and MCU access only when DDC is not busy 6 R/W Reserved 5 R/W 1: Original power up sequence, turn on R/G when DE low 128 clocks 0: Turn On R/G channel when DE low 128 clocks and VS rising and falling appears 4 R Chbok: Detect Blue Channel DE low last 128 dclk High: Active, Low: Non-Active 61 Realtek Input control by auto function High: Auto enable, Low: Manual 2:0 R/W Bit 0: Enable Blue input port. Bit 1: Enable Green input port Bit 2: Enable Red input port Address A2: Analog Performance#1 Bit Mode Function 7 R/W WDmode: Select Watch Dog mode, Low: Analog, High: Digital. 6:5 R/W 00: Auto 10: Watch Dog Pin=’1’ x1: Watch Dog Pin=’0’ 4:3 R/W sr[1:0]: The resistor of LPF in PLL. 2:0 R/W si[2:0]: Charge pump current in PLL, Icp=si[2:0]*5u+5u. Address A3: Analog Performance#2 Bit Mode Function 7 R/W anaWDen: Analog watch dog when ckonctrl =1, control pllckon High: Analog & Digital Low: Digital 6 R/W ckon_manual: control pllckon when ckon_ctrl =0, Low: off, High: on. 5 R/W ckonctrl: Low: Manual, High: Auto 4 R/W z0pow: MCU must pull it up after power stable 3 R/W down: When down=0, Z0 is auto set 50 ohm. 2:1 R/W selTST[1:0]: Select the TSTout function of clock port & RD port. 0 R/W ENTST: Enable clock port TSTout pin. 0:Analog to TSTPAD (20k ohm to GND) 1:Digital to TSTPAD (50 ohm to VDD) ENTST::Enable TMDS test singal 0: Disable 1: Enable TMDS power down: set A0[7] & A3[4] to 0 TMDS power save: set A0[7] to 0, A3[4] to 1 Address A4: Analog Performance#3 Bit Mode Function 7:6 Read as “00” 5:4 R/W selTST[1:0]: Select the TSTout pin of Z0_control. 3:0 R/W When down=1, Z0 can be controlled by [3:0] Address A5: Analog_Test_Output_Selection & Digital WD h Bit Mode Function 7:6 R/W selperd: Choose the freq stable time to turn on pllckon Perd Stable Time 00: 16us 32~48us 01: 64us 128~192us 10:256us 512~768us 11: 1ms 2~3ms 5:3 R/W HZTST: Enable TMDS TSTout pin. 0:Enable TSTOUTPAD 1:High impedance STSTPAD 3 R/W RTD2523/2513 Default: 8Bh Default: 26h www.DataSheet4U.com Default: 35h Default: 9f 62 Realtek RTD2523/2513 000:TMDS bias to TSTPAD 001:TMDS test singal to TSTPAD 010:D2P (PWM1) singal to TSTPAD 011:P2D (Reserved) singal from TSTPAD (power on latch to select parallel/serial port) 1xx:Force high impedance of TSTPAD selTST[2:0]: Select the TSTout pin to PAD. 2:0 R/W www.DataSheet4U.com Figure 15 TSTOUT Pin Internal Configuration Address A6: Control Register Function Bit Mode 7 R/W High: CRC check during the next full frame and clear reg. 0xA7~0xA9. Low: After start CRC 6 R CRCdone High: When CRC done Low: When set 0xA6[7] 5 R/W Indicate VSYNC Polarity Mode: High: manual, decided by 0xA6[0] Low: auto, indicate by 0xA6[4] 4 R Indicate VSYNC Polarity High: Negative Low: Positive 3 R/W Reserved to 0 2 R/W Reserved 1 R/W Always PRE-charge: Default: 08h 63 Realtek RTD2523/2513 www.DataSheet4U.com High: Enable, Low: Disable 0 R/W Reserved Address A7: CRC Output Byte_0 Default: XX Bit Mode Function 7:0 R CRC output bit 7~0 Cleared when 0x04[2] is set. Address A8: CRC Output Byte_1 Default: XX Bit Mode Function 7:0 R CRC output bit 15~8 Address A9: CRC Output Byte_2 Default: XX Bit Mode Function 7:0 R CRC output bit 23~16 Address AA: DB Test Mode Default: 00h Bit Mode Function 7 R/W Reserved to 0 6 R Reserved 5 R/W TMDS test output enable (only when ADC test output disable) High: TMDS test data output to VIDEO8 PAD Low: Disable 4 R/W Shwp: show write pointer High: show wp at VIDEO8 [5:0] wp decided by wpsel[1:0] Low: other bits make decision 3 R/W Shctl: High: bypass CTL3~0 to VIDEO8 [3:0] Low: VIDEO8[3:0]=[0000] 2 R/W f25tst: After the rising edge first full cycle data and hold system when TI,TO,TCK active, data could be shift out by the order R30bit 0~29,R12bit 0~11,G,B; where 12bit and 30bit data decided by f25sel Z0TST= VIDEO8 [2] Z0TST= VIDEO8 [3] TCK2= AVS, decided by 0xAB[7] TO = VIDEO8 [5], TI = DDCSDA, TCK = DDCSCL, 1 R/W shauth: High: show authst, authkm, authdone to VIDEO8[2:0] Low: VIDEO8[2:0]={000} 0 R/W shclk: High: show crystal, fbakdiv5, findiv2, dclk (dclk/2) to VIDEO8[3:0] Low: VIDEO8[3:0]=[0000] Address AB: DVI_REG_TEST Default: 00h Bit Mode Function 7 R/W tck_mode: High: TCK2 mode Low: Original 6:4 R/W f25sel: Decision latched data of F2x5FIFOT: check 12bit 30bit 000 [11:0] lat0 29:0 001 [23:12] lat1 29:0 010 [47:36] lat3 59:30 011 [59:48] lat4 59:30 10x [29:24] lat2 29:0 11x [35:30] lat2 59:30 64 Realtek 3 2:1 R/W R/W RTD2523/2513 www.DataSheet4U.com Reserved wpsel: Display selection of write pointer of TMDS, 00: wp=6’h00, 01: wp of blue channel 10: wp of green channel 11: wp of red channel 0 R/W dclkdiv: Low: out dclk when shwp=0,shck=1 to VIDEO8[0] High: dclk/2 Address AC: Pattern Comparator Default: 90h Bit Mode Function 7 R/W Calibration of FIFO write pointer after Vsync High: Enable calibration, Low: Disable 6 R/W Calibration write pointer Vsync edge select High: Falling, Low: Rising 5 R/W Hsync edge select after Vsync calibrate write pointer High: Falling, Low: Rising 4 R/W Clock delay select after Hsync calibrate write pointer High: Enable delay 5 clock Low: Disable 3 R/W Calibration of FIFO write pointer and boundary detection after falling DE High: Enable calibration, Low: Disable 2 R/W pertst: High: start to do pixel error rate test wait for matched pattern Low: stop PERT and clear numerr and perten 1 R/W pertmode: High: PN code PERT Low: Half clock PERT 0 R perten: High: matched pattern found PERT(Pixel Error Rate Test) enable Low: clear by pertst reset Address AD: Pixel Error Rate Low Byte Default: 00h Bit Mode Function 7:0 R Numerr low byte: Total count of pixel error Address AE: Pixel Error Rate High Byte Default: 00h Bit Mode Function 7:0 R Numerr high byte: Total count of pixel error Address AF: DVI_CTRL1 Default: 00h Bit Mode Function 7 R/W Reserved 6:4 R If Red/Green/Blue FIFO overflow or underflow, These will set ‘1’, clear ‘0’ after read. 3 R/W Reserved 2 R/W OCLK divide 2: High: Enable Low: Disable 1:0 R/W Reserved F25CK Delay: 00 : 2ns 01 : 2.7ns 10 : 3.7ns 11 : 4.7ns delay clock 1x from analog Address B0: TMDS CTL0~3 Signal Status Default:30h 65 Realtek Bit 7:4 3 2 1 0 Mode R/W R R R R Function Reserved TMDS internal CTL3 signal status TMDS internal CTL2 signal status TMDS internal CTL1 signal status TMDS internal CTL0 signal status RTD2523/2513 Address B1: Reserved Bit Mode 7:0 R/W Reserved Address B2: Device Key BIST Pattern Bit Mode 7 R/W Reserved 6:0 W BIST Pattern Input Address B3: TMDS_TEST_MODE_1 Bit Mode 7:6 R/W Phase select Mode BLUE 00: Original 01: Fix middle 10: Fix back 11: Fix front 5:4 R/W Phase select Mode GREEN 3:0 R/W Continuous Change 0000: 1 ~ 1111: 16 www.DataSheet4U.com Default: 00h Function Function Default: 00h Function Address B4: TMDS_TEST_MODE_2 Bit Mode 7:6 R/W Phase select Mode RED 5:4 R/W Data Picking Select BLUE 0x: Middle 10: Front 11: Back 3:2 R/W Data Picking Select GREEN 1:0 R/W Data Picking Select RED Address B5: Reserved Address B6: Reserved Bit Mode 7:0 R/W Reserved Address B7: Reserved Bit Mode 7:0 R/W Reserved Address B8~BF Reserved Default: 00h Function Default: 00h Function Function DVI DDC Channel (Refers to the VESA “Display Data Channel Standard” for detailed, DVI channel only support DDC2B) Address: BC DDC_ENABLE (DDC Channel Enable Register) Default: 00h Bit Mode Function 7:5 R/W DDC Channel Address Least Significant 3 Bits 66 Realtek 4 3 R R/W (The default DDC channel address MSB 4 Bits is “A”) DDC Write Status (for external DDC access only) It is cleared after write. DDC SRAM Write Enable (for external DDC access only) 0: Disable 1: Enable DDC Debounce Enable 0: Disable 1: Enable (with crystal / 4) DDC Channel RAM Size 0: 128 bytes 1: 256 bytes DDC Channel Enable Bit 0: MCU access Enable 1: DDC channel Enable RTD2523/2513 2 R/W 1 R/W 0 R/W Address: BD DDC_INDEX (DDC SRAM R/W Index Register) Bit Mode Function 7:0 R/W DDC SRAM Read/Write Index Register [7:0] The DDC channel index register will be auto increased one by one after each read or write cycle. Address: BE DDC_ACCESS_PORT (DDC Channel ACCESS Port) Function Bit Mode 7:0 R/W DDC SRAM Read/Write Port ** The DDC function can still work when Power_Down & Power_Save. ** After reset, the register will be set to default value, but the SRAM will keep original data. www.DataSheet4U.com 67 Realtek Control for LVDS RTD2523/2513 www.DataSheet4U.com Address: C0 LVDS_CTRL0 Default: 00h Bit Mode Function 7 R/W Power down PLL 0: Power down 1: Normal 6 R/W Power down even-port 0: Power down 1: Normal 5 R/W Power down odd-port 0: Power down 1: Normal 4 R/W Enable PLL test signal to PLLTST 0: Disable 1: Enable 3 R/W Select PLLtest-pin 0: Fbak 1: Fin 2:1 R/W Watch Dog Model 00: Enable Watch Dog 01: Keep PLL VCO = 1V 1x: Disable Watch Dog 0 R Watch Dog Control Flag 0: Disable watch dog 1: Reset PLL and set VCO = 1V Address: C1 LVDS_CTRL1 Default: 04h Function Bit Mode 7 R/W TTL_TST_EN 0: Disable 1: Enable 7:4 --Reserved 3 R/W Pin connected with capacitors (2.6pF) 0: yes 1: no 2:0 R/W RSDS / LVDS Output Common Mode (100) For TTL_TST_EN test mode, we use the video port as input, then we could not test the signal output from video port. In 8 bit TTL mode, if set to 1, these signals will be redirect to other pins, and the test fault coverage will be higher.... Address: C2 LVDS_CTRL2 Default: 52h Function Bit Mode 7:6 R/W SBGL [1:0]: Bandgap Voltage (~1.2V) 5:3 R/W SIL [2:0]: PLL charge pump current (I=5uA+5uA*code) 2:1 R/W SRL [1:0]: PLL resistor 0 R/W BMTS: Bit-Mapping Table Select High: Table 2 Low: Table 1 TCLK+ LVDS Even A Even B Even C Even D Odd A Bit 1 ER1 EG2 EB3 ER7 OR1 Bit 0 ER0 EG1 EB2 ER6 OR0 Bit 6 EG0 EB1 DEN*6 RSV*7 OG0 Bit 5 ER5 EB0 VS*5 EB7 OR5 Bit 4 ER4 EG5 HS*5 EB6 OR4 Bit 3 ER3 EG4 EB5 EG7 OR3 Bit 2 ER2 EG3 EB4 EG6 OR2 Bit 1 ER1 EG2 EB3 ER7 OR1 Bit 0 ER0 EG1 EB2 ER6 OR0 Bit 6 EG0 EB1 DEN*6 RSV*7 OG0 Bit 5 ER5 EB0 VS*5 EB7 OR5 68 Realtek Odd B Odd C Odd E OG2 OB3 OR7 OG1 OB2 OR6 OB1 DEN*2 RSV*3 OB0 VS*1 OB7 OG5 HS*0 OB6 OG4 OB5 OG7 OG3 OB4 OG6 OG2 OB3 OR7 RTD2523/2513 OG1 OB2 OR6 OB1 DEN*2 RSV*3 OB0 VS*1 OB7 TABLE 1 Bit-Mapping 6bit(5~0)+2bit(7~6) TCLK+ LVDS Even A Even B Even C Even D Odd A Odd B Odd C Odd E Bit 1 ER3 EG4 EB5 ER1 OR3 OG4 OB5 OR1 Bit 0 ER2 EG3 EB4 ER0 OR2 OG3 OB4 OR0 Bit 6 EG2 EB3 DEN*6 RSV*7 OG2 OB3 DEN*2 RSV*3 Bit 5 ER7 EB2 VS*5 EB1 OR7 OB2 VS*1 OB1 Bit 4 ER6 EG7 HS*5 EB0 OR6 OG7 HS*0 OB0 Bit 3 ER5 EG6 EB7 EG1 OR5 OG6 OB7 OG1 Bit 2 ER4 EG5 EB6 EG0 OR4 OG5 OB6 OG0 Bit 1 ER3 EG4 EB5 ER1 OR3 OG4 OB5 OR1 Bit 0 ER2 EG3 EB4 ER0 OR2 OG3 OB4 OR0 Bit 6 EG2 EB3 DEN*6 RSV*7 OG2 OB3 DEN*2 RSV*3 Default: 80h Bit 5 ER7 EB2 VS*5 EB1 OR7 OB2 VS*1 OB1 TABLE 2 Bit-Mapping 6bit(7~2)+2bit(1~0) Address: C3 LVDS_CTRL3 Bit Mode Function 7:6 R/W E_RSV_s: even port reserve signal select 11: Alawys ‘1’ 10: Alawys ‘0’ 01: TCON [3] 00: PWM_0 5:4 R/W E_DEN_s: even port data enable signal select 11: Alawys ‘1’ 10: Alawys ‘0’ 01: TCON [2] 00: E_DEN (DENA) 3:2 R/W E_VS_s: even port VS signal select 11: Alawys ‘1’ 10: Alawys ‘0’ 01: TCON [1] 00: E_VS (DVS) 1:0 R/W E_HS_s: even port HS signal select 11: Alawys ‘1’ 10: Alawys ‘0’ 01: TCON [0] 00: E_HS (DHS) Address: C4 LVDS_CTRL4 Bit Mode Function 7:6 R/W O_RSV_s: odd port reserve signal select 11: Alawys ‘1’ 10: Alawys ‘0’ 01: TCON [4] 00: PWM_1 5:4 R/W O_DEN_s: odd port data enable signal select 11: Alawys ‘1’ 10: Alawys ‘0’ 01: TCON [2] 00: O_DEN (DENA) 3:2 R/W O_VS_s: odd port VS signal select 11: Alawys ‘1’ 10: Alawys ‘0’ 01: TCON [1] www.DataSheet4U.com Default: 80h 69 Realtek 1:0 R/W 00: O_VS (DVS) O_HS_s: odd port HS signal select 11: Alawys ‘1’ 10: Alawys ‘0’ 01: TCON [0] 00: O_HS (DHS) LVDS_CTRL5 RTD2523/2513 Address: C5 Bit Mode 7:4 R/W Bias Generator Adjust (0110) 3 R/W Bandgap of LVDS/RSDS Power on 0: Off 1: On 2:0 R/W STSTL [2:0]: select test attribute 000: High Impedance 001: VOCME 010: VBG 011: 60uA (20K ohm to GND) 1xx: TSTPLL (50 ohm to VDD) Default: 60h Function Power save & power down: set C0[7:5] to 0, C5[3] to 0 www.DataSheet4U.com 70 Realtek Control for PLL DIV Address: C8 PLL_DIV_CTRL0 Bit Mode Function 7:6 Reserved. --5 R/W DDS Reset Enable 0: Normal function 1: DDS circuit’ reset will be asserted, for test only s 4 R/W Test Mode: (for production test) 0: Normal 1: Test Mode 3 R/W HS output synchronized by 0: phase 16 1: phase 0 2:1 R/W Phase error detect mode 00: zero mode (FB is aligned to nedegde of Fav) 01: ±1 mode (FB is aligned to posedge of Fav) 1x: direct mode (FB is direct to PFD) 0 R/W Clock select for DIV 0: phase 0 (phase-0 of PLL2) 1: internal CLK (Fav) Address: C9 I_CODE_L Bit Mode Function 7:5 R/W I_Code [7:5] For old I or New_I mechanism depending on 0xc9[0] & 0xc9[4] 4 R/W I_Code [4] / I-code control mechanism 0: new linear mode, PE*(2+NEW_I[12])*2^(NEW_P+2) 1: old mode, P-code = P-code_2011 - 1 3:2 R/W I_Code [3:2] / P-code protection mode 00 => No protection 01 => 1 bit protection 10 => 2 bits protection 11 => 3 bits protection 1 R/W I_Code [1] / P-code mapping curve 0: choose the new P-code mapping curve 1: choose the old P-code mapping curve 0 R/W I_Code [0] /I-code multiplication factor 0: choose the new I-code multiplication factor = NEW_I[9:5] (PE)*(2+NEW_I[13])* 2^(NEW_I[9:5]+2) 1: choose the old I-code multiplication factor Address: CA Bit Mode 7:6 R/W 5 R/W 4 R/W 3 R/W 2 R/W I_CODE_M Function RTD2523/2513 Default: 00h Default: 61h www.DataSheet4U.com Default: 18h 1:0 R/W I_Code [15:14] I_Code [13] / I_code calibrated setting I_Code [12] / P_code calibrated setting I_Code [11] / Overwrite 0 to 1 return a new PFD calibrated value. I_Code [10] / 0: Old PFD 1: New PFD I_Code [9:8] / For old I or New_I mechanism depending on 0xc9[0] & 0xc9[4] Default: 18h Function Address: CB P_CODE Bit Mode 7 Reserved --- 71 Realtek RTD2523/2513 6:5 R/W I_Code[17:16]//00 4:0 R/W P_Code[4:0] //0x18 N P_Code=2 * γ ; N is bit number, N=32 ; γ is ratio of phase error correction. Default γ=2-7 , P_Code=225 ; P[4:0]=25-1=24=5’h18 ; P[4:0] can not bigger than 5’h1F-6=5’h19 . When phase-error is too large, P_Code will enlarge to at most 64 times automatically. I_Code=(α*2N)/PLLDIV ; N is bit number, N=32 ; α is ratio of frequency error correction. Default α=2-9, PLLDIV=1344, I_Code=6241=18’h01861. α must be smaller than γ. Address: CC PLLDIV_HI Bit Mode Function 3:0 R/W PLL Divider Ratio Control. High-Byte [11:8]. Default: 05h Address: CD PLLDIV_LO Default: 3Fh Bit Mode Function 7:0 R/W PLL Divider Ratio Control. Low-Byte [7:0]. This register determines the number of output pixel per horizontal line. PLL derives the sampling clock and data output clock (DCLK) from input HSYNC. The real operation Divider Ratio = PLLDIV+1 The power up default value of PLLDIV is 053Fh(=1343, VESA timing standard, 1024x768 60Hz, Horizontal time). The setting of PLLDIV must include sync, back-porch, left border, active, right border, and front-porch times. Control-Register CC & CD will filled in when Control-Register CD is written. Address: CE PFD Calibrated Results Function Bit Mode 5:0 R/W PFD Calibrated Results This register determines the number of output pixel per horizontal line. PLL derives the sampling clock and data output Address: CF www.DataSheet4U.com Reserved 72 Realtek Phase Lock Loop Address: D0 DPLL_CRNT (DPLL Charge Pump Current Register) Bit Mode Function 7:3 R/W Charge Pump Current Idch [4:0] 2 R Watch Dog Status 0: Normal 1: Abnormal 0 R/W Charge Pump Current Idch [5] I = 2.5u + D0 [3]*2.5u + D0 [4]*5u + D0 [5]*10u + D0[6]*20u + D0[7]*30u (A) Ich (Charge pump current) = I * ( D0[0] + 1) / 2 Address: D1 DPLL_M (DPLL M Divider Register) Bit Mode 7:0 R/W DPM value – 2 RTD2523/2513 Default: 00010xx0b Default: 01111101b Function www.DataSheet4U.com Address: D2 DPLL_N (DPLLN Divider Register) Default: 00001010b Bit Mode Function 7:6 R/W DPLL Output Divider (00à 1, 01 à 1/2, 10à1/4, 11à1/8) // (01) 5 R/W DPLL Spread Spectrum Enable 0: Disable 1: Enable 4 R/W Offset Frequency Direction Induced by Spread Spectrum 0: Upward 1: Downward 3:0 R/W DPN value – 2 DPLL must be twice DCLK frequency and max DPLL frequency is 320MHz. Assume DPLL_M=0x7D, DPM =0x7D+2=127; DPLL_N=0x0A, DPN=0x0A+2=12; Divider=1/4, F_IN = 24.576MHz. F_DPLL = F_IN x DPM / DPN x Divider = 24.576 x 127 / 12 / 4 = 65.024MHz. If LPF_Mode = 1, suppose DPM =110, DPN = 12, Ich = Idch[000100] = 6.25uA, DPLL=225MHz, then DPM / Ich =17.6. Please keep the ratio as constant. If LPF_Mode = 0, suppose DPM =46, DPN = 5, Ich = Idch [101010] =27.5uA, DPLL=226MHz, then DPM / Ich = 1.67. Please keep the ratio as constant. Address: D3 DPLL_FILTER (Loop Filter Control Register) Function Bit Mode 7 R/W DPLL Output Enable 0: Enable 1: Disable 6:3 R/W Reserved 2 R/W LPF Mode 0: DPN