S1D15609D00B

8. S1D15605 Series Rev. 2.4a Contents 1. DESCRIPTION ................................................................................................................................................ 8-1 2. FEATURES ...................................................................................................................................................... 8-1 3. BLOCK DIAGRAM ........................................................................................................................................... 8-3 4. PAD ................................................................................................................................................................. 8-4 5. PIN DESCRIPTIONS .....................................................................................................................................8-20 6. DESCRIPTION OF FUNCTIONS .................................................................................................................. 8-24 7. COMMANDS .................................................................................................................................................8-49 8. COMMAND DESCRIPTION .......................................................................................................................... 8-58 9. ABSOLUTE MAXIMUM RATINGS ................................................................................................................ 8-64 10. DC CHARACTERISTICS ...............................................................................................................................8-65 11. TIMING CHARACTERISTICS .......................................................................................................................8-73 12. THE MPU INTERFACE (REFERENCE EXAMPLES) ...................................................................................8-81 13. CONNECTIONS BETWEEN LCD DRIVERS (REFERENCE EXAMPLE) ..................................................... 8-82 14. CONNECTIONS BETWEEN LCD DRIVERS (REFERENCE EXAMPLES) .................................................. 8-83 15. A SAMPLE TCP PIN ASSIGNMENT .............................................................................................................8-84 16. EXTERNAL VIEW OF TCP PINS .................................................................................................................. 8-85 –i– Rev. 2.4a S1D15605 Series 1. DESCRIPTION The S1D15605 Series is a series of single-chip dot matrix liquid crystal display drivers that can be connected directly to a microprocessor bus. 8-bit parallel or serial display data sent from the microprocessor is stored in the internal display data RAM and the chip generates a liquid crystal drive signal independent of the microprocessor. Because the chips in the S1D15605 ***** contain 65 × 132 bits of display data RAM and there is a 1-to-1 correspondence between the liquid crystal panel pixels and the internal RAM bits, these chips enable displays with a high degree of freedom. The S1D15606***** chips contain 49 common output circuits and 132 segment output circuits, so that a single chip can drive a 49 × 1 32 dot display (capable of displaying 8 columns × 4 rows of a 16 × 16 dot kanji font). The S1D15607***** chips contain 33 common output circuits and 132 segment output circuits, so that a single chip can drive 33 × 132 dot display (capable of displaying 8 columns × 2 rows of 16 × 16 dot kanji fonts). Thanks to the built-in 55 common output circuits and 132 segment output circuits, the S1D15608***** is capable of displaying 55 × 132 dots (11 columns × 4 lines using 11 × 12 dots Kanji font) with a single chip. The S1D15609***** chips contain 53 common output circuits and 132 segment output circuits, so that a single chip can drive 53 × 132 dot display (capable of displaying 11 columns × 4 r ows of 11 × 1 2 dot kanji fonts). Moreover, the capacity of the display can be extended through the use of master/slave structures between chips. The chips are able to minimize power consumption because no external operating clock is necessary for the display data RAM read/write operation. Furthermore, because each chip is equipped internally with a lowpower liquid crystal driver power supply, resistors for liquid crystal driver power voltage adjustment and a display clock CR oscillator circuit, the S1D15605 Series chips can be used to create the lowest power display system with the fewest components for highperformance portable devices. 2. FEATURES • Direct display of RAM data through the display data RAM. RAM bit data: “1” Display on “0” Display off (during normal display) • RAM capacity 65 × 132 = 8580 bits • Display driver circuits S1D15605 ***** :65 common output and 132 segment outputs S1D15606 ***** :49 common output and 132 segment outputs S1D15607 *****:33 common outputs and 132 segment outputs S1D15608 *****:55 common outputs and 132 segment outputs S1D15609 *****:53 common outputs and 132 segment outputs Rev. 2.4a • High-speed 8-bit MPU interface (The chip can be connected directly to the both the 80x86 series MPUs and the 68000 series MPUs) /Serial interfaces are supported. • Abundant command functions Display data Read/Write, display ON/OFF, Normal/ Reverse display mode, page address set, display start line set, column address set, status read, display all points ON/OFF, LCD bias set, electronic volume, read/modify/write, segment driver direction select, power saver, static indicator, common output status select, V5 voltage regulation internal resistor ratio set. • Static drive circuit equipped internally for indicators. (1 system, with variable flashing speed.) • Low-power liquid crystal display power supply circuit equipped internally. Booster circuit (with Boost ratios of Double/Triple/ Quad, where the step-up voltage reference power supply can be input externally) High-accuracy voltage adjustment circuit (Thermal gradient –0.05%/°C or –0.2%/ °C or external input) V5 voltage regulator resistors equipped internally, V1 to V4 voltage divider resistors equipped internally, electronic volume function equipped internally, voltage follower. • CR oscillator circuit equipped internally (external clock can also be input) • Extremely low power consumption Operating power when the built-in power supply is used (an example) S1D15605D00B* 81 µA (VDD – VSS = VDD – VSS2= /S1D15605D11B* 3.0 V, Quad voltage, V5 – VDD = –11.0 V) S1D15606D00B* 43 µA (VDD – VSS = VDD – VSS2 = /S1D15606D11B* 3.0 V, Triple voltage, V5 – VDD = –8.0 V) S1D15607D00B* 29 µA (VDD – VSS = VDD – VSS2 = /S1D15607D11B* 3.0 V, Triple voltage, V5 – VDD = –8.0 V) S1D15608D00B*/S1D15608D11B* /S1D15609D00B*/S1D15609D11B* 46µA (VDD – VSS = VDD – VSS2 = 3.0 V, Triple voltage, V5 – VDD = – 8.0 V) Conditions: When all displays are in white and the normal mode is selected (see page 60 *12 for details of the conditions). • Power supply Operable on the low 1.8 voltage Logic power supply VDD – VSS = 1.8 V to 5.5 V Boost reference voltage: V DD – VSS2 = 1.8 V to 6.0 V Liquid crystal drive power supply: V5 – VDD = –4.5 V to –16.0 V • Wide range of operating temperatures: –40 to 85°C • CMOS process • Shipping forms include bare chip and TCP. • These chips not designed for resistance to light or resistance to radiation. EPSON 8–1 S1D15605 Series Series Specifications Bare chip Product Name S1D15605D00B* S1D15605D11B* S1D15605D11E* S1D15605D01B* S1D15605D02B* S1D15606D00B* S1D15606D01B* S1D15606D02B* S1D15606D11B* S1D15607D00B* S1D15607D01B* S1D15607D02B* S1D15607D11B* S1D15608D00B* S1D15609D00B* TCP Product Name Duty Bias SEG Dr COM Dr 1/65 1/9, 1/7 132 65 S1D15605T00** 1/49 1/8, 1/6 132 49 S1D15606T00** 1/33 1/6, 1/5 132 33 S1D15607T00** Product name of custom TCP can be coped with specially. VREG Temperature Gradient –0.05%/°C –0.05%/°C –0.05%/°C Duty 1/65 1/65 1/65 1/65 1/65 1/49 1/49 1/49 1/49 1/33 1/33 1/33 1/33 1/55 1/53 Bias 1/9, 1/7 1/9, 1/7 1/9, 1/7 1/9, 1/7 1/9, 1/7 1/8, 1/6 1/8, 1/6 1/8, 1/6 1/8, 1/6 1/6, 1/5 1/6, 1/5 1/6, 1/5 1/6, 1/5 1/8, 1/6 1/8, 1/6 SEG Dr 132 132 132 132 132 132 132 132 132 132 132 132 132 132 132 COM Dr 65 65 65 65 65 49 49 49 49 33 33 33 33 55 53 VREG Temperature Gradient –0.05%/°C –0.05%/°C –0.05%/°C –0.2%/°C External Input –0.05%/°C –0.2%/°C External Input –0.05%/°C –0.05%/°C –0.2%/°C External Input –0.05%/°C –0.05%/°C –0.05%/°C Chip Thickness 625 µm 625 µm 300 µm 625 µm 625 µm 625 µm 625 µm 625 µm 625 µm 625 µm 625 µm 625 µm 625 µm 625 µm 625 µm 8–2 EPSON Rev. 2.4a S1D15605 Series 3. BLOCK DIAGRAM Example: S1D15605 ***** SEG131 COM63 Display timing generation circuit ••••••••••••••••••••••••• •••••••••• VSS VDD V2 V3 V4 V5 Shift register COMS V1 SEG Drivers COM Drivers CAP1+ CAP1– Page address circuit CAP2+ CAP2– CAP3+ VOUT Power supply circuit Display data latch circuit COMS COM0 SEG0 Line address circuit FRS FR CL DOF M/S I/O buffer Display data RAM 132 x 65 VSS2 VR VRS IRS HPM Column address circuit Oscillator circuit CLS Bus holder Command decoder Status MPU interface D6 (SCL) WR (R/W) D7 (SI) RD (E) RES CS1 CS2 P/S D5 D4 D3 D2 D1 Rev. 2.4a EPSON D0 A0 8–3 S1D15605 Series 4. PAD Pad Layout 99 100 S1D15605 Series Die No. (0, 0) D1565D0B 1 309 134 135 274 275 Chip Size Chip Thickness Bump Pitch Bump Size 10.82 mm × 2.81 mm 0.625 mm 71 µm (Min.) PAD No. 1~24 PAD No. 25~82 PAD No. 83~99 PAD No. 100 PAD No. 101~133 PAD No. 134 PAD No. 135 PAD No. 136~273 PAD No. 274 PAD No. 275 PAD No. 276~308 PAD No. 309 17 µm (Typ.) 85 µm × 64 µm × 85 µm × 85 µm × 85 µm × 85 µm × 73 µm × 47 µm × 73 µm × 86 µm × 85 µm × 85 µm × 85 µm 85 µm 85 µm 73 µm 47 µm 73 µm 85 µm 85 µm 85 µm 73 µm 47 µm 73 µm Bump Height 8–4 EPSON Rev. 2.4a S1D15605 Series S1D15605***** Pad Center Coordinates Units: µm PAD PIN No. Name 1 (NC) 2 FRS 3 FR 4 CL 5 DOF 6 TEST0 7 V SS 8 CS1 9 CS2 10 VDD 11 RES 12 A0 13 V SS 14 WR, R/W 15 RD, E 16 VDD 17 D0 18 D1 19 D2 20 D3 21 D4 22 D5 23 D6, SCL 24 D7, SI 25 (NC) 26 VDD 27 VDD 28 VDD 29 VDD 30 V SS 31 V SS 32 V SS 33 V SS2 34 V SS2 35 V SS2 36 V SS2 37 (NC) 38 VOUT 39 VOUT 40 CAP3– X 4973 4853 4734 4614 4494 4375 4255 4136 4016 3896 3777 3657 3538 3418 3298 3179 3059 2940 2820 2700 2581 2461 2342 2222 2119 2030 1941 1852 1763 1674 1585 1496 1407 1318 1229 1140 1051 962 873 784 Y 1246 PAD No. 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 PIN Name CAP3– (NC) CAP1+ CAP1+ CAP1– CAP1– CAP2– CAP2– CAP2+ CAP2+ V SS V SS VRS VRS VDD VDD V1 V1 V2 V2 (NC) V3 V3 V4 V4 V5 V5 (NC) VR VR VDD VDD TEST1 TEST1 TEST2 TEST2 (NC) TEST3 TEST3 TEST4 X 695 605 516 427 338 249 160 71 –18 –107 –196 –285 –374 –463 –552 –641 –730 –819 –908 –997 –1086 –1176 –1265 –1354 –1443 –1532 –1621 –1710 –1799 –1888 –1977 –2066 –2155 –2244 –2333 –2422 –2511 –2600 –2689 –2778 Y 1246 PAD No. 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 PIN Name TEST4 (NC) V DD M/S CLS VSS C86 P/S V DD HPM VSS IRS V DD TEST5 TEST6 TEST7 TEST8 TEST9 (NC) (NC) COM31 COM30 COM29 COM28 COM27 COM26 COM25 COM24 COM23 COM22 COM21 COM20 COM19 COM18 COM17 COM16 COM15 COM14 COM13 COM12 X –2867 –2957 –3059 –3179 –3298 –3418 –3538 –3657 –3777 –3896 –4016 –4136 –4255 –4375 –4494 –4614 –4734 –4853 –4973 –5252 Y 1246 1248 1163 1090 1017 945 872 799 727 654 581 509 436 363 291 218 145 73 0 –73 –145 –218 Rev. 2.4a EPSON 8–5 S1D15605 Series Units: µm PAD No. 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 PIN Name COM11 COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 COMS (NC) (NC) (NC) (NC) (NC) SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 X –5252 Y –291 –363 –436 –509 –581 –654 –727 –800 –872 –945 –1018 –1090 –1163 –1248 –1246 PAD No. 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 PIN Name SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 X –3127 –3055 –2983 –2912 –2840 –2768 –2696 –2624 –2552 –2480 –2408 –2336 –2265 –2193 –2121 –2049 –1977 –1905 –1833 –1761 –1689 –1618 –1546 –1474 –1402 –1330 –1258 –1186 –1114 –1042 –971 –899 –827 –755 –683 –611 –539 –467 –395 –324 Y –1246 PAD PIN No. Name 201 SEG62 202 SEG63 203 SEG64 204 SEG65 205 SEG66 206 SEG67 207 SEG68 208 SEG69 209 SEG70 210 SEG71 211 SEG72 212 SEG73 213 SEG74 214 SEG75 215 SEG76 216 SEG77 217 SEG78 218 SEG79 219 SEG80 220 SEG81 221 SEG82 222 SEG83 223 SEG84 224 SEG85 225 SEG86 226 SEG87 227 SEG88 228 SEG89 229 SEG90 230 SEG91 231 SEG92 232 SEG93 233 SEG94 234 SEG95 235 SEG96 236 SEG97 237 SEG98 238 SEG99 239 SEG100 240 SEG101 X –252 –180 –108 –36 36 108 180 252 324 395 467 539 611 683 755 827 899 971 1042 1114 1186 1258 1330 1402 1474 1546 1618 1689 1761 1833 1905 1977 2049 2121 2193 2265 2336 2408 2480 2552 Y –1246 –5009 –4924 –4853 –4781 –4709 –4637 –4565 –4493 –4421 –4349 –4277 –4206 –4134 –4062 –3990 –3918 –3846 –3774 –3702 –3630 –3559 –3487 –3415 –3343 –3271 –3199 8–6 EPSON Rev. 2.4a S1D15605 Series Units: µm PAD No. 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 PIN Name SEG102 SEG103 SEG104 SEG105 SEG106 SEG107 SEG108 SEG109 SEG110 SEG111 SEG112 SEG113 SEG114 SEG115 SEG116 SEG117 SEG118 SEG119 SEG120 SEG121 SEG122 SEG123 SEG124 SEG125 SEG126 SEG127 SEG128 SEG129 SEG130 SEG131 (NC) (NC) (NC) (NC) (NC) COM32 COM33 COM34 COM35 COM36 X 2624 2696 2768 2840 2912 2983 3055 3127 3199 3271 3343 3415 3487 3558 3630 3702 3774 3846 3918 3990 4062 4134 4206 4277 4349 4421 4493 4565 4637 4709 4781 4853 4924 5009 5252 Y –1246 PAD No. 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 PIN Name COM37 COM38 COM39 COM40 COM41 COM42 COM43 COM44 COM45 COM46 COM47 COM48 COM49 COM50 COM51 COM52 COM53 COM54 COM55 COM56 COM57 COM58 COM59 COM60 COM61 COM62 COM63 COMS (NC) X 5252 Y –800 –727 –654 –581 –509 –436 –363 –291 –218 –145 –73 0 73 145 218 291 363 436 509 581 654 727 799 872 945 1017 1090 1163 1248 –1248 –1163 –1090 –1018 –945 –872 Rev. 2.4a EPSON 8–7 S1D15605 Series S1D15606***** Pad Center Coordinates Units: µm PAD PIN No. Name 1 (NC) 2 FRS 3 FR 4 CL 5 DOF 6 TEST0 7 VSS 8 CS1 9 CS2 10 VDD 11 RES 12 A0 13 VSS 14 WR, R/W 15 RD, E 16 VDD 17 D0 18 D1 19 D2 20 D3 21 D4 22 D5 23 D6, SCL 24 D7, SI 25 (NC) 26 VDD 27 VDD 28 VDD 29 VDD 30 VSS 31 VSS 32 VSS 33 VSS2 34 VSS2 35 VSS2 36 VSS2 37 (NC) 38 V OUT 39 V OUT 40 CAP3– X 4973 4853 4734 4614 4494 4375 4255 4136 4016 3896 3777 3657 3538 3418 3298 3179 3059 2940 2820 2700 2581 2461 2342 2222 2119 2030 1941 1852 1763 1674 1585 1496 1407 1318 1229 1140 1051 962 873 784 Y 1246 PAD No. 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 PIN Name CAP3– (NC) CAP1+ CAP1+ CAP1– CAP1– CAP2– CAP2– CAP2+ CAP2+ VSS VSS V RS V RS VDD VDD V1 V1 V2 V2 (NC) V3 V3 V4 V4 V5 V5 (NC) VR VR VDD VDD TEST1 TEST1 TEST2 TEST2 (NC) TEST3 TEST3 TEST4 X 695 605 516 427 338 249 160 71 –18 –107 –196 –285 –374 –463 –552 –641 –730 –819 –908 –997 –1086 –1176 –1265 –1354 –1443 –1532 –1621 –1710 –1799 –1888 –1977 –2066 –2155 –2244 –2333 –2422 –2511 –2600 –2689 –2778 Y 1246 PAD No. 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 PIN Name TEST4 (NC) VDD M/S CLS V SS C86 P/S VDD HPM V SS IRS VDD TEST5 TEST6 TEST7 TEST8 TEST9 (NC) (NC) (NC) (NC) COM23 (NC) COM22 (NC) COM21 COM20 COM19 COM18 COM17 COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8 X –2867 –2957 –3059 –3179 –3298 –3418 –3538 –3657 –3777 –3896 –4016 –4136 –4255 –4375 –4494 –4614 –4734 –4853 –4973 –5252 Y 1246 1248 1163 1090 1017 945 872 799 727 654 581 509 436 363 291 218 145 73 0 –73 –145 –218 8–8 EPSON Rev. 2.4a S1D15605 Series Units: µm PAD No. 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 PIN Name COM7 COM6 COM5 COM4 COM3 COM2 COM1 (NC) COM0 (NC) COMS (NC) (NC) (NC) (NC) (NC) (NC) (NC) SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 X –5252 Y –291 –363 –436 –509 –581 –654 –727 –800 –872 –945 –1018 –1090 –1163 –1248 –1246 PAD No. 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 PIN Name SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 X –3127 –3055 –2983 –2912 –2840 –2768 –2696 –2624 –2552 –2480 –2408 –2336 –2265 –2193 –2121 –2049 –1977 –1905 –1833 –1761 –1689 –1618 –1546 –1474 –1402 –1330 –1258 –1186 –1114 –1042 –971 –899 –827 –755 –683 –611 –539 –467 –395 –324 Y –1246 PAD PIN No. Name 201 SEG62 202 SEG63 203 SEG64 204 SEG65 205 SEG66 206 SEG67 207 SEG68 208 SEG69 209 SEG70 210 SEG71 211 SEG72 212 SEG73 213 SEG74 214 SEG75 215 SEG76 216 SEG77 217 SEG78 218 SEG79 219 SEG80 220 SEG81 221 SEG82 222 SEG83 223 SEG84 224 SEG85 225 SEG86 226 SEG87 227 SEG88 228 SEG89 229 SEG90 230 SEG91 231 SEG92 232 SEG93 233 SEG94 234 SEG95 235 SEG96 236 SEG97 237 SEG98 238 SEG99 239 SEG100 240 SEG101 X –252 –180 –108 –36 36 108 180 252 324 395 467 539 611 683 755 827 899 971 1042 1114 1186 1258 1330 1402 1474 1546 1618 1689 1761 1833 1905 1977 2049 2121 2193 2265 2336 2408 2480 2552 Y –1246 –5009 –4924 –4853 –4781 –4709 –4637 –4565 –4493 –4421 –4349 –4277 –4206 –4134 –4062 –3990 –3918 –3846 –3774 –3702 –3630 –3559 –3487 –3415 –3343 –3271 –3199 Rev. 2.4a EPSON 8–9 S1D15605 Series Units: µm PAD No. 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 PIN Name SEG102 SEG103 SEG104 SEG105 SEG106 SEG107 SEG108 SEG109 SEG110 SEG111 SEG112 SEG113 SEG114 SEG115 SEG116 SEG117 SEG118 SEG119 SEG120 SEG121 SEG122 SEG123 SEG124 SEG125 SEG126 SEG127 SEG128 SEG129 SEG130 SEG131 (NC) (NC) (NC) (NC) (NC) (NC) (NC) COM24 (NC) COM25 X 2624 2696 2768 2840 2912 2983 3055 3127 3199 3271 3343 3415 3487 3558 3630 3702 3774 3846 3918 3990 4062 4134 4206 4277 4349 4421 4493 4565 4637 4709 4781 4853 4924 5009 5252 Y –1246 PAD No. 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 PIN Name (NC) COM26 COM27 COM28 COM29 COM30 COM31 COM32 COM33 COM34 COM35 COM36 COM37 COM38 COM39 COM40 COM41 COM42 COM43 COM44 COM45 COM46 (NC) COM47 (NC) COMS (NC) (NC) (NC) X 5252 Y –800 –727 –654 –581 –509 –436 –363 –291 –218 –145 –73 0 73 145 218 291 363 436 509 581 654 727 799 872 945 1017 1090 1163 1248 –1248 –1163 –1090 –1018 –945 –872 8–10 EPSON Rev. 2.4a S1D15605 Series S1D15607***** Pad Center Coordinates Units: µm PAD PIN No. Name 1 (NC) 2 FRS 3 FR 4 CL 5 DOF 6 TEST0 7 V SS 8 CS1 9 CS2 10 VDD 11 RES 12 A0 13 V SS 14 WR, R/W 15 RD, E 16 VDD 17 D0 18 D1 19 D2 20 D3 21 D4 22 D5 23 D6, SCL 24 D7, SI 25 (NC) 26 VDD 27 VDD 28 VDD 29 VDD 30 V SS 31 V SS 32 V SS 33 V SS2 34 V SS2 35 V SS2 36 V SS2 37 (NC) 38 VOUT 39 VOUT 40 CAP3– X 4973 4853 4734 4614 4494 4375 4255 4136 4016 3896 3777 3657 3538 3418 3298 3179 3059 2940 2820 2700 2581 2461 2342 2222 2119 2030 1941 1852 1763 1674 1585 1496 1407 1318 1229 1140 1051 962 873 784 Y 1246 PAD No. 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 PIN Name CAP3– (NC) CAP1+ CAP1+ CAP1– CAP1– CAP2– CAP2– CAP2+ CAP2+ VSS VSS VRS VRS V DD V DD V1 V1 V2 V2 (NC) V3 V3 V4 V4 V5 V5 (NC) VR VR V DD V DD TEST1 TEST1 TEST2 TEST2 (NC) TEST3 TEST3 TEST4 X 695 605 516 427 338 249 160 71 –18 –107 –196 –285 –374 –463 –552 –641 –730 –819 –908 –997 –1086 –1176 –1265 –1354 –1443 –1532 –1621 –1710 –1799 –1888 –1977 –2066 –2155 –2244 –2333 –2422 –2511 –2600 –2689 –2778 Y 1246 PAD No. 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 PIN Name TEST4 (NC) VDD M/S CLS VSS C86 P/S VDD HPM VSS IRS VDD TEST5 TEST6 TEST7 TEST8 TEST9 (NC) (NC) COM15 COM15 COM14 COM14 COM13 COM13 COM12 COM12 COM11 COM11 COM10 COM10 COM9 COM9 COM8 COM8 COM7 COM7 COM6 COM6 X –2867 –2957 –3059 –3179 –3298 –3418 –3538 –3657 –3777 –3896 –4016 –4136 –4255 –4375 –4494 –4614 –4734 –4853 –4973 –5252 Y 1246 1248 1163 1090 1017 945 872 799 727 654 581 509 436 363 291 218 145 73 0 –73 –145 –218 Rev. 2.4a EPSON 8–11 S1D15605 Series Units: µm PAD No. 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 PIN Name COM5 COM5 COM4 COM4 COM3 COM3 COM2 COM2 COM1 COM1 COM0 COM0 COMS (NC) (NC) (NC) (NC) (NC) SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 X –5252 Y –291 –363 –436 –509 –581 –654 –727 –800 –872 –945 –1018 –1090 –1163 –1248 –1246 PAD No. 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 PIN Name SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 X –3127 –3055 –2983 –2912 –2840 –2768 –2696 –2624 –2552 –2480 –2408 –2336 –2265 –2193 –2121 –2049 –1977 –1905 –1833 –1761 –1689 –1618 –1546 –1474 –1402 –1330 –1258 –1186 –1114 –1042 –971 –899 –827 –755 –683 –611 –539 –467 –395 –324 Y –1246 PAD PIN No. Name 201 SEG62 202 SEG63 203 SEG64 204 SEG65 205 SEG66 206 SEG67 207 SEG68 208 SEG69 209 SEG70 210 SEG71 211 SEG72 212 SEG73 213 SEG74 214 SEG75 215 SEG76 216 SEG77 217 SEG78 218 SEG79 219 SEG80 220 SEG81 221 SEG82 222 SEG83 223 SEG84 224 SEG85 225 SEG86 226 SEG87 227 SEG88 228 SEG89 229 SEG90 230 SEG91 231 SEG92 232 SEG93 233 SEG94 234 SEG95 235 SEG96 236 SEG97 237 SEG98 238 SEG99 239 SEG100 240 SEG101 X –252 –180 –108 –36 36 108 180 252 324 395 467 539 611 683 755 827 899 971 1042 1114 1186 1258 1330 1402 1474 1546 1618 1689 1761 1833 1905 1977 2049 2121 2193 2265 2336 2408 2480 2552 Y –1246 –5009 –4924 –4853 –4781 –4709 –4637 –4565 –4493 –4421 –4349 –4277 –4206 –4134 –4062 –3990 –3918 –3846 –3774 –3702 –3630 –3559 –3487 –3415 –3343 –3271 –3199 8–12 EPSON Rev. 2.4a S1D15605 Series Units: µm PAD No. 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 PIN Name SEG102 SEG103 SEG104 SEG105 SEG106 SEG107 SEG108 SEG109 SEG110 SEG111 SEG112 SEG113 SEG114 SEG115 SEG116 SEG117 SEG118 SEG119 SEG120 SEG121 SEG122 SEG123 SEG124 SEG125 SEG126 SEG127 SEG128 SEG129 SEG130 SEG131 (NC) (NC) (NC) (NC) (NC) COM16 COM16 COM17 COM17 COM18 X 2624 2696 2768 2840 2912 2983 3055 3127 3199 3271 3343 3415 3487 3558 3630 3702 3774 3846 3918 3990 4062 4134 4206 4277 4349 4421 4493 4565 4637 4709 4781 4853 4924 5009 5252 Y –1246 PAD No. 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 PIN Name COM18 COM19 COM19 COM20 COM20 COM21 COM21 COM22 COM22 COM23 COM23 COM24 COM24 COM25 COM25 COM26 COM26 COM27 COM27 COM28 COM28 COM29 COM29 COM30 COM30 COM31 COM31 COMS (NC) X 5252 Y –800 –727 –654 –581 –509 –436 –363 –291 –218 –145 –73 0 73 145 218 291 363 436 509 581 654 727 799 872 945 1017 1090 1163 1248 –1248 –1163 –1090 –1018 –945 –872 Rev. 2.4a EPSON 8–13 S1D15605 Series S1D15608***** Pad Center Coordinates Units: µm PAD PIN No. Name 1 (NC) 2 FRS 3 FR 4 CL 5 DOF 6 TEST0 7 VSS 8 CS1 9 CS2 10 VDD 11 RES 12 A0 13 VSS 14 WR, R/W 15 RD, E 16 VDD 17 D0 18 D1 19 D2 20 D3 21 D4 22 D5 23 D6, SCL 24 D7, SI 25 (NC) 26 VDD 27 VDD 28 VDD 29 VDD 30 VSS 31 VSS 32 VSS 33 VSS2 34 VSS2 35 VSS2 36 VSS2 37 (NC) 38 V OUT 39 V OUT 40 CAP3– X 4973 4853 4734 4614 4494 4375 4255 4136 4016 3896 3777 3657 3538 3418 3298 3179 3059 2940 2820 2700 2581 2461 2342 2222 2119 2030 1941 1852 1763 1674 1585 1496 1407 1318 1229 1140 1051 962 873 784 Y 1246 PAD No. 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 PIN Name CAP3– (NC) CAP1+ CAP1+ CAP1– CAP1– CAP2– CAP2– CAP2+ CAP2+ VSS VSS VRS VRS VDD VDD V1 V1 V2 V2 (NC) V3 V3 V4 V4 V5 V5 (NC) VR VR VDD VDD TEST1 TEST1 TEST2 TEST2 (NC) TEST3 TEST3 TEST4 X 695 605 516 427 338 249 160 71 –18 –107 –196 –285 –374 –463 –552 –641 –730 –819 –908 –997 –1086 –1176 –1265 –1354 –1443 –1532 –1621 –1710 –1799 –1888 –1977 –2066 –2155 –2244 –2333 –2422 –2511 –2600 –2689 –2778 Y 1246 PAD No. 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 PIN Name TEST4 (NC) VDD M/S CLS V SS C86 P/S VDD HPM V SS IRS VDD TEST5 TEST6 TEST7 TEST8 TEST9 (NC) (NC) (NC) COM26 (NC) COM25 COM25 COM23 COM22 COM21 COM20 COM19 COM18 COM17 COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9 X –2867 –2957 –3059 –3179 –3298 –3418 –3538 –3657 –3777 –3896 –4016 –4136 –4255 –4375 –4494 –4614 –4734 –4853 –4973 –5252 Y 1246 1248 1163 1090 1017 945 872 799 727 654 581 509 436 363 291 218 145 73 0 –73 –145 –218 8–14 EPSON Rev. 2.4a S1D15605 Series Units: µm PAD No. 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 PIN Name COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 (NC) COM0 (NC) COMS (NC) (NC) (NC) (NC) (NC) (NC) SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 X –5252 Y –291 –363 –436 –509 –581 –654 –727 –800 –872 –945 –1018 –1090 –1163 –1248 –1246 PAD No. 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 PIN Name SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 X –3127 –3055 –2983 –2912 –2840 –2768 –2696 –2624 –2552 –2480 –2408 –2336 –2265 –2193 –2121 –2049 –1977 –1905 –1833 –1761 –1689 –1618 –1546 –1474 –1402 –1330 –1258 –1186 –1114 –1042 –971 –899 –827 –755 –683 –611 –539 –467 –395 –324 Y –1246 PAD PIN No. Name 201 SEG62 202 SEG63 203 SEG64 204 SEG65 205 SEG66 206 SEG67 207 SEG68 208 SEG69 209 SEG70 210 SEG71 211 SEG72 212 SEG73 213 SEG74 214 SEG75 215 SEG76 216 SEG77 217 SEG78 218 SEG79 219 SEG80 220 SEG81 221 SEG82 222 SEG83 223 SEG84 224 SEG85 225 SEG86 226 SEG87 227 SEG88 228 SEG89 229 SEG90 230 SEG91 231 SEG92 232 SEG93 233 SEG94 234 SEG95 235 SEG96 236 SEG97 237 SEG98 238 SEG99 239 SEG100 240 SEG101 X –252 –180 –108 –36 36 108 180 252 324 395 467 539 611 683 755 827 899 971 1042 1114 1186 1258 1330 1402 1474 1546 1618 1689 1761 1833 1905 1977 2049 2121 2193 2265 2336 2408 2480 2552 Y –1246 –5009 –4924 –4853 –4781 –4709 –4637 –4565 –4493 –4421 –4349 –4277 –4206 –4134 –4062 –3990 –3918 –3846 –3774 –3702 –3630 –3559 –3487 –3415 –3343 –3271 –3199 Rev. 2.4a EPSON 8–15 S1D15605 Series Units: µm PAD No. 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 PIN Name SEG102 SEG103 SEG104 SEG105 SEG106 SEG107 SEG108 SEG109 SEG110 SEG111 SEG112 SEG113 SEG114 SEG115 SEG116 SEG117 SEG118 SEG119 SEG120 SEG121 SEG122 SEG123 SEG124 SEG125 SEG126 SEG127 SEG128 SEG129 SEG130 SEG131 (NC) (NC) (NC) (NC) (NC) (NC) COM27 (NC) COM28 (NC) X 2624 2696 2768 2840 2912 2983 3055 3127 3199 3271 3343 3415 3487 3558 3630 3702 3774 3846 3918 3990 4062 4134 4206 4277 4349 4421 4493 4565 4637 4709 4781 4853 4924 5009 5252 Y –1246 PAD No. 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 PIN Name COM29 COM30 COM31 COM32 COM33 COM34 COM35 COM36 COM37 COM38 COM39 COM40 COM41 COM42 COM43 COM44 COM45 COM46 COM47 COM48 COM48 COM50 COM51 COM52 COM53 (NC) COMS (NC) (NC) X 5252 Y –800 –727 –654 –581 –509 –436 –363 –291 –218 –145 –73 0 73 145 218 291 363 436 509 581 654 727 799 872 945 1017 1090 1163 1248 –1248 –1163 –1090 –1018 –945 –872 8–16 EPSON Rev. 2.4a S1D15605 Series S1D15609***** Pad Center Coordinates Units: µm PAD PIN No. Name 1 (NC) 2 FRS 3 FR 4 CL 5 DOF 6 TEST0 7 V SS 8 CS1 9 CS2 10 VDD 11 RES 12 A0 13 V SS 14 WR, R/W 15 RD, E 16 VDD 17 D0 18 D1 19 D2 20 D3 21 D4 22 D5 23 D6, SCL 24 D7, SI 25 (NC) 26 VDD 27 VDD 28 VDD 29 VDD 30 V SS 31 V SS 32 V SS 33 V SS2 34 V SS2 35 V SS2 36 V SS2 37 (NC) 38 VOUT 39 VOUT 40 CAP3– X 4973 4853 4734 4614 4494 4375 4255 4136 4016 3896 3777 3657 3538 3418 3298 3179 3059 2940 2820 2700 2581 2461 2342 2222 2119 2030 1941 1852 1763 1674 1585 1496 1407 1318 1229 1140 1051 962 873 784 Y 1246 PAD No. 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 PIN Name CAP3– (NC) CAP1+ CAP1+ CAP1– CAP1– CAP2– CAP2– CAP2+ CAP2+ VSS VSS VRS VRS V DD V DD V1 V1 V2 V2 (NC) V3 V3 V4 V4 V5 V5 (NC) VR VR V DD V DD TEST1 TEST1 TEST2 TEST2 (NC) TEST3 TEST3 TEST4 X 695 605 516 427 338 249 160 71 –18 –107 –196 –285 –374 –463 –552 –641 –730 –819 –908 –997 –1086 –1176 –1265 –1354 –1443 –1532 –1621 –1710 –1799 –1888 –1977 –2066 –2155 –2244 –2333 –2422 –2511 –2600 –2689 –2778 Y 1246 PAD No. 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 PIN Name TEST4 (NC) VDD M/S CLS VSS C86 P/S VDD HPM VSS IRS VDD TEST5 TEST6 TEST7 TEST8 TEST9 (NC) (NC) (NC) COM25 (NC) COM24 (NC) COM23 COM22 COM21 COM20 COM19 COM18 COM17 COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9 X –2867 –2957 –3059 –3179 –3298 –3418 –3538 –3657 –3777 –3896 –4016 –4136 –4255 –4375 –4494 –4614 –4734 –4853 –4973 –5252 Y 1246 1248 1163 1090 1017 945 872 799 727 654 581 509 436 363 291 218 145 73 0 –73 –145 –218 Rev. 2.4a EPSON 8–17 S1D15605 Series Units: µm PAD No. 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 PIN Name COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 (NC) COM0 (NC) COMS (NC) (NC) (NC) (NC) (NC) (NC) SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 X –5252 Y –291 –363 –436 –509 –581 –654 –727 –800 –872 –945 –1018 –1090 –1163 –1248 –1246 PAD No. 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 PIN Name SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 X –3127 –3055 –2983 –2912 –2840 –2768 –2696 –2624 –2552 –2480 –2408 –2336 –2265 –2193 –2121 –2049 –1977 –1905 –1833 –1761 –1689 –1618 –1546 –1474 –1402 –1330 –1258 –1186 –1114 –1042 –971 –899 –827 –755 –683 –611 –539 –467 –395 –324 Y –1246 PAD PIN No. Name 201 SEG62 202 SEG63 203 SEG64 204 SEG65 205 SEG66 206 SEG67 207 SEG68 208 SEG69 209 SEG70 210 SEG71 211 SEG72 212 SEG73 213 SEG74 214 SEG75 215 SEG76 216 SEG77 217 SEG78 218 SEG79 219 SEG80 220 SEG81 221 SEG82 222 SEG83 223 SEG84 224 SEG85 225 SEG86 226 SEG87 227 SEG88 228 SEG89 229 SEG90 230 SEG91 231 SEG92 232 SEG93 233 SEG94 234 SEG95 235 SEG96 236 SEG97 237 SEG98 238 SEG99 239 SEG100 240 SEG101 X –252 –180 –108 –36 36 108 180 252 324 395 467 539 611 683 755 827 899 971 1042 1114 1186 1258 1330 1402 1474 1546 1618 1689 1761 1833 1905 1977 2049 2121 2193 2265 2336 2408 2480 2552 Y –1246 –5009 –4924 –4853 –4781 –4709 –4637 –4565 –4493 –4421 –4349 –4277 –4206 –4134 –4062 –3990 –3918 –3846 –3774 –3702 –3630 –3559 –3487 –3415 –3343 –3271 –3199 8–18 EPSON Rev. 2.4a S1D15605 Series Units: µm PAD No. 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 PIN Name SEG102 SEG103 SEG104 SEG105 SEG106 SEG107 SEG108 SEG109 SEG110 SEG111 SEG112 SEG113 SEG114 SEG115 SEG116 SEG117 SEG118 SEG119 SEG120 SEG121 SEG122 SEG123 SEG124 SEG125 SEG126 SEG127 SEG128 SEG129 SEG130 SEG131 (NC) (NC) (NC) (NC) (NC) (NC) COM26 (NC) COM27 (NC) X 2624 2696 2768 2840 2912 2983 3055 3127 3199 3271 3343 3415 3487 3558 3630 3702 3774 3846 3918 3990 4062 4134 4206 4277 4349 4421 4493 4565 4637 4709 4781 4853 4924 5009 5252 Y –1246 PAD No. 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 PIN Name COM28 COM29 COM30 COM31 COM32 COM33 COM34 COM35 COM36 COM37 COM38 COM39 COM40 COM41 COM42 COM43 COM44 COM45 COM46 COM47 COM48 COM49 COM50 (NC) COM51 (NC) COMS (NC) (NC) X 5252 Y –800 –727 –654 –581 –509 –436 –363 –291 –218 –145 –73 0 73 145 218 291 363 436 509 581 654 727 799 872 945 1017 1090 1163 1248 –1248 –1163 –1090 –1018 –945 –872 Rev. 2.4a EPSON 8–19 S1D15605 Series 5. PIN DESCRIPTIONS Power Supply Pins Pin Name VDD VSS VSS2 VRS I/O Power Supply Power Supply Power Supply Power Supply Power Supply Function Shared with the MPU power supply terminal V CC. This is a 0V terminal connected to the system GND. This is the reference power supply for the step-up voltage circuit for the liquid crystal drive. This is the externally-input VREG power supply for the LCD power supply voltage regulator. These are only enabled for the models with the VREG external input option. This is a multi-level power supply for the liquid crystal drive. The voltage applied is determined by the liquid crystal cell, and is changed through the use of a resistive voltage divided or through changing the impedance using an op. amp. Voltage levels are determined based on V DD, and must maintain the relative magnitudes shown below. VDD (= V0) ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ V5 Master operation: When the power supply turns ON, the internal power supply circuits produce the V1 to V4 voltages shown below. The voltage settings are selected using the LCD bias set command. S1D15605***** S1D15606***** S1D15607***** S1D15608***** S1D15609***** 1/9•V5 1/7•V5 1/8•V5 1/6•V5 1/6•V5 1/5•V5 1/8•V5 1/6•V5 1/8•V5 1/6•V5 2/9•V5 2/7•V5 2/8•V5 2/6•V5 2/6•V5 2/5•V5 2/8•V5 2/6•V5 2/8•V5 2/6•V5 7/9•V5 5/7•V5 6/8•V5 4/6•V5 4/6•V5 3/5•V5 6/8•V5 4/6•V5 6/8•V5 4/6•V5 8/9•V5 6/7•V5 7/8•V5 5/6•V5 5/6•V5 4/5•V5 7/8•V5 5/6•V5 7/6•V5 5/6•V5 No. of Pins 13 9 4 2 V1, V 2, V3, V 4, V5 10 V1 V2 V3 V4 LCD Power Supply Circuit Terminals Pin Name CAP1+ CAP1– CAP2+ CAP2– CAP3– VOUT VR I/O O O O O O I/O I Function DC/DC voltage converter. Connect a capacitor between this terminal and the CAP1- terminal. DC/DC voltage converter. Connect a capacitor between this terminal and the CAP1+ terminal. DC/DC voltage converter. Connect a capacitor between this terminal and the CAP2- terminal. DC/DC voltage converter. Connect a capacitor between this terminal and the CAP2+ terminal. DC/DC voltage converter. Connect a capacitor between this terminal and the CAP1+ terminal. DC/DC voltage converter. Connect a capacitor between this terminal and VSS2. Output voltage regulator terminal. Provides the voltage between VDD and V5 through a resistive voltage divider. These are only enabled when the V5 voltage regulator internal resistors are not used (IRS = LOW). These cannot be used when the V5 voltage regulator internal resistors are used (IRS = HIGH). No. of Pins 2 2 2 2 2 2 2 8–20 EPSON Rev. 2.4a S1D15605 Series System Bus Connection Terminals Pin Name D7 to D0 (SI) (SCL) I/O I/O Function This is an 8-bit bi-directional data bus that connects to an 8-bit or 16-bit standard MPU data bus. When the serial interface is selected (P/S = LOW), then D7 serves as the serial data input terminal (SI) and D6 serves as the serial clock input terminal (SCL). At this time, D0 to D5 are set to high impedance. When the chip select is inactive, D0 to D7 are set to high impedance. This is connect to the least significant bit of the normal MPU address bus, and it determines whether the data bits are data or a command. A0 = HIGH: Indicates that D0 to D7 are display data. A0 = LOW: Indicates that D0 to D7 are display control data. When RES is set to LOW, the settings are initialized. The reset operation is performed by the RES signal level. This is the chip select signal. When CS1 = LOW and CS2 = HIGH, then the chip select becomes active, and data/command I/O is enabled. • When connected to an 8080 MPU, this is active LOW. This pin is connected to the RD signal of the 8080 MPU, and the S1D15605 series data bus is in an output status when this signal is LOW. • When connected to a 6800 Series MPU, this is active HIGH. This is the 6800 Series MPU enable clock input terminal. • When connected to an 8080 MPU, this is active LOW. This terminal connects to the 8080 MPU WR signal. The signals on the data bus are latched at the rising edge of the WR signal. • When connected to a 6800 Series MPU: This is the read/write control signal input terminal. When R/W = HIGH: Read. When R/W = LOW: Write. This is the MPU interface switch terminal. C86 = HIGH: 6800 Series MPU interface. C86 = LOW: 8080 MPU interface. This is the parallel data input/serial data input switch terminal. P/S = HIGH: Parallel data input. P/S = LOW: Serial data input. The following applies depending on the P/S status: P/S Data/Command Data Read/Write Serial Clock HIGH A0 D0 to D7 RD, WR LOW A0 SI (D7) Write only SCL (D6) When P/S = LOW, D0 to D5 are HZ. D0 to D5 may be HIGH, LOW or Open. RD (E) and WR (P/W) are fixed to either HGIH or LOW. With serial data input, RAM display data reading is not supported. Terminal to select whether or enable or disable the display clock internal oscillator circuit. CLS = HIGH: Internal oscillator circuit is enabled CLS = LOW: Internal oscillator circuit is disabled (requires external input) When CLS = LOW, input the display clock through the CL terminal. When using the S1D15605 Series as a master or slave, set respective CLS pins at the same level. Display clock Built-in oscillator circuit used External input Master HIGH LOW Slave HIGH LOW No. of Pins 8 A0 I 1 RES CS1 CS2 RD (E) I I I 1 2 1 WR (R/W) I 1 C86 I 1 P/S I 1 CLS I 1 Rev. 2.4a EPSON 8–21 S1D15605 Series Pin Name M/S I/O I Function This terminal selects the master/slave operation for the S1D15605 Series chips. Master operation outputs the timing signals that are required for the LCD display, while slave operation inputs the timing signals required for the liquid crystal display, synchronizing the liquid crystal display system. M/S = HIGH: Master operation M/S = LOW: Slave operation The following is true depending on the M/S and CLS status: M/S CLS Oscillator Circuit HIGH HIGH Enabled LOW Disabled LOW HIGH Disabled LOW Disabled CL I/O Power Supply Circuit Enabled Enabled Disabled Disabled CL Output Input Input Input FR Output Output Input Input FRS Output Output Output Output DOF Output Output Input Input 1 No. of Pins 1 This is the display clock input terminal The following is true depending on the M/S and CLS status. M/S CLS HIGH HIGH LOW LOW HIGH LOW CL Output Input Input Input FR I/O DOF I/O FRS O IRS I HPM I When the S1D15605 Series chips are used in master/slave mode, the various CL terminals must be connected. This is the liquid crystal alternating current signal I/O terminal. M/S = HIGH: Output M/S = LOW: Input When the S1D15605 Series chip is used in master/slave mode, the various FR terminals must be connected. This is the liquid crystal display blanking control terminal. M/S = HIGH: Output M/S = LOW: Input When the S1D15605 Series chip is used in master/slave mode, the various DOF terminals must be connected. This is the output terminal for the static drive. This terminal is only enabled when the static indicator display is ON when in master operation mode, and is used in conjunction with the FR terminal. This terminal selects the resistors for the V5 voltage level adjustment. IRS = HIGH: Use the internal resistors IRS = LOW: Do not use the internal resistors. The V5 voltage level is regulated by an external resistive voltage divider attached to the VR terminal. This pin is enabled only when the master operation mode is selected. It is fixed to either HIGH or LOW when the slave operation mode is selected. This is the power control terminal for the power supply circuit for liquid crystal drive. HPM = HIGH: Normal mode HPM = LOW: High power mode This pin is enabled only when the master operation mode is selected. It is fixed to either HIGH or LOW when the slave operation mode is selected. 1 1 1 1 1 8–22 EPSON Rev. 2.4a S1D15605 Series Liquid Crystal Drive Terminals Pin Name SEG0 to SEG131 I/O O Function These are the liquid crystal segment drive outputs. Through a combination of the contents of the display RAM and with the FR signal, a single level is selected from VDD, V2, V3, and V5. RAM DATA HIGH HIGH LOW LOW Power save COM0 to COMn O FR HIGH LOW HIGH LOW — Output Voltage Normal Display Reverse Display VDD V2 V5 V3 V2 VDD V3 V5 VDD No. of Pins 132 These are the liquid crystal common drive outputs. Part No. S1D15605***** S1D15606***** S1D15607***** S1D15608***** S1D15609***** COM COM 0 ~ COM 63 COM 0 ~ COM 47 COM 0 ~ COM 31 COM 0 ~ COM 53 COM 0 ~ COM 51 Part No. No. of pins S1D15605***** 64 S1D15606***** 48 S1D15607***** 32 S1D15608***** 54 S1D15609***** 52 Through a combination of the contents of the scan data and with the FR signal, a single level is selected from VDD, V1, V 4, and V5. Scan Data HIGH HIGH LOW LOW Power Save COMS O FR Output Voltage HIGH V5 LOW VDD HIGH V1 LOW V4 — VDD 2 These are the COM output terminals for the indicator. Both terminals output the same signal. Leave these open if they are not used. When in master/slave mode, the same signal is output by both master and slave. Test Terminals Pin Name TEST0 to 9 I/O I/O Function No. of Pins 14 These are terminals for IC chip testing. TEST0 to 4 and 7 to 9 should be open, TEST 5 and 6 should be fixed to HIGH. Total: 288 pins for the S1D15605*****. 272 pins for the S1D15606*****. 256 pins for the S1D15607*****. 278 pins for the S1D15608*****. 276 pins for the S1D15609*****. Rev. 2.4a EPSON 8–23 S1D15605 Series 6. DESCRIPTION OF FUNCTIONS The MPU Interface Selecting the Interface Type With the S1D15605 Series chips, data transfers are done through an 8-bit bi-directional data bus (D7 to D0) or through a serial data input (SI). Through selecting the P/ S terminal polarity to the HIGH or LOW it is possible to select either parallel data input or serial data input as shown in Table 1. Table 1 P/S CS1 CS2 A0 RD HIGH: Parallel Input CS1 CS2 A0 RD LOW: Serial Input CS1 CS2 A0 — “—” indicates fixed to either HIGH or to LOW. The Parallel Interface When the parallel interface has been selected (P/S = HIGH), then it is possible to connect directly to either an WR C86 D7 D6 D5~D0 WR C86 D7 D6 D5~D0 — — SI SCL (HZ) HZ is in the state of High Impedance. 8080-system MPU or a 6800 Series MPU (as shown in Table 2) by selecting the C86 terminal to either HIGH or to LOW. Table 2 P/S CS1 CS2 HIGH: 6800 Series MPU Bus CS1 CS2 LOW: 8080 MPU Bus CS1 CS2 Moreover, data bus signals are recognized by a combination of A0, RD (E), WR (R/W) signals, as shown in Table 3. Table 3 8080 Series RD WR 0 1 1 0 0 1 1 0 A0 A0 A0 RD E RD WR R/W WR D7~D0 D7~D0 D7~D0 Shared A0 1 1 0 0 6800 Series R/W 1 0 1 0 Function Reads the display data Writes the display data Status read Write control data (command) 8–24 EPSON Rev. 2.4a S1D15605 Series The Serial Interface When the serial interface has been selected (P/S = LOW) then when the chip is in active state (CS1 = LOW and CS2 = HIGH) the serial data input (SI) and the serial clock input (SCL) can be received. The serial data is read from the serial data input pin in the rising edge of the serial clocks D7, D6 through D0, in this order. This data is converted to 8 bits parallel data in the rising edge of the eighth serial clock for the processing. The A0 input is used to determine whether or the serial data input is display data or command data; when A0 = HIGH, the data is display data, and when A0 = LOW then the data is command data. The A0 input is read and used for detection every 8th rising edge of the serial clock after the chip becomes active. Figure 1 is a serial interface signal chart. CS1 CS2 SI SCL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 A0 Figure 1 * When the chip is not active, the shift registers and the counter are reset to their initial states. * Reading is not possible while in serial interface mode. * Caution is required on the SCL signal when it comes to line-end reflections and external noise. We recommend that operation be rechecked on the actual equipment. The Chip Select The S1D15605 Series chips have two chip select terminals: CS1 and CS2. The MPU interface or the serial interface is enabled only when CS1 = LOW and CS2 = HIGH. When the chip select is inactive, D0 to D7 enter a high impedance state, and the A0, RD, and WR inputs are inactive. When the serial interface is selected, the shift register and the counter are reset. Accessing the Display Data RAM and the Internal Registers Data transfer at a higher speed is ensured since the MPU is required to satisfy the cycle time (tCYC) requirement alone in accessing the S1D15605 Series. Wait time may not be considered. And, in the S1D15605 Series chips, each time data is sent from the MPU, a type of pipeline process between LSIs is performed through the bus holder attached to the internal data bus. For example, when the MPU writes data to the display data RAM, once the data is stored in the bus holder, then it is written to the display data RAM before the next data write cycle. Moreover, when the MPU reads the display data RAM, the first data read cycle (dummy) stores the read data in the bus holder, and then the data is read from the bus holder to the system bus at the next data read cycle. There is a certain restriction in the read sequence of the display data RAM. Please be advised that data of the specified address is not generated by the read instruction issued immediately after the address setup. This data is generated in data read of the second time. Thus, a dummy read is required whenever the address setup or write cycle operation is conducted. This relationship is shown in Figure 2. Rev. 2.4a EPSON 8–25 S1D15605 Series The Busy Flag When the busy flag is “1” it indicates that the S1D15605 Series chip is running internal processes, and at this time no command aside from a status read will be received. The busy flag is outputted to D7 pin with the read instruction. If the cycle time (tCYC) is maintained, it is not necessary to check for this flag before each command. This makes vast improvements in MPU processing capabilities possible. Writing MPU WR DATA N Latch BUS Holder Write Signal N N+1 N+2 N+3 N+1 N+2 N+3 Internal Timing Reading WR MPU RD DATA N N n n+1 Internal Timing Address Preset Read Signal Column Address Bus Holder Preset N N Increment N+1 n n+1 N+2 n+2 Address Set #n Dummy Read Data Read #n Data Read #n+1 Figure 2 8–26 EPSON Rev. 2.4a S1D15605 Series Display Data RAM Display Data RAM The display data RAM is a RAM that stores the dot data for the display. It has a 65 (8 page × 8 bit +1) × 132 bit structure. It is possible to access the desired bit by specifying the page address and the column address. Because, as is shown in Figure 3, the D7 to D0 display data from the MPU corresponds to the liquid crystal display common direction, there are few constraints at the time of display data transfer when multiple S1D15605 series chips are used, thus and display structures can be created easily and with a high degree of freedom. Moreover, reading from and writing to the display RAM from the MPU side is performed through the I/O buffer, which is an independent operation from signal reading for the liquid crystal driver. Consequently, even if the display data RAM is accessed asynchronously during liquid crystal display, it will not cause adverse effects on the display (such as flickering). D0 D1 D2 D3 D4 — 0111 1000 0000 0111 1000 0 0 0 0 0 COM0 COM1 COM2 COM3 COM4 — Display data RAM Liquid crystal display Figure 3 The Page Address Circuit As shown in Figure 6-4, page address of the display data RAM is specified through the Page Address Set Command. The page address must be specified again when changing pages to perform access. Page address 8 (D3, D2, D1, D0 = 1, 0, 0, 0) is the page for the RAM region used only by the indicators, and only display data D0 is used. The Column Addresses As is shown in Figure 4, the display data RAM column address is specified by the Column Address Set command. The specified column address is incremented (+1) with each display data read/write command. This allows the MPU display data to be accessed continuously. Moreover, the incrementation of column addresses stops with 83H. Because the column address is independent of the page address, when moving, for example, from page 0 column 83H to page 1 column 00H, it is necessary to respecify both the page address and the column address. Furthermore, as is shown in Table 4, the ADC command (segment driver direction select command) can be used to reverse the relationship between the display data RAM column address and the segment output. Because of this, the constraints on the IC layout when the LCD module is assembled can be minimized. Table 4 SEG SEG 131 Output SEG0 ADC “0” 0 (H) → Column Address → 83 (H) (D0) “1” 83 (H) ← Column Address ← 0 (H) The Line Address Circuit The line address circuit, as shown in Table 4, specifies the line address relating to the COM output when the contents of the display data RAM are displayed. Using the display start line address set command, what is normally the top line of the display can be specified (this is the COM0 output when the common output mode is normal, and the COM63 output for S1D15605 Series, COM47 output for S1D15606 Series, COM31 output for the S1D15607 Series, COM53 output for S1D15608***** and COM51 output for S1D15609*****) when the common output mode is reversed. The display area is a 65 line area for the S1D15605 Series, a 49 line are for the S1D15606, a 33 line area for the S1D15607 Series , 55 line area for the S1D15608 ***** a nd 53 line area for the S1D15609***** from the display start line address. If the line addresses are changed dynamically using the display start line address set command, screen scrolling, page swapping, etc. can be performed. Rev. 2.4a EPSON 8–27 S1D15605 Series Page Address D3 D2 D1 D0 Data D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 00 01 02 03 04 05 06 07 Line common output Address mode is normal 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 11H 12H 13H 14H 15H 16H 17H 18H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 7C 7D 7E 7F 80 81 82 83 When the COM Output COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COM32 COM33 COM34 COM35 COM36 COM37 COM38 COM39 COM40 COM41 COM42 COM43 COM44 COM45 COM46 COM47 COM48 COM49 COM50 COM51 COM52 COM53 COM54 COM55 COM56 COM57 COM58 COM59 COM60 COM61 COM62 COM63 COMS 52 lines 0 0 0 1 Page 1 48 lines 0 0 0 0 Page 0 0 0 1 0 Page 2 0 0 1 1 Page 3 Start 0 1 0 0 Page 4 0 1 0 1 Page 5 63 lines 0 1 1 0 Page 6 0 1 1 1 Page 7 1 0 0 0 Page 8 10 D0 D0 ADC Column Address LCD Out 83 82 81 80 7F 7E 7D 7C Figure 4 8–28 EPSON SEG127 SEG125 SEG126 SEG127 SEG128 SEG129 SEG130 SEG131 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 07 06 05 04 03 02 01 00 32 lines 54 lines Regardless of the display start line address, the S1D15605 Series accesses 65th line, the S1D15606 Series accesses 49th line and the S1D15607 Series accesses 33th line and the S1D15608 Series accesses 55th line, the S1D15609 Series accesses 53 lines. Rev. 2.4a S1D15605 Series The Display Data Latch Circuit The display data latch circuit is a latch that temporarily stores the display data that is output to the liquid crystal driver circuit from the display data RAM. Because the display normal/reverse status, display ON/ OFF status, and display all points ON/OFF commands control only the data within the latch, they do not change the data within the display data RAM itself. Display Timing Generator Circuit The display timing generator circuit generates the timing signal to the line address circuit and the display data latch circuit using the display clock. The display data is latched into the display data latch circuit synchronized with the display clock, and is output to the data driver output terminal. Reading to the display data liquid crystal driver circuits is completely independent of accesses to the display data RAM by the MPU. Consequently, even if the display data RAM is accessed asynchronously during liquid crystal display, there is absolutely no adverse effect (such as flickering) on the display. Moreover, the display timing generator circuit generates the common timing and the liquid crystal alternating current signal (FR) from the display clock. It generates a drive wave form using a 2 frame alternating current drive method, as is shown in Figure 5, for the liquid crystal drive circuit. The Oscillator Circuit This is a CR-type oscillator that produces the display clock. The oscillator circuit is only enabled when M/S = HIGH and CLS = HIGH. When CLS = LOW the oscillation stops, and the display clock is input through the CL terminal. Two-frame alternating current drive wave form (S1D15605*****) 64 65 1 CL FR VDD V1 COM0 V4 V5 VDD V1 COM1 V4 V5 RAM DATA SEGn 2 3 4 5 6 60 61 62 63 64 65 1 2 3 4 5 6 VDD V2 V3 V5 Figure 5 Rev. 2.4a EPSON 8–29 S1D15605 Series When multiple S1D15605 Series chips are used, the slave chips must be supplied the display timing signals (FR, CL, DOF) from the master chip[s]. Table 5 shows the status of the FR, CL, and DOF signals. Table 5 Operating Mode Master (M/S = HIGH) The internal oscillator circuit is enabled (CLS = HIGH) The internal oscillator circuit is disabled (CLS = LOW) Slave (M/S = LOW) Set the CLS pin to the same level as with the master. FR Output Output Input Input CL Output Input Input Input DOF Output Output Input Input The Common Output Status Select Circuit In the S1D15605 Series chips, the COM output scan direction can be selected by the common output status select command. (See Table 6.) Consequently, the constraints in IC layout at the time of LCD module assembly can be minimized. Table 6 Status COM Scan Direction S1D15605***** S1D15606***** S1D15607***** S1D15608***** S1D15609***** Normal COM0 → COM63 COM0 → COM47 COM0 → COM31 COM0 → COM53 COM0 → COM51 Reverse COM63 → COM0 COM47 → COM0 COM31 → COM0 COM53 → COM0 COM51 → COM0 The Liquid Crystal Driver Circuits These are a 197-channel (S1D15605 Series), a 181channel (S1D15606 Series) multiplexers 165-channel (S1D15607 Series), 187-channel (S1D15608 Series) and a 185-channel (S1D15609 Series) that generate four voltage levels for driving the liquid crystal. The combination of the display data, the COM scan signal, and the FR signal produces the liquid crystal drive voltage output. Figure 6 shows examples of the SEG and COM output wave form. 8–30 EPSON Rev. 2.4a S1D15605 Series COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 FR VDD VSS COM0 VDD V1 V2 V3 V4 V5 VDD V1 V2 V3 V4 V5 VDD V1 V2 V3 V4 V5 VDD V1 V2 V3 V4 V5 VDD V1 V2 V3 V4 V5 VDD V1 V2 V3 V4 V5 V5 V4 V3 V2 V1 V∞ –V1 –V2 –V3 –V4 –V5 V5 V4 V3 V2 V1 V∞ –V1 –V2 –V3 –V4 –V5 COM1 COM2 SEG0 SEG1 SEG2 COM0–SEG0 COM0–SEG1 Figure 6 Rev. 2.4a EPSON 8–31 S1D15605 Series operation. The power supply circuits can turn the Booster circuits, the voltage regulator circuits, and the voltage follower circuits ON of OFF independently through the use of the Power Control Set command. Consequently, it is possible to make an external power supply and the internal power supply function somewhat in parallel. Table 7 shows the Power Control Set Command 3-bit data control function, and Table 8 shows reference combinations. The Power Supply Circuits The power supply circuits are low-power consumption power supply circuits that generate the voltage levels required for the liquid crystal drivers. They comprise Booster circuits, voltage regulator circuits, and voltage follower circuits. They are only enabled in master Table 7 The Control Details of Each Bit of the Power Control Set Command Status Item “1” “0” D2 Booster circuit control bit ON OFF D1 Voltage regulator circuit (V regulator circuit) control bit ON OFF D0 Voltage follower circuit (V/F circuit) control bit ON OFF Table 8 Reference Combinations Use Settings 1 Step-up D2 D1 D0 circuit V V/F regulator circuit circuit Only the internal power supply is 1 1 1 O O O used 2 Only the V regulator circuit and 0 1 1 X O O VOUT, VSS2 Open the V/F circuit are used 3 Only the V/F circuit is used 0 0 1 X X O V5, VSS2 Open 4 Only the external power supply is 0 0 0 X X X V1 to V5 Open used * The “step-up system terminals” refer CAP1+, CAP1–, CAP2+, CAP2–, and CAP3–. * While other combinations, not shown above, are also possible, these combinations are not recommended because they have no practical use. difference between VDD and VSS2 . Double step-up: Connect capacitor C1 between CAP1+ and CAP1–, and between VSS2 and V OUT , leave CAP2+ open, and short between CAP2–, CAP3– and VOUT t o produce a voltage in the negative direction at the VOUT terminal that is twice the voltage between VDD and VSS2 . The step-up voltage relationships are shown in Figure 7. Step-up External voltage voltage system input terminal VSS2 Used The Step-up Voltage Circuits Using the step-up voltage circuits equipped within the S1D15605 Series chips it is possible to product a Quad step-up, a Triple step-up, and a Double step-up of the VDD – V SS2 voltage levels. Quad step-up: Connect capacitor C1 between CAP1+ and CAP1–, between CAP2+ and CAP2–, between CAP1+ and CAP3–, and between VSS2 and VOUT, to produce a voltage level in the negative direction at the VOUT terminal that is 4 times the voltage level between VDD and VSS2 . Triple step-up: Connect capacitor C1 between CAP1+ and CAP1–, between CAP2+ and CAP2– and between V SS2 and VOUT , and short between CAP3– and V OUT to produce a voltage level in the negative direction at the VOUT terminal that is 3 times the voltage 8–32 EPSON Rev. 2.4a S1D15605 Series + C1 VSS2 C1 VOUT CAP3– + VSS2 C1 VOUT CAP3– + VSS2 VOUT CAP3– S1D15605 Series S1D15605 Series C1 + C1 CAP1– CAP2– C1 + CAP2+ CAP1+ + C1 CAP1+ CAP1– CAP2– + C1 CAP1+ CAP1– CAP2– OPEN CAP2+ C1 + CAP2+ 4 x step-up voltage circuit 3 x step-up voltage circuit 2 x step-up voltage circuit VDD = 0V VSS2 = –3V VDD = 0V VSS2 = –3V VDD = 0V VSS2 = –5V VOUT = 3 x VSS2 = –9V VOUT = 4 x VSS2 = –12V 4x step-up voltage relationships 3x step-up voltage relationships VOUT = 2 x VSS2 = –10V 2x step-up voltage relationships Figure 7 * The VSS2 voltage range must be set so that the VOUT terminal voltage does not exceed the absolute maximum rated value. The Voltage Regulator Circuit The step-up voltage generated at V OUT outputs the liquid crystal driver voltage V5 through the voltage regulator circuit. Because the S1D15605 Series chips have an internal high-accuracy fixed voltage power supply with a 64level electronic volume function and internal resistors for the V5 voltage regulator, systems can be constructed without having to include high-accuracy voltage regulator circuit components. Moreover, in the S1D15605 Series, three types of thermal gradients have been prepared as V REG options: (1) approximately -0.05%/°C (2) approximately -0.2%/° C, and (3) external input (supplied to the VRS terminal). (A) When the V5 Voltage Regulator Internal Resistors Are Used Through the use of the V 5 voltage regulator internal resistors and the electronic volume function the liquid crystal power supply voltage V5 can be controlled by commands alone (without adding any external resistors), making it possible to adjust the liquid crystal display brightness. The V5 voltage can be calculated using equation A-1 over the range where | V5 | < | VOUT |. Rev. 2.4a EPSON S1D15605 Series 8–33 S1D15605 Series Rb   V5 = 1 + ⋅ VEV  Ra  [Q V = (1 − α 162) ⋅ V ] ∴ EV REG α Rb    = 1+ ⋅ 1– ⋅ VREG  Ra   162  (Equation A-1) VDD VEV (constant voltage supply + electronic volume) Internal Ra + V5 – Internal Rb Figure 8 VREG is the IC-internal fixed voltage supply, and its voltage at Ta = 25° C is as shown in Table 9. Table 9 Equipment Type Thermal Gradient (1) Internal Power Supply –0.05 (2) Internal Power Supply –0.2 (3) External Input — Units [%/° C ] [%/° C ] — VREG –2.1 –4.9 VRS Units [V] [V] [V] α is set to 1 level of 64 possible levels by the electronic volume function depending on the data set in the 6-bit electronic volume register. Table 10 shows the value for α depending on the electronic volume register settings. Table 10 D5 D4 D3 D2 D1 D0 α 0 0 0 0 0 0 63 0 0 0 0 0 1 62 0 0 0 0 1 0 61 . . . . . . 1 1 1 1 0 1 2 1 1 1 1 1 0 1 1 1 1 1 1 1 0 Rb/Ra is the V5 voltage regulator internal resistor ratio, and can be set to 8 different levels through the V 5 voltage regulator internal resistor ratio set command. The (1 + Rb/Ra) ratio assumes the values shown in Table 11 depending on the 3-bit data settings in the V 5 voltage regulator internal resistor ratio register. 8–34 EPSON Rev. 2.4a S1D15605 Series V 5 voltage regulator internal resistance ratio register value and (1 + Rb/Ra) ratio (Reference value) Table 11 S1D15605 ***** S1D15606***** Register Equipment Type by Thermal Gradient [Units: %/°C ] Equipment Type by Thermal Gradient [Units: %/°C ] D2 D1 D0 (1) –0.05 (2) –0.2 (3) VREG External Input (1) –0.05 (2) –0.2 (3) VREG External Input 00 0 3.0 1.3 1.5 3.0 1.3 1.5 00 1 3.5 1.5 2.0 3.5 1.5 2.0 01 0 4.0 1.8 2.5 4.0 1.8 2.5 01 1 4.5 2.0 3.0 4.5 2.0 3.0 10 0 5.0 2.3 3.5 5.0 2.3 3.5 10 1 5.5 2.5 4.0 5.4 2.5 4.0 11 0 6.0 2.8 4.5 5.9 2.8 4.5 11 1 6.4 3.0 5.0 6.4 3.0 5.0 S1D15607***** S1D15608*****/S1D15609***** Register Equipment Type by Thermal Gradient [Units: %/°C ] Equipment Type by Thermal Gradient [Units: %/°C ] D2 D1 D0 (1) –0.05 (2) –0.2 (3) VREG External Input –0.05 00 0 3.0 1.3 1.5 3 00 1 3.5 1.5 2.0 3.5 01 0 4.0 1.8 2.5 4 01 1 4.5 2.0 3.0 4.5 10 0 5.0 2.3 3.5 5 10 1 5.4 2.5 4.0 5.4 11 0 5.9 2.8 4.5 5.9 11 1 6.4 3.0 5.0 6.4 For the internal resistance ratio, a manufacturing dispersion of up to ± 7% should be taken into account. When not within the tolerance, adjust the V 5 voltage by externally mounting Ra and Rb. Figs. 9, 10, 11 (for S1D15605 Series), 12, 13, 14 (for S1D15606 Series), 15, 16, 17 (for S1D15607 Series), 18 (for S1D15608D00B* ) and Figs. 19 (for S1D15609D00B*) show V5 voltage measured by values of the internal resistance ratio resistor for V 5 voltage adjustment and electric volume resister for each temperature grade model, when Ta = 25 ° C. Rev. 2.4a EPSON 8–35 S1D15605 Series S1D15605D00B*/S1D15605D11B* –16 –15 –14 –13 –12 –11 –10 –9 V5 [v] 111 110 101 100 011 010 001 000 –8 –7 –6 –5 –4 –3 –2 –1 0 Electric Volume Resister 3FH 00H 18H 30H The V5 voltage regulator internal resistance ratio registers (D2, D1, D0) Figure 9: S1D15605D00B */S1D15605D11B* (1) For Models Where the Thermal Gradient = -0.05%/°C The V5 voltage as a function of the V5 voltage regulator internal resistor ratio register and the electronic volume register. –16 –15 –14 –13 –12 –11 –10 –9 V5 [v] S1D15605D01B* 111 110 101 100 011 010 001 –8 –7 –6 –5 –4 –3 –2 –1 0 Electric Volume Resister 3FH 00H 18H 30H 000 The V5 voltage regulator internal resistance ratio registers (D2, D1, D0) Figure 10: S1D15605D01B* (2) For Models Where the Thermal Gradient = -0.2%/ °C The V5 voltage as a function of the V5 voltage regulator internal resistor ratio register and the electronic volume register. 8–36 EPSON Rev. 2.4a S1D15605 Series –16 –15 –14 –13 –12 –11 –10 –9 V5 [v] S1D15605D02B* 111 110 101 100 011 010 001 000 The V5 voltage regulator internal resistance ratio registers (D2, D1, D0) Electric Volume Resister 3FH –8 –7 –6 –5 –4 –3 –2 –1 0 00H 18H 30H Figure 11: S1D15605D02B* (3) For models with External Input The V5 voltage as a function of the V 5 voltage regulator internal resistor ratio register and the electronic volume register. –16 –15 –14 –13 –12 –11 –10 –9 111 110 101 100 011 010 –8 001 –7 000 –6 –5 –4 –3 –2 –1 0 Electric Volume Resister The V5 voltage regulator internal resistance ratio registers (D2, D1, D0) S1D15606D00B*/S1D15606D11B * V5 [v] Figure 12: S1D15606D00B*/S1D15606D11B* (1) For Models Where the Thermal Gradient = -0.05%/°C The V5 voltage as a function of the V 5 voltage regulator internal resistor ratio register and the electronic volume register. Rev. 2.4a EPSON 3FH 00H 18H 30H 8–37 S1D15605 Series –16 –15 –14 –13 –12 100 –11 –10 –9 V5 [v] S1D15606D01B* 111 110 101 011 010 001 000 –8 –7 –6 –5 –4 –3 –2 –1 0 Electric Volume Resister 3FH 00H 18H 30H The V5 voltage regulator internal resistance ratio registers (D2, D1, D0) Figure 13: S1D15606D01B* (2) For Models Where the Thermal Gradient = -0.2%/ °C The V5 voltage as a function of the V5 voltage regulator internal resistor ratio register and the electronic volume register. –16 –15 –14 –13 101 –12 –11 –10 011 –9 V5 [v] S1D15606D02B* 111 110 100 –8 –7 010 001 –6 –5 –4 –3 –2 –1 0 Electric Volume Resister 3FH 00H 18H 30H 000 The V5 voltage regulator internal resistance ratio registers (D2, D1, D0) Figure 14: S1D15606D02B * (3) For models with External Input The V5 voltage as a function of the V5 voltage regulator internal resistor ratio register and the electronic volume register. 8–38 EPSON Rev. 2.4a S1D15605 Series –16 –15 –14 –13 –12 –11 –10 011 –9 010 001 000 111 110 101 100 S1D15607D00B*/S1D15607D11B * V5 [v] –8 –7 –6 –5 –4 –3 –2 –1 0 Electric Volume Resister The V5 voltage regulator internal resistance ratio registers (D2, D1, D0) Figure 15: S1D15607D00B*/S1D15607D11B* (1) For Models Where the Thermal Gradient = -0.05%/°C The V5 voltage as a function of the V 5 voltage regulator internal resistor ratio register and the electronic volume register. –16 –15 –14 –13 –12 –11 –10 –9 011 010 001 000 110 101 100 S1D15607D01B* 3FH 00H 18H 30H 111 V5 [v] –8 –7 –6 –5 –4 –3 –2 –1 0 Electric Volume Resister The V5 voltage regulator internal resistance ratio registers (D2, D1, D0) Figure 16: S1D15607D01B* (2) For Models Where the Thermal Gradient = -0.2%/° C The V5 voltage as a function of the V 5 voltage regulator internal resistor ratio register and the electronic volume register. Rev. 2.4a EPSON 3FH 00H 18H 30H 8–39 S1D15605 Series –16 –15 –14 –13 –12 –11 –10 –9 V5 [v] S1D15607D02B* 111 110 101 100 011 010 001 000 –8 –7 –6 –5 –4 –3 –2 –1 0 Electric Volume Resister 3FH 00H 18H 30H The V5 voltage regulator internal resistance ratio registers (D2, D1, D0) Figure 17: S1D15607D02B * (3) For models with External Input The V5 voltage as a function of the V5 voltage regulator internal resistor ratio register and the electronic volume register. –16 –15 –14 –13 –12 –11 –10 –9 V5 [v] S1D15608D00B* 111 110 101 100 011 010 001 000 –8 –7 –6 –5 –4 –3 –2 –1 0 Electric Volume Resister 3FH 00H 18H 30H The V5 voltage regulator internal resistance ratio registers (D2, D1, D0) Figure 18: S1D15608D00B * (1) For Models Where the Thermal Gradient = –0.05%/ °C The V5 voltage as a function of the V5 voltage regulator internal resistor ratio register and the electronic volume register. 8–40 EPSON Rev. 2.4a S1D15605 Series S1D15609D00B* 111 110 101 100 011 010 001 000 –16 –15 –14 –13 –12 –11 –10 –9 V5 [v] –8 –7 –6 –5 –4 –3 –2 –1 0 Electric Volume Resister 3FH 00H 18H 30H The V5 voltage regulator internal resistance ratio registers (D2, D1, D0) Figure 19: S1D15609D00B* Temperature Gradient = –0.05%/°C Model The V5 voltage as a function of the V 5 voltage regulator internal resistor ratio register and the electronic volume register. Setup example: When selecting Ta = 25° C and V5 = 7 V for an S1D15607 model on which Temperature gradient = –0.05%/ °C. Using Figure 15 and the equation A-1, the following setup is enabled. Table 12 Contents For V5 voltage regulator Electronic Volume Register D5 D4 D3 D2 D1 D0 ———0 1 0 1 0 0 1 0 1 Table 13 Typ. Max. –6.8 (central value) –5.1 (0 level) 51 At this time, the variable range and the notch width of the V5 voltage is, as shown Table 13, as dependent on the electronic volume. V5 Variable Range Notch width Min. –8.4 (63 levels) Units [V] [mV] Rev. 2.4a EPSON 8–41 S1D15605 Series (B) When an External Resistance is Used (i.e., The V5 Voltage Regulator Internal Resistors Are Not Used) (1) The liquid crystal power supply voltage V5 can also be set without using the V 5 v oltage regulator internal resistors (IRS terminal = LOW) by adding resistors Ra’ and Rb’ between VDD and VR, and between VR and V5, Rb'   V5 = 1 + ⋅ VEV  Ra'  Rb'   α  = 1+ ⋅ 1– ⋅ VREG  Ra'   162  respectively. When this is done, the use of the electronic volume function makes it possible to adjust the brightness of the liquid crystal display by controlling the liquid crystal power supply voltage V5 through commands. In the range where | V5 | < | VOUT |, the V5 voltage can be calculated using equation B-1 based on the external resistances Ra’ and Rb’. [Q V = (1 − α 162) ⋅ V ] ∴ EV REG ( Equation B-1) VDD VEV (fixed voltage power supply + electronic volume) External resistor Ra' + V5 – External resistor Rb' Figure 20 Setup example: When selecting Ta = 25°C and V5 = – 7 V for an S1D15607 Series model where the temperature gradient = –0.05%/° C. When the central value of the electron volume register is (D5, D4, D3, D2, D1, D0) = (1, 0, 0, 0, 0, 0), then α = 31 and VREG = –2.1 V so, according to equation B-1, α Rb'    V5 = 1 + ⋅ 1− ⋅ VREG  Ra'   162  31  Rb'    −11V = 1 + ⋅ 1− ⋅ ( −2.1) (Equation B-2)  Ra'   162  Consequently, by equations B-2 and B-3, Rb' = 3.12 Ra' Ra' = 340 kΩ Rb' = 1060 kΩ At this time, the V5 voltage variable range and notch width, based on the electron volume function, is as given in Table 14. Moreover, when the value of the current running through Ra’ and Rb’ is set to 5 µA, (Equation B-3) Ra' + Rb' = 1.4 MΩ V5 Variable Range Notch width Min. –8.6 (63 levels) Table 14 Typ. Max. –7.0 (central value) –5.3 (0 level) 52 Units [V] [mV] 8–42 EPSON Rev. 2.4a S1D15605 Series (C) When External Resistors are Used (i.e. The V5 Voltage Regulator Internal Resistors Are Not Used). (2) When the external resistor described above are used, adding a variable resistor as well makes it possible to perform fine adjustments on Ra’ and Rb’, to set the liquid crystal drive voltage V 5. In this case, the use of  R + R2 − ∆R2  V5 = 1 + 3 ⋅ VEV R1 + ∆R2     R + R2 − ∆R2   α ⋅ 1– ⋅ VREG = 1 + 3 R1 + ∆R2   162    the electronic volume function makes it possible to control the liquid crystal power supply voltage V5 by commands to adjust the liquid crystal display brightness. In the range where | V5 | < | VOUT | the V5 voltage can be calculated by equation C-1 below based on the R1 and R2 (variable resistor) and R3 settings, where R2 can be subjected to fine adjustments (∆ R2 ). [Q V = (1 − α 162) ⋅ V ] ∴ EV REG (Equation C-1) VDD VEV (fixed voltage supply + electronic volume) Ra' External resistor R1 External resistor R2 External resistor R3 ∆R2 VR + V5 – Rb' Figure 21 Setup example: When selecting Ta = 25° C and V5 = – 5 to –9 V (using R2) for an S1D15607 model where the temperature gradient = –0.05%/ °C. When the central value for the electronic volume register is set at (D5, D4, D3, D2, D1, D0) = (1, 0, 0, 0, 0, 0), α = 31 VREG = −2.1V When ∆ R2 = R2 , in order to make V = –5 V,  R3   31  −5V = 1 + ⋅ 1− ⋅ ( −2.1) R1 + R2   162    so, according to equation C-1, when ∆ R2 = 0 Ω, in order to make V5 = –9 V,  R + R2   31  −9V = 1 + 3 ⋅ 1− ⋅ ( −2.1) R1   162    (Equation C-3) Moreover, when the current flowing VDD and V5 is set to 5 µA, R1 + R2 + R3 = 1.4 MΩ (Equation C-4) With this, according to equation C-2, C-3 and C-4, R1 = 264 kΩ R2 = 211kΩ R3 = 925kΩ (Equation C-2) At this time, the V5 voltage variable range and notch width based on the electron volume function is as shown in Table 15. Table 15 Typ. Max. –7.0 (central value) –5.3 (0 level) 53 V5 Variable Range Notch width Min. –8.7 (63 levels) Units [V] [mV] Rev. 2.4a EPSON 8–43 S1D15605 Series * When the V5 voltage regulator internal resistors or the electronic volume function is used, it is necessary to at least set the voltage regulator circuit and the voltage follower circuit to an operating mode using the power control set commands. Moreover, it is necessary to provide a voltage from VOUT when the Booster circuit is OFF. * The V R terminal is enabled only when the V5 voltage regulator internal resistors are not uesd (i.e. the IRS terminal = LOW). When the V 5 voltage regulator internal resistors are uesd (i.e. when the IRS terminal = HIGH), then the V R terminal is left open. * Because the input impedance of the VR terminal is high, it is necessary to take into consideration short leads, shield cables, etc. to handle noise. The Liquid Crystal Voltage Generator Circuit The V5 v oltage is produced by a resistive voltage divider within the IC, and can be produced at the V1, V2, V3, and V4 voltage levels required for liquid crystal driving. Moreover, when the voltage follower changes the impedance, it provides V1, V 2, V3 and V4 to the liquid crystal drive circuit. 1/9 bias or 1/7 bias for S1D15605 Series, 1/8 bias or 1/6 bias for S1D15606 Series, 1/6 bias or 1/5 bias for the S1D15607 Series, 1/ 8 bias or 1/6 bias for S1D15608 Series and 1/8 bias or 1/6 bias for S1D15609 Series can be selected. High Power Mode The power supply circuit equipped in the S1D15605 Series chips has very low power consumption (normal mode: HPM = HIGH). However, for LCDs or panels with large loads, this low-power power supply may cause display quality to degrade. When this occurs, setting the HPM terminal to LOW (high power mode) can improve the quality of the display. We recommend that the display be checked on actual equipment to determine whether or not to use this mode. Moreover, if the improvement to the display is inadequate even after high power mode has been set, then it is necessary to add a liquid crystal drive power supply externally. The Internal Power Supply Shutdown Command Sequence The sequence shown in Figure 22 is recommended for shutting down the internal power supply, first placing the power supply in power saver mode and then turning the power supply OFF. Sequence Step1 Step2 End Details (Command, status) Display OFF Display all points ON Internal power supply OFF Command address D7 D6 D5 D4 D3 D2 D1 D0 1 1 0 0 1 1 0 0 1 0 1 1 1 0 0 1 Power saver commands (compound) Figure 22 8–44 EPSON Rev. 2.4a S1D15605 Series Reference Circuit Examples Figure 22 shows reference circuit examples. Œ When used all of the step-up circuit, voltage regulating circuit and V/F circuit (1) When the voltage regulator internal resistor is used. (Example where VSS2 = VSS, with 4x step-up) VDD IRS C1 VSS C1 C1 C1 VSS2 VOUT CAP3– CAP1+ CAP1– CAP2+ CAP2– V5 VR VDD C2 C2 C2 C2 C2 V1 V2 V3 V4 V5 M/S C1 VSS C1 C1 S1D15605 Series (2) When the voltage regulator internal resistor is not used. (Example where VSS2 = VSS, with 4x step-up) VDD IRS VSS2 VOUT CAP3– CAP1+ CAP1– CAP2+ CAP2– V5 VR VDD C2 C2 C2 C2 C2 V1 V2 V3 V4 V5 M/S C1 R3 R2 VDD R1 VDD  When the voltage regulator circuit and V/F circuit alone are used (1) When the V5 voltage regulator internal resistor is not used. VDD IRS VSS2 VOUT CAP3– CAP1+ CAP1– CAP2+ CAP2– V5 VR VDD C2 C2 C2 C2 C2 V1 V2 V3 V4 V5 M/S (2) When the V5 voltage regulator internal resistor is used. VDD IRS VSS2 VOUT CAP3– CAP1+ CAP1– CAP2+ CAP2– V5 VR VDD C2 C2 C2 C2 C2 V1 V2 V3 V4 V5 M/S VSS External power supply R3 R2 VDD R1 VSS External power supply S1D15605 Series VDD Rev. 2.4a EPSON S1D15605 Series S1D15605 Series 8–45 S1D15605 Series Ž When the V/F circuit alone is used VDD IRS VSS2 VOUT CAP3– CAP1+ CAP1– CAP2+ CAP2– V5 VR VDD C2 C2 C2 C2 C2 V1 V2 V3 V4 V5 M/S  When the built-in power is not used VSS IRS VSS2 VOUT CAP3– CAP1+ CAP1– CAP2+ CAP2– V5 VR VDD VDD V1 External power supply V2 V3 V4 V5 VDD M/S VSS External power supply S1D15605 Series VDD 5 When the built-in power circuit is used to drive a liquid crystal panel heavily loaded with AC or DC, it is recommended to connect an external resistor to stabilize potentials of V1, V2, V3 and V 4 which are output from the built-in voltage follower. Examples of shared reference settings When V5 can vary between –8 and 12 V Item C1 C2 Set value 1.0 to 4.7 0.01 to 1.0 Units µF µF VDD, V0 R4 C2 R4 V1 V2 V3 V4 S1D15605 Series R4 R4 Reference set value R4: 100k Ω ~ 1M Ω It is recommended to set an optimum resistance value R4 taking the liquid crystal display and the drive waveform. V5 Figure 23 * 1 Because the VR terminal input impedance is high, use short leads and shielded lines. * 2 C1 and C2 are determined by the size of the LCD being driven. Select a value that will stabilize the liquid crystal drive voltage. Example of the Process by which to Determine the Settings: • Turn the voltage regulator circuit and voltage follower circuit ON and supply a voltage to V OUT from the outside. • Determine C2 by displaying an LCD pattern with a heavy load (such as horizontal stripes) and selecting a C2 that stabilizes the liquid crystal drive voltages (V 1 to V5 ). Note that all C2 capacitors must have the same capacitance value. • Next turn all the power supplies ON and determine C1. 8–46 EPSON S1D15605 Series Rev. 2.4a S1D15605 Series * Precautions when installing the COG When installing the COG, it is necessary to duly consider the fact that there exists a resistance of the ITO wiring occurring between the driver chip and the externally connected parts (such as capacitors and resistors). By the influence of this resistance, non-conformity may occur with the indications on the liquid crystal display. Therefore, when installing the COG design the module paying sufficient considerations to the following three points. 1. Suppress the resistance occurring between the driver chip pin to the externally connected parts as much as possible. 2. Suppress the resistance connecting to the power supply pin of the driver chip. 3. Make various COG module samples with different ITO sheet resistance to select the module with the sheet resistance with sufficient operation margin. Also, as for this driver IC, pay sufficient attention to the following points when connecting to external parts for the characteristics of the circuit. 1. Connection to the boosting capacitors The boosting capacitors (the capacitors connecting to respective CAP pins and capacitor being inserted between VOUT and VSS2) of this IC are being switched over by use of the transistor with very low ON-resistance of about 10Ω. However, when installing the COG, Exemplary connection diagram 1. VDD VDD R4 C2 R4 V1 C2 V1 2. the resistance of ITO wiring is being inserted in series with the switching transistor, thus dominating the boosting ability. Consequently, the boosting ability will be hindered as a result and pay sufficient attention to the wiring to respective boosting capacitors. Connection of the smoothing capacitors for the liquid crystal drive The smoothing capacitors for the liquid crystal driving potentials (V 1 . V 2 , V 3 a nd V 4 ) are indispensable for liquid crystal drives not only for the purpose of mere stabilization of the voltage levels. If the ITO wiring resistance which occurs pursuant to installation of the COG is supplemented to these smoothing capacitors, the liquid crystal driving potentials become unstable to cause nonconformity with the indications of the liquid crystal display. Therefore, when using the COG module, we definitely recommend to connect reinforcing resistors externally. Reference value of the resistance is 100kΩ to 1MΩ. Meanwhile, because of the existence of these reinforcing resistors, current consumption will increase. Indicated below is an exemplary connection diagram of external resistors. Please make sufficient evaluation work for the display statuses with any connection tests. Exemplary connection diagram 2. VDD VDD S1D15605 Series C2 V2 C2 V2 C2 V3 C2 R4 V3 C2 R4 R4 C2 V4 C2 V4 V5 C2 V5 Rev. 2.4a EPSON S1D15605 Series R4 8–47 S1D15605 Series The Reset Circuit When the RES input comes to the LOW level, these LSIs return to the default state. Their default states are as follows: 1. Display OFF 2. Normal display 3. ADC select: Normal (ADC command D0 = LOW) 4. Power control register: (D2, D1, D0) = (0, 0, 0) 5. Serial interface internal register data clear 6. LCD power supply bias rate: S1D15605***** ........................ 1/9 bias S1D15606*****, 15608*****, 15609 ***** ................................................................ 1/8 bias S1D15607********* ................ 1/6 bias 7. All-indicator lamps-on OFF (All-indicator lamps ON/OFF command D0 = LOW) 8. Power saving clear 9. V5 voltage regulator internal resistors Ra and Rb separation (In case of S1D15605D11B*, S1D15606D11B*, S1D15607D11B * , S1D15608D11B * a nd S1D15609D11B*, internal resistors are connected while RES is LOW.) 10. Output conditions of SEG and COM terminals SEG : V2/V3 , COM : V1/V4 (In case of S1D15605D11B*, S1D15606D11B*, S1D15607D11B * , S1D15608D11B * a nd S1D15609D11B*, both the SEG terminal and the COM terminal output the VDA level while RES is LOW. In case of other models, the SEG terminal outputs V2 and the COM terminal outputs V1 while RES is LOW.) 11. Read modify write OFF 12. Static indicator OFF Static indicator register : (D1, D2) = (0, 0) 13. Display start line set to first line 14. Column address set to Address 0 15. Page address set to Page 0 16. Common output status normal 17. V5 voltage regulator internal resistor ratio set mode clear 18. Electronic volume register set mode clear Electronic volume register : (D5, D4, D3, D2, D1, D0) = (1, 0. 0, 0, 0, 0) 19. Test mode clear On the other hand, when the reset command is used, the above default settings from 11 to 19 are only executed. When the power is turned on, the IC internal state becomes unstable, and it is necessary to initialize it using the RES terminal. After the initialization, each input terminal should be controlled normally. Moreover, when the control signal from the MPU is in the high impedance, an overcurrent may flow to the IC. After applying a current, it is necessary to take proper measures to prevent the input terminal from getting into the high impedance state. If the internal liquid crystal power supply circuit is not used on S1D15605D11B * , S1D15606D11B * , S1D15607D11B* , S1D15608D11B* and S1D15609D11B *, it is necessary that RES is HIGH when the external liquid crystal power supply is turned on. This IC has the function to discharge V5 when RES is LOW, and the external power supply short-circuits to VDD when RES is LOW. While RES is LOW, the oscillator and the display timing generator stop, and the CL, FR, FRS and DOF terminals are fixed to HIGH. The terminals D0 to D7 are not affected. The VDD level is output from the SEG and COM output terminals. This means that an internal resistor is connected between V DD and V5 . When the internal liquid crystal power supply circuit is not used on other models of S1D15605 series, it is necessary that RE is LOWwhen the external liquid crystal power supply is turned on. While RES is LOW, the oscillator works but the display timing generator stops, and the CL, FR, FRS and DOF terminals are fixed to HIGH. The terminals D0 to D7 are not affected. 8–48 EPSON Rev. 2.4a S1D15605 Series 7. COMMANDS The S1D15605 Series chips identify the data bus signals by a combination of A0, RD (E), WR (R/W) signals. Command interpretation and execution does not depend on the external clock, but rather is performed through internal timing only, and thus the processing is fast enough that normally a busy check is not required. In the 8080 MPU interface, commands are launched by inputting a low pulse to the RD terminal for reading, and inputting a low pulse to the WR terminal for writing. In the 6800 Series MPU interface, the interface is placed in a read mode when an HIGH signal is input to the R/W terminal and placed in a write mode when a LOW signal is input to the R/W terminal and then the command is launched by inputting a high pulse to the E terminal. (See “10. Timing Characteristics” regarding the timing.) Consequently, the 6800 Series MPU interface is different than the 80x86 Series MPU interface in that in the explanation of commands and the display commands the status read and display data read RD (E) becomes “1(H)”. In the explanations below the commands are explained using the 8080 Series MPU interface as the example. When the serial interface is selected, the data is input in sequence starting with D7. (1) Display ON/OFF This command turns the display ON and OFF. A0 0 E R/W RD WR D7 D6 D5 D4 D3 D2 D1 D0 1 0 1 0 1 0 1 1 1 1 0 Setting Display ON Display OFF When the display OFF command is executed when in the display all points ON mode, power saver mode is entered. See the section on the power saver for details. (2) Display Start Line Set This command is used to specify the display start line address of the display data RAM shown in Figure 4. For further details see the explanation of this function in “The Line Address Circuit”. A0 0 E R/W RD WR D7 D6 D5 D4 D3 D2 D1 D0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 ↓ 1 1 1 1 1 0 1 1 1 1 1 1 Line address 0 1 2 ↓ 62 63 (3) Page Address Set This command specifies the page address corresponding to the low address when the MPU accesses the display data RAM (see Figure 4). Specifying the page address and column address enables to access a desired bit of the display data RAM. Changing the page address does not accompany a change in the status display. See the page address circuit in the Function Description (page 1–20) for the detail. A0 0 E R/W RD WR D7 D6 D5 D4 D3 D2 D1 D0 1 0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 1 0 ↓ 0 1 1 1 1 0 0 0 Page address 0 1 2 ↓ 7 8 Rev. 2.4a EPSON 8–49 S1D15605 Series (4) Column Address Set This command specifies the column address of the display data RAM shown in Figure 4. The column address is split into two sections (the higher 4 bits and the lower 4 bits) when it is set (fundamentally, set continuously). Each time the display data RAM is accessed, the column address automatically increments (+1), making it possible for the MPU to continuously read from/write to the display data. The column address increment is topped at 83H. This does not change the page address continuously. See the function explanation in “The Column Address Circuit,” for details. E R/W A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 A7 A6 HIGH bits → 0 1 0 0 0 0 1 A7 A6 A5 A4 0 0 LOW bits → 0 A3 A2 A1 A0 0 0 00 ↓↓ 10 10 (5) Status Read A0 0 E R/W RD WR 0 1 D7 BUSY D6 ADC D5 D4 ON/OFF RESET D3 D2 D1 D0 0 0 0 0 A5 0 0 0 0 0 A4 0 0 0 0 0 A3 0 0 0 0 0 A2 0 0 0 0 0 A1 0 0 1 1 1 Column A0 address 0 0 1 1 0 2 0 1 130 131 BUSY ADC ON/OFF RESET When BUSY = 1, it indicates that either processing is occurring internally or a reset condition is in process. While the chip does not accept commands until BUSY = 0, if the cycle time can be satisfied, there is no need to check for BUSY conditions. This shows the relationship between the column address and the segment driver. 0: Reverse (column address 131-n ↔ SEG n) 1: Normal (column address n ↔ SEG n) (The ADC command switches the polarity.) ON/OFF: indicates the display ON/OFF state. 0: Display ON 1: Display OFF (This display ON/OFF command switches the polarity.) This indicates that the chip is in the process of initialization either because of a RES signal or because of a reset command. 0: Operating state 1: Reset in progress (6) Display Data Write This command writes 8-bit data to the specified display data RAM address. Since the column address is automatically incremented by “1” after the write, the MPU can write the display data. E R/W A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 1 1 0 Write data (7) Display Data Read This command reads 8-bit data from the specified display data RAM address. Since the column address is automatically incremented by “1” after the read, the CPU can continuously read multiple-word data. One dummy read is required immediately after the column address has been set. See the function explanation in “Display Data RAM” for the explanation of accessing the internal registers. When the serial interface is used, reading of the display data becomes unavailable. E R/W A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 1 0 1 Read Data 8–50 EPSON Rev. 2.4a S1D15605 Series (8) ADC Select (Segment Driver Direction Select) This command can reverse the correspondence between the display RAM data column address and the segment driver output. Thus, sequence of the segment driver output pins may be reversed by the command. See the column address circuit (page 1–20) for the detail. Increment of the column address (by “1”) accompanying the reading or writing the display data is done according to the column address indicated in Figure 4. E R/W A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 10100000 1 Setting Normal Reverse (9) Display Normal/Reverse This command can reverse the lit and unlit display without overwriting the contents of the display data RAM. When this is done the display data RAM contents are maintained. E R/W A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 10100110 1 Setting RAM Data HIGH LCD ON voltage (normal) RAM Data LOW LCD ON voltage (reverse) (10) Display All Points ON/OFF This command makes it possible to force all display points ON regardless of the content of the display data RAM. The contents of the display data RAM are maintained when this is done. This command takes priority over the display normal/reverse command. E R/W A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 10100100 1 Setting Normal display mode Display all points ON When the display is in an OFF mode, executing the display all points ON command will place the display in power save mode. For details, see the (20) Power Save section. (11) LCD Bias Set This command selects the voltage bias ratio required for the liquid crystal display. This command can be valid while the V/F circuit of Power Supply circuit is in operation. E R/W Select Status A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 S1D15605***** S1D15606***** S1D15607***** S1D15608***** S1D15609 ***** 0 1 0 10100010 1/9 bias 1/8 bias 1/6 bias 1/8 bias 1/8 bias 1 1/7 bias 1/6 bias 1/5 bias 1/6 bias 1/6 bias (12) Read/Modify/Write This command is used paired with the “END” command. Once this command has been input, the display data read command does not change the column address, but only the display data write command increments (+1) the column address. This mode is maintained until the END command is input. When the END command is input, the column address returns to the address it was at when the read/modify/write command was entered. This function makes it possible to reduce the load on the MPU when there are repeating data changes in a specified display region, such as when there is a blanking cursor. E R/W A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 11100000 * Even in read/modify/write mode, other commands aside from display data read/write commands can also be used. However, the column address set command cannot be used. Rev. 2.4a EPSON 8–51 S1D15605 Series • The sequence for cursor display Page address set Column address set Read/modify/write Dummy read Data read Data process Data write No Change complete? Yes End Figure 24 (13) End This command releases the read/modify/write mode, and returns the column address to the address it was at when the mode was entered. E R/W A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 11101110 Return Column address N N+1 N+2 N+3 ••• N+m N End Read/modify/write mode set Figure 25 (14) Reset This command initializes the display start line, the column address, the page address, the common output mode, the V 5 voltage regulator internal resistor ratio, the electronic volume, and the static indicator are reset, and the read/modify/ write mode and test mode are released. There is no impact on the display data RAM. See the function explanation in “Reset” for details. The reset operation is performed after the reset command is entered. E R/W A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 11100010 The initialization when the power supply is applied must be done through applying a reset signal to the RES terminal. The reset command must not be used instead. 8–52 EPSON Rev. 2.4a S1D15605 Series (15) Common Output Mode Select This command can select the scan direction of the COM output terminal. For details, see the function explanation in “Common Output Mode Select Circuit.” E R/W A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 1 0 0 0 * * * Normal COM0→COM63 COM0→COM47 COM0→COM31 COM0→COM53 COM0 →COM51 1 Reverse COM63→COM0 COM47→COM0 COM31→COM0 COM53→COM0 COM51→COM0 Selected Mode S1D15605***** S1D15606***** S1D15607***** S1D15608***** S1D15609***** * Disabled bit (16) Power Controller Set This command sets the power supply circuit functions. See the function explanation in “The Power Supply Circuit,” for details E R/W A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 Selected Mode 0 1 0 001010 Booster circuit: OFF 1 Booster circuit: ON 0 Voltage regulator circuit: OFF 1 Voltage regulator circuit: ON 0 Voltage follower circuit: OFF 1 Voltage follower circuit: ON [Translator’s Note: the abbreviations explained within these parentheses for V and V/F have been written out in the English translation and are therefore no longer necessary.] (17) V 5 Voltage Regulator Internal Resistor Ratio Set This command sets the V 5 voltage regulator internal resistor ratio. For details, see the function explanation is “The Power Supply Circuits.” E R/W A0 RD WR D7 D6 D5 D4 D3 D2 0 1 0 001000 0 0 D1 0 0 1 ↓ 11 11 D0 0 1 0 0 1 Rb/Ra Ratio Small ↓ Large (18) The Electronic Volume (Double Byte Command) This command makes it possible to adjust the brightness of the liquid crystal display by controlling the liquid crystal drive voltage V 5 through the output from the voltage regulator circuits of the internal liquid crystal power supply. This command is a two byte command used as a pair with the electronic volume mode set command and the electronic volume register set command, and both commands must be issued one after the other. • The Electronic Volume Mode Set When this command is input, the electronic volume register set command becomes enabled. Once the electronic volume mode has been set, no other command except for the electronic volume register command can be used. Once the electronic volume register set command has been used to set data into the register, then the electronic volume mode is released. E R/W A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 10000001 Rev. 2.4a EPSON 8–53 S1D15605 Series • Electronic Volume Register Set By using this command to set six bits of data to the electronic volume register, the liquid crystal drive voltage V5 assumes one of the 64 voltage levels. When this command is input, the electronic volume mode is released after the electronic volume register has been set. E R/W A0 RD WR D7 D6 D5 0 1 0 * *0 0 1 0 * *0 0 1 0 * *0 0 0 1 1 0 0 * * * * D4 D3 00 00 00 ↓ 111 111 D2 0 0 0 1 1 D1 0 1 1 1 1 D0 1 0 1 0 1 | V5 | Small ↓ Large * Inactive bit When the electronic volume function is not used, set this to (1, 0, 0, 0, 0, 0) • The Electronic Volume Register Set Sequence Electronic volume mode set Electronic volume register set No Electronic volume mode clear Changes complete? Yes Figure 26 (19) Static Indicator (Double Byte Command) This command controls the static drive system indicator display. The static indicator display is controlled by this command only, and is independent of other display control commands. This is used when one of the static indicator liquid crystal drive electrodes is connected to the FR terminal, and the other is connected to the FRS terminal. A different pattern is recommended for the static indicator electrodes than for the dynamic drive electrodes. If the pattern is too close, it can result in deterioration of the liquid crystal and of the electrodes. The static indicator ON command is a double byte command paired with the static indicator register set command, and thus one must execute one after the other. (The static indicator OFF command is a single byte command.) • Static Indicator ON/OFF When the static indicator ON command is entered, the static indicator register set command is enabled. Once the static indicator ON command has been entered, no other command aside from the static indicator register set command can be used. This mode is cleared when data is set in the register by the static indicator register set command. E R/W A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 10101100 1 Static Indicator OFF ON 8–54 EPSON Rev. 2.4a S1D15605 Series • Static Indicator Register Set This command sets two bits of data into the static indicator register, and is used to set the static indicator into a blinking mode. E R/W A0 RD WR D7 D6 D5 D4 D3 D2 D1 0 1 0 ***** *0 0 1 1 D0 0 1 0 1 Indicator Display State OFF ON (blinking at approximately one second intervals) ON (blinking at approximately 0.5 second intervals) ON (constantly on) * Disabled bit • Static Indicator Register Set Sequence Static indicator mode set Static indicator register set Static indicator mode clear No Changes complete? Yes Figure 27 (20) Power Save (Compound Command) When the display all points ON is performed while the display is in the OFF mode, the power saver mode is entered, thus greatly reducing power consumption. The power saver mode has two different modes: the sleep mode and the standby mode. When the static indicator is OFF, it is the sleep mode that is entered. When the static indicator is ON, it is the standby mode that is entered. In the sleep mode and in the standby mode, the display data is saved as is the operating mode that was in effect before the power saver mode was initiated, and the MPU is still able to access the display data RAM. Refer to figure 28 for power save off sequence. Static indicator OFF Static indicator ON Power saver (compound command) Sleep mode Power save OFF (compound command) Display all points OFF command Static indicator ON (2 bytes command) Sleep mode cancel Standby mode Power save OFF (Display all points OFF command) Standby mode cancel Figure 28 Rev. 2.4a EPSON 8–55 S1D15605 Series • Sleep Mode This stops all operations in the LCD display system, and as long as there are no accesses from the MPU, the consumption current is reduced to a value near the static current. The internal modes during sleep mode are as follows: 1 The oscillator circuit and the LCD power supply circuit are halted. 2 All liquid crystal drive circuits are halted, and the segment in common drive outputs output a VDD level. • Standby Mode The duty LCD display system operations are halted and only the static drive system for the indicator continues to operate, providing the minimum required consumption current for the static drive. The internal modes are in the following states during standby mode. 1 The LCD power supply circuits are halted. The oscillator circuit continues to operate. 2 The duty drive system liquid crystal drive circuits are halted and the segment and common driver outputs output a VDD level. The static drive system does not operate. When a reset command is performed while in standby mode, the system enters sleep mode. * When an external power supply is used, it is recommended that the functions of the external power supply circuit be stopped when the power saver mode is started. For example, when the various levels of liquid crystal drive voltage are provided by external resistive voltage dividers, it is recommended that a circuit be added in order to cut the electrical current flowing through the resistive voltage divider circuit when the power saver mode is in effect. The S1D15605 series chips have a liquid crystal display blanking control terminal DOF. This terminal enters an LOW state when the power saver mode is launched. Using the output of DOF, it is possible to stop the function of an external power supply circuit. * When the master is turned on, the oscillator circuit is operable immediately after the powering on. (21) NOP Non-OPeration Command E R/W A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 11100011 (22) Test This is a command for IC chip testing. Please do not use it. If the test command is used by accident, it can be cleared by applying a LOW signal to the RES input by the reset command or by using an NOP. E R/W A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1111**** * Inactive bit Note: The S1D15605 Series chips maintain their operating modes until something happens to change them. Consequently, excessive external noise, etc., can change the internal modes of the S1D15605 Series chip. Thus in the packaging and system design it is necessary to suppress the noise or take measure to prevent the noise from influencing the chip. Moreover, it is recommended that the operating modes be refreshed periodically to prevent the effects of unanticipated noise. 8–56 EPSON Rev. 2.4a S1D15605 Series Table 16 Table of S1D15605 Series Commands Command Display ON/OFF Display start line set Page address set Column address set upper bit Column address set lower bit Status read Display data write Display data read ADC select A0 0 0 0 0 0 0 1 1 0 RD 1 1 1 1 1 0 1 0 1 WR 0 0 0 0 0 1 0 1 0 1 D7 1 0 1 0 0 Command Code D6 D5 D4 0 1 0 1 0 0 0 1 0 0 D3 1 D2 1 D1 1 D0 0 1 Function LCD display ON/OFF 0: OFF, 1: ON Sets the display RAM display start line address Sets the display RAM page address Sets the most significant 4 bits of the display RAM column address. Sets the least significant 4 bits of the display RAM column address. Reads the status data Writes to the display RAM Reads from the display RAM Sets the display RAM address SEG output correspondence 0: normal, 1: reverse Sets the LCD display normal/ reverse 0: normal, 1: reverse Display all points 0: normal display 1: all points ON Sets the LCD drive voltage bias ratio S1D15605***** .. 0: 1/9, 1: 1/7 S1D15606***** /S1D15608***** /S1D15609***** . 0: 1/8, 1: 1/6 S1D15607***** .. 0: 1/6, 1: 1/5 Column address increment At write: +1 At read: 0 Clear read/modify/write Internal reset Select COM output scan direction 0: normal direction, 1: reverse direction Select internal power supply operating mode Select internal resistor ratio (Rb/Ra) mode (1) (2) (3) (4) Display start address 1 1 0 Page address Most significant column address (5) (6) (7) (8) Status Least significant column address 0 0 0 0 Write data Read data 0 0 0 0 0 1 0 1 0 1 0 1 0 1 (9) Display normal/ reverse 0 1 0 1 0 1 0 0 1 1 (10) Display all points ON/OFF (11) LCD bias set 0 1 0 1 0 1 0 0 1 0 0 1 0 1 0 1 0 0 0 1 (12) Read/modify/write 0 1 0 1 1 1 0 0 0 0 0 (13) End (14) Reset (15) Common output mode select 0 0 0 1 1 1 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 0 0 1 1 0 * 1 1 * 0 0 * (16) Power control set (17) V5 voltage regulator internal resistor ratio set (18) Electronic volume mode set Electronic volume register set (19) Static indicator ON/OFF Static indicator register set (20) Power saver (21) NOP (22) Test 0 0 1 1 0 0 0 0 0 0 1 1 0 0 1 0 Operating mode Resistor ratio 0 0 0 0 1 1 1 1 0 0 0 0 1 * 1 * 0 * 0 * 0 0 0 0 0 1 Set the V5 output voltage electronic volume register 0: OFF, 1: ON Set the flashing mode Display OFF and display all points ON compound command Command for non-operation Command for IC test. Do not use this command (Note) *: disabled data Electronic volume value 1 * 0 * 1 * 1 * 0 0 1 Mode 0 0 1 1 0 0 1 1 1 1 1 1 0 1 0 * 0 * 1 * 1 * Rev. 2.4a EPSON 8–57 S1D15605 Series 8. COMMAND DESCRIPTION Instruction Setup: Reference (reference) (1) Initialization Note: With this IC, when the power is applied, LCD driving non-selective potentials V2 and V3 (SEG pin) and V1 and V4 (COM pin) are output through the LCD driving output pins SEG and COM. When electric charge is remaining in the smoothing capacitor connecting between the LCD driving voltage output pins (V1 ~ V5) and the VDD pin, the picture on the display may become totally dark instantaneously when the power is turned on. To avoid occurrence of such a failure, we recommend the following flow when turning on the power. 1 When the built-in power is being used immediately after turning on the power: Turn ON the VDD-VSS power keeping the RES pin = LOW. When the power is stabilized Release the reset state. (RES pin = HIGH) Initialized state (Default) *1 (In case of S1D15605D11B , * S1D15606D11B*, S1D15607D11B*, S1D15608D11B* and S1D15609D11B*) Arrange to execute all the procedures from releasing the reset state through setting the power control within 5ms. (In case of other models) execute the procedures from turning on the power to setting the power control in 5ms. Function setup by command input (User setup) (11) LCD bias setting *2 (8) ADC selection *3 (15) Common output state selection *4 Function setup by command input (User setup) (17) Setting the built-in resistance radio for regulation of the V5 voltage *5 (18) Electronic volume control *6 Function setup by command input (User setup) (16) Power control setting *7 This concludes the initialization * The target time of 5ms will result to vary depending on the panel characteristics and the capacitance of the smoothing capacitor. Therefore, we suggest you to conduct an operation check using the actual equipment. Notes: Refer to respective sections or paragraphs listed below. *1: 6. Description of functions; “Resetting circuit” (If takes not more than 2 ms from Power Supply ON to the stability of internal oscillating circuit.) *2: 7. Command description; “(11) LCD bias setting” *3: 7. Command description; “(8) ADC selection” *4: 7. Command description; “(15) Common output state selection” *5: 6. Description of functions; “Power circuit” & Command description; “(17) Setting the built-in resistance radio for regulation of the V5 voltage” *6: 6. Description of functions; “Power circuit” & Command description; “(18) Electronic volume control” *7: 6. Description of functions; “Power circuit” & Command description; “(16) Power control setting” 8–58 EPSON Rev. 2.4a S1D15605 Series 2 When the built-in power is not being used immediately after turning on the power: Turn ON the VDD-VSS power keeping the RES pin = LOW. When the power is stabilized Release the reset state. (RES pin = HIGH) Initialized state (Default) *1 Power saver START (multiple commands) *8 (In case of S1D15605D11B*, S1D15606D11B , S1D15607D11B , * * S1D15608D11B and S1D15609D11B ) * power saver within * Arrange to start the 5ms after releasing the reset state. (In case of other models) execute the procedures from turning on the power to setting the power control in 5ms. Function setup by command input (User setup) (11) LCD bias setting *2 (8) ADC selection *3 (15) Common output state selection *4 Function setup by command input (User setup) (17) Setting the built-in resistance radio for regulation of the V5 voltage *5 (18) Electronic volume control *6 Power saver OFF *8 Arrange to start power control setting within 5ms after turning OFF the power saver. Function setup by command input (User setup) (16) Power control setting *7 This concludes the initialization * The target time of 5ms will result to vary depending on the panel characteristics and the capacitance of the smoothing capacitor. Therefore, we suggest you to conduct an operation check using the actual equipment. Notes: Refer to respective sections or paragraphs listed below. *1: 6. Description of functions; “Resetting circuit” (The contents of DDRAM can be variable even in the initial setting (Default) at the reset state.) *2: 7. Command description; “(11) LCD bias setting” *3: 7. Command description; “(8) ADC selection” *4: 7. Command description; “(15) Common output state selection” *5: 6. Description of functions; “Power circuit” & “(17) Command description; Setting the built-in resistance radio for regulation of the V5 voltage” *6: 6. Description of functions; “Power circuit” & “(18) Command description; Electronic volume control” *7: 6. Description of functions; “Power circuit” & “(16) Command description; Power control setting” *8: 7. The power saver ON state can either be in sleep state or stand-by state. Command description; “Power saver START (multiple commands)” Rev. 2.4a EPSON 8–59 S1D15605 Series (2) Data Display End of initialization Function setup by command input (User setup) (2) Display start line set *9 (3) Page address set *10 (4) Column address set *11 Function setup by command input (User setup) (6) Display data write *12 Function setup by command input (User setup) (1) Display ON/OFF *13 End of data display Notes: Reference items *9: Command Description; Display start line set *10: Command Description; Page address set *11: Command Description; Column address set *12: Command Description; Display data write *13: Command Description; Display ON/OFF Avoid displaying all the data at the data display start (when the display is ON) in white. (3) Power OFF *14 • In case of S1D15605D11B*, S1D15606D11B*, S1D15607D11B*, S1D15608D11B* and S1D15609D11B*, Optional status Function setup by command input (User setup) (20) Power save *15 Reset active (RES pin = LOW) VDD – VSS power OFF Set the time (tL) from reset active to turning off the VDD - VSS power (VDD - VSS = 1.8 V) longer than the time (tH) when the potential of V5 ~ V1 becomes below the threshold voltage (approximately 1 V) of the LCD panel. For tH, refer to the of this event. When tH is too long, insert a resistor between V5 and VDD to reduce it. • In case of other models, Optional status Set the time (tL) from power save to turning off the VDD - VSS power (VDD - VSS = 1.8 V) longer than the time (tH) when the potential of V5 ~ V1 becomes below the threshold voltage (approximately 1V) of the LCD panel. • tH is determined depending on the voltage regulator external resistors Ra and Rb and the time constant of V5 ~ V1 smoothing capacity C2. • When an internal resistor is used, it is recommended to insert a resistor R between VDD and V5 to reduce tH. Function setup by command input (User setup) (20) Power save *15 VDD – VSS power OFF Notes: Reference items *14: The logic circuit of this IC’s power supply VDD - VSS controls the driver of the LCD power supply VDD - V5. So, if the power supply VDD - VSS is cut off when the LCD power supply VDD - V5 has still any residual voltage, the driver (COM. SEG) may output any uncontrolled voltage. When turning off the power, observe the following basic procedures: • After turning off the internal power supply, make sure that the potential V5 ~ V1 has become below the threshold voltage of the LCD panel, and then turn off this IC’s power supply (VDD - VSS ). 6. Description of Function, 6.7 Power Circuit *15: After inputting the power save command, be sure to reset the function using the RES terminal until the power supply VDD - VSS is turned off. 7. Command Description (20) Power Save *16: After inputting the power save command, do not reset the function using the RES terminal until the power supply VDD - VSS is turned off. 7. Command Description (20) Power Save 8–60 EPSON Rev. 2.4a S1D15605 Series (4) Refresh It is recommended that the operating modes and display contents be refreshed periodically to prevent the effect of unexpected noise. Refresh sequence NOP command Set all commands to the ready state (Including default state setting.) Refreshing of DRAM Precautions on Turning off the power • In case of S1D15605D11B*, S1D15606D11B*, S1D15607D11B*, S1D15608D11B* and S1D15609D11B*, Observe Paragraph 1) as the basic rule. 1) Power Save (The LCD powers (VDD - V5 ) are off.) → Reset input → Power (VDD - VSS) OFF • Observe tL > tH. • When tL < tH, an irregular display may occur. Set tL on the MPU according to the software. tH is determined according to the external capacity C 2 (smoothing capacity of V5 ~ V1) and the driver’s discharging capacity. Power save Reset Power Off tL VDD RES VDD SEG VDD COM Since the power (VDD-VSS) is cut off, the output comes not to be fixed. 1.8 V V1 V2 V3 V4 V5 About 1 V: Below Vth of the LCD panel tH For tH, see Figure 29. Rev. 2.4a EPSON 8–61 S1D15605 Series 2) Reset (The LCD powers (VDD - VSS) are off.) → Power (VDD - VSS) OFF • Observe tL > tH. • When tL < tH, an irregular display may occur. For t L, make the power (VDD - VSS) falling characteristics longer or consider any other method. t H is determined according to the external capacity C2 (smoothing capacity of V5 to V1) and the driver’s discharging capacity. Reset Power Off tL VDD RES VDD SEG VDD COM Since the power (VDD-VSS) is cut off, the output comes not be fixed. 1.8 V V1 V2 V3 V4 V5 About 1 V: Below Vth of the LCD panel tH For tH, see Figure 29. V5 voltage falling (discharge) time (tH) after the process of operation → power save → reset. V5 voltage falling (discharge) time (tH) after the process of operation → reset. 100 V5 voltage falling time (mSec) VDD-VSS(V) 1.8 2.4 50 3.0 4.0 5.0 0 0.5 C2: V1 to V5 capacity (uF) 1.0 Figure 29 8–62 EPSON Rev. 2.4a S1D15605 Series • In case of other models than the above Power save (The LCD powers (VDD - VSS) are off.) -> Power (V DD - VSS) OFF • Observe tL > tH. • When tL < tH, an irregular display may occur. Set tL on the MPU according to the software. tH is determined according to the external capacity C (smoothing capacity of V5 to V1) and the external resisters Ra + Rb (for V5 voltage regulation) Power save Power Off tL VDD 1.8 V SEG COM Since the power (VDD-VSS) is cut off, the output comes not be fixed. V1 V2 V3 V4 V5 About 1 V: Below Vth of the LCD panel tH tH is determined depending on the time constant of (Ra + Rb) C. Rev. 2.4a EPSON 8–63 S1D15605 Series 9. ABSOLUTE MAXIMUM RATINGS Unless otherwise noted, VSS = 0 V Table 17 Parameter Power Supply Voltage Power supply voltage (2) (VDD standard) With Triple step-up With Quad step-up Power supply voltage (3) (VDD standard) Power supply voltage (4) (VDD standard) Input voltage Output voltage Operating temperature Storage temperature TCP Bare chip Symbol VDD VSS2 Conditions –0.3 to +7.0 –7.0 to +0.3 –6.0 to +0.3 –4.5 to +0.3 –18.0 to +0.3 V5 to +0.3 –0.3 to VDD + 0.3 –0.3 to VDD + 0.3 –40 to +85 –55 to +100 –55 to +125 Unit V V V5, VOUT V1, V2 , V3 , V4 VIN VO TOPR TSTR V V V V °C °C VCC GND VDD VSS VDD VSS2, V1 to V4 V5, VOUT System (MPU) side S1D15605 Series chip side Figure 30 Notes and Cautions 1. The VSS2, V1 to V5 and VOUT are relative to the VDD = 0V reference. 2. Insure that the voltage levels of V1, V2, V3, and V 4 are always such that VDD ≥ V1 ≥ V 2 ≥ V3 ≥ V4 ≥ V 5. 3. Permanent damage to the LSI may result if the LSI is used outside of the absolute maximum ratings. Moreover, it is recommended that in normal operation the chip be used at the electrical characteristic conditions, and use of the LSI outside of these conditions may not only result in malfunctions of the LSI, but may have a negative impact on the LSI reliability as well. 8–64 EPSON Rev. 2.4a S1D15605 Series 10. DC CHARACTERISTICS Unless otherwise specified, VSS = 0 V, V DD = 3.0 V ± 10%, Ta = –40 to 85°C Table 18 Item Symbol Condition Rating Typ. — — Units V V Applicable Pin V DD*1 V DD*1 VDD Operating RecomVoltage (1) mended Voltage Possible Operating Voltage Operating RecomVSS2 Voltage (2) mended Voltage VSS2 Possible Operating Voltage Operating Possible V5 Voltage (3) Operating Voltage Possible V1, V2 Operating Voltage Possible V3, V4 Operating Voltage High-level Input Voltage Low-level Input Voltage High-level Output Voltage Low-level Output Voltage Input leakage current Output leakage current Liquid Crystal Driver ON Resistance Static Consumption Current Output Leakage Current Input Terminal Capacitance Oscillator Internal Frequency Oscillator External Input Internal Oscillator External Input VIHC VILC VOHC VOLC ILI ILO RON ISSQ I5Q C IN Min. 2.7 1.8 Max. 3.3 5.5 (Relative to V DD) (Relative to V DD) –3.3 –6.0 — — –2.7 –1.8 V V VSS2 VSS2 (Relative to V DD) (Relative to V DD) (Relative to V DD) –16.0 0.4 × V5 V5 — — — –4.5 VDD 0.6 × V5 V V V V5 *2 V1, V2 V3, V4 0.8 × VDD V SS IOH = –0.5 mA IOL = 0.5 mA VIN = VDD or VSS 0.8 × VDD V SS –1.0 –3.0 Ta = 25°C V5 = –14.0 V (Relative To VDD) V5 = –8.0 V — — — V5 = –18.0 V (Relative To VDD) Ta = 25°C f = 1 MHz Ta = 25°C S1D15605*****/15607***** Ta = 25°C S1D15606*****/15608*****/ 15609 — — 18 18 27 14 — — — — — — 2.0 3.2 0.01 0.01 5.0 22 22 33 17 VDD 0.2 × VDD VDD 0.2 × VDD 1.0 3.0 3.5 5.4 5 15 8.0 26 26 39 20 V V V V µA µA kΩ kΩ µA µA pF kHz kHz kHz kHz *3 *3 *4 *4 *5 *6 SEGn COMn *7 V SS, VSS2 V5 fOSC fCL fOSC fCL *8 CL *8 CL ***** Rev. 2.4a EPSON 8–65 S1D15605 Series Table 19 Rating Typ. — — — Applicable Pin VSS2 VSS2 VOUT Item Input voltage Symbol VSS2 VSS2 Condition With Triple (Relative To VDD) With Quad (Relative To VDD) (Relative to VDD) Min. –6.0 –4.5 –18.0 Max. –1.8 –1.8 — Units V V V Supply Step-up VOUT output voltage Circuit Voltage regulator VOUT Circuit Operating Voltage V5 Voltage Follower Circuit Operating Voltage Base Voltage VREG0 VREG1 Internal Power (Relative to VDD) –18.0 — –6.0 V VOUT (Relative to VDD) Ta = 25°C –0.05%/°C (Relative to VDD) –0.2%/°C –16.0 — –4.5 V V5 *9 –2.04 –4.65 –2.10 –4.9 –2.16 –5.15 V V *10 *10 8–66 EPSON Rev. 2.4a S1D15605 Series • Dynamic Consumption Current (1), During Display, with the Internal Power Supply OFF Current consumed by total ICs when an external power supply is used. Table 20 Display Pattern OFF Item S1D15605***** S1D15606***** S1D15607***** S1D15608*****/ S1D15609***** Symbol IDD (1) Condition VDD = 5.0 V, V5 – VDD = –11.0 V VDD = 3.0 V, V5 – VDD = –11.0 V VDD = 3.0 V, V5 – VDD = –11.0 V VDD = 5.0 V, V5 – VDD = –8.0 V VDD = 3.0 V, V5 – VDD = –8.0 V VDD = 5.0 V, V5 – VDD = –8.0 V VDD = 3.0 V, V5 – VDD = –8.0 V VDD = 5.0 V, V5 – VDD = –8.0 V VDD = 3.0 V, V5 – VDD = –8.0 V Table 21 Display Pattern Checker Item S1D15605***** S1D15606***** S1D15607***** S1D15608*****/ S1D15609***** Symbol IDD (1) Condition VDD = 5.0 V, V5 – VDD = –11.0 V VDD = 3.0 V, V5 – VDD = –11.0 V VDD = 3.0 V, V5 – VDD = –11.0 V VDD = 5.0 V, V5 – VDD = –8.0 V VDD = 3.0 V, V5 – VDD = –8.0 V VDD = 5.0 V, V5 – VDD = –8.0 V VDD = 3.0 V, V5 – VDD = –8.0 V VDD = 5.0 V, V5 – VDD = –8.0 V VDD = 3.0 V, V5 – VDD = –8.0 V Ta = 25°C Min. — — — — — — — — — Rating Units Notes Typ. Max. 18 30 µA *11 16 27 13 22 11 19 9 15 8 13 7 12 12 20 10 17 Ta = 25°C Rating Units Notes Min. Typ. Max. — 23 38 µA *11 — 21 35 — 17 29 — 14 24 — 12 20 — 11 18 — 10 17 — 15 25 — 13 22 • Dynamic Consumption Current (2), During Display, with the Internal Power Supply ON The values of curret consumed in all the IC including internal power supply circuit. Table 22 Display Pattern OFF Item S1D15605***** Symbol Condition Ta = 25°C Rating Units Notes Min. Typ. Max. — 67 112 µA *12 — 114 190 — 81 135 — 138 230 — 35 59 — 64 107 — 43 72 — 84 140 — 72 121 — 128 214 — 26 44 — 60 100 — 29 49 — 73 122 — 37 62 — 67 112 — 46 77 — 87 145 8–67 S1D15606***** S1D15607***** S1D15608*****/ S1D15609***** IDD (2) VDD = 5.0 V, Triple step-up voltage. Normal Mode V5 – VDD = –11.0 V High-Power Mode VDD = 3.0 V, Quad step-up voltage. Normal Mode V5 – VDD = –11.0 V High-Power Mode VDD = 5.0 V, Double step-up voltage. Normal Mode V5 – VDD = –8.0 V High-Power Mode VDD = 3.0 V, Triple step-up voltage. Normal Mode V5 – VDD = –8.0 V High-Power Mode VDD = 3.0 V, Quad step-up voltage. Normal Mode V5 – VDD = –11.0 V High-Power Mode VDD = 5.0 V, Double step-up voltage. Normal Mode V5 – VDD = –8.0 V High-Power Mode VDD = 3.0 V, Triple step-up voltage. Normal Mode V5 – VDD = –8.0 V High-Power Mode VDD = 5.0 V, Double step-up voltage. Normal Mode V5 – VDD = –8.0 V High-Power Mode VDD = 3.0 V, Triple step-up voltage. Normal Mode V5 – VDD = –8.0 V High-Power Mode Rev. 2.4a EPSON S1D15605 Series Table 23 Display Pattern Checker Item S1D15605***** Symbol Condition S1D15606***** S1D15607***** S1D15608*****/ S1D15609***** IDD (2) V DD = 5.0 V, Triple step-up voltage. Normal Mode V5 – V DD = –11.0 V High-Power Mode V DD = 3.0 V, Quad step-up voltage. Normal Mode V5 – V DD = –11.0 V High-Power Mode VDD = 5.0 V, Double step-up voltage. Normal Mode V5 – V DD = –8.0 V High-Power Mode V DD = 3.0 V, Triple step-up voltage. Normal Mode V5 – V DD = –8.0 V High-Power Mode V DD = 3.0 V, Quad step-up voltage. Normal Mode V5 – V DD = –11.0 V High-Power Mode VDD = 5.0 V, Double step-up voltage. Normal Mode V5 – V DD = –8.0 V High-Power Mode V DD = 3.0 V, Triple step-up voltage. Normal Mode V5 – V DD = –8.0 V High-Power Mode VDD = 5.0 V, Double step-up voltage. Normal Mode V5 – V DD = –8.0 V High-Power Mode V DD = 3.0 V, Triple step-up voltage. Normal Mode V5 – V DD = –8.0 V High-Power Mode Ta = 25° C Rating Units Notes Min. Typ. Max. — 81 135 µA *12 — 127 212 — 96 160 — 153 255 — 41 69 — 71 119 — 51 85 — 92 154 — 85 142 — 142 237 — 32 53 — 62 103 — 44 73 — 89 148 — 44 74 — 74 127 — 54 90 — 95 159 • Consumption Current at Time of Power Saver Mode, VSS = 0 V, V DD = 3.0 V ± 10% Table 24 Ta = 25° C Item Sleep mode Standby Mode Sleep mode Standby Mode Sleep mode Standby Mode Sleep mode S1D15605***** S1D15605***** S1D15606***** S1D15606***** S1D15607***** S1D15607***** S1D15608*****/ S1D15609***** Standby Mode S1D15608*****/ S1D15609***** Symbol IDDS1 IDDS2 IDDS1 IDDS2 IDDS1 IDDS2 IDDS1 IDDS2 Condition — — — — — — — — Rating Units Notes Min. Typ. Max. 0.01 5 µA 4 8 µA 0.01 5 µA 4 8 µA 0.01 5 µA 3 6 µA 0.01 5 µA 4 8 µA TBD: To Be Determined 8–68 EPSON Rev. 2.4a S1D15605 Series Reference Data 1 • Dynamic Consumption Current (1) During LCD Display Using an External Power Supply 40 IDD (1) (ISS + I5) [µA] 30 20 10 Conditions: Internal power supply OFF External power supply in use S1D15605/S1D15606 (–11.0V): V5 – VDD = –11.0 V S1D15606 (–8.0V)/S1D15607/ S1D15608/S1D15609: V5 – VDD = –8.0 V Display pattern: OFF Ta = 25°C S1D15605 S1D15606 (–11.0V) S1D15608/S1D15609 (–8.0V) S1D15606 (–8.0V) S1D15607 Note: *11 0 0 2 4 VDD [V] 6 8 Figure 31 40 IDD (1) (ISS + I5) [µA] 30 20 10 Conditions: Internal power supply OFF External power supply in use S1D15605/S1D15606 (–11.0V): V5 – VDD = –11.0 V S1D15606 (–8.0V)/S1D15607/ S1D15608/S1D15609: V5 – VDD = –8.0 V S1D15605 Display pattern: Checker S1D15606 (–11.0V) Ta = 25°C S1D15608/S1D15609 (–8.0V) S1D15606 (–8.0V) S1D15607 Note: *11 0 0 2 4 VDD [V] 6 8 Figure 32 Rev. 2.4a EPSON 8–69 S1D15605 Series Reference Data 2 • Dynamic Consumption Current (2) During LCD display using the internal power supply 140 120 100 IDD (2) [µA] 80 60 40 20 0 0 2 4 VDD [V] Conditions: Internal power supply ON S1D15605/S1D15606 (×4, –11.0V)/ S1D15608/S1D15609 (×4, –11.0V): 4× step-up voltage: V5 – VDD = –11.0 V S1D15606 (×3, –8.0V)/S1D15607/ S1D15608/S1D15609 (×3, –8.0V): 3× step-up voltage: V5 – VDD = –8.0 V S1D15605 Normal mode S1D15608/15609 (x4, –11.0V) Display pattern: OFF S1D15606 (x4, –11.0V) Ta = 25°C S1D15608/S1D15609 (x3, –8.0V) S1D15606 (x3, –8.0V) S1D15607 Note: *12 6 8 Figure 33 120 100 80 60 40 20 0 0 IDD (2) [µA] Conditions: Internal power supply ON S1D15605/S1D15606 (×4, –11.0V)/ S1D15608/S1D15609 (×4, –11.0V): 4× step-up voltage: V5 – VDD = –11.0 V S1D15606 (×3, –8.0V)/S1D15607/ S1D15608/S1D15609 (×3, –8.0V): S1D15605 3× step-up voltage: V5 – VDD = –8.0 V S1D15608/15609 (x4, –11.0V) Normal mode S1D15606 (x4, –11.0V) Display pattern: Checker Ta = 25°C S1D15608/S1D15609 (x3, –8.0V) S1D15606 (x3, –8.0V) S1D15607 Note: *12 2 4 VDD [V] 6 8 Figure 34 8–70 EPSON Rev. 2.4a S1D15605 Series Reference Data 3 • Dynamic Consumption Current (3) During access 10 This figure indicates the consumption current while the checker pattern is constantly written through fCYC. If there is no access, then only (1) remains. Conditions: Internal power supply OFF, external power supply used S1D15605: VDD – VSS = 3.0 V, V5=–11.0 V S1D15606/S1D15607/ S1D15608/S1D15609: VDD – VSS = 3.0 V, V5=–8.0 V Ta = 25°C 1 IDD(3)[mA] 0.1 S1D15605 S1D15606 S1D15607 S1D15608/S1D15609 0.01 0.001 0.01 0.1 fCYC[MHz] 1 10 Figure 35 Reference Data 4 • Operating voltage range of VSS and V5 systems –20 S1D15605 Series Note: *2 –16 –15 V5-VDD[V] –10 –7.2 Operating range –5 –4.5 0 0 1.8 2 3.0 4 VDD[V] 5.5 6 8 Figure 36 Rev. 2.4a EPSON 8–71 S1D15605 Series • The Relationship Between Oscillator Frequency fOSC, Display Clock Frequency fCL and the Liquid Crystal Frame Rate Frequency f FR Table 25 S1D15605***** Item When the internal oscillator circuit is used When the internal oscillator circuit is not used S1D15606***** When the internal oscillator circuit is used When the internal oscillator circuit is not used S1D15607***** When the internal oscillator circuit is used When the internal oscillator circuit is not used S1D15608***** When the internal oscillator circuit is used When the internal oscillator circuit is not used S1D15609***** When the internal oscillator circuit is used When the internal oscillator circuit is not used fCL fOSC ____ 4 External input (fCL) fOSC ____ 8 External input (fCL) fOSC ____ 8 External input (fCL) fOSC ____ 8 External input (fCL) fOSC ____ 8 External input (fCL) fFR fOSC _____ 4 × 65 fCL ____ 260 fOSC _____ 8 × 49 fCL ____ 196 fOSC _____ 8 × 33 fCL ____ 264 fOSC _____ 8 × 55 fCL ____ 220 fOSC _____ 8 × 53 fCL ____ 212 (fFR is the liquid crystal alternating current period, and not the FR signal period.) References for items market with * *1 While a broad range of operating voltages is guaranteed, performance cannot be guaranteed if there are sudden fluctuations to the voltage while the MPU is being accessed. *2 The operating voltage range for the VDD system and the V5 system is as shown in Figure 36. This applies when the external power supply is being used. *3 The A0, D0 to D5, D6 (SCL), D7 (SI), RD (E), WR (R/W), CS1, CS2, CLS, CL, FR, M/S, C86, P/S, DOF, RES, IRS, and HPM terminals. *4 The D0 to D7, FR, FRS, DOF, and CL terminals. *5 The A0, RD (E), WR (R/W), CS1, CS2, CLS, M/S, C86, P/S, RES, IRS, and HPM terminals. *6 Applies when the D0 to D5, D6 (SCL), D7 (SI), CL, FR, and DOF terminals are in a high impedance state. *7 These are the resistance values for when a 0.1 V voltage is applied between the output terminal SEGn or COMn and the various power supply terminals (V1, V2, V3, and V 4). These are specified for the operating voltage (3) range. RON = 0.1 V/∆ I (Where ∆ I is the current that flows when 0.1 V is applied while the power supply is ON.) *8 See Table 9-7 for the relationship between the oscillator frequency and the frame rate frequency. *9 The V5 voltage regulator circuit regulates within the operating voltage range of the voltage follower. *10 This is the internal voltage reference supply for the V5 voltage regulator circuit. In the S1D15605/S1D15606/ S1D15607 chips, the temperature range can come in three types as VREG options: (1) approximately–0.05%/ °C, (2) –0.2%/° C, and (3) external input. *11, 12 It indicates the current consumed on ICs alone when the internal oscillator circuit and display are turned on. The S1D15605 is 1/9 biased, S1D15606/S1D15608/S1D15609 is 1/8 biased and S1D15607 is 1/6 biased. Does not include the current due to the LCD panel capacity and wiring capacity. Applicable only when there is no access from the MPU. *12 It is the value on a model having the VREG option temperature gradient is –0.05%/°C when the V 5 voltage regulator internal resistor is used. 8–72 EPSON Rev. 2.4a S1D15605 Series 11. TIMING CHARACTERISTICS (1) System Bus Read/Write Characteristics 1 (For the 8080 Series MPU) A0 tAW8 CS1 (CS2="1") *1 WR, RD CS1 (CS2="1") *2 WR, RD tAH8 tCYC8 tCCLR, tCCLW tCCHR, tCCHW tf tr tDS8 D0 to D7 (Write) tDH8 tACC8 D0 to D7 (Read) tOH8 Figure 37 Table 26 Item Address hold time Address setup time System cycle time Control LOW pulse width (WR) Control LOW pulse width (RD) Control HIGH pulse width (WR) Control HIGH pulse width (RD) Data setup time Address hold time RD access time Output disable time Signal A0 A0 WR RD WR RD D0 to D7 Symbol tAH8 tAW8 tCYC8 tCCLW tCCLR tCCHW tCCHR tDS8 tDH8 tACC8 tOH8 (VDD = 4.5 V to 5.5 V, Ta = –40 to 85° C ) Rating Condition Units Min. Max. 0 — ns 0 — ns 166 — ns 30 — ns 70 — ns 30 — ns 30 — ns 30 — ns 10 — ns CL = 100 pF — 70 ns 5 50 ns Rev. 2.4a EPSON 8–73 S1D15605 Series Table 27 Item Address hold time Address setup time System cycle time Control LOW pulse width (WR) Control LOW pulse width (RD) Control HIGH pulse width (WR) Control HIGH pulse width (RD) Data setup time Address hold time RD access time Output disable time Signal A0 A0 WR RD WR RD D0 to D7 Symbol tAH8 tAW8 tCYC8 tCCLW tCCLR tCCHW tCCHR tDS8 tDH8 tACC8 tOH8 (VDD = 2.7 V to 4.5 V, Ta = –40 to 85°C ) Rating Condition Units Min. Max. 0 — ns 0 — ns 300 — ns 60 — ns 120 — ns 60 — ns 60 — ns 40 — ns 15 — ns CL = 100 pF — 140 ns 10 100 ns Table 28 Item Address hold time Address setup time System cycle time Control LOW pulse width (WR) Control LOW pulse width (RD) Control HIGH pulse width (WR) Control HIGH pulse width (RD) Data setup time Address hold time RD access time Output disable time *1 *2 *3 *4 *5 Signal A0 A0 WR RD WR RD D0 to D7 Symbol tAH8 tAW8 tCYC8 tCCLW tCCLR tCCHW tCCHR tDS8 tDH8 tACC8 tOH8 (VDD = 1.8 V to 2.7 V, Ta = –40 to 85° C ) Rating Condition Units Min. Max. 0 — ns 0 — ns 1000 — ns 120 — ns 240 — ns 120 — ns 120 — ns 80 — ns 30 — ns CL = 100 pF — 280 ns 10 200 ns This is in the case of making the access by WR and RD,setting the CS1=LOW. This is the case of making the accese by CS1,setting the WR,RD=LOW. The rise and fall times (tr and tf) of the input signal are specified for less than 15 ns.When using the system cycle time at high speed, they are specified for (tr + tf) ≤ (tCYC8-tCCLR-tCCHR). All timings are specified based on the 20 and 80% of VDD. tCCLW and tCCLR are specified for the overlap period when CS1 is at LOW (CS2=HIGH) level and WR,RD are at the LOW level. 8–74 EPSON Rev. 2.4a S1D15605 Series (2) System Bus Read/Write Characteristics 2 (6800 Series MPU) A0 R/W tAW6 CS1 (CS2="1") *1 E tAH6 tEWHR, tEWHW tCYC6 tEWLR, tEWLWW CS1 (CS2="1") *2 E tr tf tDS6 D0 to D7 (Write) tDH6 tACC6 D0 to D7 (Read) tOH6 Figure 38 Table 29 Item Address hold time Address setup time System cycle time Data setup time Data hold time Access time Output disable time Enable HIGH pulse time Enable LOW pulse time Signal A0 A0 D0 to D7 Symbol Read Write Read Write E E tAH6 tAW6 tCYC6 tDS6 tDH6 tACC6 tOH6 tEWHR tEWHW tEWLR tEWLW (VDD = 4.5 V to 5.5 V, Ta = –40 to 85° C ) Rating Condition Units Min. Max. 0 — ns 0 — ns 166 — ns 30 — ns 10 — ns CL = 100 pF — 70 ns 10 50 ns 70 — ns 30 — ns 30 — ns 30 — ns Rev. 2.4a EPSON 8–75 S1D15605 Series Table 30 Item Address hold time Address setup time System cycle time Data setup time Data hold time Access time Output disable time Enable HIGH pulse time Enable LOW pulse time Signal A0 A0 D0 to D7 Symbol Read Write Read Write E E tAH6 tAW6 tCYC6 tDS6 tDH6 tACC6 tOH6 tEWHR tEWHW tEWLR tEWLW (VDD = 2.7 V to 4.5 V, Ta = –40 to 85°C ) Rating Condition Units Min. Max. 0 — ns 0 — ns 300 — ns 40 — ns 15 — ns CL = 100 pF — 140 ns 10 100 ns 120 — ns 60 — ns 60 — ns 60 — ns Table 31 Item Address hold time Address setup time System cycle time Data setup time Data hold time Access time Output disable time Enable HIGH pulse time Enable LOW pulse time *1 *2 *3 *4 *5 Signal A0 A0 D0 to D7 Symbol Read Write Read Write E E tAH6 tAW6 tCYC6 tDS6 tDH6 tACC6 tOH6 tEWHR tEWHW tEWLR tEWLW (VDD = 1.8 V to 2.7 V, Ta = –40 to 85°C ) Rating Condition Units Min. Max. 0 — ns 0 — ns 1000 — ns 80 — ns 30 — ns CL = 100 pF — 280 ns 10 200 ns 240 — ns 120 — ns 120 — ns 120 — ns This is in the case of making the access by E, setting the CS1=LOW. This is the case of making the accese by CS1,setting the E=HIGH. The rise and fall times ((tr and tf) of the input signal are specified for less than 15 ns.When using the system cycle time at high speed, they are specified for (tr + tf) ≤ (tCYC6-tEWLW-tEWHW) or (tr + tf) ≤ (tCYC6-tEWLR-tEWHR). All timings are specified based on the 20 and 80% of VDD. tEWLW and tEWLR are specified for the overlap period when CS1 is at LOW (CS2=HIGH) level and E is at the HIGH level. 8–76 EPSON Rev. 2.4a S1D15605 Series (3) The Serial Interface CS1 (CS2="1") tCSS tCSH tSAS A0 tSAH tSCYC tSLW SCL tSHW tf tSDS SI tr tSDH Figure 39 Table 32 Item Serial Clock Period SCL HIGH pulse width SCL LOW pulse width Address setup time Address hold time Data setup time Data hold time CS-SCL time Signal SCL Symbol A0 SI CS tSCYC tSHW tSLW tSAS tSAH tSDS tSDH tCSS tCSH (VDD = 4.5 V to 5.5 V, Ta = –40 to 85° C ) Rating Condition Units Min. Max. 200 — ns 75 — ns 75 — ns 50 — ns 100 — ns 50 — ns 50 — ns 100 — ns 100 — ns Rev. 2.4a EPSON 8–77 S1D15605 Series Table 33 Item Serial Clock Period SCL HIGH pulse width SCL LOW pulse width Address setup time Address hold time Data setup time Data hold time CS-SCL time Signal SCL Symbol A0 SI CS tSCYC tSHW tSLW tSAS tSAH tSDS tSDH tCSS tCSH Table 34 (VDD = 2.7 V to 4.5 V, Ta = –40 to 85° C ) Rating Condition Units Min. Max. 250 — ns 100 — ns 100 — ns 150 — ns 150 — ns 100 — ns 100 — ns 150 — ns 150 — ns Item Serial Clock Period SCL HIGH pulse width SCL LOW pulse width Address setup time Address hold time Data setup time Data hold time CS-SCL time Signal SCL Symbol A0 SI CS tSCYC tSHW tSLW tSAS tSAH tSDS tSDH tCSS tCSH (VDD = 1.8 V to 2.7 V, Ta = –40 to 85° C ) Rating Condition Units Min. Max. 400 — ns 150 — ns 150 — ns 250 — ns 250 — ns 150 — ns 150 — ns 250 — ns 250 — ns *1 The input signal rise and fall time (tr, tf) are specified at 15 ns or less. *2 All timing is specified using 20% and 80% of VDD as the standard. 8–78 EPSON Rev. 2.4a S1D15605 Series (4) Display Control Output Timing CL (OUT) tDFR FR Figure 40 Table 35 Item FR delay time Signal FR Symbol tDFR (VDD = 4.5 V to 5.5 V, Ta = –40 to 85°C) Rating Condition Units Min. Typ. Max. CL = 50 pF — 10 40 ns Table 36 Item FR delay time Signal FR Symbol tDFR (VDD = 2.7 V to 4.5 V, Ta = –40 to 85°C) Rating Condition Units Min. Typ. Max. CL = 50 pF — 20 80 ns Table 37 Item FR delay time Signal FR Symbol tDFR (VDD = 1.8 V to 2.7 V, Ta = –40 to 85°C) Rating Condition Units Min. Typ. Max. CL = 50 pF — 50 200 ns *1 Valid only when the master mode is selected. *2 All timing is based on 20% and 80% of VDD. Rev. 2.4a EPSON 8–79 S1D15605 Series Reset Timing tRW RES tR Internal status During reset Reset complete Figure 41 Table 38 Item Reset time Reset LOW pulse width Signal Symbol (VDD = 4.5 V to 5.5 V, Ta = –40 to 85°C) Rating Condition Units Min. Typ. Max. — — 0.5 µs 0.5 — — µs tR RES tRW Table 39 Item Reset time Reset LOW pulse width Signal Symbol tR RES tRW (VDD = 2.7 V to 4.5 V, Ta = –40 to 85°C) Rating Condition Units Min. Typ. Max. — — 1 µs 1 — — µs Table 40 Item Reset time Reset LOW pulse width Signal Symbol tR RES tRW (VDD = 1.8 V to 2.7 V, Ta = –40 to 85°C) Rating Condition Units Min. Typ. Max. — — 1.5 µs 1.5 — — µs *1 All timing is specified with 20% and 80% of VDD as the standard. 8–80 EPSON Rev. 2.4a S1D15605 Series 12. THE MPU INTERFACE (REFERENCE EXAMPLES) The S1D15605 Series can be connected to either 80 × 86 Series MPUs or to 6800 Series MPUs. Moreover, using the serial interface it is possible to operate the S1D15605 series chips with fewer signal lines. The display area can be enlarged by using multiple S1D15605 Series chips. When this is done, the chip select signal can be used to select the individual ICs to access. (1) 8080 Series MPUs VDD VCC A0 MPU VDD A0 Decoder CS1 CS2 D0 to D7 RD WR RES VSS A1 to A7 IORQ C86 S1D15605 Series D0 to D7 RD WR RES GND P/S RESET VSS Figure 42-1 (2) 6800 Series MPUs VDD VCC A0 A0 Decoder CS1 CS2 D0 to D7 E R/W RES VSS A1 to A15 VMA VDD C86 D0 to D7 E R/W RES GND RESET S1D15605 Series P/S VSS MPU Figure 42-2 (3) Using the Serial Interface VDD or VSS VCC A0 A1 to A7 A0 Decoder CS1 CS2 SI SCL RES VSS VDD C86 Port 1 Port 2 RES GND RESET S1D15605 Series P/S VSS MPU Figure 42-3 Rev. 2.4a EPSON 8–81 S1D15605 Series 13. CONNECTIONS BETWEEN LCD DRIVERS (REFERENCE EXAMPLE) The liquid crystal display area can be enlarged with ease through the use of multiple S1D15605 Series chips. Use a same equipment type. (1) S1D15605 (master) ↔ S1D15605 (slave) VDD M/S S1D15605 Series Master M/S FR CL DOF Output Input FR CL DOF S1D15605 Series Slave VSS Figure 43 8–82 EPSON Rev. 2.4a S1D15605 Series 14. CONNECTIONS BETWEEN LCD DRIVERS (REFERENCE EXAMPLES) The liquid crystal display area can be enlarged with ease through the use of multiple S1D15605 Series chips. Use a same equipment type, in the composition of these chips. (1) Single-chip Structure 132 x 65 Dots COM SEG S1D15605 Series Master COM Figure 44-1 (2) Double-chip Structure, #1 264 x 65 Dots COM SEG S1D15605 Series Master SEG S1D15605 Series Slave COM Figure 44-2 Rev. 2.4a EPSON 8–83 S1D15605 Series 15. A SAMPLE TCP PIN ASSIGNMENT S1D15605T00B* TCP Pin Layout Note: The following does not specify dimensions of the TCP pins. An example FR FR CL DOF CS1 CS2 RES A0 WR,R/W RD, E D0 D1 D2 D3 D4 D5 D6, SCL D7, SI VDD VSS VSS2 VOUT CAP3CAP1+ CAP1CAP2CAP2+ VRS VDD V1 V2 V3 V4 V5 VR VDD M/S CLS C86 P/S HPM IRS COM 0 • • • • • COM 30 COM 31 FRS COM S COM 63 • • • • • COM 33 COM 32 CHIP TOP VIEW SEG 131 SEG 130 • • • • • SEG 1 SEG 0 COM S 8–84 EPSON Rev. 2.4a (Mold, marking area) (Mold, marking area) Rev. 2.4a Section A Section A (Mold, marking area) (Mold, marking area) 16. EXTERNAL VIEW OF TCP PINS EPSON Specifications • Base: U-rexS, 75µm • Copper foil: Electrolytic copper foil, 25µm • Sn plating • Product pitch: 41P (19.0mm) • Solder resist positional tolerance: ±0.3 Section A Output terminal pattern shape Section B Test pat detailed view S1D15605 Series 8–85