SCG4501 Synchronous Clock Generators
P LL
2111 Comprehensive Drive Aurora, Illinois 60505 Phone: 630-851-4722 Fax: 630-851-5040 www.conwin.com
Features • ± 32 ppm Capture/Pull-In Range • Phase Locked Output Frequency Control • Intrinsically Low Jitter Crystal Oscillator • LVPECL Outputs with Disable Function • Dual Input References • LOR & LOL combined alarm output • Force Free Run Function • Automatic Free Run operation on loss of both References A & B • Input Duty Cycle Tolerant
Bulletin Page Revision Date Issued By
SG040 1 of 16 P01 13 NOV 03 MBatts
• 3.3V dc Power Supply • Small Size: 1 Square Inch
General Description
The SCG4501 is a mixed-signal phase locked loop generating LVPECL outputs from an intrinsically low jitter, voltage controlled, crystal oscillator. The LVPECL outputs may be disabled. The SCG4501 can lock to one of two external references, which is selectable using the SELAB input select pin. The unit has a fast acquisition time of about 1.5 seconds and it is tolerant of different reference duty cycles. The SCG4501 includes an alarm output that indicates deviations from normal operation. If a Lossof-Reference (LOR) or Loss-of-Lock (LOL) is detected the alarm with indicate the need for a reference rearrangement. If both references A and B are absent the module will enter Free Run operation. The FRstatus pin will indicate that the module is in Free Run operation. Frequency stability during Free Run operation is guaranteed to ±20 ppm. Additionally the Free Run mode may be entered manually. The package dimensions are 1” x 1.025” x .45” on a 6 layer FR4 board with castellated pins. Parts are assembled using high temperature solder to withstand 63/37 alloys, 180°C surface mount reflow processes.
Maximum Dimension Package Outline
Figure 1
Block Diagram
Figure 2
10 kΩ
FORCE FREE RUN
33 Ω
FREE RUN STATUS
10 kΩ
ALARM Q QN
REFA REFB
33 Ω
8 KHz PHASE ALIGNER
DPFD
ANALOG FILTER
LOW JITTER VCXO
SEL AB
10 kΩ
1/N
33 Ω
ENABLE/ TRI-STATE
10 kΩ
OPTIONAL REFERENCE OUTPUT
Absolute Maximum Rating
Table 1
Symbol Vcc Vi Ts Parameter Power Supply Voltage Input Voltage Storage Temperature Minimum -0.5 -0.5 -65.0 Nominal Maximum +4.0 +5.5 +100 Units Volts Volts °C Notes 1.0 1.0 1.0
Preliminary Data Sheet #: SG040
Page 2 of 16
Rev: P01
Date: 11/13/03
© Copyright 2003 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Operating Specifications
Table 2
Symbol Vcc Icc To Ffr Fcap Fbw Tjtol Taq Parameter Power Supply Voltage Power Supply Current Temperature Range Free Run Frequency Capture/pull-in range Jitter Filter Bandwidth Input Jitter Tolerance
(Input Jitter Frequencies ≥ 10 Hz)
Minimum 3.135 170 0 -20 -32 31.25 1
Nominal 3.3 230 -
Maximum 3.465 280 70 20 32 10 -
Units Volts mA °C ppm ppm Hz µs µs
Notes 2.0 4.0
3.0 8 kHz Ref. units 19.44 MHz Ref. units
Typical Acquisition Time Data
Acquisition from a cold power-up: Phase lock within 12ns: 50 sec Phase lock settled: 220 sec Alarm time: 31.25 µsec 125 µsec wide range Minimum pulse width = 62.5 µsec < 1 µsec 1 µsec > 1 µsec LOR is active when LOL is active Minimum pulse width = 2 µsec
1 2 3 4 5
Start-up Region
During Start-up, The LOL Alaram will pulse during the few seconds of operation
Preliminary Data Sheet #: SG040
Page 8 of 16
Rev: P01
Date: 11/13/03
© Copyright 2003 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Loss of Lock Condition Alarm Timing
Figure 8
Alarm Output (LOR + LOL) LOR (Internal Signal)
LOL (Internal Signal)
5
Phase Detector (Internal Signal)
1
1 3 3
1
1
1
External Reference (Selected Input A or B)
Internal Reference (Internal Signal) 2 2 2 2 2 2 2 2 2 2 2 2 2 2
Preliminary Data Sheet #: SG040
© Copyright 2003 The Connor-Winfield Corp.
Page 9 of 16
Rev: P01
Date: 11/13/03
All Rights Reserved Specifications subject to change without notice
Switch from A to B when both are good signals
Figure 9
Ref A Ref B Alarm
LOL portion of Alarm is Blanked 0.5 sec
Sel A/B
New Reference Qualification time
Switch from A to B when Reference B is lost
Figure 10
Ref A Ref B
~8ns
Alarm
Sel A/B
Preliminary Data Sheet #: SG040
Page 10 of 16
Rev: P01
Date: 11/13/03
© Copyright 2003 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Switch from A to B after Reference A is lost
Figure 11
Ref A Ref B Alarm
156.25µs (8 kHz Ref units) 126µs (19.44 MHz Ref units) Alarm Blanked
Sel A/B
New Reference Qualification time
Switch from A to B when A is out of range
Figure 12
Ref A Ref B Alarm
Alarm Blanked
Out of Range
In Range
Sel A/B
New Reference Qualification time
Preliminary Data Sheet #: SG040
© Copyright 2003 The Connor-Winfield Corp.
Page 11 of 16
Rev: P01
Date: 11/13/03
All Rights Reserved Specifications subject to change without notice
Switch from A to B when B is out of range
Figure 13
Switch from A to B when B is out of range
Ref A Ref B Alarm
Alarm Blanked
In Range
Out of Range
SEL A/B
New Reference Qualification Time 0.5 sec.
Switch from A to B when B is out of range
Figure 14
Ref A Ref B Alarm
Alarm Blanked
Sel A/B
New Reference Qualification time
Free Run Status
Preliminary Data Sheet #: SG040
Page 12 of 16
Rev: P01
Date: 11/13/03
© Copyright 2003 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Recommended PECL Termination
Figure 15
3.3 VDC 3.3 VDC 3.3 VDC
130Ω Vcc Q
82Ω Vcc D
50Ω Transmission Line
SCGXXXX LVPECL OUTPUT
QN GND
LVPECL INPUT 50Ω Transmission Line
130Ω 82Ω DN GND
3.3 VDC
3.3 VDC
Vcc - 2 VDC
50Ω Vcc Q
50Ω Transmission Line
Vcc D
SCGXXXX LVPECL OUTPUT
QN GND
LVPECL INPUT 50Ω Transmission Line
50Ω DN GND
Vcc - 2 VDC
3.3 VDC
3.3 VDC
150Ω Vcc Q
50Ω Transmission Line
100Ω
Vcc D
SCGXXXX LVPECL OUTPUT
QN GND 150Ω
LVPECL INPUT
DN GND
50Ω Transmission Line
If PECL outputs do not drive a long line (< 0.5”), a single 150Ω termination resistor to ground may be used for each pin.
Preliminary Data Sheet #: SG040
© Copyright 2003 The Connor-Winfield Corp.
Page 13 of 16
Rev: P01
Date: 11/13/03
All Rights Reserved Specifications subject to change without notice
Tape and Reel Packaging
Figure 16
Preliminary Data Sheet #: SG040
Page 14 of 16
Rev: P01
Date: 11/13/03
© Copyright 2003 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
Solder Profile
Figure 17
250
200
Temp (C˚)
150
100
50
0
1
2
3
4
5
6
7
8
Time(minutes) Recommended Reflow Profile
Peak Temp:217C˚ MaxRiseSlope:1.5 C˚/Sec Time Above150C˚:100Sec
Model Comparison Table
Table 8
Model SCG4500 SCG4501 SCG4510 SCG4520 SCG4540 Input Ref Freq 8 kHz/8 kHz 8 kHz/8 kHz 2@1.544 MHz 2@19.44 MHz 2@10 kHz Max Duty Cycle 40/60 40/60 40/60 40/60 40/60 Oscillator Output (Synchronized Output) 77.76 MHz,155.52 MHz,125 MHz 77.76 MHz,155.52 MHz,125 MHz 155.52 MHz 77.76 MHz,155.52 MHz 163.84 MHz Notes Basic Model ±32 ppm Pull-in range
Other low jitter line card solutions from Connor-Winfield
SCG51 Series SCG102A/104A SCG2000 Series SCG2500 Series SCG3000 Series SCG4000 Series SCG4600 Series Single input, jitter filtered with Free Run, 1 CMOS and 3 LVPECL outputs up to 622.08 MHz. Single input, frequency selectable, LVPECL clock smoothers from 77.76 to 777.76 MHz. Single input, jitter filtered with 20ppm Free Run, CMOS outputs from 8 kHz to 125.0 MHz. Dual input, jitter filtered with Free Run, CMOS outputs from 8 kHz to 125.0 MHz. Single input, jitter filtered with Dual LVPECL outputs. Single input, jitter filtered with 20ppm Free Run, LVPECL outputs from 77.76 MHz to 180 MHz. Dual input, jitter filtered with Free Run, 1 CML differential pair output up to 622.08 MHz.
Preliminary Data Sheet #: SG040
© Copyright 2003 The Connor-Winfield Corp.
Page 15 of 16
Rev: P01
Date: 11/13/03
All Rights Reserved Specifications subject to change without notice
Revision P00 P01
Revision Date 12/20/01 11/13/03
Note Preliminary Release Updated to V3.01
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