SOC-3000

SOC-3000/i Scale-On-Chip ASIC Technical Specification Rev.B1 July 2002 Document order number: SOC-3000-0001-SP  2001 CybraTech (1998) Ltd. All rights reserved. CybraTech (1998) Ltd. reserves the right to alter the equipment specifications and descriptions in this publication without prior notice. No part of this publication shall be deemed to be part of any contract or warranty unless specifically incorporated by reference into such contract or warranty. The information contained herein is merely descriptive in nature, and does not constitute a binding offer for the sale of the product described herein. CybraTech (2000) Ltd. SOC-3000/i Scale-On-Chip ASIC Technical Specification TABLE OF CONTENTS LIST OF FIGURES .................................................................................................................................. IV LIST OF TABLES ......................................................................................................................................V GENERAL ....................................................................................................................................................1 GENERAL DESCRIPTION ............................................................................................................................2 ADVANTAGES ............................................................................................................................................2 SPECIFICATIONS......................................................................................................................................3 ANALOG-TO-DIGITAL CONVERTER (ADC)...............................................................................................3 ADC Converter Main Channel – Wheatstone Bridge (Load Cell)........................................................3 ADC Converter Auxiliary Channel .......................................................................................................3 REFERENCE INPUTS ...................................................................................................................................4 DIGITAL INPUT ..........................................................................................................................................4 DIGITAL OUTPUT .......................................................................................................................................4 FLASH MEMORY ........................................................................................................................................4 CPU ...........................................................................................................................................................5 FREQUENCY SOURCE INPUT ......................................................................................................................5 POWER SUPPLY AND MONITOR .................................................................................................................5 ENVIRONMENTAL CONDITIONS .................................................................................................................5 ABSOLUTE MAXIMUM RATING* ...............................................................................................................6 OUTLINE DIMENSIONS...............................................................................................................................6 SCALE MAIN BOARD LAYOUT AND ASSEMBLY PROCESS PARAMETERS FOR SOC-3000........................7 PIN CONFIGURATION .............................................................................................................................9 CPU 80C51TBO .........................................................................................................................................21 MEMORY ORGANIZATION .......................................................................................................................22 Flash (Program & Non-Volatile Data) Memory Mapping and Usage ...............................................22 Application Program Start Address ....................................................................................................23 Serial Downloading (In-Circuit Programming)..................................................................................23 Using the Flash for Data Memory ......................................................................................................24 Data Memory Mapping .......................................................................................................................25 Memory Bank Select Register .............................................................................................................25 CPU SFRs and Configuration Registers (CFR)..................................................................................25 INSTRUCTION SET ....................................................................................................................................25 RESET ......................................................................................................................................................26 INTERRUPT VECTORS ..............................................................................................................................26 ADC CONTROLLER INTERFACE .......................................................................................................27 CONTROLLER REGISTERS ........................................................................................................................27 Semaphore Register.............................................................................................................................27 Control Register ..................................................................................................................................27 Revision B Page i July, 2002 CybraTech (2000) Ltd. SOC-3000/i Scale-On-Chip ASIC Technical Specification Status/Data Registers ..........................................................................................................................28 OPERATION ..............................................................................................................................................29 KEYBOARD CONTROLLER................................................................................................................. 31 CONTROLLER REGISTERS ........................................................................................................................32 REGISTERS DESCRIPTION.........................................................................................................................32 Control Register ..................................................................................................................................32 Data Registers .....................................................................................................................................32 OPERATION ..............................................................................................................................................33 LCD CONTROLLER/DRIVER .............................................................................................................. 35 LCD Bias Generator............................................................................................................................36 Drive Mode Waveforms.......................................................................................................................36 REGISTERS DESCRIPTION.........................................................................................................................42 Control Register ..................................................................................................................................42 Data Registers .....................................................................................................................................43 OPERATION ..............................................................................................................................................44 LED PARALLEL DISPLAY CONTROLLER ...................................................................................... 45 REGISTERS DESCRIPTION.........................................................................................................................46 Semaphore Register.............................................................................................................................47 Data Registers .....................................................................................................................................47 OPERATION ..............................................................................................................................................48 LED SERIAL INTERFACE DISPLAY CONTROLLER..................................................................... 49 REGISTERS DESCRIPTION.........................................................................................................................50 Control Register ..................................................................................................................................51 Semaphore Register.............................................................................................................................51 Data Registers .....................................................................................................................................52 OPERATION ..............................................................................................................................................53 PROGRAMMABLE FREQUENCY CONTROLLER.......................................................................... 55 OPERATION ..............................................................................................................................................56 CONTROL REGISTERS DESCRIPTION ........................................................................................................56 WATCHDOG TIMER.............................................................................................................................. 57 OPERATION ..............................................................................................................................................57 CONTROL REGISTERS DESCRIPTION ........................................................................................................57 LOW VOLTAGE DETECTOR ............................................................................................................... 59 INTERRUPT REGISTER ..............................................................................................................................59 CONFIGURATION REGISTERS (CFR)............................................................................................... 61 SPECIAL FUNCTION REGISTERS (SFR) .......................................................................................... 65 GLOBAL CONFIGURATION REGISTER ......................................................................................................65 Operation.............................................................................................................................................65 CONTROLLERS CLOCK ENABLE REGISTER ..............................................................................................66 CONTROLLERS RESET REGISTERS .........................................................................................................67 Revision B Page ii July, 2002 CybraTech (2000) Ltd. SOC-3000/i Scale-On-Chip ASIC Technical Specification I/O OPERATION.......................................................................................................................................69 8051-COMPATIBLE ON-CHIP PERIPHERALS..................................................................................71 PARALLEL I/O PORTS ..............................................................................................................................71 Timers/Counters..................................................................................................................................71 SOC-3000 INITIALIZATION ..................................................................................................................73 SOC-3000 HARDWARE DESIGN CONSIDERATIONS AND PERIPHERAL INTERFACE CONNECTIONS ........................................................................................................................................75 LOAD CELL INTERFACE ...........................................................................................................................75 4-Wire and 6-Wire Interfaces..............................................................................................................75 Load Cells Connected in Parallel .......................................................................................................77 Load Cell Impedance ..........................................................................................................................78 KEYBOARD INTERFACE ...........................................................................................................................78 LCD DISPLAY INTERFACE ......................................................................................................................79 LED DISPLAY INTERFACE .......................................................................................................................80 EXTERNAL INTERRUPT SOURCES ............................................................................................................80 Using the Vdet input:...........................................................................................................................80 Using Timer0 and Timer1 inputs: .......................................................................................................81 2 I C-COMPATIBLE INTERFACE ..................................................................................................................81 POWER SAVING SCHEMES .......................................................................................................................81 GROUNDING AND BOARD LAYOUT RECOMMENDATIONS .......................................................................82 IN-CIRCUIT EMULATOR (ICE) SYSTEM ..........................................................................................83 EXAMPLES OF PIN CONFIGURATION PROGRAMMING ............................................................85 EXAMPLE 1: CONFIGURING A 20-DIGIT LCD DISPLAY AND AN 8X8 KEYBOARD...................................85 EXAMPLE 2: CONFIGURING A 16-DIGIT LCD DISPLAY, AN 8X4 KEYBOARD, 8 OUTPUT AND 4 I/O PORTS ......................................................................................................................................................86 EXAMPLE 3: CONFIGURING A 21-DIGIT LED PARALLEL DISPLAY, AN 8X8 KEYBOARD AND 13 OUTPUT PORTS ........................................................................................................................................87 EXAMPLE 4: OUTPUTS AND I/O PORTS PROGRAMMING .........................................................................88 Revision B Page iii July, 2002 CybraTech (2000) Ltd. SOC-3000/i Scale-On-Chip ASIC Technical Specification LIST OF FIGURES FIGURE 1: FIGURE 2: FIGURE 3: FIGURE 4: FIGURE 5: FIGURE 6: FIGURE 7: FIGURE 8: FIGURE 9: FIGURE 10: FIGURE 11: FIGURE 12: FIGURE 13: FIGURE 14: FIGURE 15: FIGURE 16: FIGURE 17: FIGURE 18: FIGURE 19: FIGURE 20: FIGURE 21: FIGURE 22: FIGURE 23: FIGURE 24: FIGURE 25: FIGURE 26: FIGURE 27: FIGURE 28: FIGURE 29: FIGURE 30: FIGURE 31: SOC-3000 TYPICAL APPLICATION ........................................................................................ 1 SOC-3000 BLOCK DIAGRAM................................................................................................. 2 MECHANICAL OUTLINE DRAWING ........................................................................................ 6 MAIN BOARD PADS DIMENSIONS RECOMMENDATION ........................................................ 7 SOC-3000 PIN ARRANGEMENT ........................................................................................... 15 SOC-3000 LCD DISPLAY PIN CONFIGURATION ................................................................. 16 SOC-3000 LED DISPLAY PIN CONFIGURATION ................................................................. 17 CPU BLOCK DIAGRAM ........................................................................................................ 21 SOC-3000 PROGRAM MEMORY MAP .................................................................................. 22 SOC-3000/I STARTUP PROCEDURE .................................................................................... 24 SOC-3000 DATA MEMORY MAP ......................................................................................... 25 KEYBOARD MATRIX CONFIGURATION ................................................................................ 31 LCD CONTROLLER/DRIVER BLOCK DIAGRAM ................................................................... 35 STATIC DRIVE MODE WAVEFORMS..................................................................................... 37 1:2 MULTIPLEX DRIVE RATIO–1/2 BIAS WAVEFORMS ....................................................... 38 1:2 MULTIPLEX DRIVE RATIO–1/3 BIAS WAVEFORMS ....................................................... 39 1:3 MULTIPLEX DRIVE RATIO WAVEFORMS ....................................................................... 40 1:4 MULTIPLEX DRIVE RATIO WAVEFORMS ....................................................................... 41 BACKPLANE OUTPUTS PER LCD DIGIT ............................................................................... 43 LED PARALLEL DISPLAY CONTROLLER BLOCK DIAGRAM ................................................ 45 LED PARALLEL DISPLAY CONTROLLER TIMING DIAGRAM ............................................... 46 LED SERIAL INTERFACE DISPLAY BLOCK DIAGRAM ......................................................... 49 LED SERIAL INTERFACE CONTROLLER TIMING DIAGRAM ................................................. 50 CLOCK GENERATOR BLOCK DIAGRAM ............................................................................... 55 LOW VOLTAGE DETECTOR .................................................................................................. 59 4-WIRE LOAD-CELL CONNECTION ...................................................................................... 76 6-WIRE LOAD-CELL CONNECTION ...................................................................................... 76 MULTIPLE LOAD-CELL CONNECTION.................................................................................. 77 KEYBOARD INTERFACE ....................................................................................................... 78 LCD DISPLAY INTERFACE ................................................................................................... 79 LED PARALLEL DISPLAY INTERFACE ................................................................................. 80 Revision B Page iv July, 2002 CybraTech (2000) Ltd. SOC-3000/i Scale-On-Chip ASIC Technical Specification LIST OF TABLES TABLE 1: TABLE 2: TABLE 3: TABLE 4: TABLE 5: TABLE 6: TABLE 7: TABLE 8: TABLE 9: TABLE 10: TABLE 11: TABLE 12: TABLE 13: TABLE 14: TABLE 15: TABLE 16: TABLE 17: TABLE 18: TABLE 19: TABLE 20: TABLE 21: TABLE 22: TABLE 23: TABLE 24: TABLE 25: TABLE 26: TABLE 27: TABLE 28: TABLE 29: TABLE 30: TABLE 31: TABLE 32: TABLE 33: TABLE 34: TABLE 35: TABLE 36: TABLE 37: TABLE 38: TABLE 39: TABLE 40: TABLE 41: TABLE 42: TABLE 43: TABLE 44: SOC-3000 PIN CONFIGURATION FOR LCD DISPLAY .................................................................9 SOC-3000 PIN CONFIGURATION FOR LED DISPLAY ...............................................................12 NOTES ON SOC-3000 PIN CONFIGURATION.............................................................................15 SOC-3000 QUICK REFERENCE PIN CONFIGURATION FOR LCD DISPLAY ...............................18 SOC-3000 QUICK REFERENCE PIN CONFIGURATION FOR LED DISPLAY ...............................19 INTERRUPT VECTORS DESCRIPTION .........................................................................................26 ADC CONTROLLER REGISTERS DESCRIPTION .........................................................................27 ADC CONTROLLER INTERFACE SEMAPHORE REGISTER BIT DEFINITIONS .............................27 ADC CONTROLLER INTERFACE CONTROL REGISTER BIT FUNCTIONS ....................................28 ADC CONTROLLER INTERFACE DATA REGISTER BIT DEFINITIONS ....................................28 ADC CONTROLLER INTERFACE DATA REGISTER BIT FUNCTIONS ......................................28 ADC OUTPUT COUNTS VS. ADC SETTINGS ......................................................................30 KEYBOARD CONTROLLER REGISTERS DESCRIPTION ...........................................................32 KEYBOARD CONTROLLER CONTROL REGISTER BIT FUNCTIONS .........................................32 KEYBOARD CONTROLLER DATA REGISTER BIT DEFINITIONS .............................................33 MAXIMUM DISPLAY CAPACITY PER DISPLAY CONFIGURATION..........................................36 LCD BIAS CONFIGURATIONS ...............................................................................................36 LCD CONTROLLER/DRIVER REGISTERS DESCRIPTION ........................................................42 LCD CONTROLLER CONTROL REGISTER BIT FUNCTIONS ...................................................42 LCD CONTROLLER DATA REGISTER BIT DEFINITIONS – 20-DIGIT DISPLAY ......................43 LED PARALLEL DISPLAY CONTROLLER DRIVER REGISTERS DESCRIPTION .......................46 LED PARALLEL DISPLAY CONTROLLER SEMAPHORE REGISTER BIT DEFINITIONS ............47 LED PARALLEL DISPLAY CONTROLLER SEMAPHORE REGISTER BIT FUNCTIONS ..............47 LED PARALLEL CONTROLLER DATA REGISTER BIT DEFINITIONS ......................................47 LED SERIAL CONTROLLER DRIVER REGISTERS DESCRIPTION ............................................50 LED SERIAL INTERFACE DISPLAY CONTROL REGISTER BIT FUNCTIONS ...........................51 LED SERIAL INTERFACE DISPLAY DATA REGISTER BIT DEFINITIONS ................................52 CLOCK FREQUENCY CONTROL REGISTER BIT SETTINGS .....................................................56 WATCHDOG TIMER OPERATING PARAMETERS ....................................................................57 WATCHDOG TIMER COMMAND SEQUENCE ..........................................................................57 POWER-FAILURE INTERRUPT REGISTER BIT SETTINGS .......................................................59 CFR BIT ASSIGNMENT .........................................................................................................62 GLOBAL CFR REGISTER .......................................................................................................65 CLOCK ENABLE REGISTER ...................................................................................................66 CONTROLLERS CLOCK ENABLE REGISTER BIT FUNCTIONS.................................................67 CONTROLLERS RESET REGISTER ........................................................................................67 BIT-ORIENTED I/O PORTS ADDRESSES, PIN AND BIT ASSIGNMENT ....................................69 BYTE-ORIENTED OUTPUT PORTS ADDRESSES AND PIN ASSIGNMENT ................................69 AVAILABLE PINS ON THE 80C51 I/O PORT ..........................................................................71 I2C-COMPATIBLE INTERFACE HARDWARE INTERFACE .......................................................81 EXAMPLE 1: 20-DIGIT LCD DISPLAY, 8×8 KEYBOARD ......................................................85 EXAMPLE 2: 16-DIGIT LCD DISPLAY, 8×4 KEYBOARD, 8 OUTPUT, 4 I/O..........................86 EXAMPLE 3: 21-DIGIT LED DISPLAY, 8×8 KEYBOARD, 13 OUTPUT ..................................87 OUTPUT AND I/O PORTS PROGRAMMING .............................................................................88 Revision B Page v July, 2002 CybraTech (2000) Ltd. SOC-3000/i Scale-On-Chip ASIC Technical Specification GENERAL Features Scale-On-Chip System • Single-Chip Scale electronics • Full OIML R-76 compliance SOC-3000 - 3000 d SOC-3000i - 6000 d • Up to eight load cells • 6-wire load cell connection (including Sense inputs) Peripherals • 4 cycles/instruction • 120KByte, field-programmable Flash program and data memory • 4KByte RAM • 4KByte non-volatile Data Flash Analog–to–Digital Converter • Resolution-20 bits • Sample rate-5, 10, 20 samples per second • Programmable gain-0.5, 0.75, 1, 1.5, 2 Power • Supports LCD and LED displays: LCD: Up to 20 digits (160 segments, 4×40) LED: Up to 24 digits • Keyboard: Up to 64 keys • Serial communication: RS-232/485 • I/O (set-points): Up to 40 lines • Temperature sensor input CPU • 5/3.3V operation, 15mA • Battery operation support • Power failure detector Applications • • • • Price computing scales Weighing indicators Counting scales Checkout scales • Enhanced 80C51TBO +5V 8 . . . . . 888 SEN+ SIG+ SEN– SIG– S 0-39 BP 0-3 LCD (20 digits) LED (21 digits) LED/LCD Module TxD RxD RS-232 Printer RS-485 Load Cell (Up to 8) SOC-3000 I/O Set Point 8 VIN Buzzer KB 1-8 KBI 1-8 VInp 5V + 3.3V Up to 64 keys FIGURE 1: SOC-3000 TYPICAL APPLICATION Revision B Page 1 July, 2002 CybraTech (2000) Ltd. SOC-3000/i Scale-On-Chip ASIC Technical Specification General Description The SOC-3000 ASIC is an 84-pin, single-chip scale intended to replace present-day, multiple-component weighing scale electronic circuitry designs. It includes the pre-amplifier, ADC converter, display drivers, keyboard controller, serial communication, embedded CPU and field-programmable program and data memory. As a "stand-alone" unit it incorporates all scale hardware functions and represents a true breakthrough in scale manufacturing. It eliminates the risks, costs and inventory needs associated with discrete components. The SOC-3000 comes with a comprehensive software library, which implements hardware drivers, such as the display and keyboard, as well as most of the standard weighing functions. A complete development environment is available, enabling youto tailor and customize the application according to specific needs. The general SOC-3000 block diagram is presented in Figure 2. Advantages • • • • Generic OIML R-76 approval Minimize hardware and software development Significantly cuts time-to-market Reduces inventory needs Ref+ RefDisplay .... Display Controllers / Drivers LCD / LED 20 - 24 Digits Load Cell PGA Delta - Sigma ADC 20 Bits MUX MicroController Core And Peripherals 80C51TBO 120Kx8 Program/Data Flash 4K x 8 RAM Watchdog Timer 3x16-Bit Timers Serial Communication Aux. Channel VDET Power-Down Detector Internal Bandgap Reference Power Supply Monitor I2C Compatible SPI Like Serial Interfaces UART 8 I/O Frequency Controller Keyboard Controller 8x8 8 8 Oscillator/ Resonator Keyboard FIGURE 2: SOC-3000 BLOCK DIAGRAM Revision B Page 2 July, 2002 CybraTech (2000) Ltd. SOC-3000/i Scale-On-Chip ASIC Technical Specification SPECIFICATIONS Analog-to-Digital Converter (ADC) ADC Converter Main Channel – Wheatstone Bridge (Load Cell) PARAMETER Differential Input Voltage Programmable Gain Offset Drift vs. Temperature Gain Drift vs. Temperature Integral Non-linearity Common-Mode Rejection (CMR) Power Supply Rejection Output Noise Resolution Sample Rate 5 10 120 120 200 20 20 MIN 0 0.5 TYP MAX +10 2 20 4 UNIT mV COMMENTS Up to 8 load cell ppm/ºC ppm/ºC Of full scale 0.004 % dB dB nVp-t-p bit Samples/s ±1 count ADC Converter Auxiliary Channel PARAMETER Analog Input Voltage Offset Drift Gain Drift Resolution Sample Rate 5 10 MIN 0 TYP MAX 0.8 20 4 20 20 V UNIT COMMENTS ppm/ºC ppm/ºC Bit Samples/s Revision B Page 3 July, 2002 CybraTech (2000) Ltd. SOC-3000/i Scale-On-Chip ASIC Technical Specification Reference Inputs PARAMETER Reference Input MIN TYP MAX 5 UNIT V COMMENTS Ratiometric Digital Input PARAMETER VIH (Input High Voltage) VIL (Input Low Voltage) XTAL Input VIH (Input High Voltage) VIL (Input Low Voltage) MIN 2 0.0 2.5 TYP MAX 5 0.8 UNIT V V V V COMMENTS TTL Level excluding XTAL TTL Level excluding XTAL VDD = 3.3V VDD = 3.3V 0.4 Digital Output For LCD Display mode: PARAMETER VOH (Output High Voltage) VOL (Output Low Voltage) 0.0 MIN TYP MAX UNIT 5 VLCD V V COMMENTS LCD Output set by user by external resistors LCD Output set by user by external resistors For I/O mode: PARAMETER VOH (Output High Voltage) VOL (Output Low Voltage) 0.0 MIN TYP MAX UNIT 3.3 0.8 V V COMMENTS Flash Memory PARAMETER Endurance Data Retention Erase Full Memory Single Block (4kByte) Program Byte MIN 10,000 100 TYP 100,000 MAX UNIT Cycles Years 100 25 20 ms ms us Revision B Page 4 July, 2002 CybraTech (2000) Ltd. SOC-3000/i Scale-On-Chip ASIC Technical Specification CPU PARAMETER Enhanced 80C51TBO Reset Signal Threshold Start-Up Time • • • From Power On From Idle Mode From Power Down 500 1 1 500 1 3.98 V ms ms ms ms ms MIN TYP MAX UNIT COMMENTS Oscillator power-down not through OSCEN bit. Oscillator power-down through OSCEN bit. From Watchdog Reset Frequency Source Input PARAMETER Frequency Level MIN TYP MAX 16 UNIT MHz COMMENTS Crystal oscillator or resonator Power Supply and Monitor PARAMETER Input Voltage Monitor Power Fail Input Monitor Level Analog Voltage Input (AVCC) Digital Voltage Input (VCC) Power Supply Current (IIN) CPU Freq. = 16 MHz CPU Freq. = 8 MHz CPU Freq. = 4 MHz CPU Freq. = 2 MHz CPU Freq. = 1 MHz CPU Freq. = 0.5 MHz 4.75 3.00 5.00 3.30 21 15 12 11 10 10 MIN 4.50 TYP MAX 4.75 2.21 5.25 3.60 UNIT V V V V mA mA mA mA mA mA COMMENTS Set by external resistors 5V and 3.3V . Without connected I/O ports All controllers operating. Depends on the software program and the Flash memory utilization. Environmental Conditions PARAMETER Temperature MIN -10 -20 TYP 20 20 MAX 40 70 95 UNIT ºC ºC % COMMENTS Full performance Operation Non-condensing Humidity 0 Revision B Page 5 July, 2002 CybraTech (2000) Ltd. SOC-3000/i Scale-On-Chip ASIC Technical Specification Absolute Maximum Rating* PARAMETER AVCC VDD VCC Input Signal Voltage Operating Temperature Storage Temperature Lead Temperature Manual soldering Reflow soldering –20 –20 MIN TYP MAX 6 4 6 3.6 +70 +85 300 225 UNIT V V V V ºC ºC ºC ºC COMMENTS Analog power Digital power Power Soldering for 10 seconds 60 seconds * Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only. The functional operation of the device under these or any other conditions outside of the range listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect the reliability of the device. Outline Dimensions The outline dimensions of the SOC-3000 PLCC-84 case is shown in Figure 3. 0.045 X 45º (1.143) PIN 1 Indicates relative locations of Pin 1 1.150 (29.20) Sq. 1.158 (29.41) 1.185 (30.09) Sq. 1.155 (30.35) FIGURE 3: MECHANICAL OUTLINE DRAWING Revision B Page 6 July, 2002 CybraTech (2000) Ltd. SOC-3000/i Scale-On-Chip ASIC Technical Specification Scale Main Board Layout And Assembly Process Parameters For SOC-3000 1. 2. 3. Pad definition will be according to Figure 4. Solder mask opening should be 3mil (total 6 mil). Board finish may be HAL (hot air leveling), immersion gold over nickel or immersion. Verify that the SOC-3000 components are packaged in hermetically sealed package. If the packaging is damaged or has been opened, perform the following drying procedure to assure that SOC-3000 components are completely dry: • Components drying procedure: Place the SOC-3000 components in their tray and put them into a baking oven to dry at a temperature of 105ºC for a minimum of 6 hours. Reflow temperature profile should be set according to the paste parameters. Maximum reflow temperature should be less than 225 ºC. Recommended paste: Koki, AIM, Multicore a. Type 3 b. NC c. RMA or equivalent 4. 5. 6. 7. FIGURE 4: PCB BOARD LAYOUT (Dimensions are in milli inches (mil)) Revision B Page 7 July, 2002 CybraTech (2000) Ltd. SOC-3000/i Scale-On-Chip ASIC Technical Specification PIN CONFIGURATION The SOC-3000 pin configuration for LCD and LED displays is presented in Table 1 and Table 2, respectively, followed by a glossary of terms used in the tables. General notes on SOC-3000 pin configuration are presented in Table 3, page 15. The physical pin arrangement is shown in Figure 5, page 15. The physical pin configuration for an LCD display is shown in Figure 6, page 16, followed by a quick reference table in Table 4, page 18. The physical pin configuration for a LED display is shown in Figure 7, page 17, followed by a quick reference table in Table 5, page 19. TABLE 1: PIN 1 2 3 4 5 6 7 SOC-3000 PIN CONFIGURATION FOR LCD DISPLAY DESCRIPTION Keyboard Controller Input See “Keyboard Controller”, page 31 NAME KIN4 KIN3 KIN2 KIN1 KIN0 VDD BUZZER / P1.7 (CPU) P1.5 (CPU) P1.4 (CPU) XTAL OUT XTAL IN TXD RXD 2 DESCRIPTION PULL-UP FUNCTION RESISTOR I.O 15.3 I.O 15.4 I.O 15.5 I.O 15.6 I.O 15.7 I/O, See “I/O Operation”, page 65 50k nd Digital Power Supply Buzzer 25k 8 9 10 11 12 13 14 15 16 17 18 19 20 21 CPU I/O Port See Note 11 Frequency Clock Source 10k Serial Communication Tx Serial Communication Rx P3.4 (CPU) 100k CPU I/O Ports, or: 50k P3.4 – Timer 0 PWR_OFF / Power Off Control P3.4/Timer 0 MAIN_DET / Battery/AC power supply detector input P3.5 (CPU) P3.5 /Timer1 EL / P1.6 (CPU) VLCD BP1 BP2 BP3 BP4 Electro-luminescent light control See Note 11 LCD Display voltage LCD Display Multiplexer Backplanes, See “LCD Controller/Driver”, page 35 OUT 4.0 OUT 4.1 OUT 4.2 OUT 4.3 I/O See “I/O Operation”, page 69 P1.6 (CPU) Revision B Page 9 July, 2002 CybraTech (2000) Ltd. PIN 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 S30 S31 S32 S33 S34 S35 S36 S37 SOC-3000/i Scale-On-Chip ASIC DESCRIPTION nd Technical Specification NAME 2 DESCRIPTION PULL-UP FUNCTION RESISTOR OUT 5.0 OUT 5.1 OUT 5.2 OUT 6.0 OUT 6.1 OUT 6.2 OUT 6.3 OUT 7.0 OUT 7.1 OUT 7.2 OUT 7.3 OUT 8.0 OUT 8.1 OUT 8.2 OUT 8.3 OUT 9.0 OUT 9.1 OUT 9.2 I/O See “I/O Operation”, page 69 LCD Display Segment See “LCD Controller/Driver”, page 35 OUT 10.0 OUT 11.0 OUT 11.1 OUT 11.2 OUT 11.3 OUT 12.0 OUT 12.1 OUT 12.2 OUT 12.3 OUT 12.4 OUT 13.0 Revision B Page 10 July, 2002 CybraTech (2000) Ltd. PIN 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 SOC-3000/i Scale-On-Chip ASIC DESCRIPTION nd Technical Specification NAME S38 S39 S40 VCC RESET GND VDET/ INT0~ SIG2+ SIG2– AGND SEN– SIG1– SIG1+ SEN+ AVCC KOUT7 KOUT6 KOUT5 KOUT4 KOUT3 KOUT2 KOUT1 KOUT0 KIN7 KIN6 KIN5 2 DESCRIPTION PULL-UP FUNCTION RESISTOR OUT 13.1 OUT 13.2 OUT 13.3 Power Supply Reset Digital Ground Power voltage detector input / Interrupt 0 Input 2nd AD channel input signal + 2nd AD channel input signal – Analog Ground Load cell sense input – Load cell signal input – Load cell signal input + Load cell sense input + Analog power supply Keyboard Controller Inputs See “Keyboard Controller”, page 31 I.O 14.0 I.O 14.1 I.O 14.2 I.O 14.3 I.O 14.4 I.O 14.5 I.O 14.6 I.O 14.7 Keyboard Controller Inputs See “Keyboard Controller”, page 31 I.O 15.0 I.O 15.1 I.O 15.2 I/O See “I/O Operation”, page 69 50k 50k Revision B Page 11 July, 2002 CybraTech (2000) Ltd. TABLE 2: PIN 1 2 3 4 5 6 7 SOC-3000/i Scale-On-Chip ASIC Technical Specification SOC-3000 PIN CONFIGURATION FOR LED DISPLAY DESCRIPTION Keyboard Controller Input See “Keyboard Controller”, page 31 NAME KIN4 KIN3 KIN2 KIN1 KIN0 VDD BUZZER / P1.7 (CPU) P1.5 (CPU) P1.4 (CPU) XTAL OUT XTAL IN TXD RXD 2 DESCRIPTION PULL-UP FUNCTION RESISTOR I.O 15.3 I.O 15.4 I.O 15.5 I.O 15.6 I.O 15.7 I/O See “I/O Operation”, page 69 50k nd Digital Power Supply Buzzer P1.7=’1’ – ON P1.7=’0’ – OFF See Note 10, 11 CPU I/O Port. See Note 11 Frequency Clock Source 25k 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 10k Serial Communication Tx Serial Communication Rx P3.4 (CPU) CPU I/O port, or: P3.4 – Timer 0 P3.5 – Timer 1 See Note 11 See Note 11 100k 50k PWR_OFF / Power Off Control P3.4 / Timer 0 MAIN_DET / Battery/AC power supply detector input P3.5 (CPU) P3.5 / Timer 1 EL NC OUT 4.0 OUT 4.1 OUT 4.2 OUT 4.3 SEG A1 SEG B1 SEG C1 SEG D1 SEG E1 SEG F1 SEG G1 SEG DP1 SEG A2 SEG B2 SEG C2 SEG D2 Display Segment Out, see “LED Parallel Display Controller Block Diagram”, page 45 Electro-luminescent light control Not Used Outputs. OUT 4.0 OUT 4.1 OUT 4.2 OUT 4.3 OUT 5.0 OUT 5.1 OUT 5.2 OUT 6.0 OUT 6.1 OUT 6.2 OUT 6.3 OUT 7.0 OUT 7.1 OUT 7.2 OUT 7.3 OUT 8.0 P1.6 (CPU) I/O See “I/O Operation”, page 69 Revision B Page 12 July, 2002 CybraTech (2000) Ltd. PIN 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 SOC-3000/i Scale-On-Chip ASIC DESCRIPTION nd Technical Specification NAME SEG E2 SEG F2 SEG G2 SEG DP2 SEG A3 SEG B3 SEG C3 SEG D3 SEG E3 SEG F3 SEG G3 SEG DP3 DIG 1 DIG 2 DIG 3 DIG 4 DIG 5 DIG 6 DIG 7 OUT 12.0 OUT 12.1 OUT 12.2 OUT 12.3 OUT 12.4 2 DESCRIPTION PULL-UP FUNCTION RESISTOR OUT 8.1 OUT 8.2 OUT 8.3 OUT 9.0 OUT 9.1 OUT 9.2 Output, I/O See “I/O Operation”, page 69 Display Segment Out, see “LED Parallel Display Controller Block Diagram”, page 45. Display Digit Mux Control See “LED Parallel Display Controller”, page 45 OUT 10.0 OUT 11.0 OUT 11.1 OUT 11.2 OUT 11.3 Output See “I/O Operation”, page 69 I/O See “I/O Operation”, page 69 LED Serial Interface Display Module Clock, Data, Strobe and Blank LED_SI_Data See “LED Serial Interface Display Controller”, page 49. LED_SI_ST LED_SI_CLK LED_SI_BL VCC RESET GND VDET/ INT0~ SIG2+ SIG2– AGND SEN– Power Supply Reset Digital Ground Power voltage detector input / Interrupt 0 Input 2 2 nd nd OUT 13.0 OUT 13.1 OUT 13.2 OUT 13.3 I/O See “I/O Operation”, page 69 50k ADC channel input signal + ADC channel input signal – Analog Ground Load cell sense input – Revision B Page 13 July, 2002 CybraTech (2000) Ltd. PIN 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 SOC-3000/i Scale-On-Chip ASIC DESCRIPTION nd Technical Specification NAME SIG1– SIG1+ SEN+ AVCC KOUT7 KOUT6 KOUT5 KOUT4 KOUT3 KOUT2 KOUT1 KOUT0 KIN7 KIN6 KIN5 2 DESCRIPTION PULL-UP FUNCTION RESISTOR Load cell signal input – Load cell signal input + Load cell sense input + Analog power supply Keyboard Controller Output, See “Keyboard Controller”, page 31 I.O 14.0 I.O 14.1 I.O 14.2 I.O 14.3 I.O 14.4 I.O 14.5 I.O 14.6 I.O 14.7 Keyboard Controller Input, See “Keyboard Controller”, page 31 I.O 15.0 I.O 15.1 I.O 15.2 I/O See “I/O Operation”, page 69 50k GLOSSARY OF TERMS TERM BP CLK DIG I.O KIN KOUT P/PWR REG RX SEG SI TX DEFINITION Backplane Clock Digit Input/Output Keyboard In Keyboard Out Power Register Receive Segment Serial Interface Transmit Revision B Page 14 July, 2002 CybraTech (2000) Ltd. TABLE 3: # 1 2 3 4 5 SOC-3000/i Scale-On-Chip ASIC NOTES ON SOC-3000 PIN CONFIGURATION Technical Specification COMPONENT LCD Controller/Driver LED Controller Output Pins Input Pins VDET • • • Bit programmable Voh @ Io = 1.5mA Bit programmable REMARKS CMOS–3.3V CMOS–3.3V • • • Less than 5V Threshold level – 2.1V. The input (on the analog chip) tolerates input voltage applied while the SOC-3000 is powered off. 6 7 8 9 10 11 VDD VCC AVCC Keyboard Controller Buzzer Port 1.x 3.3V ±5% 5V ±5% 5V ±5% Bit programmable P1.7 is used as the BUZZER control pin. During power-up the SOC-3000 asserts 3 pulses on this line. Manipulation of this pin should be made using BIT mapping of the port, since bits P1.0-P1.1 are allocated to the bank select register. P11 P12 P1 P84 PIN 1 IDENTIFIER P75 P74 SOC3000 PLCC84 P32 P33 P53 P54 FIGURE 5: SOC-3000 PIN ARRANGEMENT Revision B Page 15 July, 2002 CybraTech (2000) Ltd. SOC-3000/i Scale-On-Chip ASIC Technical Specification FIGURE 6: SOC-3000 LCD DISPLAY PIN CONFIGURATION Revision B Page 16 July, 2002 CybraTech (2000) Ltd. SOC-3000/i Scale-On-Chip ASIC Technical Specification FIGURE 7: SOC-3000 LED DISPLAY PIN CONFIGURATION Revision B Page 17 July, 2002 CybraTech (2000) Ltd. TABLE 4: PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 SOC-3000/i Scale-On-Chip ASIC Technical Specification SOC-3000 QUICK REFERENCE PIN CONFIGURATION FOR LCD DISPLAY PIN 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 NAME KIN4 / I.O 15.3 KIN3 / I.O 15.4 KIN2 / I.O 15.5 KIN1 / I.O 15.6 KIN0 / I.O 15.7 VDD BUZZER / P1.7 P1.5 (CPU) P1.4 (CPU) XTAL OUT XTAL IN TXD RXD PWR_OFF / P3.4 (CPU) / Timer 0 MAIN_DET / P3.5 (CPU) / Timer 1 EL / P1.6 (CPU) VLCD BP1 / OUT 4.0 BP2 / OUT 4.1 BP3 / OUT 4.2 BP4 / OUT 4.3 NAME S1 / OUT 5.0 S2 / OUT 5.1 S3 / OUT 5.2 S4 / OUT 6.0 S5 / OUT 6.1 S6 / OUT 6.2 S7 / OUT 6.3 S8 / OUT 7.0 S9 / OUT 7.1 S10 / OUT 7.2 S11 / OUT 7.3 S12 / OUT 8.0 S13 / OUT 8.1 S14 / OUT 8.2 S15 / OUT 8.3 S16 / OUT 9.0 S17 / OUT 9.1 S18 / OUT 9.2 S19 S20 S21 PIN 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 S22 S23 S24 S25 S26 NAME PIN 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 GND NAME VDET / INT 0~ SIG2+ SIG2– AGND SEN– SIG1– SIG1+ SEN+ AVCC KOUT7 / I.O 14.0 KOUT6 / I.O 14.1 KOUT5 / I.O 14.2 KOUT4 / I.O 14.3 KOUT3 / I.O 14.4 KOUT2 / I.O 14.5 KOUT1 / I.O 14.6 KOUT0 / I.O 14.7 KIN7 / I.O 15.0 KIN6 / I.O 15.1 KIN5 / I.O 15.2 S27 / OUT 10.0 S28 / OUT 11.0 S29 / OUT 11.1 S30 / OUT 11.2 S31 / OUT 11.3 S32 / OUT 12.0 S33 / OUT 12.1 S34 / OUT 12.2 S35 / OUT 12.3 S36 / OUT 12.4 S37 / OUT 13.0 S38 / OUT 13.1 S39 / OUT 13.2 S40 / OUT 13.3 VCC RESET Revision B Page 18 July, 2002 CybraTech (2000) Ltd. TABLE 5: PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 SOC-3000/i Scale-On-Chip ASIC Technical Specification SOC-3000 QUICK REFERENCE PIN CONFIGURATION FOR LED DISPLAY PIN 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 NAME KIN4 / I.O 15.3 KIN3 / I.O 15.4 KIN2 / I.O 15.5 KIN1 / I.O 15.6 KIN0 / I.O 15.7 VDD BUZZER / P1.7 P1.5 (CPU) P1.4 (CPU) XTAL OUT XTAL IN TXD RXD PWR_OFF / P3.4 / Timer 0 MAIN_DET / P3.5 / Timer 1 EL / P1.6 Not Connected OUT / OUT 4.0 OUT / OUT 4.1 OUT / OUT 4.2 OUT / OUT 4.3 NAME SEG A1 / OUT 5.0 SEG B1 / OUT 5.1 SEG C1 / OUT 5.2 SEG D1 / OUT 6.0 SEG E1 / OUT 6.1 SEG F1 / OUT 6.2 SEG G1 / OUT 6.3 SEG DP1 / OUT 7.0 SEG A2 / OUT 7.1 SEG B2 / OUT 7.2 SEG C2 / OUT 7.3 SEG D2 / OUT 8.0 SEG E2 / OUT 8.1 SEG F2 / OUT 8.2 SEG G2 / OUT 8.3 SEG DP2 / OUT 9.0 SEG A3 / OUT 9.1 SEG B3 / OUT 9.2 SEG C3 SEG D3 SEG E3 PIN 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 NAME SEG F3 SEG G3 SEG DP3 DIG 1 DIG 2 DIG 3 / OUT 10.0 DIG 4 / OUT 11.0 DIG 5 / OUT 11.1 DIG 6 / OUT 11.2 DIG 7 / OUT 11.3 OUT 12.0 OUT 12.1 OUT 12.2 OUT 12.3 OUT 12.4 OUT 13.0 OUT 13.1 OUT 13.2 OUT 13.3 VCC RESET PIN 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 GND NAME VDET / INT 0 ~ SIG2+ SIG2– AGND SEN– SIG1– SIG1+ SEN+ AVCC KOUT7/I.O 14.0 KOUT6/I.O 14.1 KOUT5/I.O 14.2 KOUT4/I.O 14.3 KOUT3/I.O 14.4 KOUT2/I.O 14.5 KOUT1/I.O 14.6 KOUT0/I.O 14.7 KIN7/I.O 15.0 KIN6/I.O 15.1 KIN5/I.O 15.2 Revision B Page 19 July, 2002 CybraTech (2000) Ltd. . SOC-3000/i Scale-On-Chip ASIC Technical Specification Revision B Page 20 July, 2002 CybraTech (2000) Ltd. SOC-3000/i Scale-On-Chip ASIC Technical Specification CPU 80C51TBO The reference source for data given here is “M8051TBO Technical Specifications”, Virtual IP Group, Inc., Version M8051TS97DF01. Refer to this manual for complete CPU specification. Features • • • • • • • • • • 8-bit CPU Compatible with standard 80C31 Four 8-bit I/O ports Three 16-bit timers On-chip oscillator and clock circuitry 256-byte on-chip, 8051-compatible SFR RAM 64Kbyte program memory with bank switching 4Kbyte XDATA RAM for data memory High-speed architecture of 4 cycles/instruction Dual data pointers Advantages • Fast running and improved performance • No wasted clock and memory cycles • Works efficiently with all types of peripheral devices • Improved power consumption characteristics • On-chip Power-On/Reset Architecture The CPU block diagram is presented in Figure 8. P1.0 to P1.7 Port Latch Timer 2 B Register ALU Reg. 1 ALU Reg. 2 PSW Interrupt Logic ALU Stack Pointer DPTR1 PC Address Reg. Address Bus Serial Port 0 Timer 1 Timed Access Buffer SFR RAM Address P3.0 to P3.7 Port 3 256 Bytes SFR 8 RAM PC Increm ent Program Counter DPTR0 Port Latch Timer 0 Port Latch RST XTAL2 Reset Control O scillator XTAL1 Clocks and M ory Control em PSE N ALE Power Control Register Data Bus FIGURE 8: CPU BLOCK DIAGRAM Revision B Page 21 July, 2002 P2.0 to P2.7 Port 2 Interrupt Reg. Instruction Decoder Port 0 Accum ulator AD0 to AD7 Port 1 CybraTech (2000) Ltd. . SOC-3000/i Scale-On-Chip ASIC Technical Specification Memory Organization The SOC-3000 is an 8051-compatible device with an 80C310 memory chip. As with all such devices, the SOC-3000 has separate address spaces for Program and Data memory. They are: • Flash memory – memory space containing non-volatile, in-circuit re-programmable code and data (such as calibration data). The code in the Flash memory may be in-circuit programmed at a byte level, although it must first be erased, the erasing being performed in page blocks. The program memory space can be in-circuit programmed through the serial port. RAM memory – Random Access memory used as “scratchpad memory” for the software. • Flash (Program & Non-Volatile Data) Memory Mapping and Usage The 8051-compatible SOC-3000 supports a maximum code space of 64K. Programs larger than 64K are handled by bank switching to select one of a number of code banks residing at one physical address. In the SOC-3000, there is one 32K Common-Program Area mapped from address 0000H to 7FFFH (Figure 9) and three 32K code banks mapped from code address 8000H to FFFFH (Figure 9). The code banks are selected using bits in a memory- mapped address. The Flash memory may be dynamically allocated between the Program and the Non-Volatile Data memory. This eliminates the need of external EEPROM usually used for storing calibration parameters and other non-volatile variable data. The Flash memory is built of 4K Bytes of erasable blocks whose boundary is located at 4k address (multiples of 1000H). FFFFH F800H Flash Data M ory em ROM Bank 1 32K ROM Bank 2 32K ROM Bank 3 32K 8000H 7FFFH FFFH ROM Com mon Area 32K 4K Reserved by System 0000H FIGURE 9: SOC-3000 PROGRAM MEMORY MAP Revision B Page 22 July, 2002 CybraTech (2000) Ltd. SOC-3000/i Scale-On-Chip ASIC Technical Specification Application Program Start Address The start address of the application program should be located at 1000H, as the first 4kBytes are reserved for the SOC-3000/I system. Serial Downloading (In-Circuit Programming) As part of its embedded boot software the SOC-3000 facilitates serial code and data download via the standard UART serial port. Serial download mode is automatically entered upon power-up or reset if one of the following conditions exist: 1. No valid program is programmed in the Flash memory. 2. A request for download process was initiated via the UART during the first 200 ms after power-up/reset. Once in this mode, you can download code or data files into the Flash memory, while the device is located on its target board. The is the PC serial download utility, CybraTech Cloader executable, is provided together with the device and its documentation and software library. The SOC-3000/I may be programmed only if, within 200ms after power-up or RESET, it establishes communication with the Cloader executable, or if the application program is not available or not valid (checksum error). Figure 10describes the startup procedure of the SOC-3000. Revision B Page 23 July, 2002 CybraTech (2000) Ltd. . SOC-3000/i Scale-On-Chip ASIC Technical Specification Power-Up / Reset Start Programming mode Yes Is Cloader Communicating ? No 200 ms elapsed ? Yes Is the Application Program OK? No No Yes Start Application Program FIGURE 10: SOC-3000/I STARTUP PROCEDURE Using the Flash for Data Memory The Flash memory may be used for storing non-volatile data. To update the data area while the program is running, the Flash must be defined as DATA area instead of as CODE area. CybraTech Flash Manager software manages this process in an efficient and reliable manner. It provides the means to read, write, erase and update the Flash Data area. A detailed description of the CybraTech Flash Manager function is included in the SOC-3000 Software Function Library user manual, document number: SOC-0000-SW01-OM. Revision B Page 24 July, 2002 CybraTech (2000) Ltd. SOC-3000/i Scale-On-Chip ASIC Technical Specification Data Memory Mapping The SOC-3000 “scratchpad” data memory is stored in 4Kbyte RAM mapped as XDATA, as shown in Figure 11, in addition to the CPU 256-byte RAM. 8FFFH Reserved 8C00H 8BFFH External RAM 3K 8000H FIGURE 11: SOC-3000 DATA MEMORY MAP Memory Bank Select Register The memory bank select register is implemented using the 80C51TBO Port 1 bits P1.0 – P1.1. P1.0 is the least significant bit. Manipulation of other Port 1 I/O pins must be carried out without affecting these bits. NOTE: The page register is WRITE ONLY! Reading P1.0-P1.1 may result in an ambiguous result. CPU SFRs and Configuration Registers (CFR) The CPU SFRs (Special Function Registers) are compatible with the 8051 instruction set. For more information, please refer to “M8051TBO Technical Specifications”. The CPU controls the peripherals and their operating modes through Configuration Registers (CFR) mapped as XDATA. The CFR registers for each peripheral are described below in Table 32, page 62. Instruction Set All instructions in the 8051-compatible SOC-3000 instruction set perform the same functions as in the 8051. They identically oversee bit and flag operations and other status functions. Only the clock configuration differs. For absolute timing of real time events, the timing of software loops can be calculated. However, counter/timers default to run at the older 12 clocks per increment. In this way, timer-based events occur at the standard intervals with software executing at higher speed. Timers optionally can run at 4 clocks per increment to take advantage of faster processor operation. Revision B Page 25 July, 2002 CybraTech (2000) Ltd. . SOC-3000/i Scale-On-Chip ASIC Technical Specification In the SOC-3000, the MOVX instruction may take only two machine cycles or eight oscillator cycles, while the “MOV direct, direct” instruction uses three machine cycles or 12 oscillator cycles. Thus, the execution times of the two instructions differ. This is because the SOC-3000 usually uses one instruction cycle for each instruction byte. Note that a machine cycle requires just four clocks, and provides one ALE pulse per cycle. Many instructions require only one cycle, but some require five. Reset The Reset signal is generated by an internal circuitry in the ASIC. The signal thresholds are: RESET Falling edge on Vcc=3.98V. RESET Rising edge on Vcc=4.19V. The hystheresis of the RESET signal is set so that normal operation of the internal Flash memory is guaranteed. Interrupt Vectors The interrupt vectors of the SOC-3000/I are shifted compared with the interrupt vectors of a standard 80C51TBO vectors by an offset of 1000H. Table 6 details the SOC-3000/I interrupt vectors: TABLE 6: INTERRUPT VECTORS DESCRIPTION FLAG IE0 TF0 IE1 TF1 RI + TI TF2 + EXF2 INTERRUPT SOURCE External Interrupt 0 Timer 0 Overflow External Interrupt 1 Timer 1 Overflow Serial Port Timer 2 Overflow VECTOR LOCATION 1003H 100BH 1013H 101BH 1023H 102BH PRIORITY 1 (Highest) 2 3 4 5 6 Revision B Page 26 July, 2002 CybraTech (2000) Ltd. SOC-3000/i Scale-On-Chip ASIC Technical Specification ADC CONTROLLER INTERFACE Features • Resolution – 20 bit • Programmable gain –0.5, 0.75, 1, 1.5, 2 • Programmable sample rate of 5, 10 or 20 samples per second • Voltage detection input and alarm Controller Registers ADC Converter (ADC) controller interface includes a semaphore register (one byte), a control register (two bytes) and a data/status register (four bytes). The ADC controller registers are defined in Table 7. TABLE 7: ADC CONTROLLER REGISTERS DESCRIPTION FUNCTION Controller Clock Enable Controller RESET Semaphore Register Data Registers Control Register ADDRESS C200H C406H E100H E103H to E106H E101H to E102H BIT 7 All 0-1 All All REMARKS 1 = Enable 0 =Disable 0xFF = Reset Read/Write Read only Write only Semaphore Register The semaphore register bit definitions are shown in Table 8. TABLE 8: ADDRESS E100H ADC CONTROLLER INTERFACE SEMAPHORE REGISTER BIT DEFINITIONS BIT 7 … BIT 2 Don’t Care BIT 1 BIT 0 (LSB) Tx Semaphore Rx Semaphore (Controller to ADC Converter) (ADC Converter to Controller) Control Register The control register bit definitions and its functions and are given in Table 9, page 28. Revision B Page 27 July, 2002 CybraTech (2000) Ltd. . TABLE 9: 1 SOC-3000/i Scale-On-Chip ASIC Technical Specification ADC CONTROLLER INTERFACE CONTROL REGISTER BIT FUNCTIONS BIT FUNCTION 0 = Disable 1 = Enable Don’t Care 00 = 20 Hz (default) & F.S=100,000 Counts 01 = 10 Hz & F.S. = 200,000 Counts 10 = 10 Hz& F.S. = 100,000 Counts 11 = 5 Hz& F.S. = 200,000 Counts 000 = 0.50 001 = 0.75 010 = 1.00 011 = 1.50 100 = 2.00 111 = Power Down 0 = Main (default) channel 1 = Secondary channel Don’t Care Don’t Care BYTE # ADDRESS E101H SETTINGS 0 Interrupt Enable (LSB) 1-7 Don’t Care Sample Rate 2 E102H 0-1 (bit 0 – LSB) 2-4 Gain Power Down 5 6 7 ADC Channel Don’t Care Don’t Care Status/Data Registers The data register bit definitions are shown in Table 10. The bit functions are described in Table 11. TABLE 10: ADC CONTROLLER INTERFACE DATA REGISTER BIT DEFINITIONS BYTE # ADDRESS BIT 7 1 2 3 4 E103H E104H E105H E106H D7 D15 BIT 6 D6 D14 BIT 5 D5 D13 SR1 0 BIT 4 D4 D12 SR0 0 BIT 3 D3 D11 D19 0 BIT 2 D2 D10 D18 0 BIT 1 D1 D9 D17 CH BIT 0 (LSB) D0 D8 D16 G2/PD2 G1/PD1 G0/PD0 0 0 TABLE 11: ADC CONTROLLER INTERFACE DATA REGISTER BIT FUNCTIONS BIT Di ADC Reading Data D0 = LSB D19 = MSB Sample Rate Gain/Power Down Active ADC Channel FUNCTION SRi Gi/PDi CH Revision B Page 28 July, 2002 CybraTech (2000) Ltd. SOC-3000/i Scale-On-Chip ASIC Technical Specification Operation Initialization: To enable the ADC controller interface: 1. Enable the ADC controller interface clock source in Clock Enable register C200H: Set C200H, Bit 7 to 1. 2. Reset the ADC controller interface: Write FF to register C406H. 3. Set the Configuration registers (CFR) address for ADC controller interface function: CFR address C10CH = 1FH. 4. Enable interrupt: Set E101H, Bit 0 to 1. 5. Check the semaphore byte at address E100H. If Receive semaphore bit at E100H is Ready (Bit 0 = 0), signaling the CPU that the ADC controller can receive data, the CPU performs the following operations: a. Sets the Transmit semaphore bit at E100H to Busy (Bit 1 = 1) to prevent transmission of data from the ADC controller. b. Programs the control register E101–E102H of the ADC controller to initialize controller operation. Normal operation: 6. After the ADC controller has been initialized, the following operations are performed: a. The CPU resets the Transmit semaphore bit at E100H to Ready (Bit 1 = 0) to signal the ADC controller that it can now transmit data. b. The ADC controller sets the Receive semaphore bit at E100H to Busy (Bit 0 = 1) to prevent further data transmission to the controller. c. The ADC controller sends ADC converter data to data registers at E103H to E106H. 7. After sending the data of registers E103H to E106H, the ADC controller resets the Receive semaphore bit at E100H to Ready (Bit 0 = 0), signaling the CPU that the controller can now receive new data. One ADC controller operation cycle is now complete. Steps 6 through 7 are repeated cyclically. The ADC internal counts output is dependent upon the input signal, the gain and the operation mode setting. Table 12 defines the relation between the internal counts output of the zero signal input of the full-scale signal and the ADC settings. Revision B Page 29 July, 2002 CybraTech (2000) Ltd. . SOC-3000/i Scale-On-Chip ASIC Technical Specification TABLE 12: ADC OUTPUT COUNTS VS. ADC SETTINGS GAIN SAMPLE RATE * (HZ) 20 10 10 5 0.75 20 10 10 5 1.0 20 10 10 5 1.5 20 10 10 5 2.0 20 10 10 5 ADC RESOLUTION MODE * (IN COUNTS) 100,000 100,000 200,000 200,000 100,000 100,000 200,000 200,000 100,000 100,000 200,000 200,000 100,000 100,000 200,000 200,000 100,000 100,000 200,000 200,000 ADC OUTPUT AT ZERO SIGNAL INPUT (COUNTS) 153,200 153,200 306,400 306,400 153,200 153,200 306,400 306,400 153,200 153,200 306,400 306,400 153,200 153,200 306,400 306,400 153,200 153,200 306,400 306,400 MAXIMUM FULL-SCALE INPUT (MILLI-VOLTS) 10 10 10 10 10 10 10 10 10 10 10 10 6.6 6.6 6.6 6.6 5 5 5 5 ADC OUTPUT (COUNTS) 0.5 205,000 205,000 412,000 412,000 231,000 231,000 464,000 464,000 257,000 257,000 514,000 514,000 257,000 257,000 514,000 514,000 257,000 257,000 514,000 514,000 * ADC Resolution mode is defined in Table 9, Register E102H, bits 0-1 – Sample Rate. Revision B Page 30 July, 2002 CybraTech (2000) Ltd. SOC-3000/i Scale-On-Chip ASIC Technical Specification KEYBOARD CONTROLLER Features • Supports up to 64 keys (8×8) • Programmable anti-bounce mechanism (4-18 ms) • Automatic key matrix scanning • Automatically detects excessively long or constant key depression • When Interrupt mode enabled, generates an interrupt when any key is pressed or released KIN 0 KIN 1 KIN 2 Functional Description Keyboard Controller Matrix Configuration The keyboard matrix configuration showing the 8 × 8 matrix is given in Figure 12. The key values at each junction are in hexadecimal. KIN 3 KIN 4 KIN 5 KIN 6 KIN 7 KOUT 0 * 00 01 02 03 04 05 06 07 KOUT 1 10 11 12 13 14 15 16 17 KOUT 2 20 21 22 23 24 25 26 27 KOUT 3 30 31 32 33 34 35 36 37 KOUT 4 40 41 42 43 44 45 46 47 KOUT 5 50 51 52 53 54 55 56 57 KOUT 6 60 61 62 63 64 65 66 67 KOUT 7 70 71 72 73 74 75 76 77 *Key values are in hexadecimal. FIGURE 12: KEYBOARD MATRIX CONFIGURATION Revision B Page 31 July, 2002 CybraTech (2000) Ltd. SOC-3000/i Scale-On-Chip ASIC Technical Specification Controller Registers Keyboard controller interface includes a control register (one byte) and a data/status register (two bytes). The Keyboard controller registers are defined in Table 13. TABLE 13: KEYBOARD CONTROLLER REGISTERS DESCRIPTION FUNCTION Controller Clock Enable Controller RESET Data Registers Control Register ADDRESS C200H C400H F100H to F101H F100H BIT 2 All All All REMARKS 1= Enable 0= Disable 0xFF = Reset Read only Write only Registers Description Control Register The keyboard control register bit definitions, functions, and settings are displayed in Table 14. TABLE 14: KEYBOARD CONTROLLER CONTROL REGISTER BIT FUNCTIONS ADDRESS F100H BIT FUNCTION 000 = 4 ms 001 = 6 ms 010 = 8 ms 011 = 10 ms 100 = 12 ms 101 = 14 ms 110 = 16 ms 111 = 18 ms SETTINGS 0-2 Anti-Bounce Timeout (bit 0 -LSB) 3 4-7 Interrupt Enable/Disable Don’t Care 0 = Enable 1 = Disable (default) Don’t Care Data Registers Keyboard data is stored in two 8-bit registers. The data register bit functions are shown in Table 15. Revision B Page 32 July, 2002 CybraTech (2000) Ltd. SOC-3000/i Scale-On-Chip ASIC Technical Specification NOTE When Control Register Address F101H, bit 7 is set to 1 (Released), key-code value bits 0 to 6 in address F101H are meaningless. TABLE 15: KEYBOARD CONTROLLER DATA REGISTER BIT DEFINITIONS BYTE # ADDRESS 1 F100H BIT 7 X BIT 6 X BIT 5 X BIT 4 X BIT 3 X BIT 2 X BIT 1 X BIT 0 (LSB) Key Error 0 = Legal 1 = Error D0 2 F101H Release Sign 0 = Pressed 1 = Released D6 D5 D4 D3 D2 D1 Operation At power on, the keyboard controller is reset and the scanning rate is set to 10 µs. Initialization: To enable the keyboard controller: 1. Enable the keyboard controller clock source in Clock Enable register C200H: Set C200H, Bit 2 to 1. 2. Reset the keyboard controller: Write FF to register C400H. 3. Set CFR address for keyboard controller function: CFR addresses C10DH and C10EH = FF (Table 32, page 62). This causes the following results: • Enables keyboard input pins (1 to 5 and 82 to 84) (Table 32; page 62; Table 1, page 9; Table 2, page 12) • Enables keyboard output pins (74 to 81) (Table 32, Table 1, Table 2) 4. Enable keyboard interrupt: Set F100H, Bit 3 to 0. 5. Set anti-bounce timeout: Set F100H, Bits 0, 1 and 2, as shown in Table 14. Normal Operation: 6. Read keyboard key-code value bits, as follows: • Read register F100H, Bit 0: If 0, key-code value is legal. If 1, key-code value is illegal (Error). • Read key code from register F101H, bits 0 to 6: When key pressed, values are valid. • Read F101H, bit 7: If 0, key pressed and keyboard values (bits 0 to 6) are valid. If 1, key released and keyboard values are meaningless. Revision B Page 33 July, 2002 CybraTech (2000) Ltd. SOC-3000/i Scale-On-Chip ASIC Technical Specification LCD CONTROLLER/DRIVER Features • Selectable backplane drive configuration, static or multiplex drive ratios of 1:2, 1:3 or 1:4 • Selectable display bias configuration, static, or 1/2 bias or 1/3 bias • Internal LCD bias generation with voltagefollower buffers • Drives up to 40 segments with the capacity to generate 20 numeric characters • 20 × 8-bit memory display data • User-selected LCD voltages Functional Description The SOC-3000 LCD controller/driver interfaces to LCD (Liquid Crystal Display) with low multiplex rates. The controller/driver generates drive signals for static drive mode (no multiplexing) or multiplexed LCDs with multiplex drive ratios of 1:2, 1:3 or 1:4, depending on the number of backplane outputs. The driver supports up to four backplanes, each supporting 40 segments. The LCD Controller/Driver block diagram is shown in Figure 13. The driver supports numeric, alphanumeric and dot matrix display configurations. The number of characters of each type that can be displayed depends on the number of backplanes and the number of segments required per character. The maximum display capacity for each display configuration is shown in Table 16. VDD Backplane O utputs R Display Segm ent O utputs – + Display Latch R – + LCD Voltage Selector Shift Register R VLCD LCD Bias G enerator FIGURE 13: LCD CONTROLLER/DRIVER BLOCK DIAGRAM Revision B Page 35 0 to 39 BP0 BP1 BP2 BP3 July, 2002 CybraTech (2000) Ltd. SOC-3000/i Scale-On-Chip ASIC Technical Specification TABLE 16: MAXIMUM DISPLAY CAPACITY PER DISPLAY CONFIGURATION NUMBER OF BACKPLANES 4 3 2 1 SEGMENTS OR SYMBOLS 160 120 80 40 NUMERIC (7 SEGMENTS) 20 15 10 5 LCD Bias Generator The operative LCD voltage is derived from VDD – VLCD (Figure 13). The three resistors connected in series between VDD and VLCD in the bias generator function as a voltage divider to produce 1/2 (for the 1:2 multiplex drive ratio) and 1/3 (for the 1:2, 1:3 and 1:4 multiplex drive ratio) biasing voltages. The bias configuration for each of the multiplex drive ratios is given in Table 17. For additional information on LCD drivers refer to LCD driver components datasheets such as Phillips PCF8756. TABLE 17: LCD BIAS CONFIGURATIONS MULTIPLEX DRIVE MODE Static 1:2 1:2 1:3 1:4 # BACKPLANES 1 2 2 3 4 # LEVELS 2 3 4 4 4 BIAS CONFIGURATION Static 1/2 1/3 1/3 1/3 Drive Mode Waveforms The waveforms for the Static drive mode are given in Figure 14, page 37. The waveforms for the 1:2 Multiplex Drive Ratio–1/2 Bias are given in Figure 15, page 38. The waveforms for the 1:2 Multiplex Drive Ratio–1/3 Bias are given in Figure 16, page 39. The waveforms for the 1:3 Multiplex Drive Ratio are given in Figure 17, page 40. The waveforms for the 1:4 Multiplex Drive Ratio are given in Figure 18, page 41. Revision B Page 36 July, 2002 CybraTech (2000) Ltd. SOC-3000/i Scale-On-Chip ASIC T Frame VDD Technical Specification Backplane 0 VLCD Driver Waveforms Segment n On VDD VLCD VDD Segment n+1 Off VLCD + VOPER Segment On 0V LCD Segment Waveforms On/Off – VOPER + VOPER Segment Off 0V – VOPER FIGURE 14: STATIC DRIVE MODE WAVEFORMS Revision B Page 37 July, 2002 CybraTech (2000) Ltd. SOC-3000/i Scale-On-Chip ASIC Technical Specification Backplane 0 Backplane 1 Driver Waveforms Segment n Segment n+1 LCD Segment Waveforms On/Off Segment On Segment Off FIGURE 15: 1:2 MULTIPLEX DRIVE RATIO–1/2 BIAS WAVEFORMS Revision B Page 38 July, 2002 CybraTech (2000) Ltd. SOC-3000/i Scale-On-Chip ASIC Technical Specification T Frame Backplane 0 Backplane 1 Driver Waveforms Segment n Segment n+1 LCD Segment Waveforms On/Off Segment On Segment Off FIGURE 16: 1:2 MULTIPLEX DRIVE RATIO–1/3 BIAS WAVEFORMS Revision B Page 39 July, 2002 CybraTech (2000) Ltd. SOC-3000/i Scale-On-Chip ASIC Technical Specification T Frame Backplane 0 Backplane 1 Driver Waveforms Backplane 2 Segment n Segment n+1 Segment n+2 Segment On LCD Segment Waveforms On/Off Segment Off FIGURE 17: 1:3 MULTIPLEX DRIVE RATIO WAVEFORMS Revision B Page 40 July, 2002 CybraTech (2000) Ltd. SOC-3000/i Scale-On-Chip ASIC Technical Specification T Frame Backplane 0 Backplane 1 Driver Waveforms Backplane 2 Backplane 3 Segment n Segment n+1 Segment n+2 Segment n+3 LCD Segment Waveforms On/Off Segment On Segment Off FIGURE 18: 1:4 MULTIPLEX DRIVE RATIO WAVEFORMS Revision B Page 41 July, 2002 CybraTech (2000) Ltd. SOC-3000/i Scale-On-Chip ASIC Technical Specification Registers Description LCD controller /driver command and data are stored in a 21-byte × 8-bit, static display RAM with one control register and 20 data registers. The controller registers are defined in Table 18. TABLE 18: LCD CONTROLLER/DRIVER REGISTERS DESCRIPTION FUNCTION Controller Clock Enable Controller RESET Data Registers Control Register ADDRESS C200H C401H C801H to C814H C800H BIT 0 All All All REMARKS 1= Enable 0= Disable 0xFF = Reset Write only Read/Write Control Register The control-register bit definitions and functions are displayed in Table 19. The Type definitions are Static and Dynamic: Static bits update only after an external Reset and first chip select (first command write cycle). Dynamic bits can be updated at any time. TABLE 19: LCD CONTROLLER CONTROL REGISTER BIT FUNCTIONS ADDRESS C800H BIT NAME UPDATE FUNCTION SETTINGS 0-1 M0 and M1 After Reset Only ( 0LSB) Bits 0 (M0) and 1 (M1) set 00 = Static (5 seven-segment the multiplex drive ratio. digits) 01 = 1:2 (10 seven-segment digits) 10 = 1:3 (15 seven-segment digits) 11 = 1:4 (20 seven-segment digits) Sets the bias voltage. Sets LCD display operation. Bits 4 (X0), 5 (X1) and 6 (X2) set the refresh clock frequency. 0 = 1/2 1 = 1/3 0 = Disable 1 = Enable 000 = 52 Hz 001 = 104 Hz 010 = 156 Hz 011 = 208 Hz 100 = 62 Hz 101 = 125 Hz 110 = 178 Hz 111 = 250 Hz 2 3 4-6 B E X0 (LSB), X1 and X2 After Reset Only Anytime After Reset Only 7 C Anytime Sets the command operating mode. 0 = Continuous Data Reading 1= Command Only Revision B Page 42 July, 2002 CybraTech (2000) Ltd. SOC-3000/i Scale-On-Chip ASIC Technical Specification Data Registers LCD display data is stored in a 20-byte × 8-bit RAM. The number of registers used depends on the number of digits displayed, 5, 10, 15 or 20. The data register bit definitions for a 20-digit display, for which the entire RAM is used, are shown in Table 20. TABLE 20: LCD CONTROLLER DATA REGISTER BIT DEFINITIONS – 20-DIGIT DISPLAY Byte # 1 2 … 20 Address C801H C802H … C814H Bit 7 DP DP … DP Bit 6 g g … g Bit 5 f f … f Bit 4 e e … e Bit 3 d d … d Bit 2 c c … c Bit 1 b b … b Bit 0 a a … a For other displays, Data Registers utilization is as follows: • For 15-digit command, write data to C801H to C80FH • For 10-digit command, write data to C801H to C80AH • For 5-digit command, write data to C801H to C805H Each byte in the register defines a seven-segment digit and decimal point (DP). Each bit of a register address corresponds to a segment of each digit, as shown in Figure 19. When the bit is set to 1, it is on. When it is set to 0, it is off. Figure 19 also shows the backplane outputs per LCD digit for each multiplex drive ratio. BP 0 a f g b f g BP 0 a BP 1 BP 0 a BP 0 a b g f g b b f BP 1 e c BP 2 c d DP BP 1 e c d BP 2 e c d DP e d DP BP 3 DP Static 1:2 M ultiplex 1:3 Multiplex 1:4 Multiplex FIGURE 19: BACKPLANE OUTPUTS PER LCD DIGIT Revision B Page 43 July, 2002 CybraTech (2000) Ltd. SOC-3000/i Scale-On-Chip ASIC Technical Specification Operation Initialization: At power on, the LCD controller performs the following operations: 1. Resets its backplane and segment outputs to VDD. After power on, the actual operating LCD voltage VOPER is set according to the multiplexing drive mode and the bias generator. 2. After reset, the LCD pins are routed to the Output function. To enable the LCD controller: 1. Enable the LCD controller clock source in Clock Enable register C200H: Set C200H, Bit 0 to 1. 2. Reset the LCD controller: Write FF to register C401H. 3. Set CFR addresses for LCD controller function: CFR addresses C101H to C10BH = 00H (Table 32, page 62). This enables LCD controller output pins (18 to 61) (Table 32, page 62; Table 1, page 9). Normal Operation: 4. Write data to LCD data registers C801H to C814H. 5. Set Write command in LCD control register C800H. 6. Repeat steps 4 and 5 for new data. The trigger for sending the data out to the display interface is: Programming the control register at address C800H AND writing data to the LCD data registers (C801H to C814H). Revision B Page 44 July, 2002 CybraTech (2000) Ltd. SOC-3000/i Scale-On-Chip ASIC Technical Specification LED PARALLEL DISPLAY CONTROLLER Features • Supports up to 21 digits (7 segments + Decimal Point) • Power-save by LED refresh mechanism • Programmable-display data registers • Supports common-anode, seven-segment LED Reg. Address Seg a–1 Seg b–1 Seg c–1 Seg d–1 Seg e–1 Seg f–1 Seg g–1 DP–1 D101 a f g e d e DP d b f g e DP d Functional Description The LED display block diagram showing the relationship between the 21-digit LED display, the SOC-3000 LED controller and the data register is given in Figure 20. The LED Controller timing diagram is shown in Figure 21. D104 a b g e DP d f g e DP d b f g e DP d D102 a b f D103 a D105 a b f D106 a b g e DP f D107 a b g c c c c c c c d DP DIG 1 DIG 2 D109 a DIG 3 D10A a DIG 4 D10B a DIG 5 D10C a DIG 6 D10D a DIG 7 D10E a Reg. Address Seg a–2 Seg b–2 Seg c–2 Seg d–2 Seg e–2 Seg f–2 Seg g–2 DP–2 D108 a f g e d e DP b f b g f g e DP d b f g e DP d b f g e DP d b f g e DP d b f g e DP d b c c d c c c c c DP DIG 1 DIG 2 D110 a DIG 3 D111 a DIG 4 D112 a DIG 5 D113 a DIG 6 D114 a DIG 7 D115 a Reg. Address Seg a–3 Seg b–3 Seg c–3 Seg d–3 Seg e–3 Seg f–3 Seg g–3 DP–3 D10F a f g e d e DP b f b g f g e DP d b f g e DP d b f g e DP d b f g e DP d b f g e DP d b c c d c c c c c DP DIG 1 DIG 2 DIG 3 DIG 4 DIG 5 DIG 6 DIG 7 Seg a–1 Seg b–1 Seg c–1 Seg d–1 Seg e–1 Seg f–1 Seg g–1 DP–1 Seg a–2 Seg b–2 Seg c–2 Seg d–2 Seg e–2 Seg f–2 Seg g–2 DP–2 Seg a–3 Seg b–3 Seg c–3 Seg d–3 Seg e–3 Seg f–3 Seg g–3 DP–3 SOC–3000 FIGURE 20: LED PARALLEL DISPLAY CONTROLLER BLOCK DIAGRAM Revision B Page 45 DIG DIG DIG DIG DIG DIG DIG 1 2 3 4 5 6 7 July, 2002 CybraTech (2000) Ltd. SOC-3000/i Scale-On-Chip ASIC Technical Specification SEGMENT 500 µs 500 µs 30 µs 30 µs DIG 1 440 µs 60 µs DIG 2 440 µs FIGURE 21: LED PARALLEL DISPLAY CONTROLLER TIMING DIAGRAM Registers Description The LED controller registers are defined in Table 21. TABLE 21: LED PARALLEL DISPLAY CONTROLLER DRIVER REGISTERS DESCRIPTION FUNCTION Controller Clock Enable Controller RESET Semaphore Bit Data Registers ADDRESS C200H C402H D100H D101H to D115H BIT 1 All 0 All REMARK 1= Enable 0= Disable 0xFF = Reset Read only Write only LED display data is stored in a 21-byte × 8-bit static display RAM. The display RAM has one Read-only semaphore register containing the semaphore byte and 21 Write-only data registers. All 22 bytes (one semaphore byte and 21 data bytes) must be written before any new data is applied. Revision B Page 46 July, 2002 CybraTech (2000) Ltd. SOC-3000/i Scale-On-Chip ASIC Technical Specification Semaphore Register The Semaphore register bit definitions are shown in Table 22. TABLE 22: LED PARALLEL DISPLAY CONTROLLER SEMAPHORE REGISTER BIT DEFINITIONS ADDRESS D100H BIT 7 X BIT 6 X BIT 5 X BIT 4 X BIT 3 X BIT 2 X BIT 1 X BIT 0 (LSB) E Only Bit 0, the Semaphore bit, is active in the LED Controller control register (Table 23). The semaphore is used to synchronize the access to the control registers. TABLE 23: LED PARALLEL DISPLAY CONTROLLER SEMAPHORE REGISTER BIT FUNCTIONS BIT 0 NAME E TYPE Read-only FUNCTION Semaphore bit SETTINGS 0 = Ready 1 = Busy Data Registers LED data is stored in a 21-byte × 8-bit RAM. The data is organized in three groups of seven digits, as follows: • Group 1: D101H to D107H - multiplexed on SEC A1 to DP1 Pins. • Group 2: D108H to D10EH - multiplexed on SEC A2 to DP2 Pins. • Group 3: D10FH to D115H - multiplexed on SEC A3 to DP3 Pins. The data register bit definitions for a 21-digit display are shown in Table 24. TABLE 24: LED PARALLEL CONTROLLER DATA REGISTER BIT DEFINITIONS GROUP 1 BYTE # 1 2 3 to 7 ADDRESS D101H D102H D103H to D107H D108H D109H D10AH to D10EH D10FH D110H D111H to D115H BIT 7 DP DP DP DP DP DP DP DP DP BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 (LSB) g g g g g g g g g f f f f f f f f f e e e e e e e e e d d d d d d d d d c c c c c c c c c b b b b b b b b b a a a a a a a a a 2 8 9 10 to 14 3 15 16 17 to 21 Note: The trigger for sending the data to the display hardware is writing data to address D115H. Revision B Page 47 July, 2002 CybraTech (2000) Ltd. SOC-3000/i Scale-On-Chip ASIC Technical Specification Operation At power-on or reset the LED Parallel display controller is disabled. Initialization: To enable the LED Parallel display controller: 1. Enable the controller clock source in Clock Enable register C200H: Set C200H, Bit 1 to 1. 2. Reset the controller: Write FF to register C402H. 3. Set CFR addresses for LED Parallel display controller function: CFR addresses C103H to C109H = 55H, CFR address C10A = 15H (Table 32, page 62). These result in the following operations: • Enable LED parallel display controller output pins (22 to 52) (Table 32, page 62; Table 2, page 12). • Check semaphore bit in LED parallel display controller semaphore register at address D100H. Normal Operation: 4. If semaphore bit is Ready (Bit 0 set to 0), write data to Data register addresses D101H to D115H. 5. Set Write command: Write 01H to D100H. The trigger for sending the data out to the display serial interface is: • Programming the semaphore register at address D100H AND writing data to the 21 data registers (D101H to D115H). OR • Programming the semaphore register at D100H AND writing data to the last data register at D115H. As soon as the controller starts to send the data, it sets the semaphore bit to 1, indicating that it is busy. When the controller finishes data output, it resets the semaphore bit to 0, indicating that it is available for a new operation. Revision B Page 48 July, 2002 CybraTech (2000) Ltd. SOC-3000/i Scale-On-Chip ASIC Technical Specification LED SERIAL INTERFACE DISPLAY CONTROLLER Features • • • • • Supports up to 24 digits Serial interface Programmable control-signal polarity Programmable data registers Supports common-anode, seven-segment LED Functional Description The LED Serial Interface display comprises three groups of eight digits. The controller diagram showing the division of the 24-byte register into three eight-byte groups and the operation cycle is given in Figure 22. The LED Serial Interface Display Controller timing diagram is shown in Figure 23. The clock rate is 2 MHz. Group 1 Seg a Seg b Seg c Seg d Seg e Seg f Seg g DP Digit 8 a f g e d e DP b f Digit 7 a b g e DP f Digit 6 a b g e DP f Digit 5 a b g e DP f Digit 4 a b g e DP f Digit 3 a b g e DP f Digit 2 a b g e DP f Digit 1 a b g c c d c d c d c d c d c d c d DP Group 2 Seg a Seg b Seg c Seg d Seg e Seg f Seg g DP Digit 8 a f g e d e DP b f Digit 7 a b g e DP f Digit 6 a b g e DP f Digit 5 a b g e DP f Digit 4 a b g e DP f Digit 3 a b g e DP f Digit 2 a b g e DP f Digit 1 a b g c c d c d c d c d c d c d c d DP Group 3 Seg a Seg b Seg c Seg d Seg e Seg f Seg g DP Digit 8 a f g e d e DP b f Digit 7 a b g e DP f Digit 6 a b g e DP f Digit 5 a b g e DP f Digit 4 a b g e DP f Digit 3 a b g e DP f Digit 2 a b g e DP f Digit 1 a b g c c d c d c d c d c d c d c d DP Cycle 1 0 0 0 0 0 0 0 1 X X X X X X X X X X X X X X X X X X X X X X X X Digit 1 Cycle 8 1 0 0 0 0 0 0 0 X X X Group 1 X X X X X X X X Group 2 X X X X X X X X Group 3 X X X X X The controller transmits cycles 1 to 8 continuously. FIGURE 22: LED SERIAL INTERFACE DISPLAY BLOCK DIAGRAM Revision B Page 49 July, 2002 CybraTech (2000) Ltd. SOC-3000/i Scale-On-Chip ASIC Technical Specification 20 µs BLAN / K BLANK 20 µs t = 400 µs STR OBE / STR OBE 20 µs t1 = 8 µs CLO / CK DATA CLOCK FIGURE 23: LED SERIAL INTERFACE CONTROLLER TIMING DIAGRAM Registers Description The LED Serial controller registers description is given in Table 25. TABLE 25: LED SERIAL CONTROLLER DRIVER REGISTERS DESCRIPTION FUNCTION Controller Clock Enable Controller RESET Semaphore register Data Registers Group 1 Group 2 Group 3 Control Register ADDRESS C200H C403H D201H D201H to D208H D209H to D210H D211H to D218H D200H BIT 5 All 1= Enable 0= Disable REMARKS 0xFF = Reset Read only Write Only Write Only Write Only Read/Write LED data is stored in a 24-byte × 8-bit static display RAM. The data registers are divided into three groups, each group containing eight bytes with the segment data for eight digits. Thus, the LED display can be formatted to display eight, 16 or 24 digits. The display RAM has one Read/Write control register containing the Command byte and a Read-only semaphore byte that informs the system if the display is Busy or Ready to initiate writing of LED data. The semaphore byte address also serves as first address of the Write-only data register. The trigger for sending the data out to the display serial interface is programming the control register at address D200H. As soon as the controller starts to send data, it sets the semaphore byte to FFH, indicating that it is busy. The data is sent serially, Group 1 Digit 8 (left-most digit of the first group) mostsignificant bit (MSB) first, and continuously until Group 3 Digit 1 least-significant bit (LSB) last. Revision B Page 50 July, 2002 CybraTech (2000) Ltd. SOC-3000/i Scale-On-Chip ASIC Technical Specification When the controller has finished data output, it resets the semaphore byte to 0, indicating that it is available for a new operation. Control Register The definitions and functions of the control-register Command-byte bits are displayed in Table 26. TABLE 26: LED SERIAL INTERFACE DISPLAY CONTROL REGISTER BIT FUNCTIONS ADDRESS D200H BIT 0C (LSB) 1 2 3 4 5 6 7 X NAME FUNCTION Command bit N/A Sets the Blank polarity. Sets the Strobe polarity. Sets the Clock polarity. Enables and disables the display. SETTINGS 0 = Command Only 1 = Command + Data Don’t Care 0 = Negative Logic 1 = Positive Logic 0 = Negative Logic 1 = Positive Logic 0 = Negative Logic 1 = Positive Logic 0 = Disable Display 1 = Enable Display Blank Polarity Strobe Polarity Clock Polarity E Block N/A 0 = Close communication Opens communication or blocks the hardware communication lines. 1 = Open communication N/A Don’t Care Semaphore Register The semaphore byte is located at address D201H, which is the first address of the Write-only data register. This address is Read-only for the semaphore byte. The semaphore byte bit definitions are identical. The settings are: • Controller is Busy: Bits 0 to 7 set to 1 (FFH). • Controller is Ready: Bits 0 to 7 set to 0 (00H). Revision B Page 51 July, 2002 CybraTech (2000) Ltd. SOC-3000/i Scale-On-Chip ASIC Technical Specification Data Registers The display data is stored in a 24-byte × 8-bit RAM area. The data register bit definitions for a 21-digit display are shown in Table 27. The registers are Write-only. TABLE 27: LED SERIAL INTERFACE DISPLAY DATA REGISTER BIT DEFINITIONS GROUP DIGIT BYTE ADDRESS BIT 7 BIT 6 # # (MSB) # 1 8 7 6 5 4 3 2 1 2 8 7 6 5 4 3 2 1 3 8 8 8 8 8 8 8 8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 D201H D202H D203H D204H D205H D206H D207H D208H D209H D20AH D20BH D20CH D20DH D20EH D20FH D210H D211H D212H D213H D214H D215H D216H D217H D218H DP DP DP DP DP DP DP DP DP DP DP DP DP DP DP DP DP DP DP DP DP DP DP DP g g g g g g g g g g g g g g g g g g g g g g g g BIT 5 f f f f f f f f f f f f f f f f f f f f f f f f BIT 4 e e e e e e e e e e e e e e e e e e e e e e e e BIT 3 d d d d d d d d d d d d d d d d d d d d d d d d BIT 2 c c c c c c c c c c c c c c c c c c c c c c c c BIT 1 BIT 0 (LSB) b b b b b b b b b b b b b b b b b b b b b b b b a a a a a a a a a a a a a a a a A a a a a a a a Revision B Page 52 July, 2002 CybraTech (2000) Ltd. SOC-3000/i Scale-On-Chip ASIC Technical Specification Operation At power-on or reset the LED Serial Interface display controller is disabled. Initialization: To enable the LED Serial Interface display controller: 1. Enable the controller clock source in Clock Enable register C200H: Set C200H, Bit 5 to 1. 2. Reset the controller: Write FF to register C403H. 3. Check CFR address for LED serial Interface display controller function: CFR address C101H = AA (Table 32, page 62). This results in the following operations: • Enables serial controller output pins (58 to 61) (Table 32, page 62) • Check semaphore byte at address D201H. Normal Operation: 4. If semaphore byte is Ready (Bits 0 to 7 set to 0), write data to Data register addresses D201H to D218H. 5. Set Write command at the controller Control register address D200H. 6. Repeat steps 4 and 5 for new data. Revision B Page 53 July, 2002 CybraTech (2000) Ltd. SOC-3000/i Scale-On-Chip ASIC Technical Specification PROGRAMMABLE FREQUENCY CONTROLLER Features • Programmable CPU clock frequency: 16, 8, 4, 2, 1 or 0.5 MHz • Driven by a 16-MHz resonator or crystal oscillator Functional Description Dividing the 16-MHz frequency source according to the control register setting generates the CPU clock frequency. The CPU clock can be set to 16, 8, 4, 2, 1 or 0.5 MHz. Functions • Generates independent clocks for the CPU and Switching CPU frequency: controllers (ADC converter, display, • To switch from the 16-MHz frequency to any keyboard, watchdog timer, etc.) other frequency, program the frequencycontroller control register as shown in Clock Generator Block Diagram Table 28. The clock generator block diagram is presented in • To switch from any frequency (other than Figure 24. 16 MHz) to another frequency, first switch to 16 MHz and then switch to the desired frequency. 16 MHz Clock 16 MHz (Default) 1/2 8 MHz 1/2 4 MHz 1/2 2 MHz 1/2 1 MHz 1/2 0.5 MHz FIGURE 24: CLOCK GENERATOR BLOCK DIAGRAM Revision B Page 55 July, 2002 CybraTech (2000) Ltd. SOC-3000/i Scale-On-Chip ASIC Technical Specification Operation At Power on or Reset, the CPU frequency clock output is set to 16 MHz. The clocks for the controllers is fixed and derived directly from the external frequency source. The Frequency controller setting derives the CPU clock, as defined in Table 28. Control Registers Description The clock frequency is programmed from a single 8-bit control register. The address of the clock frequency control register is E800H. The bit settings at E800H that define the clock frequency are given in Table 28. TABLE 28: CLOCK FREQUENCY CONTROL REGISTER BIT SETTINGS ADDRESS E800H BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 (LSB) Don’t Care 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 CPU CLOCK 16 MHz 8 MHz 4 MHz 2 MHz 1 MHz 0.5 MHz Revision B Page 56 July, 2002 CybraTech (2000) Ltd. SOC-3000/i Scale-On-Chip ASIC Technical Specification WATCHDOG TIMER Functions The purpose of the watchdog timer is to generate a CPU reset at specified intervals. If the SOC-3000 software does not interrupt the watchdog cycle and instead enters an erroneous state, the watchdog time carries out its CPU reset one second after the software was supposed to make its interrupt. The erroneous state may be due to a programming error. The watchdog may be disabled or retriggered via its control register. Functional Description The operating parameters of the watchdog timer are presented in Table 29. TABLE 29: WATCHDOG TIMER OPERATING PARAMETERS PARAMETER Time Constant Trigger Enable/Disable Power Up Mode 1 second By the control register (WDI) By the control register (ENWD) Disabled VALUE Operation The application software controls the watchdog operation. It is automatically disabled in the In-circuit Emulator (ICE) mode and after power-up or reset. The application software should activate the watchdog as soon as it starts normal operation after power-on or reset conditions. The watchdog timer should be periodically re-triggered during normal operation, before the timer expires. Expiration of the watchdog timer resets the CPU. If required, disabling the watchdog timer clock input can disable the watchdog. Table 30 describes the operation of the watchdog timer. TABLE 30: WATCHDOG TIMER COMMAND SEQUENCE # COMMAND C200H F800H C200H ADDRESS BIT 3 all 3 SETTING 1= Enable 0= Disable FFH 0 1 Enable Watchdog 2 Re-trigger Timer 3 Disable Watchdog Control Registers Description Setting the Clock Enable register (C200H), bit 3 to 1 enables the watchdog timer. Setting the Clock Enable register (C200H), bit 3 to 0 disables the watchdog timer. Writing FFH to address F800H re-triggers the watchdog. Revision B Page 57 July, 2002 CybraTech (2000) Ltd. SOC-3000/i Scale-On-Chip ASIC Technical Specification LOW VOLTAGE DETECTOR The low voltage detector is a supervisory circuit in which the Power Fail Input (Vdet) is compared to an internal 2.23 V reference (Figure 25). The comparator output goes low when the voltage at Vdet is less than or equal to 2.23 V and Bit 1 of register E400H equals 0. Vdet is usually driven by an external voltage divider, which senses the unregulated DC input to the system 5V regulator. The voltage divider ratio can be chosen such that the voltage at Vdet falls below 2.23 V several milliseconds before the +5V supply falls below 4.75V. INT0 is normally used to interrupt the microprocessor so that data can be stored in non-volatile memory before VCC falls below 4.75 V and the RESET output goes low. The Power Fail Comparator output returns to High when Vdet>2.27V. DC Unreg. Vin REG VCC Recom ended m Values for Resistors 1% 133K R1 Vdet SOC-3000 Power Fail Comparator + INTØ 1% 100K R2 – INTØ INTØ 5.19V (Typ.) 5.3V (Typ.) INTØ goes low if Vdet < 2.23V. FIGURE 25: LOW VOLTAGE DETECTOR Interrupt Register The address of the power-supply interrupt register is E400H (Read/Write). The bit settings at E400H that define the power failure interrupt and flag are given in Table 31. TABLE 31: POWER-FAILURE INTERRUPT REGISTER BIT SETTINGS ADDRESS BIT BIT BIT BIT BIT BIT BIT 1 BIT 0 (LSB) 7 6 5 4 3 2 POWER FAIL FLAG INTERRUPT ENABLE E400H Don’t Care 0 = If VDET < VREF 1 = Normal 0 = Enabled 1 = Disabled Revision B Page 59 July, 2002 CybraTech (2000) Ltd. SOC-3000/i Scale-On-Chip ASIC Technical Specification Revision B Page 60 July, 2002 CybraTech (2000) Ltd. SOC-3000/i Scale-On-Chip ASIC Technical Specification CONFIGURATION REGISTERS (CFR) Programming the configuration registers (CFR) in the CPU sets the SOC-3000 pin functions. The CFR registers include control and configuration registers that provide the interface between the CPU and the other on-chip peripherals, such as the keyboard, LED and LCD controllers and input/output ports. Each peripheral operates as designated in the CFR registers, where each register may be programmed to perform alternative functions. (See “Examples of Pin Configuration Programming”, on page 85). The complete CFR-register bit assignment for all peripherals and input/output and corresponding PLCC-84 pins are given on the following pages in Table 32. Revision B Page 61 July, 2002 CybraTech (2000) Ltd. SOC-3000/i Scale-On-Chip ASIC Technical Specification TABLE 32: CFR BIT ASSIGNMENT PLCC-84 PIN 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 C106H C105H C104H C103H C102H REG ADD. C101H BIT 7-6 5-4 3-2 1-0 7 6 5-4 3-2 1-0 7-6 5-4 3-2 1-0 7-6 5-4 3-2 1-0 7-6 5-4 3-2 1-0 7-6 5-4 00=LCD Display S40 00=LCD Display S39 00=LCD Display S38 00=LCD Display S37 0=LCD Display S36 0=LCD Display S35 00=LCD Display S34 00=LCD Display S33 00=LCD Display S32 00=LCD Display S31 00=LCD Display S30 00=LCD Display S29 00=LCD Display S28 00=LCD Display S27 00=LCD Display S26 00=LCD Display S25 00=LCD Display S24 00=LCD Display S23 00=LCD Display S22 00=LCD Display S21 00=LCD Display S20 00=LCD Display S19 00=LCD Display S18 BIT SETTINGS PER FUNCTION 10=LED-SI-BLANK 10=LED-SI- STROBE 10=LED-SI- STROBE 10=LED-SI- CLK 1=OUT 12.4 1=OUT 12.3 10=OUT 12.2 10=OUT 12.1 10=OUT 12.0 01=LED Display DIG 7 01=LED Display DIG 6 01=LED Display DIG 5 01=LED Display DIG 4 01=LED Display DIG 3 01=LED Display DIG 2 01=LED Display DIG 1 01=LED Display SEG DP3 01=LED Display SEG G3 01=LED Display SEG F3 01=LED Display SEG E3 01=LED Display SEG D3 01=LED Display SEG C3 01=LED Display SEG B3 10=OUT 9.2 10=OUT 11.3 10=OUT 11.2 10=OUT 11.1 10=OUT 11.0 10=OUT 10.0 11=OUT 13.3 11=OUT 13.2 11=OUT 13.1 11=OUT 13.0 NOTES SI = Serial Interface CLK = Clock DIG = Digit SEG = Segment DP = Decimal Point Revision B Page 62 July, 2002 CybraTech (2000) Ltd. SOC-3000/i Scale-On-Chip ASIC Technical Specification PLCC-84 PIN 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 REG ADD. BIT 3-2 1-0 00=LCD Display S17 00=LCD Display S16 00=LCD Display S15 00=LCD Display S14 00=LCD Display S13 00=LCD Display S12 00=LCD Display S11 00=LCD Display S10 00=LCD Display S9 00=LCD Display S8 00=LCD Display S7 00=LCD Display S6 00=LCD Display S5 00=LCD Display S4 00=LCD Display S3 00=LCD Display S2 00=LCD Display S1 BIT SETTINGS PER FUNCTION 01=LED Display SEG A3 01=LED Display SEG DP2 01=LED Display SEG G2 01=LED Display SEG F2 01=LED Display SEG E2 01=LED Display SEG D2 01=LED Display SEG C2 01=LED Display SEG B2 01=LED Display SEG A2 01=LED Display SEG DP1 01=LED Display SEG G1 01=LED Display SEG F1 01=LED Display SEG E1 01=LED Display SEG D1 01=LED Display SEG C1 01=LED Display SEG B1 01=LED Display SEG A1 10=OUT 6.2 10=OUT 6.1 10=OUT 6.0 10=OUT 5.2 10=OUT 5.1 10=OUT 5.0 10=OUT 8.1 11=OUT 8.0 11=OUT 7.3 11=OUT 7.2 11=OUT 7.1 11=OUT 7.0 11=OUT 6.3 10=OUT 9.1 10=OUT 9.0 11=OUT 8.3 11=OUT 8.2 NOTES C107H 7-6 5-4 3-2 1-0 C108H 7-6 5-4 3-2 1-0 C109H 7-6 5-4 3-2 1-0 C10AH 5-4 3-2 1-0 Revision B Page 63 July, 2002 CybraTech (2000) Ltd. SOC-3000/i Scale-On-Chip ASIC Technical Specification PLCC-84 PIN 21 20 19 18 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 74 REG ADD. C10BH BIT 6-5 4-3 2 1-0 00=BP4 00=BP3 0=BP2 00=BP1 FFH 0=I.O 15.7 0=I.O 15.6 0=I.O 15.5 0=I.O 15.4 0=I.O 15.3 0=I.O 15.2 0=I.O 15.1 0=I.O 15.0 0=I.O 14.7 0=I.O 14.6 0=I.O 14.5 0=I.O 14.4 0=I.O 14.3 0=I.O 14.2 0=I.O 14.1 0=I.O 14.0 1=KIN0 1=KIN1 1=KIN2 1=KIN3 1=KIN4 1=KIN5 1=KIN6 1=KIN7 01=VPP BIT SETTINGS PER FUNCTION 10=OUT 4.3 10=OUT 4.2 NOTES BP = Backplane 1=OUT 4.1 10=OUT 4.0 Must be always 0xFF KIN = Keyboard In I.O = Input/Output C10CH C10DH 7-0 7 6 5 4 3 2 1 0 C10EH 7 6 5 4 3 2 1 0 1=KOUT0 1=KOUT1 1=KOUT2 1=KOUT3 1=KOUT4 1=KOUT5 1=KOUT6 1=KOUT7 KOUT = Keyboard Out Revision B Page 64 July, 2002 CybraTech (2000) Ltd. SOC-3000/i Scale-On-Chip ASIC Technical Specification SPECIAL FUNCTION REGISTERS (SFR) The SOC-3000/i includes Special Function Registers (SFR) that enable the device hardware controllers and reset them. Each controller description details its specific SFR operation. This section details all the SFR registers and functions. All these registers are mapped as XDATA memory area. Global Configuration Register Register 0C100H is used as a general enable/disable of pin allocation to all the hardware controllers in the SOC-3000/i. Upon power-up or reset this register is cleared, disabling all the hardware controllers. Writing 0xFF to the register activates the allocation of pins to hardware controller, as defined by programming the CFR registers. TABLE 33: GLOBAL CFR REGISTER ADDRESS C100H FUNCTION Enable / Disable pin allocation REMARKS 0x00 – Enable 0xFF - Disable Operation 1. Upon power-up or reset, the Global CFR register is set, disabling all pin allocation to the hardware controllers. 2. Initialize the CFR registers according to the required hardware configuration as described in section “ Revision B Page 65 July, 2002 CybraTech (2000) Ltd. SOC-3000/i Scale-On-Chip ASIC Technical Specification Configuration Registers (CFR)” page 61. 3. Initialize the hardware controllers. 4. Enable the Global CFR Register: Write 0x00 to address C100H. Controllers Clock Enable Register Register C200H controls the clock source to the hardware controllers in the SOC-3000/i. Each controller operation may be disabled by inhibiting its clock. TABLE 34: CLOCK ENABLE REGISTER ADDRESS C200H BIT 7 ADC BIT 6 0 BIT 5 SLED BIT 4 0 BIT 3 WDT BIT 2 KBD BIT 1 PLED BIT 0 (LSB) LCD Revision B Page 66 July, 2002 CybraTech (2000) Ltd. SOC-3000/i Scale-On-Chip ASIC Technical Specification TABLE 35: CONTROLLERS CLOCK ENABLE REGISTER BIT FUNCTIONS BIT 0 (LSB) 1 2 3 4 5 6 7 NAME LCD PLED KBD W DT SLED AD TYPE R ead- Write FUNCTION Enable LCD display controller clock SETTINGS 0 = Disable 1 = Enable 0 = Disable 1 = Enable 0 = Disable 1 = Enable 0 = Disable 1 = Enable Always 0. 0 = Disable 1 = Enable Always 0. 0 = Disable 1 = Enable R ead-Write Enable parallel LED display controller clock R ead-Write Enable keyboard controller clock R ead-Write Enable watch-dog timer clock R ead-Write None. Set always to 0. R ead-Write Enables serial LED display controller R ead-Write None. Set always to 0. R ead-Write Enables ADC controller clock Controllers RESET Registers The SFRs listed in Table 36 provides the mechanism to reset the hardware controllers of the SOC-3000/i. TABLE 36: CONTROLLERS RESET REGISTER ADDRESS C400H C401H C402H C403H C406H TYPE FUNCTION SETTINGS 0xFF = Reset 0xFF = Reset 0xFF = Reset 0xFF = Reset 0xFF = Reset Write only Keyboard controller reset Write only LCD display controller reset Write only Parallel LED display controller reset Write only Serial LED display controller reset Write only ADC controller reset Revision B Page 67 July, 2002 CybraTech (2000) Ltd. SOC-3000/i Scale-On-Chip ASIC Technical Specification Revision B Page 68 July, 2002 CybraTech (2000) Ltd. SOC-3000/i Scale-On-Chip ASIC Technical Specification I/O OPERATION I/O operation is determined by the configuration registers (CFR) programming. The I/O ports are composed of two groups: • Byte-Oriented Output Ports – Data written to the port is byte oriented (writing FFH to the port will set it to HIGH, and writing 00H to the port will set it to LOW). • Bit-Oriented Input/Output (I/O) Ports – Data written to the port is byte oriented (FFH–to set the port, 00H–to reset the port). Data read from the port is bit-oriented (only the port allocated bit is set/reset). Table 44, the I/O ports groups, addresses and corresponding PLCC-84 pins are described in Table 37 and Table 38. TABLE 37: BIT-ORIENTED I/O PORTS ADDRESSES, PIN AND BIT ASSIGNMENT PLCC-84 PIN I/O PORT NAME PORT ADDRESS F22A F22B F22C F22D F22E F22F F230 F231 F232 F233 F234 F235 F236 F237 F238 F239 BIT ASSIGNMENT (LSB) 0000000x 000000x0 00000x00 0000x000 000x0000 00x00000 0x000000 x0000000 0000000x 000000x0 00000x00 0000x000 000x0000 00x00000 0x000000 x0000000 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 74 I.O 15.7 I.O 15.6 I.O 15.5 I.O 15.4 I.O 15.3 I.O 15.2 I.O 15.1 I.O 15.0 I.O 14.7 I.O 14.6 I.O 14.5 I.O 14.4 I.O 14.3 I.O 14.2 I.O 14.1 I.O 14.0 TABLE 38: BYTE-ORIENTED OUTPUT PORTS ADDRESSES AND PIN ASSIGNMENT PLCC-84 PIN 61 60 59 I/O FUNCTION OUT 13.3 OUT 13.2 OUT 13.1 PORT ADDRESS F205 F206 F207 Revision B Page 69 July, 2002 CybraTech (2000) Ltd. SOC-3000/i Scale-On-Chip ASIC Technical Specification PLCC-84 PIN 58 57 56 55 54 53 52 51 50 49 48 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 I/O FUNCTION OUT 13.0 OUT 12.4 OUT 12.3 OUT 12.2 OUT 12.1 OUT 12.0 OUT 11.3 OUT 11.2 OUT 11.1 OUT 11.0 OUT 10.0 OUT 9.2 OUT 9.1 OUT 9.0 OUT 8.3 OUT 8.2 OUT 8.1 OUT 8.0 OUT 7.3 OUT 7.2 OUT 7.1 OUT 7.0 OUT 6.3 OUT 6.2 OUT 6.1 OUT 6.0 OUT 5.2 OUT 5.1 OUT 5.0 OUT 4.3 OUT 4.2 OUT 4.1 OUT 4.0 PORT ADDRESS F208 F209 F20A F20B F20C F20D F20E F20F F210 F211 F212 F213 F214 F215 F216 F217 F218 F219 F21A F21B F21C F21D F21E F21F F220 F221 F222 F223 F224 F225 F226 F227 F228 Revision B Page 70 July, 2002 CybraTech (2000) Ltd. SOC-3000/i Scale-On-Chip ASIC Technical Specification 8051-COMPATIBLE ON-CHIP PERIPHERALS This section describes the standard 8051 peripheral devices available to the user. These functions are fully compatible with the standard 8051 CPUs and are controlled via the standard 8051 Special Function Registers (SFRs). Parallel I/O Ports Some of the parallel I/O ports of the 80C51TBO core are available on the SOC-3000 pins. Most of the ports are already allocated to specific functions. However, the application design may require allocating different functions to these pins. Table 39 list the available pins, 80C51 I/O port, default function and special precaution needed when changing the function of the pin. TABLE 39: AVAILABLE PINS ON THE 80C51 I/O PORT PIN # 7 8 9 14 15 16 80C51 PORT P1.7 P1.5 P1.4 P3.4 / Timer 0 P3.5 / Timer 1 P1.6 DEFAULT FUNCTION Buzzer None None None None None SPECIAL PRECAUTIONS After power-up the SOC-3000 asserts 3 pulses on this pin Used in CybraTech application for power-off control in low-power applications Used in CybraTech application for detecting power source (AC/Battery) Used in CybraTech application to control LCD electro-luminescent backlight operation The I/O ports are controlled and accessible using the 80C51TBO Special Function Registers as described in its device specification. Timers/Counters The 80C51 Timers/Counters external inputs are available for use on SOC-3000 pin #14 (Timer 0) and pin #15 (Timer 1). Using the timers is via the 80C51 Special Function Registers (SFRs) as described in the 80C51TBO specification. Revision B Page 71 July, 2002 CybraTech (2000) Ltd. SOC-3000/i Scale-On-Chip ASIC Technical Specification Revision B Page 72 July, 2002 CybraTech (2000) Ltd. SOC-3000/i Scale-On-Chip ASIC Technical Specification SOC-3000 INITIALIZATION At power-up or after RESET the SOC-3000 performs the following procedures: • Disabling all the peripheral controllers of the ASIC. • Setting the CFR and control registers to their default values. • Start the boot program (ROM mask in the chip) that checks if the chip is programmed or not. If the chip is programmed it starts running the program starting at address 1000H. Otherwise, it toggles the buzzer signal (pin 7) HIGH/LOW three times to signal that the chip is erased and waits for software download via the serial communication port. To initialize the SOC-3000: 1. Program the SOC-3000 pin configuration in the CFR registers. • For general pin configuration for an LCD display, refer to Table 1, page 9. For a quick reference, refer to Table 4, page 18. • For general pin configuration for a LED display, refer to Table 2, page 12. For a quick reference, refer to Table 5, page 19. • For CFR bit assignment, refer to Table 32, page 62. For examples of CFR bit assignment, refer to “Example of Pin Configuration Programming”, on page 85. 2. Initialize the peripheral controllers used by the application. 3. Write 0x00 to the global CFR register at address C100H. This activates all CFR registers and completes SOC-3000 initialization. Revision B Page 73 July, 2002 CybraTech (2000) Ltd. SOC-3000/i Scale-On-Chip ASIC Technical Specification SOC-3000 HARDWARE DESIGN CONSIDERATIONS AND PERIPHERAL INTERFACE CONNECTIONS Load Cell Interface The SOC-3000 supports a wide range of load-cell connection configurations, each based on various combinations of the following connection options: • 4-wire or 6-wire interface • Up to eight load cells connected in parallel • Load cell impedance range of 350 to 1000 ohms Individually and in combination, these connection options enable the SOC-3000 to function on a wide range of application platforms, each having different power consumption and system configuration requirements, while using the same electronic hardware. 4-Wire and 6-Wire Interfaces The SOC-3000 interface to the load cell carries the following electrical signals: • SIG + (Signal Input +) • SIG – (Signal Input –) • SEN + (Excitation voltage / Sense input +) • SEN – (Excitation voltage / Sense input –) A typical 4-wire load-cell connection, in which the distance between the load cells and the SOC-3000 chip is small, as in a standard retail scale, is shown in Figure 26. However, in platforms requiring long wires between the load cell and the electronic hardware, such as weighing bridges, the voltage drop over the cables is significant and affects accuracy. The 6-wire interface eliminates this error factor by using the sense wires, as shown in Figure 27. The sense wires serve as a reference for the ADC converter, thus eliminating the voltage drop over the long excitation-voltage wires. Revision B Page 75 July, 2002 CybraTech (2000) Ltd. SOC-3000/i Scale-On-Chip ASIC Technical Specification Load Cell Cable (4-Wires) Regulated 5V Reg. Unregulated Power 73 AVcc 72 SEN + 71 SIG + 70 SIG 69 SENAGND 68 SOC-3000 FIGURE 26: 4-WIRE LOAD-CELL CONNECTION Load Cell Cable (6-Wires) Regulated 5V Sense Wire 73 AVcc 72 SEN + 71 SIG + 70 SIG 69 SENAGND 68 Unregulated Power Reg. SOC-3000 Sense Wire AGND FIGURE 27: 6-WIRE LOAD-CELL CONNECTION Revision B Page 76 July, 2002 CybraTech (2000) Ltd. SOC-3000/i Scale-On-Chip ASIC Technical Specification Load Cells Connected in Parallel The SOC-3000 may be connected to up to eight load cells connected in parallel. Multiple load cells are required in heavy load applications, such as weigh bridges, that require from two to eight load cells. Load cells connected in parallel typically result in lower output impedance, which decreases in direct proportion to the number of load cells. This results in a higher excitation current and higher sensitivity to factors that throw load cells out of balance. The SOC-3000 eliminates this problem with its high Common Mode Rejection Ratio (CMRR), which allows the connection of a large number of load cells (up to eight) without losing measurement accuracy. The multiple load-cell connection is shown in Figure 28. IMPORTANT The load cells should be matched before connecting them to the SOC-3000 to ensure the same initial offset, span and impedance. This will eliminate error factors that are beyond the control of SOC-3000 electronics. NOTE These large weighing platforms may also require a 6-wire interface connection, as described above, on page 75. LO AD Cells Connection Regulated 5V 73 AVcc ( ) Output JUNCTION BOX * Trimming 72 SEN + 71 SIG + 70 SIG - Up to 8 Load Cells ( ) Zero Offset SOC-3000 * Trimming 69 SENAG ND 68 AGND FIGURE 28: MULTIPLE LOAD-CELL CONNECTION Revision B Page 77 July, 2002 CybraTech (2000) Ltd. SOC-3000/i Scale-On-Chip ASIC Technical Specification Load Cell Impedance Most load cells have output impedance of 350 ohms. However, in power-restricted applications, load cells of higher impedance, typically a 1000-ohm bridge, are used to reduce the cell’s power consumption. The SOC-3000 CMRR minimizes the error resulting from this high bridge impedance and ensures full and accurate performance under this limiting condition. The result is economical power consumption without sacrificing weighing accuracy. Keyboard Interface The SOC-3000 supports direct connection of a keyboard of up to 64 keys arranged in an 8 × 8 matrix. The hardware interface with an example of a scale keyboard is shown in Figure 29. The keyboard controller (“Keyboard Controller”, page 31) automatically scans the matrix by asserting a high signal on the output lines (KOUT 0 to 7) and reading the input lines (KIN 0 to 7). The key hardware code, which is the code returned by the keyboard controller when the key is pressed, is shown in Figure 12, page 31. The keyboard controller has a programmable anti-bounce mechanism, in which different delays can be programmed to avoid erroneous key activation due to bouncing of the keys. The delay can be set to a discrete value from 4 to 18 milliseconds, in two-millisecond increments. For programming the anti-bounce mechanism, see Table 14, page 32. Scale Keyboard KOUT7 / 7 4 1 * 8 5 2 0 W S X 9 6 3 Enter E D C + ± % = ◊ R F V F1 F2 F3 F4 Bsp F5 F6 F7 F8 Esc Y H N CM M+ O U J M CE MR P I K L KOUT6 KOUT5 KOUT4 KOUT3 . Q A Z KOUT2 T G B KOUT1 KOUT0 74 75 76 77 78 79 80 81 82 KIN7 83 KIN6 84 KIN5 1 KIN4 2 KIN3 3 KIN2 4 KIN1 5 KIN0 PIN # Signal FIGURE 29: KEYBOARD INTERFACE Revision B Page 78 July, 2002 CybraTech (2000) Ltd. SOC-3000/i Scale-On-Chip ASIC Technical Specification LCD Display Interface The SOC-3000 interface supports LCD displays as follows: • Up to four backplanes, each driving 40 LCD segments • Static, 1/2-bias and 1/3-bias display options • Electro-luminescent (EL) lighting control The hardware interface is shown in Figure 30. The SOC-3000 is equipped with bias generators with voltage-followers buffers that generate the LCD bias voltages and backplane multiplexing signals. Thus, LCD displays can be directly connected to the SOC-3000 without any external component. LCD DISPLAY Backplane Multiplexer 1 2 3 4 1 2 Segment Inputs 40 PIN # Signal 18 19 20 21 22 23 61 S40 (Up to 4 Backplanes) (Up to 40 Segments) SOC-3000 FIGURE 30: LCD DISPLAY INTERFACE Revision B Page 79 July, 2002 CybraTech (2000) Ltd. SOC-3000/i Scale-On-Chip ASIC Technical Specification LED Display Interface The SOC-3000 interface supports LED displays as follows: • Up to 21 digits each comprising eight segments–seven-segment digit plus Decimal Point (DP) • Three digit groups, Weight, Price, and Total • Automatic hardware refresh mechanism to reduce power consumption The hardware interface is shown in Figure 31. The LED display is directly connected to the SOC-3000 with the addition of only the LED display drivers. Pin 46 . . . . . Pin 52 Digit Driver (ULN2003) HiCurrent Drivers (DY9953) Pin 22 . . . . . Pin 45 A3-G3,DP3 A2-G2,DP2 A1-G1,DP1 Segment Drivers (ULN2003) 8 8 8 FIGURE 31: LED PARALLEL DISPLAY INTERFACE External Interrupt Sources External interrupt sources may be connected to the SOC-3000 using the following pins: a. Vdet / INT0~. b. P3.4 / Timer-counter 0 input. c. P3.5 / Timer-counter 1 input. Using the Vdet input: The Vdet input is connected to INT0 of the 80C51TBO core. In battery-operated equipment this input is connected to the battery voltage divider and used to detect low battery voltage. Revision B Page 80 July, 2002 CybraTech (2000) Ltd. SOC-3000/i Scale-On-Chip ASIC Technical Specification Other interrupt sources may be connected to this input using open-collector drivers operating in negative logic mode (‘0’ is active interrupt). A low voltage input triggers the INT0. The application software applies a mechanism to determine whether the interrupt was generated by low battery voltage or by other interrupt source. Using Timer0 and Timer1 inputs: SOC-3000 pin #14 is connected to the 80C51 Timer 0 input and pin #15 is connected to Timer1 input. These inputs may be used for counting or timer operations, or as additional interrupt inputs to the device. Using these inputs as interrupt inputs requires that the appropriate timer be set to 0xFE. The next event causes the counter to increase to 0xFF and triggers the Timer 0 (or timer 1) interrupt. I2C-Compatible Interface The SOC-3000 may supports a 2-wire I2C compatible serial interface. The I2C-compatible interface shares its pins with the CPU I/O pins (P1.4, P1.5) and is implemented in software. Table 40 provides the hardware interface information: TABLE 40: I2C-COMPATIBLE INTERFACE HARDWARE INTERFACE PIN# 8 9 NAME SDATA SCLOCK Serial Data I/O pin Serial Clock pin DESCRIPTION Power Saving Schemes SOC-3000/i provides several means for power saving for battery-operated systems: a. Set the CPU to IDLE or POWERDOWN operating modes – see detailed description in the M8051TBO Technical Specification, Power Management section. b. Disable unused hardware controllers – by disabling the controller clock via the “Controllers Clock Enable Register (C200H)”, see tables 33 and 34. c. Reduce the CPU frequency to minimum while idle by using the Frequency Controller. The CPU frequency may be increased on the fly to 16MHz when an interrupt or an event occurred. d. Switch the power to the load cell using the I/O pins of the SOC and an external switch. Revision B Page 81 July, 2002 CybraTech (2000) Ltd. SOC-3000/i Scale-On-Chip ASIC Technical Specification Grounding and Board Layout Recommendations As with all high-resolution data converters, special attention must be paid to grounding and to the PCB layout of SOC-3000 based designs in order to achieve optimum performance from the Analog-To-Digital Converter. Four-layer boards are recommended where the outer layers are ground layers covering the whole surface, and the inner layers are used for routing the signal lines. The same ground plane should be used for both the digital and analog grounds. Keep all ground connection as short as possible. Make sure that the return paths of the signals are as close as possible to the paths that the currents took to reach their destinations. Avoid digital signals flowing under the analog components area. Wherever possible, avoid large discontinuities in the ground plane, since they force the return signals to travel on a longer path. An example of correct implementation is routing all signals through the inner layers and keeping the outer layers for ground. If you plans to connect fast logic signals (rise/fall time < 5ns) to any of the SOC-3000 digital inputs, add a series resistor to each relevant line in order to keep rise and fall times longer than 5ns at the SOC-3000 input pins. A value of 100 Ω or 200 Ω is usually sufficient to prevent high-speed signals from capacitive coupling into the SOC-3000 and affecting the accuracy of the ADC. Revision B Page 82 July, 2002 CybraTech (2000) Ltd. SOC-3000/i Scale-On-Chip ASIC Technical Specification IN-CIRCUIT EMULATOR (ICE) SYSTEM The In-Circuit Emulator (ICE-3000) system provides full emulation of the SOC-3000 device. It includes a plug-in pod that replaces the SOC-3000 device thus enabling full emulation of the device in the target board. It emulates the SOC-3000 device in real-time simplifying the hardware-software integration process. The ICE-3000 is composed of 3 elements: a. DS-51 emulator. b. SOC-3000 Personality Probe. c. Windows-based software debugger. The system enables you to access all SOC-3000 device registers and memory locations and debug the application using free run or breakpoints and single step execution control. Revision B Page 83 July, 2002 CybraTech (2000) Ltd. SOC-3000/i Scale-On-Chip ASIC Technical Specification Revision B Page 84 July, 2002 CybraTech (2000) Ltd. SOC-3000/i Scale-On-Chip ASIC Technical Specification EXAMPLES OF PIN CONFIGURATION PROGRAMMING The following pages show examples of pin configuration programming, as follows: • Example 1 shows a 20-digit LCD display and an 8×8 keyboard. • Example 2 shows a 16-digit LCD display, an 8×4 keyboard, 8 output ports and 4 I/O ports. • Example 3 shows a 21-digit LED Parallel display, an 8×8 keyboard and 13 output ports. • Example 4 shows the pin programming for all output and I/O ports. Example 1: Configuring a 20-digit LCD Display and an 8x8 Keyboard • 20-digit LCD display support implies allocation of the whole LCD driver output pins to the LCD display, using 4 backplanes and 40 segments. Thus, pins 18-61 should be assigned to the LCD controller/driver. • 8x8 keyboard support implies allocation of the whole keyboard I/O pins to the keyboard controller. Thus, pins 1-5 and 74-84 should be assigned to the keyboard controller. Table 41 lists the CFR registers affected and their required values. TABLE 41: EXAMPLE 1: 20-DIGIT LCD DISPLAY, 8×8 KEYBOARD FUNCTION LCD Display CFR REGISTER ADDRESS & VALUE C101H = 00H C102H = 00H C103H = 00H C104H = 00H C105H = 00H C106H = 00H C107H = 00H C108H = 00H C109H = 00H C10AH = 00H C10BH = 00H C10DH = FFH C10EH = FFH PORT / SEGMENT S37 – S40 S32 – S36 S28 – S31 S24 – S27 S20 – S23 S16 – S19 S12 – S15 S8 – S11 S4 – S7 S1 – S3 BP1 – BP4 KIN0 – KIN7 KOUT0 – KOUT7 AFFECTED PINS 58 – 61 53 – 57 49 – 52 45 – 48 41 – 44 37 – 40 33 – 36 29 – 32 25 – 28 22 – 24 18 – 21 1 – 5; 82 – 84 74 – 81 Keyboard Matrix Revision B Page 85 July, 2002 CybraTech (2000) Ltd. SOC-3000/i Scale-On-Chip ASIC Technical Specification Example 2: Configuring a 16-digit LCD Display, an 8x4 Keyboard, 8 Output and 4 I/O Ports • 16-digit LCD display support implies partial allocation of the LCD driver output pins to the LCD display, using 4 backplanes and 32 segments. Thus, pins 18-52 should be assigned to the LCD controller/driver. • 8x4 keyboard support implies partial allocation of the keyboard I/O pins to the keyboard controller. Thus, pins 1-5 and 78-84 should be assigned to the keyboard controller. • 8 output ports will be implemented using the 8 pins of the LCD driver that are not used for the display. Thus, pins 53-61 should be assigned as Output ports. • 4 I/O ports will be implemented using the 4 pins of the keyboard input matrix that are not used by the keyboard. Thus, pins 74-77 should be assigned as I/O ports. Table 42 lists the CFR registers affected and their required values. TABLE 42: EXAMPLE 2: 16-DIGIT LCD DISPLAY, 8×4 KEYBOARD, 8 OUTPUT, 4 I/O FUNCTION LCD Display CFR REGISTER ADDRESS & VALUE C102H = E8H C103H = 00H C104H = 00H C105H = 00H C106H = 00H C107H = 00H C108H = 00H C109H = 00H C10AH = 00H C10BH = 00H C10DH = FFH C10EH = F0H C101H = FFH C102H = E8H C10E = F0H PORT / SEGMENT S32 S28 – S31 S24 – S27 S20 – S23 S16 – S19 S12 – S15 S8 – S11 S4 – S7 S1 – S3 BP1 – BP4 KIN0 – KIN7 KOUT4 – KOUT7 P13.0 – P13.3 P12.1 – P12.4 KOUT4 – KOUT7 P14.0 – P14.3 AFFECTED PINS 53 49 – 52 45 – 48 41 – 44 37 – 40 33 – 36 29 – 32 25 – 28 22 – 24 18 – 21 1 – 5; 82 – 84 78 – 81 58 –61 54 – 57 78 – 81 74 – 77 Keyboard Matrix Output Ports I/O Ports Revision B Page 86 July, 2002 CybraTech (2000) Ltd. SOC-3000/i Scale-On-Chip ASIC Technical Specification Example 3: Configuring a 21-digit LED Parallel Display, an 8x8 Keyboard and 13 Output Ports • 21-digit LED parallel display support implies full allocation of the LED parallel display controller output pins to the LED parallel display. Thus, pins 22-52 should be assigned to the LED parallel display controller. • 8x8 keyboard support implies full allocation of the keyboard I/O pins to the keyboard controller. Thus, pins 1-5 and 74-84 should be assigned to the keyboard controller. • 13 output ports will be implemented using the available OUTPUT ports available in the ASIC. Thus, pins 53-61 should be assigned as Output ports. Table 43 lists the CFR registers affected and their required values. TABLE 43: EXAMPLE 3: 21-DIGIT LED DISPLAY, 8×8 KEYBOARD, 13 OUTPUT FUNCTION LED Display CFR REGISTER ADDRESS & VALUE C103H = 55H C104H = 55H C105H = 55H C106H = 55H C107H = 55H C108H = 55H C109H = 55H C10AH = 15H C10DH = FFH C10EH = FFH C101H = FFH C102H = EAH C10BH = 56H PORT / SEGMENT DIG4 – 7 SEG DP3; DIG1 - 3 SEG D3 – G3 SEG DP2; A3 – C3 SEG D2 – G2 SEG DP1; A2 – C2 SEG D1 – G1 SEG A1 – C1 KIN0 – KIN7 KOUT0 – KOUT7 P13.0 – P13.3 P12.0 – P12.4 P4.0 – P4.3 AFFECTED PINS 49 – 52 45 – 48 41 – 44 37 – 40 33 – 36 29 – 32 25 – 28 22 – 24 1 – 5; 82 – 84 74 – 81 58 –61 53 – 57 18 – 21 Keyboard Matrix Output Ports Revision B Page 87 July, 2002 CybraTech (2000) Ltd. SOC-3000/i Scale-On-Chip ASIC Technical Specification Example 4: Outputs and I/O Ports Programming • • Output ports support implies full allocation of the LCD display controller output pins to the OUTPUT function. Thus, pins 18-61 should be assigned to the OUTPUT controller. I/O ports support implies full assignment of the Keyboard controller pins to the I/O ports. Thus, pins 1 – 5 and 74 – 84 should be assigned to the I/O controller. TABLE 44: OUTPUT AND I/O PORTS PROGRAMMING FUNCTION OUTPUT ports CFR REGISTER ADDRESS & VALUE C101H = FFH C102H = EAH C103H = AAH C104H = 80H C106H = 2AH C107H = FCH C108H = FFH C109H = EAH C10AH = 2AH C10BH = 56H C10DH = 00H C10EH = 00H PORT / SEGMENT P13.0 – P13.4 P12.0 – P12.4 P11.0 – P11.3 P10.0 P9.0 – P9.2 P8.0 – P8.3 P7.0 – P7.3 P6.0 – P6.3 P5.0 – P5.2 P4.0 – P4.3 P15.0 – P15.7 P14.0 – P14.7 AFFECTED PINS 58 – 61 53 - 57 49 – 52 48 37 – 39 33 – 36 29 – 32 25 – 28 22 – 24 18 - 21 1 – 5; 82 - 84 74 - 81 I/O Ports Revision B Page 88 July, 2002 USA Tedea-Huntleigh Incorporated 20630 Plummer Street Chatsworth, California 91311 U.S.A. Tel: +1-818-701-2700 Fax: +1-818-701-2799 Email: sales@tedea-huntleigh.com UK Tedea-Huntleigh Europe Ltd. 37 Portmanmoor Road Cardiff CF24 5HE United Kingdom Tel: +44 (0) 29-20460231 Fax: +44 (0) 29-20462173 Email: sales@tedea-huntleigh.co.uk Germany Tedea-Huntleigh GmbH Mümlingweg 18 D-64297 Darmstadt-Eberstadt Germany Tel:+49-6151-94460 Fax:+49-6151-944640 France SEEA sa. 16 Rue Francis Vovelle 28000 Chartres France Tel: +33-2-37-33-31-20 Fax: +33-2-37-33-31-29 Taiwan Integrated Solutions Ltd. Tel: +886-2-2649-7254 Fax: +886-2-2649-7253 CybraTech (1998) Ltd. 5a Hazoran St., PO Box 8381 Netanya, 42506 ISRAEL Tel: +972-9-8638832 Fax: +972- 9-8638822 Email: info@cybratech.co.il Website: www.cybratech.com Document order number: SOC-3000-0001-SP