SPFD54126B-C

Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd w 528-channel 6-bit Source Driver with System-on-chip for Color Amorphous TFT-LCDs w w .m bt re SPFD54126B nd .co Preliminary NOV. 20, 2006 Version 0.2 Contact ORISE Technology to ORISE Technology reserves the right to change this documentation without prior notice. Information provided by ORISE Technology is believed to be accurate and reliable. However, ORISE Technology makes no warranty for any errors which may appear in this document. obtain the latest version of device specifications before placing your order. No responsibility is assumed by ORISE Technology for any infringement of patent or other rights of third parties which may result from its use. In addition, ORISE products are not authorized for use as critical components in life support devices/ systems or aviation devices/systems, where a malfunction or failure of the product may reasonably be expected to result in significant injury to the user, without the express written approval of ORISE. m Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B Table of Contents PAGE TABLE OF CONTENTS .......................................................................................................................................................................................... 2 1. GENERAL DESCRIPTION .......................................................................................................................................................................... 6 2. FEATURE .................................................................................................................................................................................................... 6 3. ORDERING INFORMATION........................................................................................................................................................................ 6 4. BLOCK DIAGRAM ...................................................................................................................................................................................... 7 4.1. BLOCK FUNCTION .................................................................................................................................................................................. 7 4.1.1. System Interface ....................................................................................................................................................................... 8 4.1.2. External Display Interface ......................................................................................................................................................... 8 4.1.5. Grayscale Voltage Generating Circuit....................................................................................................................................... 8 4.1.6. Timing Controller....................................................................................................................................................................... 8 4.1.7. Oscillator (OSC) ........................................................................................................................................................................ 8 4.1.8. Source Driver Circuit................................................................................................................................................................. 8 4.1.9. Gate Driver Circuit .................................................................................................................................................................... 9 6. INSTRUCTIONS ........................................................................................................................................................................................ 15 6.1.1. System Function Command List and Description ................................................................................................................... 15 6.1.2. Panel Function Command List and Description...................................................................................................................... 18 6.2.1. NOP (00h) ............................................................................................................................................................................... 23 6.2.2. SWRESET (01h): Software Reset .......................................................................................................................................... 24 6.2.3. RDDID (04H): Read Display ID............................................................................................................................................... 25 6.2.4. RDDST (09H): Read Display Status ....................................................................................................................................... 26 6.2.5. RDDPM (0AH): Read Display Power Mode............................................................................................................................ 28 6.2.6. RDDMADCTR (0BH): Read Display MADCTR....................................................................................................................... 29 6.2.7. RDDCOLMOD (0CH): Read Display Pixel Format ................................................................................................................. 30 6.2.8. RDDIM (0DH): Read Display Image Mode ............................................................................................................................. 31 6.2.9. RDDSM (0EH): Read Display Signal Mode ............................................................................................................................ 32 6.2.10. 6.2.11. 6.2.12. 6.2.13. 6.2.14. 6.2.15. 6.2.16. 6.2.17. 6.2.18. 6.2.19. 6.2.20. RDDSDR (0FH): Read Display Self-Diagnostic Result ...................................................................................................... 33 SLPIN (10H): Sleep In ........................................................................................................................................................ 34 SLPOUT (11H): Sleep Out ................................................................................................................................................. 36 PTLON (12H): Partial Display Mode On............................................................................................................................. 38 NORON (13H): Normal Display Mode On .......................................................................................................................... 39 INVOFF (20H): Display Inversion Off ................................................................................................................................. 40 INVON (21H): Display Inversion On ................................................................................................................................... 41 GAMSET (26H): Gamma Set ............................................................................................................................................. 42 DISPOFF (28H): Display Off .............................................................................................................................................. 43 DISPON (29H): Display On ................................................................................................................................................ 45 CASET (2AH): Column Address Set .................................................................................................................................. 47 © ORISE Technology Co., Ltd. Proprietary & Confidential w 6.2. SYSTEM COMMAND DESCRIPTION ........................................................................................................................................................ 23 w w 6.1. OUTLINE .............................................................................................................................................................................................. 15 .m 5. SIGNAL DESCRIPTIONS.......................................................................................................................................................................... 10 bt 2 4.1.10. LCD Driving Power Supply Circuit........................................................................................................................................ 9 re nd .co 4.1.4. Graphics RAM (GRAM) ............................................................................................................................................................ 8 m 4.1.3. Address Counter (AC)............................................................................................................................................................... 8 NOV. 20, 2006 Preliminary Version: 0.2 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.2.21. 6.2.22. 6.2.23. 6.2.24. 6.2.25. 6.2.26. 6.2.27. 6.2.28. 6.2.29. 6.2.30. 6.2.31. 6.2.32. 6.2.33. 6.2.34. 6.2.35. 6.2.36. 6.2.37. 6.2.38. 6.2.39. 6.2.40. 6.2.41. RASET (2BH): Row Address Set........................................................................................................................................ 49 RAMWR (2CH): Memory Write........................................................................................................................................... 51 RGBSET (2DH): Colour Setting ......................................................................................................................................... 53 RAMHD (2EH): Memory Read ........................................................................................................................................... 54 PTLAR (30H): Partial Area ................................................................................................................................................. 55 SCRLAR (33H): Scroll Area................................................................................................................................................ 58 TEOFF (34H): Tearing Effect Line OFF.............................................................................................................................. 62 TEON (35H): Tearing Effect Line ON ................................................................................................................................. 63 MADCTR (36H): Memory Data Access Control.................................................................................................................. 64 VSCSAD (37H): Vertical Scroll Start Address of RAM ....................................................................................................... 66 IDMOFF (38H): Idle Mode Off ............................................................................................................................................ 68 IDMON (39H): Idle Mode On .............................................................................................................................................. 69 RDID1 (DAH): Read ID1 Value........................................................................................................................................... 72 RDID2 (DBH): Read ID2 Value........................................................................................................................................... 73 RDID3 (DCH): Read ID3 Value .......................................................................................................................................... 74 SRGBOFF (ABH): Separate RGB Gamma ON.................................................................................................................. 76 VSYNCOFF (ACH): VSYNC Interface OFF ....................................................................................................................... 77 VSCTR1 (AEH): VSYNC Interface function control 1......................................................................................................... 79 6.3.1. RGBCTR (B0H): RGB signal control ...................................................................................................................................... 80 6.3.2. FRMCTR1 (B1h): Frame Rate Control (In normal mode/ Full colors)..................................................................................... 81 6.3.4. FRMCTR3 (B3h): Frame Rate Control (In Partial mode/ full colors)....................................................................................... 85 6.3.5. INVCTR (B4h): Display Inversion Control............................................................................................................................... 87 6.3.6. RGBBPCTR (B5h): RGB Interface Blanking Porch setting..................................................................................................... 88 6.3.7. DISSET5 (B6h): Display Function set 5.................................................................................................................................. 89 6.3.8. PWCTR1 (C0H): Power Control 1 .......................................................................................................................................... 91 6.3.9. PWCTR2 (C1H): Power Control 2 .......................................................................................................................................... 93 6.3.10. 6.3.11. 6.3.12. 6.3.13. 6.3.14. 6.3.15. 6.3.16. 6.3.17. 6.3.18. 6.3.19. 6.3.20. 6.3.21. 6.3.22. 6.3.23. PWCTR3 (C2H): Power Control 3 (in Normal mode/ Full colors)....................................................................................... 94 PWCTR4 (C3H): Power Control 4 (in Idle mode/ 8-colors) ................................................................................................ 96 PWCTR5 (C4H): Power Control 5 (in Partial mode/ full-colors) ......................................................................................... 98 VMCTR1 (C5H): VCOM Control 1.................................................................................................................................... 100 VMCTR2 (C6H): VCOM Control 2.................................................................................................................................... 102 RDVMOF (C8H): Read the VCOM Offset Value NV memory .......................................................................................... 104 WRID2 (D1h): Write ID2 Value ......................................................................................................................................... 105 WRID3 (D2h): Write ID3 Value ......................................................................................................................................... 106 RDID4 (D3h): Read the ID4 value .................................................................................................................................... 107 NVFCTR1 (D9h): NV Memory Function Controller 1 ....................................................................................................... 108 NVFCTR2 (DEh): NV Memory Function Controller 2 ........................................................................................................110 NVFCTR3 (DFh): NV Memory Function Controller 3 ........................................................................................................111 GMCTRP1 (E0H): Gamma (‘+’polarity for Red color) Correction Characteristics Setting.................................................112 GMCTRN1 (E1H): Gamma (‘-’polarity for Red color) Correction Characteristics Setting .................................................114 3 NOV. 20, 2006 Preliminary Version: 0.2 © ORISE Technology Co., Ltd. Proprietary & Confidential w 6.3.3. FRMCTR2 (B2h): Frame Rate Control (In Idle mode/ 8-colors) ............................................................................................. 83 w w 6.3. PANEL COMMAND DESCRIPTION ........................................................................................................................................................... 80 .m VSYNCON (ADH): VSYNC Interface ON ........................................................................................................................... 78 bt re SRGBOFF (AAH): Separate RGB Gamma OFF ................................................................................................................ 75 nd .co COLMOD (3AH): Interface Pixel Format ............................................................................................................................ 71 m Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.3.24. 6.3.25. 6.3.26. 6.3.27. GMCTRP2 (E2H): Gamma (‘+’polarity) for Green color Correction Characteristics Setting .............................................116 GMCTRN2 (E3H): Gamma (‘-’polarity) for Green color Correction Characteristics Setting ..............................................118 GMCTRP3 (E4H): Gamma (‘+’polarity) for Blue color correction Characteristics Setting ................................................ 120 GMCTRN3 (E5H): Gamma (‘-’polarity) for Blue color Correction Characteristics Setting................................................ 122 7. FUNCTION DESCRIPTION ..................................................................................................................................................................... 124 7.1. MCU & RGB INTERFACE ................................................................................................................................................................... 124 7.2. MPU INTERFACE ............................................................................................................................................................................... 126 7.2.1. Interface Type Selection........................................................................................................................................................ 126 7.2.2. 8080-Series Parallel interface(P68=’0’) ................................................................................................................................ 126 7.2.3. 6800-Series Parallel Interface (P68=’1’) ............................................................................................................................... 129 7.2.4. Serial Peripheral interface (SPI) ........................................................................................................................................... 132 7.2.5. Data Transfer Break and Recovery....................................................................................................................................... 134 7.2.7. Data Transfer Modes ............................................................................................................................................................ 137 7.3. MCU DATA COLOUR CODING ............................................................................................................................................................. 138 7.3.1. MCU Data Colour Coding for RAM data Write ...................................................................................................................... 138 7.3.3. Serial Interface (IM2 = ‘0’)..................................................................................................................................................... 154 7.4. RGB INTERFACE ................................................................................................................................................................................ 157 7.4.2. General Timing Diagram ....................................................................................................................................................... 158 7.4.5. RGB Interface Mode Set....................................................................................................................................................... 161 7.4.6. RGB Interface Timing Diagram ............................................................................................................................................. 162 7.4.7. RGB Data Color Coding........................................................................................................................................................ 173 7.5. DISPLAY DATA RAM ........................................................................................................................................................................... 176 7.5.1. Configuration......................................................................................................................................................................... 176 7.5.2. Memory to Display Address Mapping ................................................................................................................................... 177 7.5.3. Normal Display On or Partial Mode On, Vertical Scroll Off ................................................................................................... 180 7.5.4. Vertical Scroll Mode .............................................................................................................................................................. 183 7.5.5. Vertical Scroll Example ......................................................................................................................................................... 185 7.6. ADDRESS COUNTER........................................................................................................................................................................... 186 7.7. MEMORY DATA WRITE/ READ DIRECTION ............................................................................................................................................ 187 7.8. TEARING EFFECT OUTPUT LINE .......................................................................................................................................................... 189 7.8.1. Tearing Effect Line Modes .................................................................................................................................................... 189 7.8.2. Tearing Effect Line Timings ................................................................................................................................................... 190 7.8.3. Example 1: MPU Write is faster than panel read. ................................................................................................................. 191 7.8.4. Example 2: MPU write is slower than panel read. ................................................................................................................ 192 7.9. PRESET VALUES ................................................................................................................................................................................ 193 7.10. POWER ON/OFF SEQUENCE ............................................................................................................................................................. 193 7.10.1. 7.10.2. 7.10.3. Case 1 – RESX Line is held High or Unstable by Host at Power On ............................................................................... 193 Case 2 – RESX Line is Held Low by Host at Power On................................................................................................... 194 Uncontrolled Power Off .................................................................................................................................................... 194 7.11. POWER LEVEL DEFINITION ................................................................................................................................................................. 195 © ORISE Technology Co., Ltd. Proprietary & Confidential 4 NOV. 20, 2006 Preliminary Version: 0.2 w w 7.4.4. RGB Interface Bus Width set ................................................................................................................................................ 161 w 7.4.3. Updating Order on Display Active Area (Normal Display Mode On + Sleep Out)................................................................. 159 .m 7.4.1. General Description .............................................................................................................................................................. 157 bt re 7.3.2. MCU Data Colour Coding for RAM data Read ..................................................................................................................... 149 nd .co 7.2.6. Data Transfer Pause ............................................................................................................................................................. 136 m Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 7.11.1.Power Level .......................................................................................................................................................................... 195 7.11.2.Power Flow Chart ................................................................................................................................................................. 196 7.12. GAMMA CURVES ................................................................................................................................................................................ 197 7.13. RESET ............................................................................................................................................................................................... 198 7.13.1. 7.13.2. 7.13.3. Reset Value ...................................................................................................................................................................... 198 Module Input/Output Pins ................................................................................................................................................. 201 Reset Timing..................................................................................................................................................................... 202 7.14. COLOUR DEPTH CONVERSION LOOK UP TABLES ................................................................................................................................. 203 7.14.1. 4096 and 65536 Colour to 262,144 Colour ...................................................................................................................... 203 7.15. SLEEP OUT-COMMAND AND SELF-DIAGNOSTIC FUNCTIONS OF THE DISPLAY MODULE .......................................................................... 207 7.15.1. 7.15.2. 7.15.3. 7.15.4. Register Loading Detection .............................................................................................................................................. 207 Functionality Detection ..................................................................................................................................................... 208 Display Glass Break Detection ......................................................................................................................................... 210 7.16. OSCILLATOR .......................................................................................................................................................................................211 7.17. SYSTEM COLCK GENERATOR ..............................................................................................................................................................211 7.19. SOURCE DRIVER.................................................................................................................................................................................211 7.20. GATE DRIVER .....................................................................................................................................................................................211 7.21. Γ-CORRECTION FUNCTION .......................................................................................................................................................... 212 8.1. DC CHARACTERISTICAC CHARACTERISTIC (VDD=2.6V~3.0V, VDDIO = 1.6V~3.0V, TA = -40℃ ~ 85℃) ......................................... 216 8.2. AC TIMING CHARACTERISTICS ............................................................................................................................................................ 217 8.2.1. Parallel Interface Characteristics 18, 16 ,9 or 8-bits bus (8080-series MCU) ....................................................................... 217 8.3. PARALLEL INTERFACE CHARACTERISTICS 18, 16 ,9 OR 8-BITS BUS (6800-SERIES MCU) ...................................................................... 219 8.4. SERIAL INTERFACE CHARACTERISTICS (3-PIN SERIAL)......................................................................................................................... 220 9. PAD LOCATIONS ................................................................................................................................................................................... 221 9.1. PAD ASSIGNMENT ............................................................................................................................................................................. 221 9.2. PAD LOCATIONS ................................................................................................................................................................................ 222 9.3. WIRING RESISTANCE.......................................................................................................................................................................... 229 10. DISCLAIMER........................................................................................................................................................................................... 231 10. REVISION HISTORY............................................................................................................................................................................... 232 © ORISE Technology Co., Ltd. Proprietary & Confidential w w 8. ELECTRICAL SPECIFICATIONS ........................................................................................................................................................... 216 w 7.22. VSYNC INTERFACE ........................................................................................................................................................................... 212 .m 7.20.1. Gate Driver ........................................................................................................................................................................211 bt 5 re 7.18. INSTRUCTION DECODER AND REGISTER ...............................................................................................................................................211 nd .co Chip Attachment Detection ............................................................................................................................................... 209 m NOV. 20, 2006 Preliminary Version: 0.2 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 528-CHANNEL DRIVER WITH SYSTEM-ON-CHIP (SOC) FOR COLOR AMORPHOUS TFT LCD 1. GENERAL DESCRIPTION The SPF54126B, a 262144-color System-on-Chip (SoC) driver LSI designed for small and medium sizes of TFT LCD display, is capable of supporting up to 176xRGBx220 in resolution which can be achieved by the designated RAM for graphic data. The 528-channel source driver has true 6-bit resolution, which generates 64 Gamma-corrected values by an internal D/A converter. The source driver of SPFD54126B adopts OP-AMP structure to enhance display quality and it cooperates with advanced circuitry techniques to reduce power consumption. The SPFD54126B is able to operate with low IO interface power supply up to 1.6V and incorporate with several charge pumps to generate various voltage levels that form an on-chip power management system for gate driver and common driver. System interfaces − High-speed interfaces to 8-, 9-, 16-, and 18-bit parallel ports − Serial Peripheral Interface (SPI) Interfaces for moving picture display − 6-, 16-, and 18-bit RGB interfaces Diverse RAM accessing for functional display − Window address function to display at any area on the screen via a moving picture display interface − Window address function to limit the data rewriting area and reduce data transfer − Moving and still picture can display at the same time − Vertical scrolling function − Partial screen display Power supply − Logic power supply voltage (VDD): 2.6 ~ 3.5 V − I/O interface supply voltage (VDDI): 1.6 ~ 3.6 V On-chip power management system − Power saving mode (standby / 8-color mode, etc) − Low power consumption OP-AMP structure for source driver. Built-in Charge Pump circuits − Source driver voltage level : 2 times (x2) of Vci1 − Gate driver voltage level (VGH, VGL) up to 6 times (x6) and minus 5 times (x-5) Vci1 Built-in internal oscillator and hardware reset Built–in One-Time-Programming (OTP) function for VCOM amplitude and VcomH voltage adjustment. Built-in separate three-gamma curves (RGB) controller to fine tune display quality. The built-in timing controller in SPFD54126B can support several display. SPFD54126B provides system interfaces, which include to configure system. Not only can the system interfaces be used to configure system, they can also access RAM at high speed for still and 18-bit RGB interfaces for picture movement display. The SPFD54126B also supports a function to display eight colors and a standby mode for power control consideration. picture display. In addition, the SPFD54126B incorporates 6, 16, 2. FEATURE One-chip solution for amorphous TFT-LCD. Supports resolution up to 176xRGBx220, incorporating a 528-channel source driver and a 220-channel gate driver Outputs 64 γ -corrected values using an internal true 6-bit resolution D/A converter to achieve 262K colors 528-channel source driver adopts OP-AMP structure Built-in 87120 bytes internal RAM Line Inversion AC drive / frame inversion AC drive w w w 8-/9-/16-/18-bit parallel interfaces and 9-bit serial interface (SPI), .m interfaces for the diverse request of medium or small size portable bt re nd .co 6 3. ORDERING INFORMATION Product Number SPFD54126B-C Package Type Chip Form With Gold Bump © ORISE Technology Co., Ltd. Proprietary & Confidential m NOV. 20, 2006 Preliminary Version: 0.2 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 4. BLOCK DIAGRAM 4.1. Block Function S1 P68 DCX/SCL SDA IM[2:0] CSX RDX WRX S2 S527 S528 OTP Memory System Interface 6 Source Driver (528 channels) True 6-bit D/A Converter 6 6 6 Level Shifter (528 x 6bits) LUT D[17:0] DE PCLK VS HS 18 18 w TE RESX EXTC IDM GM[1:0] LCM[1:0] RCM[1:0] SRGB SMX SMY SHUT REV RL TB nd .co RGB Interface Graphics RAM 87120 bytes 6 6 6 6 Data Latch (176 x 3 x 6bits x2) m Shift Register (176 bits) 64 AVDD Gamma Voltage Generator GVDD re bt VDD VREF w Timing Signal Generator .m Regulator VCI1 VCOMH w VCI1 C11P/N C12P/N Gate Power Charge Pump AVDD VCOM VCOM VCOML VGL CLK VDDI Clock Generator C21P/N C22P/N C23P/N VGH Gate Driver VCL G[220:1] © ORISE Technology Co., Ltd. Proprietary & Confidential 7 NOV. 20, 2006 Preliminary Version: 0.2 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 4.1.1. System Interface The SPFD54126B supports three high-speed system interfaces: 1. 80-system high-speed interfaces with 8-, 9-, 16-, 18-bit parallel ports. 2. 68-system high-speed interfaces with 8-, 9-, 16-, 18-bit parallel ports. 3. 3-pin 9-bits Serial Peripheral Interface (SPI). The SPFD54126B has a 16-bit index register (IR) and two 18-bit data registers, a write-data register (WDR) and a read-data register (RDR). The IR register is used to store index information from control registers. The WDR register is used to temporarily store data to be written for register control and internal GRAM. The RDR register is used to temporarily store data read from the GRAM. When graphic data is written to the internal GRAM from MCU/graphic engine, the data is first written to the WDR and then automatically written to the internal GRAM in internal operation. When graphic data read operation is executed, graphic data is read via the RDR from the internal GRAM. Therefore, the SPFD54126B executes the 2 read operation. nd 4.1.2. External Display Interface The SPFD54126B supports external RGB interface for picture movement display. optimum interface is selected for still / moving picture displayed on the screen. The SPFD54126B allows switching between one of the external display interfaces and the system interface via pin configuration so that the When the RGB interface is chosen, display operations are synchronized with external supplied signals, VSYNC, HSYNC, and DOTCLK. SPFD54126B features an Address Counter (AC) giving an address to the internal GRAM. The address in the AC is automatically updated plus or minus 1. The window address function enables writing data only in the rectangular area arbitrarily set by users on the GRAM. 4.1.4. Graphics RAM (GRAM) SPFD54126B features a 87120-byte (176 x 220x 18/8) Graphic RAM (GRAM). 4.1.5. Grayscale Voltage Generating Circuit SPFD54126B has true 6-bit resolution D/A converter, which generates 64 Gamma-corrected values and cooperates with OP-AMP structure to enhance display quality. The grayscale voltage can be adjusted by grayscale data set in the γ-correction register. “γ-Correction Function” section. For details, see the 4.1.6. Timing Controller SPFD54126B has a timing controller which can generate a timing signal for internal circuit operation such as gate output timing, RAM accessing timing, etc. 4.1.7. Oscillator (OSC) The SPFD54126B also features an internal oscillator to generate RC oscillation with an internal resistor. In standby mode, RC oscillation is halted to reduce power consumption. See “Oscillator” for details. 4.1.8. Source Driver Circuit SPFD54126B consists of a 528-output source driver circuit (S1 ~ S528). Data in the GRAM are latched when the 528 bit data is input. th The latched data controls the source driver and generates a drive waveform. © ORISE Technology Co., Ltd. Proprietary & Confidential w w w 4.1.3. Address Counter (AC) .m Moreover, valid display data (DB17-0) is written to GRAM, which synchronized with signal (DE) enabling. bt 8 re nd .co m invalid data is first read out to the data bus when the SPFD54126B executes the 1 read operation. st Thus, valid data can be read out after NOV. 20, 2006 Preliminary Version: 0.2 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 4.1.9. Gate Driver Circuit SPFD54126B consists of a 220-output gate driver circuit (G1~G220). The gate driver circuit outputs gate driver signals at either VGH or VGL level. 4.1.10. LCD Driving Power Supply Circuit The LCD driving power supply circuit generates the voltage levels AVDD, VGH, VGL and VCOM for driving an LCD. All this voltages can be adjusted by register setting. © ORISE Technology Co., Ltd. Proprietary & Confidential w w w .m 9 bt re nd .co m NOV. 20, 2006 Preliminary Version: 0.2 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 5. SIGNAL DESCRIPTIONS Signal Pin No. I/O Connected with Function System Configuration Input Signal P68, IM2~0 4 I DGND/ VDDI Select system interface mode. P68 0 0 0 0 0 1 1 1 1 1 IM2 0 1 1 1 1 0 1 1 IM1 0 0 1 1 0 0 IM0 0 1 0 1 3-Pin Serial interface 8080 MCU 8-bits Parallel interface 8080 MCU 16-bits Parallel interface 8080 MCU 9-bits Parallel interface 8080 MCU 18-bits Parallel interface 3-Pin Serial interface 6800 MCU 8-bits Parallel interface 6800 MCU 16-bits Parallel interface 6800 MCU 9-bits Parallel interface 6800 MCU 18-bits Parallel interface Must connect to the GND or VDDI level when not used. RESX 1 I MPU or external RC circuit EXTC 1 I DGND/ VDDI Reset pin. This is an active low signal. w GM1~0 2 I DGND/ VDDI w w .m Extend command set access Low: Extend command set is not accessible. High: Extend command set is accessible. If this is not used. Open it (This pin is internally pull low). Resolution selection: GM1 0 0 1 1 GM0 0 1 0 1 Resolution 176*RGB*220 176*RGB*176 Reserved 176*RGB*132 RCM1~0 2 I DGND/ VDDI Interface selection: RCM1 0 0 1 1 RCM0 0 1 0 1 Interface MCU Interface MCU Interface RGB Interface RGB Interface IDM 1 I MCU In RGB interface mode: (a) Low: Normal Display. (b) High: Idle Mode (8-color mode). This pin can be only used when RGB mode is selected. LCM 2 I DGND/ VDDI Liquid Crystal Type selection: LCM1 0 0 LCM0 0 1 LC type selection Normally black type1 Normally white type1 © ORISE Technology Co., Ltd. Proprietary & Confidential bt 10 re nd .co 1 1 1 0 1 1 1 m 0 - Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B Signal Pin No. I/O Connected with Function 1 1 0 1 Normally black type2 Normally white type2 SRGB 1 I DGND/ VDDI RGB arrangement selection: RGB 0 0 1 1 SRGB 0 1 0 1 RGB filter order for CF default setting S1, S2, S3 fit ‘R’, ‘G’, ‘B S1, S2, S3 fit ‘B’, ‘G’, ‘R S1, S2, S3 fit ‘B’, ‘G’, ‘R S1, S2, S3 fit ‘R’, ‘G’, ‘B The RGB is the D4 for Command 36H (a) Low: Display On. (b) High: Display Off. REV 1 I DGND/ VDDI This pin can be only used when RGB mode is selected. Data reverse for source driver selection when RGB mode is selected. (a) Low: Reverse Off. (b) High: Reserve On. SMX 1 I DGND/ VDDI This pin can be only used when RGB mode is selected. Source driver output direction selection: SMX 0 1 Source output direction S1 => S528 S528=>S1 w SMY 1 I DGND/ VDDI w .m Gate driver output direction selection: SMY 0 1 GM=”00” G1 =>G220 G220=>G1 GM=”01” G1=>G176 G176=>G1 GM=”11” G1=>G132 G132=>G1 RL 1 I w DGND/ VDDI Source driver output direction selection: SMX 0 0 1 1 RL 0 1 0 1 Source output direction S1 => S528 S528 => S1 S528 => S1 S1 => S528 This pin can be only used when RGB mode is selected. TB 1 I DGND/ VDDI Gate driver output direction selection: SMY 0 0 1 1 TB 0 1 0 1 GM=”00” G1 =>G220 G220 =>G1 G220 =>G1 G1 =>G220 GM=”01” G1=>G176 G176 =>G1 G176 =>G1 G1=>G176 GM=”11” G1=>G132 G132=>G1 G132=>G1 G1=>G132 This pin can be only used when RGB mode is selected. Interface input Signals CSX 1 I MPU Chip select signal. Low: the SPFD54126B is accessible © ORISE Technology Co., Ltd. Proprietary & Confidential 11 Apr. 25, 2006 Preliminary Version: 0.1 bt re nd .co m SHUT 1 I DGND/ VDDI Display on/off selection when RGB mode is selected. Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B Signal Pin No. I/O Connected with Function High: the SPFD54126B is not accessible This pin has can be permanently fixed “Low” in MCU interface mode only. D/CX (SCL) 1 I MPU Display data / Command selection pin in parallel interface Low: Command data High: Display data In SPI I/F, this is used as SCL pin. Must connect to the GND or VDDI level when not used. WRX (R/WX) 1 I MPU (A) In 80-system interface mode, a write strobe signal can be input via this pin and initializes a write operation when the signal is low. (B) In 68-system interface mode, a write or read control signal can be input via Must connect to the GND or VDDI level when not used. RDX (E) 1 I MPU (A) In 80-system interface mode, a read strobe signal can be input via this pin and initializes a read operation when the signal is low. (B) In 68system interface mode, a strobe signal can be input via this pin and initializes a write or read operation when the signal is low. SPI_CSX 1 I MPU Must connect to the GND or VDDI level when not in use. (A) When RCM [1:0] = ‘01’ Chip select pin for SPI (Low active) (B) When RCM [1:0] = ‘00’ or ‘1X’ this pin and initializes a write or read operation. w w SCL 1 I MPU w SDA 1 I/O MPU DB0-DB17 2*18 I/O MPU VS HS DE 1 1 1 I I I MPU MPU MPU © ORISE Technology Co., Ltd. Proprietary & Confidential .m If not used, please fix this pin at VDDI or DGND level. (A) When RCM [1:0] = ‘01’ Serial clock signal pin for SPI (B) When RCM [1:0] = ‘00’ or ‘1X’ If not used, please fix this pin at VDDI or DGND level. (A) When RCM [1:0] = ‘01’ or ‘1X’ Serial input/ output signal in serial I/F mode. The data is input on the rising edge of the SCL signal. The data is output on the falling edge of the SCL signal. (B) When RCM [1:0] = ‘00’ If not used, please fix this pin at VDDI or DGND level. (A) When RCM [1:0] = ‘1X’ (RGB I/F), D[17:0] are used for RGB interface data bus (B) When RCM [1:0] = ‘00’ (MCU I/F), D[17:0] are used to MCU parallel interface data bus In SPI I/F, D0 is used as Serial input/ output signal. In SPI I/F, D[17:1] not used, please fix this pin at VDDI or DGND level. (C) When RCM [1:0] = ‘01’ (MCU I/F), D[17:0] are used for MCU interface data bus In SPI I/F, D[17:0] not used, please fix this pin at VDDI or DGND level. In RGB I/F or VSYNC I/F mode, served as a vertical synchronize signal input Must connect to the VDDI or DGND level when not in use. In RGB I/F mode, served as a horizontal synchronized signal input Must connect to the VDDI or DGND level when not in use. In RGB I/F mode, polarity of DE signal is synchronized with valid graphic data input. High: Valid data on DB17-DB0 Low: Invalid data on DB17-DB0 12 Apr. 25, 2006 Preliminary Version: 0.1 bt This pin is not used, and fix at VDDI or DGND level. This pin is not used, and fix at VDDI or DGND level. This pin is not used, and fix at VDDI or DGND level. re nd .co m Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B Signal Pin No. I/O Connected with Function Must connect to the VDDI or DGND level when not in use. PCLK 1 I MPU In RGB I/F mode, served as a pixel clock signal. Must connect to the VDDI or DGND level when not in use. Charge Pump and Power Supply Signal C11P/N, C12P/N C21P/N, C22P/N C23P/N VCI1 4/4 4/4 3/3 3/3 3/3 5 O Stabilizing capacitor AVDD VGH VGL VCL VCC 6 3 3 3 5 5 4 O O O O O O I/O Stabilizing capacitor Stabilizing capacitor Stabilizing capacitor Stabilizing capacitor Stabilizing capacitor VREF GVDD Stabilizing capacitor An internal reference voltage level, which is regulated from VDD. The GND. amplitude of VCI1 is from VDD-GND. Place a stabilizing capacitor between Output 2x VCI1 voltage level from the step-up circuit 1. Place a stabilizing capacitor between GND. AVDD = 4.5 ~ 5.5V An output voltage from the step-up circuit 2x, 4x ~ 6x of the VCI1 level. Connect with a stabilizing capacitor. Connect with a stabilizing capacitor. An output voltage from the step-up circuit 2, –1x of the VCI1 level. Connect with a stabilizing capacitor. An output voltage from the step-up circuit –2x, -3x ~ -5x of the VCI1 level. Step-up capacitor Connect boost capacitors for the internal DC/DC converter circuit to these pins. Leave the pins open when DC/DC converter circuits are not used. w w w Stabilizing capacitor Source/Gate Driver and VCOM Signals G1~G220 S1~S528 220 528 O O O LCD LCD TFT panel common electrode VcomH VcomL 4 4 O O Stabilizing capacitor Stabilizing capacitor or open VDDIO DGNDO VDD VDDI 5 10 10 8 12 O O I I Stabilizing capacitor Stabilizing capacitor DGND Digital ground pin. 13 Apr. 25, 2006 Preliminary Version: 0.1 Power supply Input for I/O system VDDI input voltage for control pins using DGND input voltage for control pins using Power supply Input for analog and booster system Output the low level of VCOM voltage. Connect with a capacitor to stabilize. Output gate driver signals, which has the swing from VGH to VGL Output source driver signals. The D/A converted 64-gray-scale analog voltage is output. VCOM 6 Output a square wave signal with the swing from VcomH - VcomL to the common electrode of TFT panel. The alternating cycle can be set to frame inversion or 1-line inversion. Output the high level of VCOM voltage. Connect with a capacitor to stabilize. © ORISE Technology Co., Ltd. Proprietary & Confidential .m Reference voltage for Internal logic block Connect with a stabilizing capacitor Reference voltage for power block Connect with a stabilizing capacitor. Output source driver grayscale reference voltage level. bt re nd .co m Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B Signal AGND Misc. Signal DRV FB TE 2 1 1 O I O MPU Drive signal for the power transistor of the LED booster converter LED booster regulator feedback input. Connect feedback resistive divider to GND. FB threshold is 0.6V normal. Tearing effect output pin to synchronies MCU to frame writing, activated by S/W command. When this pin is not activated (TE function OFF), this pin is DGND level. Power supply input for OTP function This pin is used for glass break detection This pin is used for glass break detection Pin No. 15 I/O Connected with Function Analog ground pin. VOTP PADA0 PADB0 PADA1/PADB1 PADA2/PADB2 PADA3/PADB3 PADA4/PADB4 TEST Dummy PREG OSC 2 1 1 8 I I O 18 22 1 1 T D D I Test pin. If not used, please open this pin. Dummy pin. If not used, please open this pin. If not used, please open this pin. © ORISE Technology Co., Ltd. Proprietary & Confidential w w w .m 14 bt External oscillator frequency input pin for oscillator testing re Dummy pin. If not used, please open this pin. nd .co m This pin is used for chip attachment detection Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6. INSTRUCTIONS 6.1. Outline The SPFD54126B supports 18-bit data bus interface to configure system via accessing command register. When the command register is executed, sending the command information to specify which index register would be accessed and following the data to that control register. Moreover, register accessing operation should cooperate with DC/X, WRX, RDX signal for SPFD54126B to recognize the control instruction. And command instruction can be accomplished using all system interfaces (18-bit, 16-bit, 9-bit, 8-bit 80- or 68-system and SPI).. 6.1.1. System Function Command List and Description Table 5.1.1 list all the system function command. After the H/W reset by RESX pin or S/W reset by SWRESET command, each internal register becomes default state (Refer “RESET TABLE” section). Commands 10h, 12h, 13h, 20h, 21h, 26h, 28h, 29h, 30h, 33h, 36h (ML parameter only), 37h, 38h and 39h are updated during V-sync when Module is in Sleep Out Mode to avoid abnormal visual effects. During Sleep In mode, these commands are updated immediately. Read status (09h), Read Display Power Mode (0Ah), Read Display MADCTR Diagnostic Result (0Fh) of these commands are updated immediately both in Sleep In mode and Sleep Out mode. (0Bh), Read Display Pixel Format (0Ch), Read Display Image Mode (0Dh), Read Display Signal Mode (0Eh) and Read Display Self Table 6.1.1 System Function command List (1) Instruction D/CX WRX RDX D17-8 NOP SWRESET 0 0 0 1 1 1 1 0 1 1 1 1 1 0 1 1 RDD MADCTR RDD COLMOD 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 ↑ ↑ ↑ 1 1 1 1 ↑ 1 1 1 1 1 ↑ 1 1 ↑ 1 1 ↑ 1 1 ↑ 1 1 ↑ 1 1 ↑ 1 1 1 1 1 ↑ ↑ ↑ ↑ 1 ↑ ↑ ↑ ↑ ↑ 1 ↑ ↑ 1 ↑ ↑ 1 ↑ ↑ 1 ↑ ↑ 1 ↑ ↑ 1 ↑ ↑ D7 0 0 0 D6 0 0 0 D5 0 0 0 D4 0 0 0 D3 0 0 0 - nd .co D2 0 0 1 D1 0 0 0 D0 0 1 0 D1 D0 m (Hex) RDDID RDDST RDDPM (00h) No Operation (01h) Software reset (04h) Read Display ID Dummy read ID17 ID16 ID15 ID14 ID13 ID12 ID11 ID10 ID1 read ID27 ID26 ID25 ID24 ID23 ID22 ID21 ID20 ID2 read ID37 ID36 ID35 ID34 ID33 ID32 ID31 ID30 ID3 read 0 0 0 0 1 0 0 1 (09h) Read Display Status Dummy read BSTON MY MX MV ML RGB ST25 ST24 ST23 IFPF2 IFPF1 IFPF0 IDMON PTLON SLOUT NORON VSSON ST14 INVON ST12 ST11 DISON TEON GCS2 GCS1 GCS0 TELOM HSON VSON PCKON DEON ST0 0 0 0 0 1 0 1 0 (0Ah) Read Display Power Mode Dummy read w w w .m bt re Function BSTON IDMON PTLON SLPOUT NORON DISON - RDDIM RDDSM RDDSDR (0Bh) Read Display MADCTR Dummy read MX MY MV ML RGB D2 D1 D0 0 0 0 0 1 1 0 0 (0Ch) Read Display Pixel Format Dummy read D7 D6 D5 D4 D3 IFPF2 IFPF1 IFPF0 0 0 0 0 1 1 0 1 (0Dh) Read Display Image Mode Dummy read VSSON D6 INVON D4 D3 GCS2 GCS1 GCS0 0 0 0 0 1 1 1 0 (0Eh) Read Display Signal Mode Dummy read TEON TELOM HSON VSON PCKON DEON D1 D0 0 0 0 0 1 1 1 1 (0Fh) Read Display Self-diagnostic result Dummy read RELD FUND ATTD BRD D3 D2 D1 D0 - 0 - 0 - 0 - 0 - 1 - 0 - 1 - 1 - “-“: Don＇t care, can be set to VDDI or DGND level © ORISE Technology Co., Ltd. Proprietary & Confidential 15 Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B Table 6.1.1 System Function command List (2) Instruction D/CX WRX RDX D17-8 SLPIN SLPOUT PTLON NORON INVOFF INVON GAMSET DISPOFF DISPON 0 0 0 0 0 0 0 1 0 0 0 1 1 1 1 0 1 1 1 1 0 1 0 1 1 0 1 1 1 1 1 1 1 1 1 ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ 1 1 ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ↑ ↑ 1 1 1 1 1 1 1 1 1 1 D17-8 D17-8 D7 0 0 0 0 0 0 0 GC7 0 0 0 XS15 XS7 XE15 XE7 0 YS15 YS7 YE15 YE7 0 D7 0 D7 0 R007 : Ra7 G007 : Gb7 B007 : Bc7 D6 0 0 0 0 0 0 0 GC6 0 0 0 XS14 XS6 XE14 XE6 0 YS14 YS6 YE14 YE6 0 D6 0 D6 0 R006 : Ra6 G006 : Gb6 B006 : Bc6 D5 0 0 0 0 1 1 1 GC5 1 1 1 XS13 XS5 XE13 XE5 1 YS13 YS5 YE13 YE5 1 D5 1 D5 1 R005 : Ra5 G005 : Gb5 B005 : Bc5 D4 1 1 1 1 0 0 0 GC4 0 0 0 XS12 XS4 XE12 XE4 0 YS12 YS4 YE12 YE4 0 D3 0 0 0 0 0 0 0 GC3 1 1 1 XS11 XS3 XE11 XE3 1 YS11 YS3 YE11 YE3 1 D2 0 0 0 0 0 0 1 GC2 0 0 0 XS10 XS2 XE10 XE2 0 YS10 YS2 YE10 YE2 1 D1 0 0 1 1 0 0 1 GC1 0 0 1 XS9 XS1 XE9 XE1 1 YS9 YS1 YE9 YE1 0 D1 1 D1 0 R001 : Ra1 G001 : Gb1 B001 : Bc1 D0 0 1 0 1 0 1 0 GC0 0 1 0 XS8 XS0 XE8 XE0 1 YS8 YS0 YE8 YE0 0 (Hex) (10h) (11h) (12h) (13h) (20h) (21h) (26h) Function Sleep in & booster off Sleep out & booster on Partial mode on Partial off (Normal) Display inversion off (normal) Display inversion on Gamma curve select (28h) Display off (29h) Display on (2Ah) Column address set X address start: 0 ≤ XS ≤ 0xAF X address end: XS ≤ XE ≤ 0xAF nd .co D2 1 D2 1 R002 : Ra2 G002 : Gb2 B002 : Bc2 CASET re D3 1 D3 1 R003 : Ra3 G003 : Gb3 B003 : Bc3 16 RASET bt D4 0 D4 0 R004 : Ra4 G004 : Gb4 B004 : Bc4 .m RAMWR RGBSET “-“: Don’t care, can be set to VDDI or DGND level © ORISE Technology Co., Ltd. Proprietary & Confidential w w w RAMHD D0 0 (2Eh) D0 1 (2Dh) R000 : Ra0 G000 : Gb0 B000 : Bc0 m (2Ch) (2Bh) Row address set Y address start: 0 ≤ YS ≤ 0xDB Y address end: YS ≤ YE ≤ 0xDB Memory write Write data Memory read Dummy read Read data LUT for 4k,65k , 262K color display Red tone 0 :Red tone “31” Green tone 0 :Green tone “63” Blue tone 0 :Blue tone “31” Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B Table 6.1.1 System Function command List (3) Instruction D/CX WRX RDX D17-8 0 1 1 1 1 0 1 1 1 1 1 1 0 0 1 0 1 0 1 1 0 0 0 1 0 1 1 0 1 1 0 1 1 0 0 0 0 0 1 ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ 1 1 ↑ 1 1 ↑ 1 1 ↑ ↑ ↑ ↑ ↑ ↑ 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ↑ ↑ 1 ↑ ↑ 1 ↑ ↑ 1 1 1 1 1 1 D7 0 D6 0 D5 1 D4 1 D3 0 D2 0 D1 0 D0 0 (Hex) Function (30h) Partial start/end address set PSL15 PSL14 PSL13 PSL12 PSL11 PSL10 PSL9 PSL8 Partial start address (0,1,2, .., 219) PSL7 PSL6 PSL5 PSL4 PSL3 PSL2 PSL1 PSL0 PEL15 PEL14 PEL13 PEL12 PEL11 PEL10 PEL9 PEL8 PEL7 PEL6 PEL5 PEL4 PEL3 PEL2 PEL1 PEL0 PTLAR Partial end address (0,1,2, .., 219) (33h) Scroll area set Top fixed area (0,1,2, .., 220) Vertical scroll area (0,1,2, ..,220) Bottom fixed area (0,1,2, ..,220) 0 0 1 1 0 0 1 1 TFA15 TFA14 TFA13 TFA12 TFA11 TFA10 TFA9 TFA8 TFA7 TFA6 TFA5 TFA4 TFA3 TFA2 TFA1 TFA0 VSA15 VSA14 VSA13 VSA12 VSA11 VSA10 VSA9 VSA8 VSA7 VSA6 VSA5 VSA4 VSA3 VSA2 VSA1 VSA0 BFA15 BFA14 BFA13 BFA12 BFA11 BFA10 BFA9 BFA8 BFA7 BFA6 BFA5 BFA4 BFA3 BFA2 BFA1 BFA0 SCRLAR TEOFF TEON MADCTR SSA7 SSA6 SSA5 SSA4 SSA3 SSA2 SSA1 SSA0 COLMOD RDID1 RDID3 SRGBOFF SRGBON VSUNCOFF VDUNCON VSCTRI w RDID2 w w .m bt 0 0 0 1 1 1 IDMOFF IDMON (38h) Idle mode off (39h) Idle mode on (3Ah) Interface pixel format IFPF2 IFPF1 IFPF0 0 0 0 0 0 Interface format 1 1 0 1 1 0 1 0 (DAh) Read ID1 Dummy read ID17 ID16 ID15 ID14 ID13 ID12 ID11 ID10 Read parameter 1 1 0 1 1 0 1 1 (DBh) Read ID2 Dummy read ID27 ID26 ID25 ID24 ID23 ID22 ID21 ID20 Read parameter 1 1 0 1 1 1 0 0 (DCh) Read ID3 Dummy read ID37 ID36 ID35 ID34 ID33 ID32 ID31 ID30 Read parameter 1 0 1 0 1 0 1 0 (AAh) Separate RGB γ function OFF 1 0 1 0 1 0 1 1 (ABh) Separate RGB γ function ON 1 1 1 0 0 0 1 1 1 1 1 1 0 0 1 0 1 0 0 0 0 0 0 0 1 1 1 1 1 1 re 1 1 1 0 0 0 17 VSCSAD (34h) Tearing effect line off (35h) Tearing effect mode set & on 0 0 0 0 0 0 0 TELOM M=”0”: Mode1, M=”1”: Mode2 0 0 1 1 0 1 1 0 (36h) Memory data access control MY MX MV ML RGB 0 0 0 0 0 1 1 0 1 1 1 (37h) Scroll start address of RAM SSA15 SSA14 SSA13 SSA12 SSA11 SSA10 SSA9 SSA8 SSA = 0, 1, 2, …, 219 VSFP3 VSFP2VSFP1VSFP0 VSBP3 VSBP2 VSBP1 VSBP0 “-“: Don’t care, can be set to VDDI or DGND level © ORISE Technology Co., Ltd. Proprietary & Confidential nd .co 0 0 1 0 1 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 0 1 m (ACh) VSYNC interace function OFF (ADh) VSYNC interace function ON (AEh) VSYNC interace control VS porch setting Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.1.2. Panel Function Command List and Description Table 6.1.2 list all the panel function command. Panel function command is only accessible when EXTC is pulled high state (by VDDIO). Table 6.1.2 Panel Function command List (1) Instruction D/CX WRX RDX D17-8 RGBCTR 0 1 0 1 FRMCTR1 1 1 0 1 FRMCTR2 1 1 0 1 FRMCTR3 1 1 INVCTR RGB PRCTR 0 1 0 1 0 1 1 ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 0 0 1 0 1 0 D7 1 0 1 D6 0 0 0 D5 1 0 1 D4 1 ICM 1 D3 0 DP D2 0 EP D1 0 D0 0 (Hex) Function (B0h) Set RGB signal control (B1h) In normal mode (Full colors) FP0: Front porch in normal mode BP0: Back porch in normal mode RTN0: Number of clock / one line HSP VSP ICM: RGB data ascess select DP,HSP,VSP:PCLK,HS,VS polarity set DISSET5 1 0 0 0 0 0 0 0 0 1 FP0 FP0 FP0 FP0 [3] [2] [1] [0] BP0 BP0 BP0 BP0 [3] [2] [1] [0] RTN0 RTN0 RTN0 RTN0 [3] [2] [1] [0] 1 1 0 0 1 0 FP1 FP1 FP1 FP1 [3] [2] [1] [0] BP1 BP1 BP1 BP1 [3] [2] [1] [0] RTN1 RTN1 RTN1 RTN1 [3] [2] [1] [0] 1 1 0 0 1 1 FP2 FP2 FP2 FP2 [3] [2] [1] [0] BP2 BP2 BP2 BP2 [3] [2] [1] [0] RTN2 RTN2 RTN2 RTN2 [3] [2] [1] [0] 1 1 0 1 0 0 0 0 0 NLA NLB NLC 1 1 0 1 0 1 VBP VBP VBP VBP [3] [2] [1] [0] 1 1 0 1 1 1 NO1 NO0 SDT1 STD0 EQ1 EQ0 nd .co PT0 m (B2h) In Idle mode (8-colors) FP1: Front porch in idle mode BP1: Back porch in idle mode RTN1: Number of clock / one line re 18 (B3h) In partial mode + Full colors FP2: Front porch in partial mode BP2: Back porch in partial mode RTN2: Number of clock / one line .m bt 0 w (B4h) Display inversion control NLA, NLB, NLC: set inversion w (B5h) RGB I/F Blanking porch setting Vertical back porch in RGB mode NO: the amount of non-overlap SDT: set amount of source delay PT: No display area source/ VCOM/ Gate output control EQ: set EQ period w (B6h) Display function setting 0 PTG1 PTG0 PT1 “-“: Don’t care, can be set to VDDI or DGND level © ORISE Technology Co., Ltd. Proprietary & Confidential Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B Table 6.1.2 Panel Function Command List (2) Instruction D/CX WRX RDX D17-8 PWCTR1 0 1 1 0 1 0 1 1 0 1 1 PWCTR5 0 1 1 0 1 0 1 1 0 1 ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ↑ ↑ D7 1 0 0 1 0 1 0 0 1 0 0 1 0 0 1 D6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D5 1 0 0 1 0 1 0 0 1 0 0 1 0 0 1 D4 D3 D2 D1 D0 (Hex) 1 0 0 0 0 VRH4 VRH3 VRH2 VRH1 VRH0 0 0 VC2 VC1 VC0 1 0 0 0 1 0 0 BT2 BT1 BT0 1 0 0 1 0 0 0 APA2 APA1 APA0 0 0 DCA2 DCA1 DCA0 1 0 0 1 1 0 0 APB2 APB1 APB0 0 1 0 0 1 0 0 0 0 0 DCB2 DCB1 DCB0 1 0 0 APC2 APC1 APC0 DCC2 DCC1 DCC0 1 0 1 Function (C0h) Power control setting VRH: Set the GVDD voltage VC : Set the VCI1 voltage Power control setting (C1h) BT: set AVDD/VCL/ VGH/ VGL voltage (C2h) n normal mode (Full colors) PWCTR2 PWCTR3 PWCTR4 VMCTR1 nVM VMH6 VMH 5 VMH4 VMH3 VMH2 VMH1 VMH0 1 0 1 nVM 0 0 1 1 0 nd .co 1 1 0 D2 0 0 D1 0 1 D0 1 0 1 1 1 1 0 1 APA: adjust the operational amplifier DCA: adjust the booster circuit for Idle mode (C3h) In Idle mode (8-colors) APB: adjust the operational amplifier DCB: adjust the booster circuit for Idle mode I (C4h) In partial mode + Full colors APC: adjust the operational amplifier DCC: adjust the booster circuit for Idle mode (C5h) VCOM control 1 nVM: VCOM input select VMH: VCOMH voltage control m (C6h) (Hex) nVM VMF6 VMF5 VMF4 VMF3 VMF2 VMF1 VMF0 “-“: Don’t care, can be set to VDDI or DGND level Instruction D/CX WRX RDX D17-8 WRID2 0 1 0 WRID3 1 0 1 1 1 1 1 0 0 NVCTR2 NVCTR3 1 0 1 ↑ ↑ ↑ ↑ ↑ 1 1 1 1 1 ↑ ↑ ↑ ↑ ↑ 1 1 1 1 1 ↑ ↑ ↑ ↑ ↑ 1 1 1 1 1 - w Table 6.1.2 Panel Function Command List (3) D7 1 1 1 w D6 1 1 .m D5 0 0 bt D4 1 1 D3 0 0 1 1 1 1 19 RVMOF CTR 0 1 1 1 0 0 0 (C8h) VCOM control 4 RVMF RVMF RVMF RVMF RVMF RVMF RVMF Read the VMOF value form NV memory 6 5 4 3 2 1 0 re VMCTR2 VMA5 VMA4 VMA3 VMA2 VMA1 VMA0 VCOM control 2 VMA: VCOMAC voltage control w Function (D1h) Panel version code ID26 ID25 ID24 ID23 ID22 ID21 ID20 ID37 ID36 ID35 ID34 ID33 ID32 ID31 ID30 Write ID2 value to NV memory Set the LCM version code at ID2 (D2h) Driver maker Project code Write ID3 value to NV memory Set the project code at ID3 IC Vender Coder Dummy read ID41:IC Vender Coder ID42: IC Part Number Coder ID43 & ID44: Chip version coder RDID4 NVCTR1 1 1 0 1 0 0 1 1 (D3h) ID417 ID416 ID415 ID414 ID413 ID412 ID411 ID410 ID427 ID426 ID425 ID424 ID423 ID422 ID421 ID420 ID437 ID436 ID435 ID434 ID43 ID432 ID431 ID430 ID447 ID446 ID445 ID444 ID443 ID442 ID441 ID440 1 1 0 1 1 0 0 1 (D9h) 1 1 1 1 0 0 NV memory function controller 1 Please refer to ‘OTP programming procedure’ for details. (DEh) NV memory function controller 2 Please refer to ‘OTP programming procedure’ for details. (DFh) NV memory function controller 3 Please refer to ‘OTP programming procedure’ for details. “-“: Don’t care, can be set to VDDI or DGND level © ORISE Technology Co., Ltd. Proprietary & Confidential Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B Table 6.1.2 Panel Function Command List (4) Instruction D/CX WRX RDX D17-8 D7 D6 0 1 1 1 1 1 1 1 ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 - D5 1 R_PVR1V1[5] R_PVR1V2[5] R_PVR1V61[5] R_PVR1V62[5] - D4 0 R_PVR1V0[4] R_PVR1V1[4] R_PVR1V2[4] R_PVR1V61[4] R_PVR1V62[4] R_PVR1V63[4] R_PVR2V13[4] R_PVR2V50[4] - D3 0 R_PVR1V0[3] R_PVR1V1[3] R_PVR1V2[3] R_PVR1V61[3] R_PVR1V62[3] R_PVR1V63[3] R_PVR2V13[3] R_PVR2V50[3] R_PVR3V4[3] R_PVR3V8[3] R_PVR3V20[3] R_PVR3V27[3] R_PVR3V36[3] R_PVR3V43[3] R_PVR3V55[3] R_PVR3V59[3] D2 0 R_PVR1V0[2] R_PVR1V1[2] R_PVR1V2[2] R_PVR1V61[2] R_PVR1V62[2] R_PVR1V63[2] R_PVR2V13[2] R_PVR2V50[2] R_PVR3V4[2] R_PVR3V8[2] R_PVR3V20[2] R_PVR3V27[2] R_PVR3V36[2] R_PVR3V43[2] R_PVR3V55[2] R_PVR3V59[2] D1 0 R_PVR1V0[1] R_PVR1V1[1] R_PVR1V2[1] R_PVR1V61[1] R_PVR1V62[1] R_PVR1V63[1] R_PVR2V13[1] R_PVR2V50[1] R_PVR3V4[1] R_PVR3V8[1] R_PVR3V20[1] R_PVR3V27[1] R_PVR3V36[1] R_PVR3V43[1] R_PVR3V55[1] R_PVR3V59[1] D0 0 R_PVR1V0[0] R_PVR1V1[0] R_PVR1V2[0] R_PVR1V61[0] R_PVR1V62[0] R_PVR1V63[0] R_PVR2V13[0] R_PVR2V50[0] R_PVR3V4[0] R_PVR3V8[0] R_PVR3V20[0] R_PVR3V27[0] R_PVR3V36[0] R_PVR3V43[0] R_PVR3V55[0] R_PVR3V59[0] (Hex) Function GAMCTRP1 1 1 1 1 1 1 1 1 1 R+ Gamma (E0h) adjustment “-“: Don’t care, can be set to VDDI or DGND level 0 1 1 1 1 1 1 1 ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 - 1 - 1 - .m Instruction D/CX WRX RDX D17-8 D7 D6 D5 1 - bt D4 0 Table 6.1.2 Panel Function Command List (5) re D3 0 R_NVR1V0[3] R_NVR1V1[3] R_NVR1V2[3] R_NVR1V61[3] R_NVR1V62[3] R_NVR1V63[3] R_NVR2V13[3] R_NVR2V50[3] R_NVR3V4[3] R_NVR3V8[3] R_NVR3V20[3] R_NVR3V27[3] R_NVR3V36[3] R_NVR3V43[3] R_NVR3V55[3] R_NVR3V59[3] nd .co D2 0 R_NVR1V0[2] R_NVR1V1[2] R_NVR1V2[2] R_NVR1V61[2] R_NVR1V62[2] R_NVR1V63[2] R_NVR2V13[2] R_NVR2V50[2] R_NVR3V4[2] R_NVR3V8[2] R_NVR3V20[2] R_NVR3V27[2] R_NVR3V36[2] R_NVR3V43[2] R_NVR3V55[2] R_NVR3V59[2] m D1 0 R_NVR1V0[1] R_NVR1V1[1] R_NVR1V2[1] R_NVR1V61[1] R_NVR1V62[1] R_NVR1V63[1] R_NVR2V13[1] R_NVR2V50[1] R_NVR3V4[1] R_NVR3V8[1] R_NVR3V20[1] R_NVR3V27[1] R_NVR3V36[1] R_NVR3V43[1] R_NVR3V55[1] R_NVR3V59[1] D0 1 R_NVR1V0[0] R_NVR1V1[0] R_NVR1V2[0] R_NVR1V61[0] R_NVR1V62[0] R_NVR1V63[0] R_NVR2V13[0] R_NVR2V50[0] R_NVR3V4[0] R_NVR3V8[0] R_NVR3V20[0] R_NVR3V27[0] R_NVR3V36[0] R_NVR3V43[0] R_NVR3V55[0] R_NVR3V59[0] (Hex) Function R_NVR1V0[4] w - R_NVR1V1[5] R_NVR1V2[5] R_NVR1V1[4] R_NVR1V2[4] R_NVR1V61[4] R_NVR1V62[4] R_NVR1V63[4] R_NVR2V13[4] R_NVR2V50[4] - w w R_NVR1V61[5] R_NVR1V62[5] GAMCTRN1 1 1 1 1 1 1 1 1 1 R- Gamma (E1h) adjustment “-“: Don’t care, can be set to VDDI or DGND level © ORISE Technology Co., Ltd. Proprietary & Confidential 20 Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B Table 6.1.2 Panel Function Command List (6) Instruction D/CX WRX RDX D17-8 D7 D6 0 1 1 1 1 1 1 1 ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 - D5 1 G_PVR1V1[5] G_PVR1V2[5] G_PVR1V61[5] G_PVR1V62[5] - D4 0 G_PVR1V0[4] G_PVR1V1[4] G_PVR1V2[4] G_PVR1V61[4] G_PVR1V62[4] G_PVR1V63[4] G_PVR2V13[4] G_PVR2V50[4] - D3 0 G_PVR1V0[3] G_PVR1V1[3] G_PVR1V2[3] G_PVR1V61[3] G_PVR1V62[3] G_PVR1V63[3] G_PVR2V13[3] G_PVR2V50[3] G_PVR3V4[3] G_PVR3V8[3] G_PVR3V20[3] G_PVR3V27[3] G_PVR3V36[3] G_PVR3V43[3] G_PVR3V55[3] G_PVR3V59[3] D2 0 G_PVR1V0[2] G_PVR1V1[2] G_PVR1V2[2] G_PVR1V61[2] G_PVR1V62[2] G_PVR1V63[2] G_PVR2V13[2] G_PVR2V50[2] G_PVR3V4[2] G_PVR3V8[2] G_PVR3V20[2] G_PVR3V27[2] G_PVR3V36[2] G_PVR3V43[2] G_PVR3V55[2] G_PVR3V59[2] D1 0 G_PVR1V0[1] G_PVR1V1[1] G_PVR1V2[1] G_PVR1V61[1] G_PVR1V62[1] G_PVR1V63[1] G_PVR2V13[1] G_PVR2V50[1] G_PVR3V4[1] G_PVR3V8[1] G_PVR3V20[1] G_PVR3V27[1] G_PVR3V36[1] G_PVR3V43[1] G_PVR3V55[1] G_PVR3V59[1] D0 0 G_PVR1V0[0] G_PVR1V1[0] G_PVR1V2[0] G_PVR1V61[0] G_PVR1V62[0] G_PVR1V63[0] G_PVR2V13[0] G_PVR2V50[0] G_PVR3V4[0] G_PVR3V8[0] G_PVR3V20[0] G_PVR3V27[0] G_PVR3V36[0] G_PVR3V43[0] G_PVR3V55[0] G_PVR3V59[0] (Hex) Function GAMCTRP1 1 1 1 1 1 1 1 1 1 G+ Gamma (E2h) adjustment “-“: Don’t care, can be set to VDDI or DGND level Instruction D/CX WRX RDX D17-8 D7 D6 0 1 1 1 1 1 1 1 ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 - D5 1 - bt D4 0 Table 6.1.2 Panel Function Command List (7) 1 - re D3 0 G_NVR1V0[3] G_NVR1V1[3] G_NVR1V2[3] G_NVR1V61[3] G_NVR1V62[3] G_NVR1V63[3] G_NVR2V13[3] G_NVR2V50[3] G_NVR3V4[3] G_NVR3V8[3] G_NVR3V20[3] G_NVR3V27[3] G_NVR3V36[3] G_NVR3V43[3] G_NVR3V55[3] G_NVR3V59[3] nd .co D2 0 G_NVR1V0[2] G_NVR1V1[2] G_NVR1V2[2] G_NVR1V61[2] G_NVR1V62[2] G_NVR1V63[2] G_NVR2V13[2] G_NVR2V50[2] G_NVR3V4[2] G_NVR3V8[2] G_NVR3V20[2] G_NVR3V27[2] G_NVR3V36[2] G_NVR3V43[2] G_NVR3V55[2] G_NVR3V59[2] m D1 0 G_NVR1V0[1] G_NVR1V1[1] G_NVR1V2[1] G_NVR1V61[1] G_NVR1V62[1] G_NVR1V63[1] G_NVR2V13[1] G_NVR2V50[1] G_NVR3V4[1] G_NVR3V8[1] G_NVR3V20[1] G_NVR3V27[1] G_NVR3V36[1] G_NVR3V43[1] G_NVR3V55[1] G_NVR3V59[1] D0 1 G_NVR1V0[0] G_NVR1V1[0] G_NVR1V2[0] G_NVR1V61[0] G_NVR1V62[0] G_NVR1V63[0] G_NVR2V13[0] G_NVR2V50[0] G_NVR3V4[0] G_NVR3V8[0] G_NVR3V20[0] G_NVR3V27[0] G_NVR3V36[0] G_NVR3V43[0] G_NVR3V55[0] G_NVR3V59[0] (Hex) Function w - G_NVR1V1[5] G_NVR1V2[5] w G_NVR1V61[5] G_NVR1V62[5] w .m G_NVR1V0[4] G_NVR1V1[4] G_NVR1V2[4] G_NVR1V61[4] G_NVR1V62[4] G_NVR1V63[4] G_NVR2V13[4] G_NVR2V50[4] - GAMCTRN1 1 1 1 1 1 1 1 1 1 G- Gamma (E3h) adjustment “-“: Don’t care, can be set to VDDI or DGND level © ORISE Technology Co., Ltd. Proprietary & Confidential 21 Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B Table 6.1.2 Panel Function Command List (8) Instruction D/CX WRX RDX D17-8 D7 D6 0 1 1 1 1 1 1 1 ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 - D5 1 B_PVR1V1[5] B_PVR1V2[5] B_PVR1V61[5] B_PVR1V62[5] - D4 0 B_PVR1V0[4] B_PVR1V1[4] B_PVR1V2[4] B_PVR1V61[4] B_PVR1V62[4] B_PVR1V63[4] B_PVR2V13[4] B_PVR2V50[4] - D3 0 B_PVR1V0[3] B_PVR1V1[3] B_PVR1V2[3] B_PVR1V61[3] B_PVR1V62[3] B_PVR1V63[3] B_PVR2V13[3] B_PVR2V50[3] B_PVR3V4[3] B_PVR3V8[3] B_PVR3V20[3] B_PVR3V27[3] B_PVR3V36[3] B_PVR3V43[3] B_PVR3V55[3] B_PVR3V59[3] D2 0 B_PVR1V0[2] B_PVR1V1[2] B_PVR1V2[2] B_PVR1V61[2] B_PVR1V62[2] B_PVR1V63[2] B_PVR2V13[2] B_PVR2V50[2] B_PVR3V4[2] B_PVR3V8[2] B_PVR3V20[2] B_PVR3V27[2] B_PVR3V36[2] B_PVR3V43[2] B_PVR3V55[2] B_PVR3V59[2] D1 0 B_PVR1V0[1] B_PVR1V1[1] B_PVR1V2[1] B_PVR1V61[1] B_PVR1V62[1] B_PVR1V63[1] B_PVR2V13[1] B_PVR2V50[1] B_PVR3V4[1] B_PVR3V8[1] B_PVR3V20[1] B_PVR3V27[1] B_PVR3V36[1] B_PVR3V43[1] B_PVR3V55[1] B_PVR3V59[1] D0 0 B_PVR1V0[0] B_PVR1V1[0] B_PVR1V2[0] B_PVR1V61[0] B_PVR1V62[0] B_PVR1V63[0] B_PVR2V13[0] B_PVR2V50[0] B_PVR3V4[0] B_PVR3V8[0] B_PVR3V20[0] B_PVR3V27[0] B_PVR3V36[0] B_PVR3V43[0] B_PVR3V55[0] B_PVR3V59[0] (Hex) Function GAMCTRP1 1 1 1 1 1 1 1 1 1 B+ Gamma (E4h) adjustment “-“: Don’t care, can be set to VDDI or DGND level Instruction D/CX WRX RDX D17-8 D7 D6 0 1 1 1 1 1 1 1 ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 - D5 1 - bt D4 0 Table 6.1.2 Panel Function Command List (9) 1 - re D3 0 B_NVR1V0[3] B_NVR1V1[3] B_NVR1V2[3] B_NVR1V61[3] B_NVR1V62[3] B_NVR1V63[3] B_NVR2V13[3] B_NVR2V50[3] B_NVR3V4[3] B_NVR3V8[3] B_NVR3V20[3] B_NVR3V27[3] B_NVR3V36[3] B_NVR3V43[3] B_NVR3V55[3] B_NVR3V59[3] nd .co D2 0 B_NVR1V0[2] B_NVR1V1[2] B_NVR1V2[2] B_NVR1V61[2] B_NVR1V62[2] B_NVR1V63[2] B_NVR2V13[2] B_NVR2V50[2] B_NVR3V4[2] B_NVR3V8[2] B_NVR3V20[2] B_NVR3V27[2] B_NVR3V36[2] B_NVR3V43[2] B_NVR3V55[2] B_NVR3V59[2] m D1 0 B_NVR1V0[1] B_NVR1V1[1] B_NVR1V2[1] B_NVR1V61[1] B_NVR1V62[1] B_NVR1V63[1] B_NVR2V13[1] B_NVR2V50[1] B_NVR3V4[1] B_NVR3V8[1] B_NVR3V20[1] B_NVR3V27[1] B_NVR3V36[1] B_NVR3V43[1] B_NVR3V55[1] B_NVR3V59[1] D0 1 B_NVR1V0[0] B_NVR1V1[0] B_NVR1V2[0] B_NVR1V61[0] B_NVR1V62[0] B_NVR1V63[0] B_NVR2V13[0] B_NVR2V50[0] B_NVR3V4[0] B_NVR3V8[0] B_NVR3V20[0] B_NVR3V27[0] B_NVR3V36[0] B_NVR3V43[0] B_NVR3V55[0] B_NVR3V59[0] (Hex) Function w - B_NVR1V1[5] B_NVR1V2[5] w B_NVR1V61[5] B_NVR1V62[5] w .m B_NVR1V0[4] B_NVR1V1[4] B_NVR1V2[4] B_NVR1V61[4] B_NVR1V62[4] B_NVR1V63[4] B_NVR2V13[4] B_NVR2V50[4] - GAMCTRN1 1 1 1 1 1 1 1 1 1 B- Gamma (E5h) adjustment “-“: Don’t care, can be set to VDDI or DGND level © ORISE Technology Co., Ltd. Proprietary & Confidential 22 Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.2. System Command Description 6.2.1. NOP (00h) 00H Inst / Para NOP D/CX 0 WRX ↑ RDX 1 D17-8 D7 0 NOP (No Operation) D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 0 (Code) (00H) - Parameter NOTE: “-” Don’t care, can be set to VDDI or DGND level No Parameter -This command is empty command. It does not have effect on the display module. Description Restriction -However it can be used to terminate RAM data write or read as described in RAMWR (Memory Write), RAMHD (Memory Read) and parameter write commands. Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Register Availability .m bt 23 Default Status Power On Sequence S/W Reset H/W Reset Flow Chart © ORISE Technology Co., Ltd. Proprietary & Confidential w w w re nd .co m Availability Yes Yes Yes Yes Yes Default Value N/A N/A N/A Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.2.2. SWRESET (01h): Software Reset 01H Inst / Para SWRESET D/CX 0 WRX ↑ RDX 1 D17-8 D7 0 SWRESET (Software Reset) D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 1 (Code) (01H) - Parameter NOTE: “-” Don’t care, can be set to VDDI or DGND level No Parameter Description -When the Software Reset command is written, it causes a software reset. It resets the commands and parameters to their S/W Reset default values and all source & gate outputs are set to VSS (display off). (See default tables in each command description) Note: The Frame Memory contents are not affected by this command. -It will be necessary to wait 5msec before sending new command following software reset. Restriction -Software Reset command cannot be sent during Sleep Out sequence. Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Default SWRESET (01H) w w Status Power On Sequence S/W Reset H/W Reset .m bt re Register Availability w nd .co -If Software Reset is applied during Sleep Out mode, it will be necessary to wait 120msec before sending Sleep Out command. m -The display module loads all display supplier’s factory default values to the registers during 5msec. Availability Yes Yes Yes Yes Yes Default Value N/A N/A N/A Legend Command Display whole blank screen Flow Chart Parameter Display Set Commands to S/W Default Value Action Mode Sequential transfer Sleep In Mode © ORISE Technology Co., Ltd. Proprietary & Confidential 24 Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.2.3. RDDID (04H): Read Display ID 04H Inst / Para RDDID 1 Parameter 2 Parameter 3 Parameter 4 Parameter th rd nd st RDDID (Read Display ID) D/CX 0 1 1 1 1 WRX ↑ 1 1 1 1 RDX 1 ↑ ↑ ↑ ↑ D17-8 D7 0 ID17 ID27 ID37 D6 0 ID16 ID26 ID36 D5 0 ID15 ID25 ID35 D4 0 ID14 ID24 ID34 D3 0 ID13 ID23 ID33 D2 1 ID12 ID22 ID32 D1 0 ID11 ID21 ID31 D0 0 ID10 ID20 ID30 (Code) (04H) 38h 80h 62h NOTE: “-” Don’t care, can be set to VDDI or DGND level -This read byte returns 18-bits display identification information. -The 2 parameter (ID17 to ID10): LCD module’s manufacturer ID. -The 3 parameter (ID27 to ID20): LCD module/driver version ID th rd nd Restriction -The 4 parameter (ID37 to UD30): LCD module/driver ID. NOTE: Commands RDID1/2/3 (DAH, DBH, DCH) read data correspond to the parameters 2,3,4 of the command 04H, respectively. Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes w .m bt ID1 38h 80h 62h Register Availability re Status Default nd .co Description Serial I/F Mode RDDID (04H) w Power On Sequence S/W Reset H/W Reset Default Value ID2 38h 80h 62h m ID3 38h 80h 62h -The 1 parameter is dummy data st w Parallel I/F M RDDID (04H) Host Driver Legend Command Dummy Clock Flow Chart Dummy Read Parameter Display Send ID1[7:0] Send ID1[7:0] Action Mode Send ID2[7:0] Send ID2[7:0] Sequential transfer Send ID3[7:0] Send ID3[7:0] © ORISE Technology Co., Ltd. Proprietary & Confidential 25 Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.2.4. RDDST (09H): Read Display Status 09H Inst / Para RDDST 1 Parameter 2 Parameter 3 Parameter 4 Parameter th rd nd st RDDST (Read Display Status) D/CX 0 1 1 1 WRX ↑ 1 1 1 RDX 1 ↑ ↑ ↑ D17-8 D7 0 BSTON ST23 D6 0 MY PF2 D5 0 MX PF1 D4 0 MV PF0 D3 1 ML D2 0 RGB D1 0 ST25 D0 1 (Code) (09H) 00h 61h 00h 00h 1 1 VSSON ST14 INVON ST12 ↑ th 5 Parameter 1 1 GCS1 GCS0 TELOM HSON ↑ NOTE: “-” Don’t care, can be set to VDDI or DGND level Bit BSTON MY MX MV ML RGB ST25 ST24 ST23 PF2 PF1 PF0 IDMON PTLON SLPOUT NORON VSSON ST14 INVON ST12 ST11 DISON TEON GCSEL2 GCSEL1 GCSEL0 TELOM HSON VSON PCLKON DEON ST0 Tearing effect line mode Horizontal Sync. (HS) Vertical Sync, (VS, RGB I/F) Pixel Clock (PCLK, RGB I/F) Data Enable (DE, RGB I/F) For Future Use Description Booster Voltage Status Row Address Order (MY) Column Address Order (MX) Row/Column Exchange (MV) Vertical Refresh Order (ML) RGB/ BGR Order (RGB) For Future Use For Future Use For Future Use ST24 NORO IDMON PTLON SLOUT N ST11 DISON TEON GCS2 VSON PCKON DEON ST0 This command indicates the current status of the display as described in the table below: Value ‘1’ =Booster on, ‘0’ =Booster off ‘1’ =Decrement, (Bottom to Top, when MADCTL (36H) D7=’1’) ‘0’ =Increment, (Top to Bottom, when MADCTL (36H) D7=’0’) ‘1’ =Decrement, (Right to Left, when MADCTL (36H) D6=’1’) ‘0’ =Increment, (Left to Right, when MADCTL (36H) D6=’0’) ‘1’ = Row/column exchange, (when MADCTL (36H) D5=’1’) ‘0’ = Normal, (when MADCTL (36H) D5=’0’) ‘1’ =Decrement, (LCD refresh Bottom to Top, when MADCTL (36H) D4=’1’) “0”=Increment, (LCD refresh Top to Bottom, when MADCTL (36H) D4=’0’) ‘1’ =BGR, (When MADCTL (36H) D3=’1’) ‘0’ =RGB, (When MADCTL (36H) D3=’0’) ‘0’ ‘0’ ‘0’ “011” = 12-bits / pixel, “101” = 16-bits / pixel, “110” = 18-bits / pixel, others are no define ‘1’ = On, “0” = Off ‘1’ = On, “0” = Off ‘1’ = Out, “0” = In ‘1’ = Normal Display, ‘0’ = Partial Display ‘1’ = Scroll on,“0” = Scroll off ‘0’ ‘1’ = On, “0” = Off ‘0’ ‘0’ ‘1’ = On, “0” = Off ‘1’ = On, “0” = Off “000” = GC0 “001” = GC1 “010” = GC2 “011” = GC3, ”100” to “111” = Not defined ‘0’ = mode1, ‘1’ = mode2 ‘1’ = On, ‘0’ = Off ‘1’ = On, ‘0’ = Off ‘1’ = On, ‘0’ = Off ‘1’ = On, ‘0’ = Off ‘0’ Color Pixel Format Definition Idle Mode On/Off Partial Mode On/Off Sleep In/Out Display Normal Mode On/Off Vertical Scrolling Status For Future Use Inversion Status For Future Use For Future Use Display On/Off Tearing effect line on/off Gamma Curve Selection Description Note: ST0, ST11-ST12, ST14, ST23, ST24 are set to ‘0’ © ORISE Technology Co., Ltd. Proprietary & Confidential w w w .m bt 26 re nd .co m Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B Restriction Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Register Availability Status Default Power On Sequence S/W Reset H/W Reset ST[31-24] 0000-0000 0xxx-xx00 0000-0000 Default Value (ST31 to ST0) ST[23-16] ST[15-8] ST[7-0] 0110-0001 0000-0000 0000-0000 0xxx-0001 0000-0000 0000-0000 0110-0001 0000-0000 0000-0000 RDDST (09H) RDDST (09H) nd .co Host Driver Serial I/F Mode Parallel I/F Mode m Legend Command bt re Dummy Clock Dummy Read .m Flow Chart Send ST[31:24] Send ST[31:24] Parameter Display w Send ST[23:16] Send ST[23:16] Action Mode Send ST[15:8] w Send ST[15:8] Send ST[7:0] w Sequential transfer Send ST[7:0] © ORISE Technology Co., Ltd. Proprietary & Confidential 27 Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.2.5. RDDPM (0AH): Read Display Power Mode 0AH Inst / Para RDDPM 1 Parameter st RDDPM (Read Display Power Mode) D/CX 0 1 WRX ↑ 1 RDX 1 ↑ D17-8 D7 0 D6 0 D5 0 D4 0 D3 1 D2 0 D1 1 D1 D0 0 D0 (Code) (0AH) 08h- SLPOU NORO nd 2 Parameter 1 1 BSTON IDMON PTLON DISON ↑ T N NOTE: “-” Don’t care, can be set to VDDI or DGND level Description w Default Status Power On Sequence S/W Reset H/W Reset w Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In .m Restriction bt -This command indicates the current status of the display as described in the table below: Bit Description Value “1”=Booster on, BSTON Booster Voltage Status “0”=Booster off “1” = Idle Mode On, IDMON Idle Mode On/Off “0” = Idle Mode Off “1” = Partial Mode On, PTLON Partial Mode On/Off “0” = Partial Mode Off “1” = Sleep Out, SLPON Sleep In/Out “0” = Sleep In “1” = Normal Display, NORON Display Normal Mode On/Off “0” = Partial Display “1” = Display On, DISON Display On/Off “0” = Display Off D1 Not Used “0” D0 Not Used “0” re - w nd .co Host Driver Default Value (D7 to D0) 0000_1000 (08h) 0000_1000 (08h) 0000_1000 (08h) m Availability Yes Yes Yes Yes Yes Legend Serial I/F Mode RDDPM (0AH) Parallel I/F Mode RDDPM (0AH) Command Parameter Display Flow Chart Send D[7:0] Dummy Read Action Mode Send D[7:0] Sequential transfer © ORISE Technology Co., Ltd. Proprietary & Confidential 28 Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.2.6. RDDMADCTR (0BH): Read Display MADCTR 0BH Inst / Para RDDMADCTR 1 Parameter nd st RDDMADCTR (Read Display MADCTR) D/CX 0 1 WRX ↑ 1 RDX 1 ↑ D17-8 D7 0 D6 0 MY D5 0 MV D4 0 ML D3 1 RGB D2 0 D2 D1 1 D1 D0 1 D0 (Code) (0BH) 00h MX 2 Parameter 1 1 ↑ NOTE: “-” Don’t care, can be set to VDDI or DGND level Description Restriction Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In bt re Status Power On Sequence S/W Reset H/W Reset w w .m Register Availability Default w nd .co Host Driver -This command indicates the current status of the display as described in the table below: Bit Description Value MX Row Address Order ‘1’ =Decrement, “0”=Increment MY Column Address Order ‘1’ =Decrement, “0”=Increment ‘1’ = Row/column exchange (MV=1) MV Row/Column Order (MV) ‘0’ = Normal (MV=0) ‘1’ =LCD Refresh Top to Bottom ML Vertical Refresh Order ‘0’ =LCD Refresh Bottom to Top RGB RGB/BGR Order ‘1’ =BGR, “0”=RGB D2 Not Used ‘0’ D1 Not Used ‘0’ D0 Not Used ‘0’ Default Value (D7 to D0) 0000_0000 (00h) No change 0000_0000 (00h) m Availability Yes Yes Yes Yes Yes Serial I/F Mode RDDMADCTR (0BH) Parallel I/F Mode RDDMADCTR (0BH) Legend Command Parameter Display Flow Chart Send D[7:0] Dummy Read Action Mode Send D[7:0] Sequential transfer © ORISE Technology Co., Ltd. Proprietary & Confidential 29 Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.2.7. RDDCOLMOD (0CH): Read Display Pixel Format 0CH Inst / Para RDDCOLMOD 1 Parameter nd st RDDCOLMOD (Read Display Pixel Format) D/CX 0 1 WRX ↑ 1 RDX 1 ↑ D17-8 D7 0 D6 0 VIPF2 D5 0 VIPF1 D4 0 VIPF0 D3 1 D3 D2 1 IFPF2 D1 0 IFPF1 D0 0 IFPF0 (Code) (0CH) 66h 2 Parameter 1 1 VIPF3 ↑ NOTE: “-” Don’t care, can be set to VDDI or DGND level Restriction w w Status w Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In bt re Availability Yes Yes Yes Yes Yes Default Value IFPF[2:0] VIPF[3:0] 0101 (16-bits/pixel) 0110 (18-bits/pixel) No Change No Change 0101 (16-bits/pixel) 0110 (18-bits/pixel) VIPF[3:0] 0101 5 0110 6 0111 7 1110 14 Others are no define and invalid RGB Interface Color Format 16-bits/pixel (1-times data transfer) 18-bits/pixel (1-times data transfer) Reserved 18-bits/pixel (3-times data transfer) Default Power On Sequence S/W Reset H/W Reset .m nd .co Host Driver Description m -This command indicates the current status of the display as described in the table below: IFPF[2:0] MCU Interface Color Format 011 3 12-bits/pixel 101 5 16-bits/pixel 110 6 18-bits/pixel 111 7 Reserved Others are no define and invalid Serial I/F Mode RDDCOLMOD (0CH) Parallel I/F Mode RDDCOLMOD (0CH) Legend Command Parameter Display Flow Chart Send D[7:0] Dummy Read Action Mode Send D[7:0] Sequential transfer © ORISE Technology Co., Ltd. Proprietary & Confidential 30 Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.2.8. RDDIM (0DH): Read Display Image Mode 0DH Inst / Para RDDIM 1 Parameter nd st RDDIM (Read Display Image Mode D/CX 0 1 WRX ↑ 1 RDX 1 ↑ D17-8 D7 0 D6 0 D6 D5 0 INVON D4 0 D4 D3 1 D3 D2 1 GCS2 D1 0 GCS1 D0 1 GCS0 (Code) (0DH) 00h 2 Parameter 1 1 VSSON ↑ NOTE: “-” Don’t care, can be set to VDDI or DGND level Restriction Register Availability Default Status Power On Sequence S/W Reset H/W Reset w w Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In bt re Availability Yes Yes Yes Yes Yes .m w nd .co Host Driver Description -This command indicates the current status of the display as described in the table below: Bit Description Value “1” = Vertical scrolling is On, VSSON Vertical Scrolling On/Off “0” = Vertical scrolling is Off D6 For Future Use “0” (Not used) “1” = Inversion is On, INVON Inversion On/Off “0” = Inversion is Off D4 For Future Use “0” (Not used) D3 For Future Use “0” (Not used) GCS2 “000” = GC0, “001” = GC1, GCS1 Gamma Curve Selection “010” = GC2, GCS0 “011” = GC3, ”100” to “111” = Not defined Default Value (D7 to D0) 0000_0000 (00h) 0000_0000 (00h) 0000_0000 (00h) m Serial I/F Mode RDDIM (0DH) Parallel I/F Mode RDDIM (0DH) Legend Command Parameter Display Flow Chart Send D[7:0] Dummy Read Action Mode Send D[7:0] Sequential transfer © ORISE Technology Co., Ltd. Proprietary & Confidential 31 Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.2.9. RDDSM (0EH): Read Display Signal Mode 0EH Inst / Para RDDSM 1 Parameter nd st RDDSM (Read Display Signal Mode) D/CX 0 1 WRX ↑ 1 RDX 1 ↑ D17-8 D7 0 D6 0 D5 0 D4 0 D3 1 D2 1 D1 1 D1 D0 0 D0 (Code) (0EH) 00h 2 Parameter 1 1 TEON TELOM HSON ↑ NOTE: “-” Don’t care, can be set to VDDI or DGND level VSON PCKON DEON -This command indicates the current status of the display as described in the table below: Bit TEON TELOM Description HSON VSON PCKON DEON D1 D0 Description Tearing Effect Line On/Off Tearing effect line mode Horizontal Sync. (RGB I/F) On/Off Vertical Sync. (RGB I/F) On/Off Pixel Clock (PCLK, RGB I/F) On/Off Data Enable (DE, RGB I/F) On/Off Not Used Not Used Value “1” = On, “0” = Off “0” = mode1, “1” = mode2 “1” = On, “0” = Off “1” = On, “0” = Off “1” = On, “0” = Off “1” = On, “0” = Off “1” = On, “0” = Off “1” = On, “0” = Off Default Status Power On Sequence S/W Reset H/W Reset w w .m Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In re Restriction bt w nd .co Availability Yes Yes Yes Yes Yes Default Value (D7 to D0) 0000_0000 (00h) 0000_0000 (00h) 0000_0000 (00h) m Legend Command Serial I/F Mode RDDSM (0EH) Parallel I/F Mode RDDSM (0EH) Host Driver Flow Chart Send D[7:0] Dummy Read Parameter Display Action Mode Send D[7:0] Sequential transfer © ORISE Technology Co., Ltd. Proprietary & Confidential 32 Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.2.10. RDDSDR (0FH): Read Display Self-Diagnostic Result 0FH Inst / Para RDDSDR 1 Parameter nd st RDDSDR (Read Display Self-Diagnostic Result) D/CX 0 1 WRX ↑ 1 RDX 1 ↑ D17-8 D7 0 D6 0 FUND D5 0 ATTD D4 0 BRD D3 1 D3 D2 1 D2 D1 1 D1 D0 1 D0 (Code) (0FH) 00h 2 Parameter 1 1 RELD ↑ NOTE: “-” Don’t care, can be set to VDDI or DGND level -This command indicates the current status of the display as described in the table below: Bit RELD FUND ATTD BRD D3 D2 D1 D0 Description Register Loading Detection Functionality Detection Chip Attachment Detection Display Glass Break Detection Not Used Not Used Not Used Not Used Value See section 6.15.1 See section 6.15.1 See section 6.15.3 See section 6.15.4 “0” “0” “0” “0” Description Restriction Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In re Default w Status Power On Sequence S/W Reset H/W Reset w .m Register Availability bt w nd .co Host Driver 33 Default Value (D7 to D0) 0000_0000 (00h) 0000_0000 (00h) 0000_0000 (00h) m Availability Yes Yes Yes Yes Yes Serial I/F Mode RDDSDR (0FH) Parallel I/F Mode RDDSTR (0FH) Legend Command Parameter Display Flow Chart Send D[7:0] Dummy Read Action Mode Send D[7:0] Sequential transfer © ORISE Technology Co., Ltd. Proprietary & Confidential Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.2.11. SLPIN (10H): Sleep In 10H Inst / Para SLPIN st SLPIN (Sleep In) D/CX 0 WRX ↑ RDX 1 D17-8 D7 0 D6 0 D5 0 D4 1 D3 0 D2 0 D1 0 D0 0 (Code) (10H) - 1 Parameter NOTE: “-” Don’t care, can be set to VDDI or DGND level No parameter -This command causes the LCD module to enter the minimum power consumption mode. -In this mode the DC/DC converter is stopped, Internal display oscillator is stopped, and panel scanning is stopped. Sleep In VDDI 1.6V-3.6V m nd .co re 34 0V 0V Blanking display (over 1frame display) * VDD Gate Output Source Output VCOM Output Description Internal counter Internal Oscillator DC charge in capacitors VGH VGL AVDD 2.6V-3.5V STOP 0V STOP STOP bt DISCHARGE 0V or VDD 0V or VDD 0V 0V or VDD 0V IC Internal reset * Note: complete 1 frame display (ex: continue 2-falling edges of VS) -MCU interface and memory are still working and the memory keeps its contents -This command has no effect when module is already in sleep in mode. Sleep In Mode can only be exit by the Sleep Out Command (11H). Restriction -It will be necessary to wait 5msec before sending next command, this is to allow time for the supply voltages and clock circuits to stabilize. -It will be necessary to wait 120msec after sending Sleep Out command (when in Sleep In Mode) before Sleep In command can be sent. Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In w w w .m Availability Yes Yes Yes Yes Yes Default Value Sleep In mode Sleep In mode Sleep In mode Default Status Power On Sequence S/W Reset H/W Reset © ORISE Technology Co., Ltd. Proprietary & Confidential Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B -It takes about 120msec to get into Sleep In mode (booster off state) after SLPIN command issued. -The results of booster off can be check by RDDST (09H) command Bit31. SPLIN (10H) Legend Stop DC/DC Converte Stop Internal Oscillator Command Flow Chart Display whole blank screen (Automatic No effect to DISP ON/OFF Command) Parameter Display Action Mode Drain charge from LCD panel © ORISE Technology Co., Ltd. Proprietary & Confidential w w w .m bt re 35 nd .co m Sleep In Sequential transfer Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.2.12. SLPOUT (11H): Sleep Out 11H Inst / Para SLPOUT st SLPOUT (Sleep Out) D/CX 0 WRX ↑ RDX 1 D17-8 D7 0 D6 0 D5 0 D4 1 D3 0 D2 0 D1 0 D0 1 (Code) (11H) - 1 Parameter NOTE: “-” Don’t care, can be set to VDDI or DGND level No Parameter -This command turns off sleep mode. -In this mode the DC/DC converter is enabled, Internal display oscillator is started, and panel scanning is started. Sleep Out VDDI 1.6V-3.6V m STOP 0V or VDD 0V 0V or VDD STOP 0V VDD Internal Oscillator AVDD VGL Description VGH Internal counter IC Internal reset Gate Output Source Output VCOM Output Start 2.6V-3.5V re STOP 0V 0V nd .co Start Memory Contents Memory Contents w w Blanking display (over 1frame display) * .m STOP 0V 0V bt If DISPON 29H is set Availability Yes Yes Yes Yes Yes Default Value Sleep In mode Sleep In mode Sleep In mode 36 * Note: complete 1 frame display (ex: continue 2-falling edges of VS) -This command has no effect when module is already in sleep out mode. Sleep Out Mode can only be exit by the Sleep In Command (10H). -It will be necessary to wait 5msec before sending next command, this is to allow time for the supply voltages and clock circuits to stabilize. Restriction -DRIVER loads all default values of extended and test command to the registers during this 5msec and there cannot be any abnormal visual effect on the display image if those default and register values are same when this load is done and when the DRIVER is already Sleep Out mode. -DRIVER is doing self-diagnostic functions during this 5msec. See also section 8.19. -It will be necessary to wait 120msec after sending Sleep In command (when in Sleep Out mode) before Sleep Out command can be sent Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Default © ORISE Technology Co., Ltd. Proprietary & Confidential w Status Power On Sequence S/W Reset H/W Reset Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B -It takes 120msec to become Sleep Out mode (booster on mode) after SLPOUT command issued. -The results of booster on can be checked by RDDST (09H) command Bit31. SLPOUT (11H) Start Internal Oscillator Start DC-DC Converter Charge Offset voltage for LCD Panel Display whole blank screen for 2 frames (Automatic No effect to DISP ON/OFF Display Memory contents in accordance with the current command Legend Command Parameter Display Flow Chart Action Mode Sequential transfer Sleep Out © ORISE Technology Co., Ltd. Proprietary & Confidential w w w .m 37 bt re nd .co m table settings Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.2.13. PTLON (12H): Partial Display Mode On 12H Inst / Para PTLON st PTLON (Partial Display Mode On) D/CX 0 WRX ↑ RDX 1 D17-8 D7 0 D6 0 D5 0 D4 1 D3 0 D2 0 D1 1 D0 0 (Code) (12H) - 1 Parameter NOTE: “-” Don’t care, can be set to VDDI or DGND level No Parameter -This command turns on Partial mode. The partial mode window is described by the Partial Area command (30H) Description Restriction -To leave Partial mode, the Normal Display Mode On command (13H) should be written. -There is no abnormal visual effect during mode change between Normal mode On Partial mode On. This command has no effect when Partial mode is active. Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default © ORISE Technology Co., Ltd. Proprietary & Confidential w w w .m 38 Flow Chart See Partial Area (30H) bt Status Power On Sequence S/W Reset H/W Reset re nd .co Register Availability Default Value Normal Mode On Normal Mode On Normal Mode On m Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.2.14. NORON (13H): Normal Display Mode On 13H Inst / Para NORON st NORON (Normal Display Mode On) D/CX 0 WRX ↑ RDX 1 D17-8 D7 0 D6 0 D5 0 D4 1 D3 0 D2 0 D1 1 D0 1 (Code) (13H) - 1 Parameter NOTE: “-” Don’t care, can be set to VDDI or DGND level No Parameter -This command returns the display to normal mode. Description -Normal display mode on means Partial mode off, Scroll mode Off. -Exit from NORON by the Partial mode On command (12H) -There is no abnormal visual effect during mode change from Normal mode On to Partial mode On. Restriction -This command has no effect when Normal Display mode is active. Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Register Availability Flow Chart -See Partial Area and Vertical Scrolling Definition Descriptions for details of when to use this command © ORISE Technology Co., Ltd. Proprietary & Confidential w w w .m bt 39 Default Status Power On Sequence S/W Reset H/W Reset re nd .co Default Value Normal Mode On Normal Mode On Normal Mode On m Availability Yes Yes Yes Yes Yes Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.2.15. INVOFF (20H): Display Inversion Off 20H Inst / Para INVOFF st INVOFF (Display Inversion Off) D/CX 0 WRX ↑ RDX 1 D17-8 D7 0 D6 0 D5 1 D4 0 D3 0 D2 0 D1 0 D0 0 (Code) (20H) - 1 Parameter NOTE: “-” Don’t care, can be set to VDDI or DGND level No Parameter -This command is used to recover from display inversion mode. -This command makes no change of contents of frame memory. -This command does not change any other status. Top-Left (0,0) Description Memory Display Restriction -This command has no effect when module is already inversion off mode. Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In .m bt re Default Status Power On Sequence S/W Reset H/W Reset w w w Register Availability nd .co Availability Yes Yes Yes Yes Yes Default Value Display Inversion off Display Inversion off Display Inversion off m Legend Command (Example) Display Inversion On Mode Parameter Display Flow Chart INVOFF (20H) Action Mode Sequential transfer Display Inversion OFF Mode © ORISE Technology Co., Ltd. Proprietary & Confidential 40 Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.2.16. INVON (21H): Display Inversion On 21H Inst / Para INVON st INVON (Display Inversion On) D/CX 0 WRX ↑ RDX 1 D17-8 D7 0 D6 0 D5 1 D4 0 D3 0 D2 0 D1 0 D0 1 (Code) (21H) - 1 Parameter NOTE: “-” Don’t care, can be set to VDDI or DGND level No Parameter -This command is used to enter into display inversion mode -This command makes no change of contents of frame memory. -This command does not change any other status. -To exit from Display Inversion On, the Display Inversion Off command (20H) should be written. Memory Restriction -This command has no effect when module is already Inversion On mode. Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In .m bt re Register Availability Default Status Power On Sequence S/W Reset H/W Reset w w w nd .co Display Availability Yes Yes Yes Yes Yes Default Value Display Inversion off Display Inversion off Display Inversion off Description Top-Left (0,0) (Example) m Legend Command Display Inversion OFF Mode Parameter Display Flow Chart INVON (21H) Action Mode Sequential transfer Display Inversion ON Mode © ORISE Technology Co., Ltd. Proprietary & Confidential 41 Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.2.17. GAMSET (26H): Gamma Set 26H Inst / Para GAMSET st GAMSET (Gamma Set) D/CX 0 WRX ↑ RDX 1 D17-8 D7 0 D6 0 GC6 D5 1 GC5 D4 0 GC4 D3 0 GC3 D2 1 GC2 D1 1 GC1 D0 0 GC0 (Code) (26H) 01h 1 Parameter 1 GC7 1 ↑ NOTE: “-” Don’t care, can be set to VDDI or DGND level -This command is used to select the desired Gamma curve for the current display. A maximum of 4 curves can be selected. The curves are defined in section 6.12. The curve is selected by setting the appropriate bit in the parameter as described in the Table. GC [7:0] Description 01h 02h 04h Parameter GC0 GC1 GC2 Curve Selected Gamma Curve 1 (G2.2) Gamma Curve 2 (G1.8) Gamma Curve 3 (G2.5) Gamma Curve 4 (G1.0) Restriction -Values of GC [7:0] not shown in table above are invalid and will not change the current selected Gamma curve until valid is received. Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes w w Default Status Power On Sequence S/W Reset H/W Reset w .m bt Register Availability re nd .co 08h GC3 Note: All other values are undefined. m Default Value 01h 01h 01h ---------------GAMSET (26H) Legend Command Parameter Display Flow Chart 1 Parameter: GC[7:0] st Action Mode Sequential transfer New Gamma Curve Loaded © ORISE Technology Co., Ltd. Proprietary & Confidential 42 Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.2.18. DISPOFF (28H): Display Off 28H Inst / Para DISPOFF st DISPOFF (Display Off) D/CX 0 WRX ↑ RDX 1 D17-8 D7 0 D6 0 D5 1 D4 0 D3 1 D2 0 D1 0 D0 0 (Code) (28H) - 1 Parameter NOTE: “-” Don’t care, can be set to VDDI or DGND level No Parameter -This command is used to enter into DISPLAY OFF mode. In this mode, the output from Frame Memory is disables and blank page inserted. -This command makes no change of contents of frame memory. -This command does not change any other status. -There will be no abnormal visible effect on the display. -Exit from this command by Display On (29H) Top-Left (0,0) Memory Display OFF Description VDDI VDD Gate Output Source Output VCOM Output bt re nd .co Display 1.6V-3.6V 2.6V-3.5V STOP 0V STOP Availability Yes Yes Yes Yes Yes Default Value Display off Display off Display off (Example) w w .m 0V 0V 43 Blanking display (over 1 frame display) * Internal counter Internal Oscillator VGH VGL AVDD IC Internal reset * Note: complete 1 frame display (ex: continue 2-falling edges of VS) Restriction -This command has no effect when module is already in Display Off mode. Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Register Availability Default Status Power On Sequence S/W Reset H/W Reset © ORISE Technology Co., Ltd. Proprietary & Confidential w m Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B Legend Display On Mode Command Parameter DISPOFF (28H) Display Flow Chart Action Mode Sequential transfer Display OFF Mode © ORISE Technology Co., Ltd. Proprietary & Confidential w w w .m 44 bt re nd .co m Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.2.19. DISPON (29H): Display On 29H Inst / Para DISPON st DISPON (Display On) D/CX 0 WRX ↑ RDX 1 D17-8 D7 0 D6 0 D5 1 D4 0 D3 1 D2 0 D1 0 D0 1 (Code) (29H) - 1 Parameter NOTE: “-” Don’t care, can be set to VDDI or DGND level No Parameter -This command is used to recover from DISPLAY OFF mode. Output from the Frame Memory is enabled. -This command makes no change of contents of frame memory. -This command does not change any other status. re nd .co Display ON m 1.6V-3.6V 2.6V-3.5V Memory Contents Memory Contents Top-Left (0,0) (Example) Memory Display VDD Description Gate Output Source Output VCOM Output Internal counter Blanking display (over 1 frame display) * w w .m STOP 0V 0V Start STOP Internal Oscillator VGH VGL AVDD IC Internal reset * Note: complete 1 frame display (ex: continue 2-falling edges of VS) Restriction -This command has no effect when module is already in Display On mode. Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Register Availability w Default Status Power On Sequence S/W Reset H/W Reset bt 45 VDDI Default Value Display off Display off Display off © ORISE Technology Co., Ltd. Proprietary & Confidential Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B Legend Display OFF Mode Command Parameter DISPON (29H) Display Flow Chart Action Mode Sequential transfer Display ON Mode © ORISE Technology Co., Ltd. Proprietary & Confidential w w w .m 46 bt re nd .co m Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.2.20. CASET (2AH): Column Address Set 2AH Inst / Para CASET 1 Parameter 2 Parameter 3 Parameter th rd nd st CASET (Column Address Set) D/CX 0 1 1 1 WRX ↑ ↑ ↑ ↑ RDX 1 1 1 1 D17-8 D7 0 XS15 XS7 XE15 D6 0 XS14 XS6 XE14 XE6 D5 1 XS13 XS5 XE13 XE5 D4 0 XS12 XS4 XE12 XE4 D3 1 XS11 XS3 XE11 XE3 D2 0 XS10 XS2 XE10 XE2 D1 1 XS9 XS1 XE9 XE1 D0 0 XS8 XS0 XE8 XE0 (Code) (2AH) 00h 00h 4 Parameter 1 1 XE7 ↑ NOTE: “-” Don’t care, can be set to VDDI or DGND level -This command is used to define area of frame memory where MCU can access. -This command makes no change on the other driver status. -Each value represents one column line in the Frame Memory. -The value of XS [15:0] and XE [15:0] are referred when RAMWR command comes. (Example) XS[15:0] Description XS [15:0] always must be equal to or less than XE [15:0] 1. 176x220 memory base (GM1, GM0 = “00”) (Parameter range: 0 ≤ XS [15:0] ≤ XE [15:0] ≤ 175 (00AFh)): MV=”0” If the “XS” or “XE” are large then 175d, it become 175d (Parameter range: 0 ≤ XS [15:0] ≤ XE [15:0] ≤ 219d (00DBh)): MV=”1” If the “XS” or “XE” are large then 219d, it become 219d 2. 176x176 memory base (GM1, GM0 = “01”) Restriction (Parameter range: 0 ≤ XS [15:0] ≤ XE [15:0] ≤ 175 (00AFh)): MV=”0” If the “XS” or “XE” are large then 175d, it become 175d (Parameter range: 0 ≤ XS [15:0] ≤ XE [15:0] ≤ 175 (00AFh)): MV=”1” If the “XS” or “XE” are large then 175d, it become 175d 1. 176x132 memory base (GM1, GM0 = “11”) (Parameter range: 0 ≤ XS [15:0] ≤ XE [15:0] ≤ 175 (00AFh)): MV=”0” If the “XS” or “XE” are large then 175d, it become 175d (Parameter range: 0 ≤ XS [15:0] ≤ XE [15:0] ≤ 131d (0083h)): MV=”1” If the “XS” or “XE” are large then 131d, it become 131d Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In w w When XS [15:0] or XE [15:0] is greater than maximum address like below, data of out of range will be ignored. w .m Availability Yes Yes Yes Yes Yes © ORISE Technology Co., Ltd. Proprietary & Confidential 47 bt re nd .co XE[15:0] m Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 1. 176x220 memory base (GM1, GM0 = “00”) Status Power On Sequence S/W Reset H/W Reset XS [15:0] 0000h Default Value XE [15:0] (MV=’0’) XE [15:0] (MV=’1’) 00AFh (175d) 00AFh (175d) 00DBh (219d) 00AFh (175d) Default Value XE [15:0] (MV=’0’) 2. 176x176 memory base (GM1, GM0 = “01”) Status Default Power On Sequence S/W Reset H/W Reset XS [15:0] 0000h XE [15:0] (MV=’1’) 00AFh (175d) 3. 176x132 memory base (GM1, GM0 = “11”) Status Power On Sequence S/W Reset H/W Reset XS [15:0] 0000h Default Value XE [15:0] (MV=’0’) XE [15:0] (MV=’1’) 00AFh (175d) 00AFh (175d) 0083h (132d) 00AFh (175d) Partial Mode CASET (2AH) Flow Chart rd w st nd 1 & 2 Parameter: YS[15:0] th w rd th RASET (2BH) w 1st & 2nd Parameter: XS[15:0] .m If Needed bt re nd .co 48 m Legend Command RAMWR (2CH) Parameter Display Image Data D1[B:0],D2[B:0]……Dn[B:0] Action Mode Note: B=17 Any Command Sequential transfer © ORISE Technology Co., Ltd. Proprietary & Confidential Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.2.21. RASET (2BH): Row Address Set 2BH Inst / Para RASET 1 Parameter 2 Parameter 3 Parameter th rd nd st RASET (Row Address Set) D/CX 0 1 1 1 WRX ↑ ↑ ↑ ↑ RDX 1 1 1 1 D17-8 D7 0 YS15 YS7 YE15 D6 0 YS14 YS6 YE14 YE6 D5 1 YS13 YS5 YE13 YE5 D4 0 YS12 YS4 YE12 YE4 D3 1 YS11 YS3 YE11 YE3 D2 0 YS10 YS2 YE10 YE2 D1 1 YS9 YS1 YE9 YE1 D0 1 YS8 YS0 YE8 YE0 (Code) (2BH) 00h 00h 4 Parameter 1 1 YE7 ↑ NOTE: “-” Don’t care, can be set to VDDI or DGND level -This command is used to define area of frame memory where MCU can access. -This command makes no change on the other driver status. -Each value represents one column line in the Frame Memory. -The value of YS [15:0] and YE [15:0] are referred when RAMWR command comes. Description YS[15:0] When YS [15:0] or YE [15:0] are greater than maximum row address like below, data of out of range will be ignored. (Parameter range: 0 ≤ YS [15:0] ≤ YE [15:0] ≤ 219 (0DBh)): MV=”0” If the “XS” or “XE” are large then 219d, it become 219d (Parameter range: 0 ≤ YS [15:0] ≤ YE [15:0] ≤ 175 (00AFh)): MV=”1” If the “XS” or “XE” are large then 175d, it become 175d 2. 176x176 memory base (GM1, GM0 = “01”) Restriction (Parameter range: 0 ≤ YS [15:0] ≤ YE [15:0] ≤ 175 (00AFh)): MV=”0” If the “XS” or “XE” are large then 175d, it become 175d (Parameter range: 0 ≤ YS [15:0] ≤ YE [15:0] ≤ 175 (00AFh)): MV=”1” If the “XS” or “XE” are large then 175d, it become 175d 3. 176x132 memory base (GM1, GM0 = “11”) (Parameter range: 0 ≤ YS [15:0] ≤ YE [15:0] ≤ 131 (0083h)): MV=”0” If the “XS” or “XE” are large then 131d, it become 131d (Parameter range: 0 ≤ YS [15:0] ≤ YE [15:0] ≤ 175 (00AFh)): MV=”1” If the “XS” or “XE” are large then 175d, it become 175d Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In w w 1. 176x220 memory base (GM1, GM0 = “00”) w YS [15:0] always must be equal to or less than YE [15:0] .m YE[15:0] bt Availability Yes Yes Yes Yes Yes 49 © ORISE Technology Co., Ltd. Proprietary & Confidential re nd .co (Example) m Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 1. 176x220 memory base (GM1, GM0 = “00”) Status Power On Sequence S/W Reset H/W Reset YS [15:0] 0000h Default Value YE [15:0] (MV=’0’) YE [15:0] (MV=’1’) 0DBh (219d) 0DBh (219d) 00AFh (175d) 0DBh (219d) Default Value YE [15:0] (MV=’0’) 2. 176x176 memory base (GM1, GM0 = “01”) Status Default Power On Sequence S/W Reset H/W Reset YS [15:0] 0000h YE [15:0] (MV=’1’) 00AFh (175d) 3. 176x132 memory base (GM1, GM0 = “11”) Status Power On Sequence S/W Reset H/W Reset YS [15:0] 0000h Default Value YE [15:0] (MV=’0’) YE [15:0] (MV=’1’) 0083h (131d) 0083h (131d) 00AFh (175d) 0083h (131d) Partial Mode CASET (2AH) bt re If Needed Flow Chart rd w st nd 1 & 2 Parameter: YS[15:0] th w rd th RASET (2BH) w st nd 1 & 2 Parameter: XS[15:0] .m nd .co If Needed 50 m Legend RAMWR (2CH) Command Parameter Image Data D1[B:0],D2[B:0]……Dn[B:0] Display Action Mode Any Command Note: B=17 Sequential transfer © ORISE Technology Co., Ltd. Proprietary & Confidential Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.2.22. RAMWR (2CH): Memory Write 2CH Inst / Para RAMWR 1 Parameter ∣ th st RAMWR (Memory Write) D/CX 0 1 1 WRX ↑ ↑ ↑ RDX 1 1 1 D17-8 D17-8 ∣ D7 0 D7 ∣ D6 0 D6 ∣ D6 D5 1 D5 ∣ D5 D4 0 D4 ∣ D4 D3 1 D3 ∣ D3 D2 1 D2 ∣ D2 D1 0 D1 ∣ D1 D0 0 D0 ∣ D0 (Code) (2CH) ∣ - N Parameter 1 1 D17-8 D7 ↑ NOTE: “-” Don’t care, can be set to VDDI or DGND level -This command is used to transfer data from MCU to frame memory. -This command makes no change to the other driver status. -When this command is accepted, the column register and the row register are reset to the Start Column/Start Row positions. -The Start Column/Start Row positions are different in accordance with MADCTR setting. (See section 6.6) -Then D[B:0] is stored in frame memory and the column register and the row register incremented as section 6.5.2. -Sending any other command can stop Frame Write. Description In all color modes, there is no restriction on length of parameters. 1. 176x220 memory base (GM1, GM0 = “00”) 176x220x18-bits memory can be written by this command Memory range: (0000h,0000h) -> (00AFh, 00DBh) Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In w w 3. 176x132 memory base (GM1, GM0 = “11”) 176x220x18-bits memory can be written by this command Memory range: (0000h,0000h) -> (00AFh, 0083h) w .m Restriction 2. 176x176 memory base (GM1, GM0 = “01”) 176x220x18-bits memory can be written by this command Memory range: (0000h,0000h) -> (00AFh, 00AFh) bt 51 re Availability Yes Yes Yes Yes Yes Default Value Contents of memory is set randomly Contents of memory is not cleared Contents of memory is not cleared Default Status Power On Sequence S/W Reset H/W Reset © ORISE Technology Co., Ltd. Proprietary & Confidential nd .co m Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B Legend RAMWR (2CH) Command Parameter Flow Chart Image Data D1[B:0],D2[B:0]……Dn[B:0] Display Action Mode Any Command Sequential transfer Note: B=17 © ORISE Technology Co., Ltd. Proprietary & Confidential w w w .m 52 bt re nd .co m Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.2.23. RGBSET (2DH): Colour Setting 2DH Inst / Para RGBSET 1 Parameter ∣ ∣ ∣ ∣ ∣ ∣ ∣ nd st RGBSET (Colour Setting) D/CX 0 1 1 1 1 1 1 1 1 WRX ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ RDX 1 1 1 1 1 1 1 1 1 D17-8 D7 0 R007 : Raa7 G007 : Gbb7 B007 : D6 0 R006 : Raa6 G006 : Gbb6 B006 : Bcc6 D5 1 R005 : Raa5 005 : Gbb5 B005 : Bcc5 D4 0 R004 : Raa4 G004 : Gbb4 B004 : Bcc4 D3 1 R003 : Raa3 G003 : Gbb3 B003 : Bcc3 D2 1 R002 : Raa2 G002 : Gbb2 B002 : Bcc2 D1 0 R001 : Raa1 G001 : Gbb1 B001 : Bcc1 D0 1 R000 : Raa0 G000 : Gbb0 B000 : Bcc0 (Code) (2DH) - -This command is used to define the LUT for 12-bits-to-18-bits / 16bits-to-18-bits colors depth conversations. -262K-colors used. -LUT has total trough 128 parameters. -In this condition, 4K-color (4-4-4) and 65K-color(5-6-5) data input are transferred 6(R)-6(G)-6(B) through RGB LUT table. (aa=31, bb=63, cc=31) -This command has no effect on other commands/parameters and Contents of frame memory. Restriction Do not send any command before the last data is sent or LUT is not defined correctly. Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Description .m bt -Visible change takes effect next time the Frame Memory is written . re Default Status Power On Sequence S/W Reset H/W Reset w w Register Availability w nd .co Default Value LUT default value Contents of the look-up table protected LUT default value m Availability Yes Yes Yes Yes Yes n Parameter 1 1 Bcc7 ↑ NOTE: “-” Don’t care, can be set to VDDI or DGND level Legend RGBSET (2DH) Command Parameter 1 Parameter: Flow Chart th st Display ∣ ∣ n arameter: Action Mode Sequential transfer © ORISE Technology Co., Ltd. Proprietary & Confidential 53 Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.2.24. RAMHD (2EH): Memory Read 2EH Inst / Para RAMHD 1 Parameter 2 Parameter ∣ th nd st RAMHD (Memory Read) D/CX 0 1 1 1 WRX ↑ 1 1 1 RDX 1 ↑ ↑ ↑ D17-8 D17-8 ∣ D7 0 D7 ∣ D6 0 D6 ∣ D6 D5 1 D5 ∣ D5 D4 0 D4 ∣ D4 D3 1 D3 ∣ D3 D2 1 D2 ∣ D2 D1 1 D1 ∣ D1 D0 0 D0 ∣ D0 (Code) (2EH) ∣ - (N+1) Parameter 1 1 D17-8 D7 ↑ NOTE: “-” Don’t care, can be set to VDDI or DGND level -This command is used to transfer data from frame memory to MCU. -This command makes no change to the other driver status. -When this command is accepted, the column register and the row register are reset to the Start Column/Start Row positions. Description -Then D[B:0] is read back from the frame memory and the column register and the row register incremented as section 6.5.2. -Frame Read can be canceled by sending any other command. -See section 6.4 “Data color coding” for color coding (18-bits cases), when there is used 12, 16, and 18-bits data lines for image data. -Memory read is only possible via the SPI and parallel interface. Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In .m bt Restriction -In all color modes, the Frame Read is always 18-bits and there is no restriction on length of parameters. re w Default Status Power On Sequence S/W Reset H/W Reset w w Register Availability Note: B=17 RAMRD (2EH) Legend Dummy Read Flow Chart Command nd .co -The Start Column/Start Row positions are different in accordance with MADCTR setting. (See section 6.7) Default Value Contents of memory is set randomly Contents of memory is not cleared Contents of memory is not cleared m Availability Yes Yes Yes Yes Yes Parameter Display Image Data D1[B:0],D2[B:0]……Dn[B:0] Action Mode Sequential transfer Any Command © ORISE Technology Co., Ltd. Proprietary & Confidential 54 Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.2.25. PTLAR (30H): Partial Area 30H Inst / Para PTLAR 1 Parameter 2 Parameter 3 Parameter th rd nd st PTLAR (Partial Area) D/CX 0 1 1 1 WRX ↑ ↑ ↑ ↑ RDX 1 1 1 1 D17-8 D7 0 PSL15 PSL7 PEL15 D6 0 PSL14 PSL6 PEL14 PEL6 D5 1 PSL13 PSL5 PEL13 PEL5 D4 1 PSL12 PSL4 PEL12 PEL4 D3 0 PSL11 PSL3 PEL11 PEL3 D2 0 PSL10 PSL2 PEL10 PEL2 D1 0 PSL9 PSL1 PEL9 PEL1 D0 0 PSL8 PSL0 PEL8 PEL0 (Code) (30H) 00h 00h 4 Parameter 1 1 PEL7 ↑ NOTE: “-” Don’t care, can be set to VDDI or DGND level -This command defines the partial mode’s display area. -There are 4 parameters associated with this command, the first defines the Start Row (PSL) and the second the End Row (PEL), as illustrated in the figures below. PSL and PEL refer to the Frame Memory row address counter. Start Row PSL [15:0] Non-displaying Area PEL [15:0] End Row Non-displaying Area -If End Row > Start Row, when MADCTL ML=’1’ End Row w w Description w PEL [15:0] .m bt 55 Non-displaying Area Partial Display Area PSL [15:0] Start Row Non-displaying Area -If End Row < Start Row, when MADCTL ML=’0’ End Row PEL [15:0] Non-displaying Area PSL [15:0] Start Row Partial Display Area Partial Display Area -If End Row = Start Row then the Partial Area will be one row deep. © ORISE Technology Co., Ltd. Proprietary & Confidential re nd .co -If End Row > Start Row, when MADCTL ML=’0’ Partial Display Area m Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B -PEL [15:0] always must be equal to or less than PSL [15:0] -When PEL [15:0] or PSL [15:0] are greater than maximum row address like below, data of out of range will be ignored. 1. 176x220 memory base (GM1, GM0 = “00”) (Parameter range: 0 ≤ PSL [15:0] ≤ PEL [15:0] ≤ 219 (0DBh)) If the “PSL” or “PEL” are large then 219d, it become 219d Restriction 2. 176x176 memory base (GM1, GM0 = “01”) (Parameter range: 0 ≤ PSL [15:0] ≤ PEL [15:0] ≤ 176 (00AFh)) If the “PSL” or “PEL” are large then 176d, it become 176d 3. 176x132 memory base (GM1, GM0 = “11”) (Parameter range: 0 ≤ PSL [15:0] ≤ PEL [15:0] ≤ 131 (0083h)) If the “PSL” or “PEL” are large then 131d, it become 131d 1. 176x220 memory base (GM1, GM0 = “00”) Status Power On Sequence S/W Reset H/W Reset re bt 56 nd .co PSL [15:0] 0000h PSL [15:0] 0000h PSL [15:0] 0000h Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes m Default Value PEL [15:0] 00DBh 2. 176x176 memory base (GM1, GM0 = “01”) Status Default .m Default Value PEL [15:0] 00AFh w 3. 176x132 memory base (GM1, GM0 = “11”) Status Default Value PEL [15:0] 0083h Power On Sequence S/W Reset H/W Reset © ORISE Technology Co., Ltd. Proprietary & Confidential w Power On Sequence S/W Reset H/W Reset w Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 1. To Enter Partial Mode PTLAR (30H) 1 & 2 Parameter: PSL[15:0] 3 & 4 Parameter: PEL[15:0] Flow Chart rd th st nd 2. To Exit Partial Mode Partial Mode DISPOFF (28H) NORON (13H) Partial Mode OFF Optional to prevent tearing effect image display Legend Command PTLON (12H) RAMRW (2CH) Partial Mode Parameter m Display nd .co DISON (29H) Image Data D1[B:0],D2[B:0]… …Dn[B:0] Action Mode Sequential transfer © ORISE Technology Co., Ltd. Proprietary & Confidential w 57 w w .m bt re Note: B=17 Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.2.26. SCRLAR (33H): Scroll Area 33H Inst / Para SCRLAR 1 Parameter 2 Parameter 3 Parameter 4 Parameter 5 Parameter th th th rd nd st SCRLAR (Scroll Area) D/CX 0 1 1 1 1 1 WRX ↑ ↑ ↑ ↑ ↑ ↑ RDX 1 1 1 1 1 1 D17-8 D7 0 TFA15 TFA7 VSA7 BFA15 D6 0 TFA14 TFA6 VSA6 BFA14 BFA6 D5 1 TFA13 TFA5 VSA5 BFA13 BFA5 D4 1 TFA12 TFA4 VSA4 BFA12 BFA4 D3 0 TFA11 TFA3 VSA3 BFA11 BFA3 D2 0 TFA10 TFA2 VSA2 BFA10 BFA2 D1 1 TFA9 TFA1 VSA9 VSA1 BFA9 BFA1 D0 1 TFA8 TFA0 VSA8 VSA0 BFA8 BFA0 00h 00h (Code) (33H) 00h 00h VSA15 VSA14 VSA13 VSA12 VSA11 VSA10 6 Parameter 1 1 BFA7 ↑ NOTE: “-” Don’t care, can be set to VDDI or DGND level -When MADCTR ML=0 st nd Top-Left (0,0) Top Fixed Area TFA [15:0] .m 58 bt －The 5 & 6 parameter BFA [15:0] describes the Bottom Fixed Area (in No. of lines from Bottom of the Frame Memory and Display). －TFA, VSA and BFA refer to the Frame Memory row address. th th re Scroll Fixed Area Description -When MADCTR ML=1 －The 1 & 2 parameter TFA [15:0] describes the Top Fixed Area (in No. of lines from Bottom of the Frame Memory and Display). rd th －The 3 & 4 parameter VSA [15:0] describes the height of the Vertical Scrolling Area (in No. of lines of the Frame Memory [not the display] from the Vertical Scrolling Start Address) －The first line appears immediately after the top most line of the Top Fixed Area. －The 5 & 6 parameter BFA [15:0] describes the Bottom Fixed Area (in No. of lines from Top of the Frame Memory and Display). Top-Left (0,0) th th st nd w w VSFA [15:0] Bottom Fixed Area BFA [15:0] Bottom Fixed Area BFA [15:0] Scroll Fixed Area VSFA [15:0] Top Fixed Area TFA [15:0] First line read from frame memory -See Section 6.5.4 for details of the Memory to Display Mapping. © ORISE Technology Co., Ltd. Proprietary & Confidential w nd .co －The 1 & 2 parameter TFA [15:0] describes the Top Fixed Area (in No. of lines from Top of the Frame Memory and Display). rd th －The 3 & 4 parameter VSA [15:0] describes the height of the Vertical Scrolling Area (in No. of lines of the Frame Memory [not the display] from the Vertical Scrolling Start Address) －The first line appears immediately after the bottom most line of the Top Fixed Area. m -This command defines the Vertical Scrolling Area of the display. First line read from frame memory Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 1. 176x220 memory base (GM1, GM0 = “00”) -The condition is 0 ≤ (TFA+VSA+BFA) ≤ 220, otherwise Scrolling mode is undefined. 2. 176x176 memory base (GM1, GM0 = “01”) Restriction -The condition is 0 ≤ (TFA+VSA+BFA) ≤ 176, otherwise Scrolling mode is undefined. 3. 176x132 memory base (GM1, GM0 = “11”) -The condition is 0 ≤ (TFA+VSA+BFA) ≤ 132, otherwise Scrolling mode is undefined. -In Vertical Scroll Mode, MADCTR parameter MV should be set to ‘0’-this only affects the Frame Memory Write. Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In 1. 176x220 memory base (GM1, GM0 = “00”) Status Power On Sequence S/W Reset H/W Reset 2. 176x176 memory base (GM1, GM0 = “01”) Status Default Power On Sequence S/W Reset H/W Reset TFA [15:0] 0000h Availability Yes Yes Yes Yes Yes Register Availability nd .co re TFA [15:0] 0000h TFA [15:0] 0000h 59 m Default Value VSA [15:0] 00DCh BFA [15:0] 0000h Default Value VSA [15:0] 00B0h BFA [15:0] 0000h 3. 176x132 memory base (GM1, GM0 = “11”) .m bt w Status Default Value VSA [15:0] 0084h BFA [15:0] 0000h © ORISE Technology Co., Ltd. Proprietary & Confidential w Power On Sequence S/W Reset H/W Reset w Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 1. To Enter Vertical Scroll Mode Normal Mode SCRLAR (33H) 1st & 2nd Parameter: TFA[15:0] 3rd & 4th Parameter VSA[15:0] 5th & 6th Parameter BFA[15:0] Legend Command Parameter Display Action Mode Sequential transfer nd .co 1st & 2nd Parameter XS[15:0] 3rd & 4th Parameter XE[15:0] RASET (2BH) m Redefines the Frame Memory Window that the scroll data will be written to. See NOTE Optional – It may be necessary to redefine the Frame Memory Write Direction. Apr. 25, 2006 Preliminary Version: 0.1 CASET (2AH) 1st & 2nd Parameter YS[15:0] 3rd & 4th Parameter YE[15:0] w w © ORISE Technology Co., Ltd. Proprietary & Confidential w .m Parameter: MY,MX,MV,ML,RGB RAMRW (2CH) Scroll Image Data VSCSAD (37H) 1st & 2nd Parameter SSA[15:0] Scroll Mode NOTE: The Frame Memory Window size must be defined correctly otherwise undesirable image will be displayed. bt 60 Flow Chart Only required for non-rolling scrolling MADCTR (36H) re Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 2. Continuous Scroll Normal Mode CASET (2AH) 1 st Legend Command Parameter Display &2 nd Parameter XS[15:0] Action Mode Sequential transfer 3rd & 4th Parameter XE[15:0] RASET (2BH) RAMRW (2CH) Only required for non-rolling scrolling Scroll Image Data Flow Chart w w w .m 1st & 2nd Parameter SSA[15:0] 3. To Exit Vertical Scroll Mode Scroll Mode DISOFF (28H) NORON (13H) / PTLON (12H) Scroll Mode OFF RAMRW (2CH) Image Data D1[B:0],D2[B:0]… …Dn[B:0] DISON (29H) OptionTo prevent Tearing Effect Image Display Note: B=17 Note: Scroll Mode can be exit by both the Normal Display Mode On (13H) and Partial Mode On (12H) commands. © ORISE Technology Co., Ltd. Proprietary & Confidential bt 61 VSCSAD (37H) re nd .co 3rd & 4th Parameter YE[15:0] m Apr. 25, 2006 Preliminary Version: 0.1 1st & 2nd Parameter YS[15:0] Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.2.27. TEOFF (34H): Tearing Effect Line OFF 34H Inst / Para TEOFF st TEOFF (Tearing Effect Line OFF) D/CX 0 WRX ↑ RDX 1 D17-8 D7 0 D6 0 D5 1 D4 1 D3 0 D2 1 D1 0 D0 0 (Code) (34H) - 1 Parameter NOTE: “-” Don’t care, can be set to VDDI or DGND level No Parameter Description Restriction -This command is used to turn OFF (Active Low) the Tearing Effect output signal from the TE signal line. -This command has no effect when Tearing Effect output is already OFF. Status Default Power On Sequence S/W Reset H/W Reset re nd .co OFF Default Value RCM1, RCM0 = “00”, “1x” RCM1, RCM0 = “01” ON .m bt m Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Legend Command TE Line Output ON w w Parameter Display Flow Chart w TEOFF (34H) Action Mode Sequential transfer TE Line Output OFF © ORISE Technology Co., Ltd. Proprietary & Confidential 62 Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.2.28. TEON (35H): Tearing Effect Line ON 35H Inst / Para TEON st TEON (Tearing Effect Line ON) D/CX 0 WRX ↑ RDX 1 D17-8 D7 0 0 D6 0 0 D5 1 0 D4 1 0 D3 0 0 D2 1 0 D1 0 0 D0 1 TELOM (Code) (35H) 00h 1 Parameter 1 1 ↑ NOTE: “-” Don’t care, can be set to VDDI or DGND level -This command is used to turn ON the Tearing Effect output signal from the TE signal line. -This output is not affected by changing MADCTR bit ML. -The Tearing Effect Line On has one parameter, which describes the mode of the Tearing Effect Output Line. (“-“=Don’t Care). －When M=’0’: The Tearing Effect Output line consists of V-Blanking information only. Description Vertical time scale －When M=’1’: re The Tearing Effect Output line consists of both V-Blanking and H-Blinking information. nd .co tvdl tvdl m Availability Yes Yes Yes Yes Yes tvdh tvdh Note: During Sleep In Mode with Tearing Effect Line On, Tearing Effect Output pin will be active Low. Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In w w w Status Restriction -This command has no effect when Tearing Effect output is already OFF. .m Vertical time scale bt Default Value RCM1, RCM0 = “00”, “1x” RCM1, RCM0 = “01” OFF & TELOM=0 ON & TELOM=0 Default Power On Sequence S/W Reset H/W Reset Legend TE Line Output OFF Command Parameter Flow Chart TEON (35H) 1st Parameter: TELOM Display Action Mode Sequential transfer TE Line Output ON © ORISE Technology Co., Ltd. Proprietary & Confidential 63 Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.2.29. MADCTR (36H): Memory Data Access Control 36H Inst / Para MADCTR st MADCTR (Memory Data Access Control) D/CX 0 WRX ↑ RDX 1 D17-8 D7 0 D6 0 MX D5 1 MV D4 1 ML D3 0 RGB D2 1 MH D1 1 0 D0 0 0 (Code) (36H) 00h 1 Parameter 1 1 MY ↑ NOTE: “-” Don’t care, can be set to VDDI or DGND level -This command defines read/ write scanning direction of frame memory. -This command makes no change on the other driver status. -Bit Assignment Bit MY MX MV ML RGB NAME Row Address Order Column Address Order Row/Column Exchange Vertical Refresh Order RGB-BGR ORDER DESCRIPTION ML: Vertical Refresh Order Top-Left (0,0) Memory bt RGB re Sent First Sent 2nd Sent 3rd Sent Last Sent Last Sent 3rd Sent 2nd Sent First w Description Top-Left (0,0) w w .m Memory ML=’0’ ML=’1’ RGB: RGB-BGR Order RGB=”0” Driver IC RGB RGB RGB nd .co RGB RGB BGR BGR 64 LCD vertical refresh direction control ‘0’ = LCD vertical refresh Top to Bottom ‘1’ = LCD vertical refresh Bottom to Top Color selector switch control ‘0’ =RGB color filter panel, ‘1’ =BGR color filter panel) Display Display m RGB BGR BGR These 3bits controls MCU to memory write/read direction. (See Section 8.11) RGB=”1” Driver IC RGB RGB RGB RGB RGB BGR BGR LCD Panel LCD Panel Restriction D1 and D0 of the 1 parameter are set to “00” internally. st © ORISE Technology Co., Ltd. Proprietary & Confidential Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Register Availability Default Status Power On Sequence S/W Reset H/W Reset Default Value MY=0,MX=0,MV=0,ML=0,RGB=0, No Change MY=0,MX=0,MV=0,ML=0,RGB=0, m nd .co re bt 65 Legend Command MADCTR (36H) Flow Chart Parameter Display 1 Parameter: MY, MX, ML, RGB st Action Mode Sequential transfer © ORISE Technology Co., Ltd. Proprietary & Confidential w w w .m Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.2.30. VSCSAD (37H): Vertical Scroll Start Address of RAM 37H Inst / Para VSCSAD 1 Parameter nd st VSCSAD (Vertical Scroll Start Address of RAM) D/CX 0 1 WRX ↑ ↑ RDX 1 1 D17-8 D7 0 D6 0 SSA6 D5 1 SSA5 D4 1 SSA4 D3 0 SSA3 D2 1 SSA2 D1 1 SSA9 SSA1 D0 1 SSA8 SSA0 (Code) (37h) SSA15 SSA14 SSA13 SSA12 SSA11 SSA10 2 Parameter 1 1 SSA7 ↑ NOTE: “-” Don’t care, can be set to VDDI or DGND level -This command is used together with Vertical Scrolling Definition (33h). These two commands describe the scrolling area and the scrolling mode. -The Vertical Scrolling Start Address command has one parameter which describes which line in the Frame Memory will be written as the first line after the last line of the Top Fixed Area on the display as illustrated below: -Exit from V-scrolling mode by commands Partial mode On (12h) or Normal mode On (13h). (Example) Memory re 0 1 2 3 ∣ ∣ 158 159 159 158 ∣ ∣ 3 2 1 0 Top-Left (0,0) nd .co Scan address Scan address When MADCTR ML= ‘0’ Example: －When Top Fixed Area=Bottom Fixed Area=00, Vertical Scrolling Area=220 and Vertical Scrolling Pointer SSA= ’3’. m G1 G2 G3 G4 | | G159 G160 G1 G2 G3 G4 | | G159 G160 -This command Start the scrolling. Display w When MADCTR ML = ‘1’ Example: －When Top Fixed Area= Bottom Fixed Area=00, Vertical Scrolling Area=220 and SSA= ’3’ w w (Example) Top-Left (0,0) Description .m Memory SSA[15:0] Scroll start address bt Display SSA[15:0] Scroll start address NOTE: -When new Pointer position and Picture Data are sent, the result on the display will happen at the next Panel Scan to avoid tearing effect. -SSA refers to the Frame Memory scan address. -Since the value of the Vertical Scrolling Start Address is absolute (with reference to the Frame Memory), it must not enter the fixed area (defined by Vertical Scrolling Definition (33h)-otherwise undesirable image will be displayed on the Panel. Restriction SSA[15:0] is based on 1-line unit. -SSA[15:0] = 0000h, 0001h, 0002h, 0003h, … , 00A1h © ORISE Technology Co., Ltd. Proprietary & Confidential 66 Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes No No Yes Register Availability Default Status Power On Sequence S/W Reset H/W Reset See Vertical Scrolling Definition (33h) description. Default Value 0000h 0000h 0000h Flow Chart © ORISE Technology Co., Ltd. Proprietary & Confidential w w w .m 67 bt re nd .co m Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.2.31. IDMOFF (38H): Idle Mode Off 38H Inst / Para IDMOFF st IDMOFF (Idle Mode Off) D/CX 0 WRX ↑ RDX 1 D17-8 D7 0 D6 0 D5 1 D4 1 D3 1 D2 0 D1 0 D0 0 (Code) (38H) - 1 Parameter NOTE: “-” Don’t care, can be set to VDDI or DGND level No Parameter -This command is used to recover from Idle mode on. -There will be no abnormal visible effect on the display mode change transition. Description -In the idle off mode, 1. LCD can display 4k, 65k and 262k -colors. 2. Normal frame frequency is applied. Register Availability Default w .m Status Power On Sequence S/W Reset H/W Reset re bt nd .co 68 Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In m Restriction -This command has no effect when module is already in idle off mode. Availability Yes Yes Yes Yes Yes Default Value Idle Mode Off Idle Mode Off Idle Mode Off Legend Command w Idle mode ON w Parameter Display Flow Chart IDMOFF (38) Action Idle mode OFF Mode Sequential transfer © ORISE Technology Co., Ltd. Proprietary & Confidential Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.2.32. IDMON (39H): Idle Mode On 39H Inst / Para IDMON st IDMON (Idle Mode On) D/CX 0 WRX ↑ RDX 1 D17-8 D7 0 D6 0 D5 1 D4 1 D3 1 D2 0 D1 0 D0 1 (Code) (39H) - 1 Parameter NOTE: “-” Don’t care, can be set to VDDI or DGND level No Parameter -This command is used to enter into Idle mode on. -There will be no abnormal visible effect on the display mode change transition. -In the idle on mode, 1. Color expression is reduced. The primary and the secondary colors using MSB of each R,G and B in the Frame Memory, 8 color depth data is displayed. 2. 8-Color mode frame frequency is applied. 3. Exit from IDMON by Idle Mode Off (38H) command Top-Left (0,0) Memory bt 69 re This command has no effect when module is already in idle on mode. Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Power On Sequence S/W Reset H/W Reset Availability Yes Yes Yes Yes Yes Default Value Idle Mode Off Idle Mode Off Idle Mode Off Description nd .co Display “x“ Don’t care B5 B4 B3 B4 B1 B0 0xxxxx 1xxxxx 0xxxxx 1xxxxx 0xxxxx 1xxxxx 0xxxxx 1xxxxx (Example) Restriction Register Availability Default © ORISE Technology Co., Ltd. Proprietary & Confidential w Color Black Blue Red Magenta Green Cyan Yellow White R5 R4 R3 R2 R1 R0 0xxxxx 0xxxxx 1xxxxx 1xxxxx 0xxxxx 0xxxxx 1xxxxx 1xxxxx G5 G4 G3 G2 G1 G0 0xxxxx 0xxxxx 0xxxxx 0xxxxx 1xxxxx 1xxxxx 1xxxxx 1xxxxx w w .m m Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B Legend Command Idle mode OFF Parameter Display Flow Chart IDMOFF (39) Action Mode Idle mode ON Sequential transfer © ORISE Technology Co., Ltd. Proprietary & Confidential w w w .m 70 bt re nd .co m Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.2.33. COLMOD (3AH): Interface Pixel Format 3AH Inst / Para COLMOD st COLMOD (Interface Pixel Format) D/CX 0 WRX ↑ RDX 1 D17-8 D7 0 D6 0 VIPF2 D5 1 VIPF1 D4 1 VIPF0 D3 1 D3 D2 0 IFPF2 D1 1 IFPF1 D0 0 IFPF0 (Code) (3AH) 66h 1 Parameter 1 1 VIPF3 ↑ NOTE: “-” Don’t care, can be set to VDDI or DGND level Description w w Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In .m Restriction There is no visible effect until the Frame Memory is written to. Availability Yes Yes Yes Yes Yes Status Default Power On Sequence S/W Reset H/W Reset Example: w bt RGB Interface Color Format 16-bits/pixel (1-times data transfer) 18-bits/pixel (1-times data transfer) Reserved 18-bits/pixel (3-times data transfer) Others are no define and invalid Note1: In 12-bits/Pixel, 16-bits/Pixel or 18-bits/Pixel mode, the LUT is applied to transfer data into the Frame Memory. Note2: When RGB I/F the 12-bit/pixel don’t care Note 3: When VIPF[3:0]=”1110”,6-bits data width of 3-times transfer is used to transmit 1 pixel data with the 18-bits color depth information. VIPF[3:0] 0101 5 0110 6 0111 7 1110 14 re nd .co Default Value IFPF[2:0] VIPF[3:0] 0101 (16-bits/pixel) 0110 (18-bits/pixel) No Change No Change 0101 (16-bits/pixel) 0110 (18-bits/pixel) m This command is used to define the format of RGB picture data, which is to be transferred via the MCU interface and RGB interface. The formats are shown in the table: IFPF[2:0] MCU Interface Color Format 011 3 12-bits/pixel 101 5 16-bits/pixel 110 6 18-bits/pixel 111 7 Reserved Others are no define and invalid Legend 16-bits/Pixel Mode Command Parameter COLMOD (3AH) Flow Chart 1 Parameter st Display Action Mode Sequential transfer 18-bits/Pixel Mode © ORISE Technology Co., Ltd. Proprietary & Confidential 71 Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.2.34. RDID1 (DAH): Read ID1 Value DAH Inst / Para RDID1 1 Parameter nd st RDID1 (Read ID1 Value) D/CX 0 1 WRX ↑ 1 RDX 1 ↑ D17-8 D7 1 D6 1 ID16 D5 0 ID15 D4 1 ID14 D3 1 ID13 D2 0 ID12 D1 1 ID11 D0 0 ID10 (Code) (DAH) 38h 2 Parameter 1 1 ID17 ↑ NOTE: “-” Don’t care, can be set to VDDI or DGND level -This read byte returns 8-bits LCD module’s manufacturer ID Description -The 1 parameter is dummy data -The 2 parameter (ID17 to ID10): LCD module’s manufacturer ID. nd NOTE: See command RDDID (04H), 2 parameter. nd st Register Availability Default w .m Status Power On Sequence S/W Reset H/W Reset re bt nd .co RDID1 (DAH) Dummy Read nd Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In m 72 Restriction Availability Yes Yes Yes Yes Yes Default Value 38h 38h 38h w Serial I/F Mode Partial I/F Mode Host Driver Legend Command w RDID1 (DAH) Parameter Display Flow Chart Send 2 parameter: ID1[7:0] nd Action Mode Send 2 parameter: ID1[7:0] Sequential transfer © ORISE Technology Co., Ltd. Proprietary & Confidential Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.2.35. RDID2 (DBH): Read ID2 Value DBH Inst / Para RDID2 1 Parameter nd st RDID2 (Read ID2 Value) D/CX 0 1 WRX ↑ 1 RDX 1 ↑ D17-8 D7 1 D6 1 ID26 D5 0 ID25 D4 1 ID24 D3 1 ID23 D2 0 ID22 D1 1 ID21 D0 1 ID20 (Code) (DBH) 80h 2 Parameter 1 1 ID27 ↑ NOTE: “-” Don’t care, can be set to VDDI or DGND level -This read byte returns 8-bits LCD module/driver version ID Description -The 1 parameter is dummy data -The 2 parameter (ID26 to ID20): LCD module/driver version ID rd NOTE: See command RDDID (04H), 3 parameter. nd st Register Availability Default w .m Status Power On Sequence S/W Reset H/W Reset re bt nd .co Partial I/F Mode RDID2 (DBH) Dummy Read Send 2 parameter: ID2[7:0] nd Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In m 73 Restriction Availability Yes Yes Yes Yes Yes Default Value 80h 80h 80h Serial I/F Mode RDID2 (DBH) Legend Command w w Host Driver Parameter Display Flow Chart Send 2 parameter: ID2[7:0] nd Action Mode Sequential transfer © ORISE Technology Co., Ltd. Proprietary & Confidential Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.2.36. RDID3 (DCH): Read ID3 Value DCH Inst / Para RDID3 1 Parameter nd st RDID3 (Read ID2 Value) D/CX 0 1 WRX ↑ 1 RDX 1 ↑ D17-8 D7 1 D6 1 ID36 D5 0 ID35 D4 1 ID34 D3 1 ID33 D2 1 ID32 D1 0 ID31 D0 0 ID30 (Code) (DCH) 62h 2 Parameter 1 1 ID37 ↑ NOTE: “-” Don’t care, can be set to VDDI or DGND level -This read byte returns 8-bits LCD module/driver ID. Description -The 1 parameter is dummy data -The 2 parameter (ID37 to ID30): LCD module/driver ID. th NOTE: See command RDDID (04H), 4 parameter. nd st Register Availability Default w .m Status Power On Sequence S/W Reset H/W Reset re bt nd .co RDID3 (DCH) Dummy Read nd Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In m 74 Restriction - Availability Yes Yes Yes Yes Yes Default Value 62h 62h 62h w Serial I/F Mode RDID3 (DCH) Flow Chart Partial I/F Mode Host Driver Legend Command w Parameter Display Send 2 parameter: ID3[7:0] nd Action Mode Send 2 parameter: ID3[7:0] Sequential transfer © ORISE Technology Co., Ltd. Proprietary & Confidential Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.2.37. SRGBOFF (AAH): Separate RGB Gamma OFF AAH Inst / Para SRGBOFF st SRGBOFF (Separate RGB Gamma OFF) D/CX 0 WRX ↑ RDX 1 D17-8 D7 1 D6 0 D5 1 D4 0 D3 1 D2 0 D1 1 D0 0 (Code) (AAH) - 1 Parameter NOTE: “-” Don’t care, can be set to VDDI or DGND level No Parameter Description Restriction -This command is used to turn OFF the separate RGB gamma function. -This command has no effect when separate RGB gamma function OFF. Status Default Power On Sequence S/W Reset H/W Reset re nd .co OFF Default Value RCM1, RCM0 = “00”, “1x” RCM1, RCM0 = “01” ON .m bt m Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Legend Command w Separate RGB gamma ON w Parameter Display Flow Chart w SRGBOFF (AAH) Action Mode Sequential transfer Separate RGB gamma OFF © ORISE Technology Co., Ltd. Proprietary & Confidential 75 Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.2.38. SRGBOFF (ABH): Separate RGB Gamma ON ABH Inst / Para SRGBON st SRGBOFF (Separate RGB Gamma ON) D/CX 0 WRX ↑ RDX 1 D17-8 D7 1 D6 0 D5 1 D4 0 D3 1 D2 0 D1 1 D0 1 (Code) (ABH) - 1 Parameter NOTE: “-” Don’t care, can be set to VDDI or DGND level No Parameter Description Restriction -This command is used to turn On the separate RGB gamma function. -In this mode, It only the gamma curve 2.2 (GC0) can be separated to R, G, and B gamma curve -This command has no effect when separate RGB gamma function ON. Status Default Power On Sequence S/W Reset H/W Reset re nd .co OFF Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Value RCM1, RCM0 = “00”, “1x” RCM1, RCM0 = “01” ON .m bt m w Separate RGB gamma OFF w Legend Command Parameter Display Flow Chart w SRGBON (ABH) Action Separate RGB gamma ON Mode Sequential transfer © ORISE Technology Co., Ltd. Proprietary & Confidential 76 Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.2.39. VSYNCOFF (ACH): VSYNC Interface OFF ACH Inst / Para VSYNCOFF st VSYNCOFF (VSYNC Interface OFF) D/CX 0 WRX ↑ RDX 1 D17-8 D7 1 D6 0 D5 1 D4 0 D3 1 D2 1 D1 0 D0 0 (Code) (ACH) -- 1 Parameter NOTE: “-” Don’t care, can be set to VDDI or DGND level No Parameter Description Restriction -This command is used to turn OFF the VSYNC interface function. -This command has no effect when VSYNC interface OFF. -Input Vs signal for more than 1 frame period after turn OFF the VSYNC I/F Status Default Power On Sequence S/W Reset H/W Reset re nd .co OFF Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Value RCM1, RCM0 = “00”, “1x” RCM1, RCM0 = “01” ON .m bt m VSYNC Interface function ON w Legend Command w w VSYNCOFF (ACH) Wait more than 1 frame Parameter Display Flow Chart Action Mode Sequential transfer VSYNC Interface function OFF Input Vs signal foe more than 1 frame period after turn OFF the VSYNC I/F © ORISE Technology Co., Ltd. Proprietary & Confidential 77 Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.2.40. VSYNCON (ADH): VSYNC Interface ON ADH Inst / Para VSYNCON st VSYNCOFF (VSYNC Interface ON) D/CX 0 WRX ↑ RDX 1 D17-8 D7 1 D6 0 D5 1 D4 0 D3 1 D2 1 D1 0 D0 1 (Code) (ADH) -- 1 Parameter NOTE: “-” Don’t care, can be set to VDDI or DGND level No Parameter Description Restriction -This command is used to turn ON the VSYNC interface function. -This command has no effect when VSYNC interface ON. -Input VS signal before turn On the VSYNC I/F Status Default Power On Sequence S/W Reset H/W Reset re nd .co OFF Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Default Value RCM1, RCM0 = “00”, “1x” RCM1, RCM0 = “01” ON .m bt m VSYNC Interface function OFF w Legend Command w w VSYNCON (ADH) Wait more than 1 frame Parameter Display Flow Chart Action Mode VSYNC Interface function ON Sequential transfer Note: Input VS signal before turn On the VSYNC I/F © ORISE Technology Co., Ltd. Proprietary & Confidential 78 Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.2.41. VSCTR1 (AEH): VSYNC Interface function control 1 AEH Inst / Para VSCTR1 st VSYNCTR1 (VSYNC Interface function control 1) D/CX 0 WRX ↑ RDX 1 D17-8 D7 1 D6 0 D5 1 D4 0 D3 1 D2 1 D1 0 D0 1 (Code) (AEH) 2Eh 1 Parameter 1 VSFP3 VSFP2 VSFP1 VSFP0 VSBP3 VSBP2 VSBP1 VSBP0 1 ↑ NOTE: “-” Don’t care, can be set to VDDI or DGND level -Set the back porch and front porch on the VSYNC interface. The setting becomes effective as soon as the command is received. -VSFP: Front porch set on VSYNC I/F -VSBP: Back porch set on VSYNC I/F VSBP[3:0] Front porch period (Line) VSFP[3:0] 0000 0 Setting inhibited 0001 1 Setting inhibited 0010 2 2-lines 0011 3 3-lines 0100 4 4-lines 0101 5 5-lines 0110 6 6-lines 0111 7 7-lines 1000 8 8-lines 1001 9 9-lines 1010 10 10-lines 1011 11 11-lines 1100 12 12-lines 1101 13 13-lines 1110 14 14-lines 1111 15 Setting inhibited Description Register Availability Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In w Restriction -The command is enabled by VSYNCON (ADH) Availability Yes Yes Yes Yes Yes w Status Default Power On Sequence S/W Reset H/W Reset VSFP[3:0] 2d No Change 2d w Setting inhibited Setting inhibited 2-lines 3-lines 4-lines 5-lines 6-lines 7-lines 8-lines 9-lines 10-lines 11-lines 12-lines 13-lines 14-lines Setting inhibited .m bt re nd .co Default Value VSBP[3:0] 14d No Change 14d m Back porch period (Line) -----------------VSCTR1 (AEH) Legend Command Parameter Display Flow Chart 1st Parameter: VSFP[3:0], VSBP[3:0] Action Mode Sequential transfer © ORISE Technology Co., Ltd. Proprietary & Confidential 79 Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.3. Panel Command Description 6.3.1. RGBCTR (B0H): RGB signal control B0H Inst / Para RGBCTR st RGBCTR (RGB signal control) D/CX 0 WRX ↑ RDX 1 D17-8 D7 1 0 D6 0 0 D5 1 0 D4 1 ICM D3 0 DP D2 0 EP D1 0 HSP D0 0 VSP (Code) (B0H) 00h 1 Parameter 1 1 ↑ NOTE: “-” Don’t care, can be set to VDDI or DGND level -Set the operation status on the RGB interface. The setting becomes effective as soon as the command is received. -ICM: GRAM Write/Read frequency and data input select on the RGB interface ICM Write/ Read frequency and input data select Write cycle Read cycle Data input 0 PCLK PCLK D[B:0] 1 SCL Internal oscillator SDA B=17 Description Symbol DP EP HSP VSP Name PCLK polarity set Enable polarity set Hsync polarity set Vsync polarity set Clock polarity set for RGB Interface ‘1’ = data fetched at the falling edge ‘0’ = data fetched at the rising edge ‘1’ = Low enable for RGB interface ‘0’ = High enable for RGB interface ‘1’ = High level sync clock ‘0’ = Low level sync clock ‘1’ = High level sync clock ‘0’ = Low level sync clock -If this register not using the register need be reserved. Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In w w Restriction .m bt re ICM 0d 0d 0d Register Availability w Status Default Power On Sequence S/W Reset H/W Reset nd .co Default Value DP/EP/HSP/VSP 0d/0d/0d/0d 0d/0d/0d/0d 0d/0d/0d/0d -----------------RGBCTR (B0H) m Availability Yes Yes Yes Yes Yes Legend Command Parameter Display Flow Chart 1st Parameter: ICM, DP, EP, HSP, VSP Action Mode Sequential transfer © ORISE Technology Co., Ltd. Proprietary & Confidential 80 Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.3.2. FRMCTR1 (B1h): Frame Rate Control (In normal mode/ Full colors) B1H Inst / Para FRMCTR1 1 Parameter 2 Parameter 3 Parameter NOTE: “-“ Don’t care rd nd st FRMCTR1 (Frame Rate Control) D/CX 0 1 1 1 WRX ↑ ↑ ↑ ↑ RDX 1 1 1 1 D17-8 D7 1 0 0 0 D6 0 0 0 0 D5 1 0 0 0 D4 1 0 0 0 D3 0 FP0[3] BP0[3] RTN0 [3] D2 0 FP0[2] BP0[2] RTN0 [2] D1 0 FP0[1] BP0[1] RTN0 [1] D0 1 FP0[0] BP0[0] RTN0 [0] (Code) (B1h) - -Set the frame frequency of the full colors normal mode in MPU interface. --The default vaule of BP0, FP0, and RTN0 can fit the frame frequency to be 65Hz ±5%. FP0[3:0] 0 1 2 3 4 … D E F BP0[3:0] 0 1 2 3 4 … D E F Amount of Front Porch 0 1 2 3 4 … 13 14 15 Description RTN0[3:0] 0 1 2 3 4 … D E F Restriction w w w .m FP0 2d 2d 2d -If this register not using the register need be reserved. Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Register Availability Status Default Power On Sequence S/W Reset H/W Reset bt Amount of Back Porch 0 1 2 3 4 … 13 14 15 No. of clock in one line 16 17 18 19 20 … 29 30 31 re nd .co Default Value BP0 14d 14d 14d RTN0 0d 0d 0d © ORISE Technology Co., Ltd. Proprietary & Confidential 81 m Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B ------------FRMCTR1 (B1h) Legend Command Parameter Display Flow Chart 1 Parameter: FP0 [3:0] nd 2 Parameter: BP0 [3:0] 3rd Parameter: RTN0 [3:0] st Action Mode Sequential transfer © ORISE Technology Co., Ltd. Proprietary & Confidential w w w .m 82 bt re nd .co m Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.3.3. FRMCTR2 (B2h): Frame Rate Control (In Idle mode/ 8-colors) B2H Inst / Para FRMCTR2 1 Parameter 2 Parameter 3 Paramete NOTE: “-“ Don’t care rd nd st FRMCTR2 (Frame Rate Control) D/CX 0 1 1 1 WRX ↑ ↑ ↑ ↑ RDX 1 1 1 1 D17-8 D7 1 0 0 0 D6 0 0 0 0 D5 1 0 0 0 D4 1 0 0 0 D3 0 FP1[3] BP1[3] RTN1 [3] D2 0 FP1[2] BP1[2] RTN1 [2] D1 1 FP1[1] BP1[1] RTN1 [1] D0 0 FP1[0] BP1[0] RTN1 [0] (Code) (B2h) - -Set the frame frequency of the Idle mode in MPU interface. -The default vaule of BP1, FP1, and RTN1 can fit the frame frequency to be 70Hz ±5%. FP1[3:0] 0 1 2 3 4 … D E F BP1[3:0] 0 1 2 3 4 … D E F Amount of Front Porch 0 1 2 3 4 … 13 14 15 Description RTN1[3:0] 0 1 2 3 4 … D E F Restriction w w w .m FP1 2d 2d 2d -If this register not using the register need be reserved. Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Register Availability Status Default Power On Sequence S/W Reset H/W Reset bt Amount of Back Porch 0 1 2 3 4 … 13 14 15 No. of clock in one line 16 17 18 19 20 … 29 30 31 re nd .co Default Value BP1 14d 14d 14d RTN1 0d 0d 0d © ORISE Technology Co., Ltd. Proprietary & Confidential 83 m Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B ------------FRMCTR2 (B2h) Legend Command Parameter Display Flow Chart 1 Parameter: FP1 [3:0] nd 2 Parameter: BP1 [3:0] 3rd Parameter: RTN1 [3:0] st Action Mode Sequential transfer © ORISE Technology Co., Ltd. Proprietary & Confidential w w w .m 84 bt re nd .co m Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.3.4. FRMCTR3 (B3h): Frame Rate Control (In Partial mode/ full colors) B3H Inst / Para FRMCTR3 1 Parameter 2 Parameter 3 Parameter NOTE: “-“ Don’t care rd nd st FRMCTR3 (Frame Rate Control) D/CX 0 1 1 1 WRX ↑ ↑ ↑ ↑ RDX 1 1 1 1 D17-8 D7 1 0 0 0 D6 0 0 0 0 D5 1 0 0 0 D4 1 0 0 0 D3 0 FP2[3] BP2[3] RTN2 [3] D2 0 FP2[2] BP2[2] RTN2 [2] D1 1 FP2[1] BP2[1] RTN2 [1] D0 1 FP2[0] BP2[0] RTN2 [0] (Code) (B3h) - -Set the frame frequency of the Partial mode/ full colors in MPU interface. -The default vaule of BP2, FP2, and RTN2 can fit the frame frequency to be 70Hz ±5% with frame inversion Description BP2[3:0] 0 1 2 3 4 … D E F .m w w w FP2 2d 2d 2d RTN2[3:0] 0 1 2 3 4 … D E F Restriction -If this register not using the register need be reserved. Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Register Availability Status Default Power On Sequence S/W Reset H/W Reset bt FP2[3:0] 0 1 2 3 4 … D E F Amount of Front Porch 0 1 2 3 4 … 13 14 15 Amount of Back Porch 0 1 2 3 4 … 13 14 15 No. of clock in one line 16 17 18 19 20 … 29 30 31 re nd .co Default Value BP2 14d 14d 14d RTN2 0d 0d 0d © ORISE Technology Co., Ltd. Proprietary & Confidential 85 m Apr. 25, 2006 Preliminary Version: 0.1 and 65Hz ±5% with line inversion in this mode Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B ------------FRMCTR3 (B3h) Legend Command Parameter Display Flow Chart 1 Parameter: FP2 [3:0] nd 2 Parameter: BP2 [3:0] 3rd Parameter: RTN2 [3:0] st Action Mode Sequential transfer © ORISE Technology Co., Ltd. Proprietary & Confidential w w w .m 86 bt re nd .co m Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.3.5. INVCTR (B4h): Display Inversion Control B4H Inst / Para INVCTR st INVCTR (Display Inversion Control) D/CX 0 WRX ↑ RDX 1 D17-8 D7 1 0 D6 0 0 D5 1 0 D4 1 0 D3 0 0 D2 1 NLA D1 0 NLB D0 0 NLC (Code) (B4h) 1 Parameter 1 1 ↑ NOTE: “-” Don’t care, can be set to VDDI or DGND level -Display Inversion mode control -NLA: Inversion setting in full colors normal mode (Normal mode on) NLA Inversion setting in full colours normal mode 0 Line Inversion 1 Frame Inversion -NLB: Inversion setting in Idle mode (Idle mode on) NLB Inversion setting in Idle mode 0 Line Inversion 1 Frame Inversion Description Restriction -If this register not using the register need be reserved. Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Status Default Power On Sequence S/W Reset H/W Reset NLA 0d 0d 0d NLB 1d 1d 1d w w Register Availability w .m bt -NLC: Inversion setting in full colors partial mode (Partial mode on / Idle mode off) NLC Inversion setting in full colours partial mode 0 Line Inversion 1 Frame Inversion re nd .co Default Value m NLC 0d 0d 0d B4h 02h 02h 02h ------------INVCTR (B4h) Legend Command Parameter Display Flow Chart 1 Parameter: st Action Mode Sequential transfer NLA, NLB, NLC © ORISE Technology Co., Ltd. Proprietary & Confidential 87 Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.3.6. RGBBPCTR (B5h): RGB Interface Blanking Porch setting B5H Inst / Para RGBBPCTR 1 Parameter NOTE: “-“ Don’t care st RGBPSET (RGB Interface Blanking Porch setting) D/CX 0 1 WRX ↑ ↑ RDX 1 1 D17-8 D7 1 D6 0 D5 1 D4 1 D3 0 D2 1 D1 0 D0 1 (Code) (B5h) - VBP[3] VBP[2] VBP[1] VBP[0] -Set the blanking porch in the RGB interface VBP[3:0] 0 1 2 3 4 … D E F Amount of Back Porch in RGB interface 0 1 2 3 4 … 13 14 15 Description Restriction -If this register not using the register need be reserved. Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Status Default Power On Sequence S/W Reset H/W Reset w .m bt Register Availability re w w ---------------RGBBPCTR (B3h) nd .co Default Value VBP 3d 3d 3d m Availability Yes Yes Yes Yes Yes Legend Command Parameter Display Flow Chart 1 Parameter: VBP [3:0] st Action Mode Sequential transfer © ORISE Technology Co., Ltd. Proprietary & Confidential 88 Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.3.7. DISSET5 (B6h): Display Function set 5 B4H Inst / Para DISSET5 1 Parameter nd 2 Parameter NOTE: “-“ Don’t care st st DISSET (Display Function set 5) D/CX 0 1 1 WRX ↑ ↑ ↑ RDX 1 1 1 D17-8 D7 1 0 0 D6 0 0 0 D5 1 NO1 0 D4 1 NO0 0 D3 0 SDT1 PTG1 D2 1 STD0 PTG0 D1 1 EQ1 PT1 D0 0 EQ0 PT0 (Code) (B6h) -1 parameter: Set output waveform relation. -NO[1:0]: Set the amount of non-overlap of the gate output NO[1:0] Amount of non-overlap of the gate output Refer the Internal oscillator Refer the PCLK 00 0 1 clock cycle 4 clock cycle 01 1 4 clock cycle 16 clock cycle 10 2 6 clock cycle 24 clock cycle 11 3 8 clock cycle 32 clock cycle -SDT[1:0]: Set delay amount from gate signal falling edge of the source output. SDT[1:0] Amount of non-overlap of the source output Refer the Internal oscillator Refer the PCLK 00 0 1 clock cycle 4 clock cycle 01 1 2 clock cycle 8 clock cycle 10 2 3 clock cycle 12 clock cycle 11 3 4 clock cycle 16 clock cycle -EQ[1:0]: Set the Equalizing period EQ[1:0] EQ period Refer the Internal oscillator 00 0 No EQ 01 1 2 clock cycle 10 2 4 clock cycle 11 3 6 clock cycle .m bt 89 re w w Description Gn Gn+1 Sn VCOM -2 parameter: Set the output waveform in non-display area. -PTG[1:0]: Determine gate output in a non-display area in the partial mode PTG[1:0] Gate output in a non-display area 00 0 Normal scan 01 1 Fix on VGL 10 2 Fix on VGL 11 3 Fix on VGL -PT[1:0]: Determine Source /VCOM output in a non-display area in the partial mode Source output on non-display VCOM output on non-display PT[1:0] area area Positive Negative Positive Negative 00 0 V63 V0 VCOML VCOMH 01 1 V0 V63 VCOML VCOMH 10 2 AGND AGND AGND AGND 11 3 Hi-z Hi-z AGND AGND nd © ORISE Technology Co., Ltd. Proprietary & Confidential w Gate Non-overlap period Delay time for source output EQ period nd .co Refer the PCLK No EQ 4 clock cycle 16 clock cycle 24 clock cycle m Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B Restriction -If this register not using the register need be reserved. Status Normal Mode On, Idle Mode Off, Sleep Out Normal Mode On, Idle Mode On, Sleep Out Partial Mode On, Idle Mode Off, Sleep Out Partial Mode On, Idle Mode On, Sleep Out Sleep In Availability Yes Yes Yes Yes Yes Register Availability Status Default Power On Sequence S/W Reset H/W Reset NO[1:0] 1d 1d 1d STD[1:0] 1d 1d 1d Default Value EQ[1:0] 2d 2d 2d PTG[1:0] 0d 0d 0d PT[1:0] 2d 2d 2d -----------------DISSET5 (B6h) m nd .co 90 Legend Command Parameter Display re Flow Chart bt 1 Parameter: NO[1:0], STD[1:0], EQ[1:0] nd 2 Parameter: PTG[1:0], PT[1:0] st Action Mode Sequential transfer © ORISE Technology Co., Ltd. Proprietary & Confidential w w w .m Apr. 25, 2006 Preliminary Version: 0.1 Evaluation Only. Created with Aspose.Pdf.Kit. Copyright 2002-2005 Aspose Pty Ltd Preliminary SPFD54126B 6.3.8. PWCTR1 (C0H): Power Control 1 C0H Inst / Para PWCTR1 1 Parameter nd st PWCTR1 (Power Control 1) D/CX 0 1 WRX ↑ ↑ RDX 1 1 D17-8 D7 1 0 0 D6 1 0 0 D5 0 0 0 D4 0 VRH4 0 D3 0 VRH3 0 D2 0 VRH2 VCI2 D1 0 VRH1 VCI1 D0 0 VRH0 VCI0 (Code) (C0H) 05h 05h 2 Parameter 1 1 ↑ NOTE: “-” Don’t care, can be set to VDDI or DGND level -Set the GVDD and VCI1 voltage VRH[4:0] 00000 0 00001 1 00010 2 00011 3 00100 4 00101 5 00110 6 00111 7 01001 9 01010 10 01011 11 01100 12 01101 13 01110 14 01111 15 10000 16 10001 17 10010 18 10011 19 10100 20 10101 21 10110 22 10111 23 11000 24 11001 25 11010 26 11011 27 11100 28 11101 29 11110 30 11111 31 GVDD 5.00 4.75 4.70 4.65 4.60 4.55 4.50 4.45 4.35 4.30 4.25 4.20 4.15 4.10 4.05 4.00 3.95 3.90 3.85 3.80 3.75 3.70 3.65 3.60 3.55 3.50 3.45 3.40 3.35 3.25 3.00 VC[2:0] 000 001 010 011 100 101 110 111 0 1 2 3 4 5 6 7 VCI1 2.75 2.70 2.65 2.60 2.55 2.50 2.80 2.90 Description -If this register not using the register need be reserved. Restriction -The deviation value of GVDD between with Measurement and Specification: Max