T108

T108 Release Copyright by Terawins, Inc. Release Version 1.0 May 27, 2007 T108 Video Display Controller 1 《液 晶 之 家》 www.fpdclub.net T108 Release Copyright by Terawins, Inc. Contents 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 Introduction .................................................................................................................... 3 Features ................................................................................................................................................. 3 General Description ............................................................................................................................... 4 Applications............................................................................................................................................ 4 System Architecture............................................................................................................................... 5 System Configurations........................................................................................................................... 6 Pinout Diagram ...................................................................................................................................... 7 Pin Description ....................................................................................................................................... 8 2 2.1 2.2 2.3 2.4 2.5 2.6 Theory of Operations ................................................................................................... 11 I²C Command Protocol ........................................................................................................................ 11 Analog Front End ................................................................................................................................. 13 Black-Level Extension (BLE) ............................................................................................................... 14 Color Space Converter ........................................................................................................................ 14 Gamma Correction............................................................................................................................... 15 OSD1 ................................................................................................................................................... 16 3 Register Description .................................................................................................... 37 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 ADC Register Set................................................................................................................................. 37 Input Timing Register Set .................................................................................................................... 45 Picture Enhancement Register Set...................................................................................................... 51 Scaling Register Set ............................................................................................................................ 54 Gamma and Pattern Gen. Register Set............................................................................................... 58 OSD1 Register Set .............................................................................................................................. 60 LCD Output Control Register Set......................................................................................................... 60 Global Control Register Set ................................................................................................................. 67 TCON Register Set .............................................................................................................................. 73 Infra-Red Register Set ......................................................................................................................... 75 ITU - 656 Decoder Register Set........................................................................................................... 76 Y/C Separation and Chroma Decoder Register Set ............................................................................ 79 Digital I/O Pad Operation Condition..................................................................................................... 84 DC Characteristics ............................................................................................................................... 85 AC Characteristics ............................................................................................................................... 86 Analog Processing and A/D Converters .............................................................................................. 86 I²C Host Interface Timing ..................................................................................................................... 87 4 4.1 4.2 4.3 4.4 4.5 Electrical Characteristics............................................................................................. 84 5 6 7 8 9 Package Dimensions ................................................................................................... 88 Ordering Information.................................................................................................... 88 Revisions Note ............................................................................................................. 89 General Disclaimer ....................................................................................................... 89 Contact Information ..................................................................................................... 89 2 《液 晶 之 家》 www.fpdclub.net T108 Release Copyright by Terawins, Inc. 1 Introduction 1.1 Features Cost Effective Highly Integrated Triple ADC + ITU656/601 Decoder + Digital RGB + 2D Video Decoder + OSD + Scaler + TCON + DAC + DCto-DC + LED/CCFL controls - Integrates 10-bit Triple Analog to Digital Converters (ADC) & Phase Locked Loop (PLL), for supporting CVBS, S-Video, YPbPr and RGB inputs - Scaler supports 2-D adaptive intra-field deinterlacer and non-linear 16:9 aspect ration. - Requires no external Frame Buffer Memory for de-interlace. - ITU656/601_8/L601_16 Decoder with digital input ports for standard ITU656/601 input data. - Support digital RGB565 inputs - Advanced On Screen Display (OSD) function - Programmable Timing Controller (Tcon) for Car TV applications - Multi-standard color decoder with 2D adaptive comb filter - Innovative and flexible design to reduce total system cost Triple 10-bits ADCs - 80MSPS Conversion Rate ADC - Built-in Pre-amp, mid-level & ground clamp - Automatic Clamp Control for CVBS, Y and C - Programmable Static Gain Control or Automatic Gain Control for CVBS or Y/C - Max Input configuration up to 9xCVBS, 3xSvideo+3xCVBS, 3YPbPr - Build-in Line-Lock PLL for RGB and YPbPr - Phases Tracking and Boundary for adjusting input quality. Digital Video Enhancement - Separate Luminance and Chroma Enhancer - Y Supports Luminance Black Level Extension., Contrast and Brightness adjustment - C Supports DCTI, Saturation and Hue adjustment. FIR Based Advanced Scaling Engine - Coefficient based sharpness filters - Independent vertical and horizontal scaling ratio - 16:9 Non-linear Aspect ratio LCD Interface Package: 100 pin LQFP Provides 256-entry TBL Gamma correction for panel compensation Supports image pan functions Programmable Timing Controller Built-in software adjustable VCOM voltage RGB Triple DAC output Integrated high efficiency DC-DC power conversion unit for gate and source drivers reduces energy consumption Integrated TFT-LCD backlight inverter drive unit supports CCFL/LED typed backlight Software adjustable lamp dimming - Built-in On Screen Display Engine - 8K-word OSD1 memory - Supports text or bitmap modes - Supports character blinking and overlay functions - Fully programmable character mapping - Supports alpha blending & Zoom-in/Zoomout function - Built-in 114+ fonts (18x12, 24x16 each) - Optional fonts stored in off-chip serial ROM - Optional Pattern-Filled background Crystal Oscillator Circuit - Direct interface to a (27.0MHz or other frequency) Crystal - Also provide a buffered clock output for external Micro-controller Digital Test Pattern Generator - Programmable standard & special panel burn-in test patterns - Support special border frame blocking mode Independent Display Phase Lock Loop - Generates pixel clock output to panel - Supports free run OSD mode Serial Bus Interface 2 - Supports 2-wire I C (Slave/Master) Pulse Width Modulation Outputs Design For Testability - Scan chain insertion - Separated analog & digital test modes Power Supply: +1.8V, +3.3V and +5V 3 《液 晶 之 家》 www.fpdclub.net T108 Release Copyright by Terawins, Inc. 1.2 General Description The T108 is a highly integrated All-in-one Visual Processor that provides major cost saving solution for the portable applications. T108 has builtin high performance Triple ADCs, TCON, triple DACs. Scaling Machine with sophisticated upscaling and downscaling algorithms. The Innovative integrated “Frame-Buffer-Less” De-interlacer can significantly reduce system cost. The T108 also integrates enhanced two layer OSD engines. The device can interface to an external micro-controller through 2wire serial bus interface. 1.3 Applications 1. Small to medium sized displayer, In-car TV 2. Progressive CRT TV 3. GPS mobile display application 4 《液 晶 之 家》 www.fpdclub.net T108 Release Copyright by Terawins, Inc. 1.4 System Architecture T108 Block Diagram CVBS, S-Video, YPbPr, RGB ADC ADC ADC Analog Front End Control Input Sample Rate Converter Y/C Separation Line Buffers U/V Demodulation YCbCr Post-filtering ADC PLL Format Detection VBI Decoder FIFO 2D-Adaptive Comb Filter HIS, VSI, SOYIN Video Decoder Slicer / Sync_Sep ITUR656 Decoder VCLK, LODD, LHREF, DHDEI, LVC[7:0], LVY[7:0] Y L601_8/16 Input MUX / Capture RGB_To_YUV 422_to_444 CC/TTX Mixer CbCr Black Level Expansion / Peaking / DLTi / Contrast / Brightness DCTi / Hue / Saturation Scaler 2D DeInterlacer Zoom Line Buffers RGB565 VIP CC_BOX, CC_Color[3:0], CC_CKO, CC_VSO, CC_HSO Image Capture & Enhancer Ext_OSD Mixer YUV_To_ RGB PT_GEN Color Processor Gamma Dither + LCD Control Serial RGB TCON Swap Analog Output VCOM DC Converter VCOM CCFL/LED DAC DAC DAC Display PLL R/ G/ B RSTB I2C Slave IR Decoder, PWM OSD1 RAMs / ROMs Timing Gen Misc. XCLK2MC SDA, SCL IR1, PWM1 CPH[3:1], TCON/sRGB Figure 1-1 System Architecture © Copyright 2007 Terawins, Inc. 5 《液 晶 之 家》 www.fpdclub.net XCLKO XCLKI T108 Release Copyright by Terawins, Inc. 1.5 System Configurations CVBS Y S-VIDEO C CCFL/LED TV Tuner Y Pb Pr T108 Video Display Controller Component RGB R G B HSYNC VSYNC TCON Signals TFT-LCD I2C Video Decoder V656/L601 8051 MCU GPS RGB565/666/888 Figure 1-2 System Configurations © Copyright 2007 Terawins, Inc. 6 《液 晶 之 家》 www.fpdclub.net T108 Release Copyright by Terawins, Inc. 1.6 Pinout Diagram VD5A LVY7/DRI7 LVY6/DRI6 LVY5/DRI5 LVY4/DRI4 LVY3/DRI3 LVY2/DGI7 LVY1/DGI6 GND VDD18 LVY0/DGI5 STV2/sD7 STV1/sD6 GOE/OEV/sD5 GCLK/CKV/sD4 VDD33 LP/OEH/VCOM_I/sD3 Q1H/sD2 GND CPH3/LLCK3/sD1 CPH2/LLCK2/sD0 CPH1/LLCK1/CLKO DEO/STH2 VSO/STH1 HSO/POL/VCOM 1 1 1 1 1 1 1 3 3 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1 1 3 3 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1 Figure 1-3 Pinout Diagram Pin 90-100, 1, 2: CCFL (LED) Backlight Pin Definitaion © Copyright 2007 Terawins, Inc. OLR (SOYIN) SOYIN(SAR1) AVDDB ACB2 ACB1 ACB0 AGNDB AVDDG AY2 AY1 AY0 AGNDG AVDDR ACR2 ACR1 ACR0 AGNDR GNDP PVS33 VPLL FILT AVDDP PVD33 GND VDD18 7 《液 晶 之 家》 www.fpdclub.net 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 3 3 1 1 1 1 1 1 1 1 13 1 1 2 1 1 1 1 1 1 1 1 1 1 1 11 3 1 1 1 1 1 1 1 1 VS5A IOB IOG IOR RSET VBGF VCOMAMP VCOMDC VD33DAC VEA CSS VFB CEXT VPWM VD33PWM (VISen) VS33PWM (VD33PWM) VEAI (VS33PWM) VFBI (VEAL) VPWMP (VFBL) VPWMN (VPWML) VCKP (NC) VCKN (NC) CSSI (CSSL) CEXT1 (CEXT1L) OLP (VISenL) 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 1 LHREF/DHSI LODD/DVSI LVCLK VDD18 LVC7/DGI4 LVC6/DGI3 LVC5/DGI2 LVC4/DBI7 LVC3/DBI6 LVC2/DBI5 LVC1/DBI4 LVC0/DBI3 GND VDD33 PWM1 IR1 XCLKO XCLKI CPUINT/GPOB3 (Strap: I2C_A3) XCLK2MC/GPIO3 SCL SDA RSTB HSI VSI T108 Release Copyright by Terawins, Inc. 1.7 Pin Description Table 1-1 Pin Description Symbol Pin # Type Description Power Supplies VDD18 VDD33 AVDDB AVDDG AVDDR VD5A VD33DAC VD33PWM AVDDP PVD33 GND AGNDB AGNDG AGNDR VS5A VS33PWM GNDP PVS33 IOR IOG IOB VCOMAMP VCOMDC VCOM_i LLCk1 LLCk2 LLCk3 POL/VCOM STH1 STH2 Q1H LP/OEH GCLK/CKV GOE/OEV STV1 STV2 VEA CSS VFB 25, 47, 66 37, 60 3 8 13 75 84 90 or 91(LED) 22 23 24, 38, 57, 67 7 12 17 76 91 or 92(LED) 18 19 79 78 77 82 83 59 54 55 56 51 52 53 58 59 61 62 63 64 85 86 87 PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR GND GND GND GND GND GND GND GND AO AO AO AO AO DI, P/D DO, P/D DO, P/D DO, P/D DO, P/D DO, P/D DO, P/D DO, P/D DO, P/D DO, P/D DO, P/D DO, P/D DO, P/D AO AO AI +1.8V digital core power supply +3.3V digital output power supply +3.3V analog power supply for ADC channel 2 +3.3V analog power supply for ADC channel 1 +3.3V analog power supply for ADC channel 0 +5.0V analog power supply for DAC +3.3V analog power supply for DAC +3.3V analog power supply for DC Converter +1.8V analog power supply for PLL +3.3V analog power supply for PLL Digital ground Analog ground for ADC channel 2 Analog ground for ADC channel 1 Analog ground for ADC channel 0 Analog ground for DAC Analog ground for DC Converter Analog ground for PLL Analog ground for PLL Channel R current output Channel G current output Channel B current output VCOM output VCOM output VCOM input Output Data Clock Output Data Clock Output Data Clock Horizontal Polarity Output Signal. Share w/ HSO Horizontal Start Pulse 1 Signal. Share w/ VSO Horizontal Start Pulse 2 Signal. Share w/ DEO Panel polarity control Latch pulse for column driver Gate driver clock Gate driver output enable Gate driver start pulse Gate driver start pulse Error Amplifier output Soft Start Feedback of Lamp current Output Interface Signals Timing Controller Interface Signals Power Management Signals 8 《液 晶 之 家》 www.fpdclub.net T108 Release Symbol CEXT VPWM VISen VEAI/VEAL VFBI/VFBL VPWMP/VPWML VPWMN VCKP/NC VCKN/NC CSSI/CSSL CEXT1/CEXT1L OLP/VISenL OLR VSO HSO DEO CLKO sD0~sD7 Pin # 88 89 90(LED) 92/93 93/94 94/95 95(CCFL) 96 97 98 99 100 1(CCFL) 52 51 53 54 55~56, 58~59, 61~64 28 29 30 Type AO AO AI AO AI AO AO AO AO AO AO AI AI DO, P/D DO, P/D DO, P/D DO, P/D DO, P/D Copyright by Terawins, Inc. Description Switching frequency of DC-DC converter PWM output, connect o external N-channel power MOSFET Feedback of DC-DC current Error Amplifier output Feedback of Lamp current PWM output, drive PMOSFET switch PWM output, drive NMOSFET switch Clock output, drive PMOSFET switch Clock output, drive NMOSFET switch Soft Start Switching frequency of Inverter Open Lamp Protection/Current Limit Open Lamp Regulation Vertical Synchronization Output Control Signal. Share w/ STH1 Horizontal Synchronization Output Control Signal. Share w/ POL/VCOM Horizontal Output Data Enable Signal. Share w/ STH2 sPanel clock sPanel data, share w/ TCON signals Serial Panel Interface Signals Configuration Interface Signals RSTB SDA SCL (SCANB) DI, P/U Whole chip reset. DIO, P/U 2-wire serial bus data. Power down does not affect SDA. DIO, P/U 2-wire serial bus clock. Power down does not affect SCL. This pin should be high when RSTB asserted for avoid entering Scan test mode. DO Buffered XCLKI for external microprocessor. DIO, P/U Internal Interrupt. This pin is a reset strap pin for I2C device address. When RSTB 2 goes high, if this pin is high, then default I C device address is 50h, else 40h. Analog input 2 of channel 2 Analog input 1 of channel 2 Analog input 0 of channel 2 Analog input 2 of channel 1 Analog input 1 of channel 1 Analog input 0 of channel 1 Analog input 2 of channel 0 Analog input 1 of channel 0 Analog input 0 of channel 0 RGB Vertical Synchronous input RGB Horizontal Synchronous input Sync on Y (of component) input SARADC for keypads sense PLL Reference PLL filter Video data port of the 2nd ITU-656 XCLK2MC CPUINT (A3) 31 32 ADC, PLL, Slicer Interface ACB2 ACB1 ACB0 AY2 AY1 AY0 ACR2 ACR1 ACR0 VSI HSI SOYIN SAR1 VPLL FILT LVC0~7 4 AI 5 AI 6 AI 9 AI 10 AI 11 AI 14 AI 15 AI 16 AI 26 DI, P/D 27 DI, P/U 2(CCFL), 1(LED) AI 2(LED) AI 20 AI 21 AI 39~46 DI, P/D Video-In Interface: ITUR656 9 《液 晶 之 家》 www.fpdclub.net T108 Release Symbol LVCLK LVC0~7 LVCLK LODD/LVSYNC LHREF/LHSYNC LVC0~7 LVY0~7 LVCLK LODD/LVSYNC LHREF/LHSYNC DRI3~7 DGI2~7 DBI3~7 LVCLK DVSI DHSI Pin # 48 39~46 48 49 50 39~46 65, 68~74 48 49 50 70~74 44~46, 65, 68~69 39~43 48 49 50 33 34 35 36 80 81 Type DI, P/D DI, P/D DI, P/D DIO, P/D DIO, P/D DI, P/D DI, P/D DI, P/D DIO, P/D DIO, P/D DI, P/D DI, P/D DI, P/D DI, P/D DIO, P/D DIO, P/D DI DO DI, P/U DIO, P/D AI AI Copyright by Terawins, Inc. Description Video clock of the 2nd ITU-656 (2x pixel rate) Video data port of 8-bit 601 or Chroma Video clock (2x pixel rate) ITU-601 Odd or VSync input ITU-601 HREF(HDE) or HSync input Video chroma data port of 16-bit 601 Video Luma data port of 16-bit 601 Video clock (1x pixel rate) ITU-601 Odd or VSync input ITU-601 HREF(HDE) or HSync input Digital RGB input: 5 MSB bits of Color R Digital RGB input: 6 MSB bits of Color G Digital RGB input: 5 MSB bits of Color B Video clock (1x pixel rate) Digital RGB VSync input Digital RGB HSync input Output PLL reference clock input and I2C, timer operating clock Output PLL reference clock output IR input Pulse Width Modulation 1 for backlight control / Volume / … DAC reference current adjust DAC voltage reference output Video-In Interface: L601_8bit Video-In Interface: L601_16bit Video-In Interface: RGB565 Misc. Signals XCLKI XCLKO IR1 PWM1 RSET VBGF 10 《液 晶 之 家》 www.fpdclub.net T108 Release Copyright by Terawins, Inc. 2 Theory of Operations 2.1 I²C Command Protocol Before your tester writes I²C commands to T108, slave address must be set at 50h. The timing sequence can be shown as below. After 4 cycles, the tester can get started IIC commands. CPUINT(A3) can affect slave address. Set it low for 40h, and high for 50h. 2 Cycles 2 Cycles XTALI RSTB Don　 care SDA SCL Don　 care Figure 2-1 Power-Up Initialization When tester issues commands to the T108, the only way the user can program the T108 is using the 2-wire serial bus protocol. This section describes the 2-wire serial bus protocol. Data transfers on the 2-wire serial bus are initiated with a START condition and are terminated with a STOP condition. Normal data on the SDA line must be stable during the high period of the SCL. The transition on the SDA is only allowed while SCL is low. The START condition is unique case and is defined by a high-tolow transition on the SDA while the SCL is high. The STOP condition is a unique case and is defined by a low-to-high transition on the SDA while the SCL is high. Each data packet on the 2-wire serial bus consists of 8 bits of data followed by an ACK bit. Data is transferred with MSB first. The transmitter releases the SDA line during the ACK bit and the receiver of data transfer must drive the SDA line low during the ACK bit to acknowledge receipt of the data. The frequency of SCL can be from 50 KHz up to 2 MHz (~=XCLK/12). 11 《液 晶 之 家》 www.fpdclub.net T108 Release SDA B it7 B it6 Copyright by Terawins, Inc. SCL S 1 2 3 7 8 9 ACK P S ta rt C o n d it io n S to p C o n d it io n Figure 2-2 Basic I2C Bus Protocol The timing below shows a typical T108 I2C single byte write command, Slave Address Write CMD Register Address Data being written to Register SDA A7 A6 A1 R7 R6 R1 R0 D7 D6 D1 D0 SCL S 1 2 7 8 9 ACK 1 2 7 8 9 ACK 1 2 7 8 9 P Start Condition Stop Condition Figure 2-3 T108 I2C Single Byte Write Command The timing below shows a typical T108 I2C single byte read command, Slave Address Read CMD Slave Address Write CMD Register Address Restart Data being Read Not Ack SDA A7 A6 A1 R7 R6 R1 R0 A7 A6 A1 D7 D6 D1 D0 SCL S 1 2 7 8 9 ACK 1 2 7 8 9 ACK 1 2 7 8 9 ACK 1 2 7 8 9 P Start Condition Stop Condition Figure 2-4 T108 I2C Single Byte Write Command 12 《液 晶 之 家》 www.fpdclub.net T108 Release Copyright by Terawins, Inc. 2.2 Analog Front End T108 contains 3 ADCs in Analog Front End. Each channel of ADCs can digitalize SDTV signals from analog to digital. The figure shown below can describe how to select a SDTV signal from 3 inputs prior to ADC. Figure 2-5 Analog Front End MUX 13 《液 晶 之 家》 www.fpdclub.net T108 Release Copyright by Terawins, Inc. 2.3 Black-Level Extension (BLE) Black Level Expansion (BLE) can enhance image contrast that makes dark regions of image darker, while bright regions remain unchanged. The figure shown below is BLE transfer function. Y out Without BLE With BLE BLE_threshold Figure 2-6 Black Level Expansion Y in Yout = Yin − (Yoffset − Yin) * BLE _ Gain / 16 Where Yoffset and BLE _ Gain can be programmed by register P0_96h. 2.4 Color Space Converter A pixel in YCbCr color space can be converted to RGB color space by using following equations, R = YCoef _ R * (Y − 16) + / − CbCoef _ R * (Cb − 128) + CrCoef _ R * (Cr − 128) G = YCoef _ G * (Y − 16) − CbCoef _ G * (Cb − 128) − CrCoef _ G * (Cr − 128) B = YCoef _ B * (Y − 16) + CbCoef _ B * (Cb − 128) + / − CrCoef _ B * (Cr − 128) The equations shown as below correspond to a typical YCbCR-to-RGB converter. 14 《液 晶 之 家》 www.fpdclub.net T108 Release Copyright by Terawins, Inc. 2.5 Gamma Correction The relation between input video signal and LCD panel may exist non-linear transfer function such as figure shown below, R /G /B o u t G am m a 255 G am m a 248 G am m a 2 G am m a 1 G am m a 0 R /G /B in 248 255 16 8 0 Id e a l T ra n s fe r F u n c tio n T 1 0 8 G a m m a C o rre c tio n Figure 2-7 Gamma LUT T108 uses 33-point piece-wise linear interpolation instead of RAM-based LUTs. Each point can be programmed via register at P0_93h and P0_94h. 15 《液 晶 之 家》 www.fpdclub.net T108 Release Copyright by Terawins, Inc. 2.6 OSD1 The OSD1 in T108 is improved in rendering and efficient memory usage. The legacy OSD is either one thread Menu or one graphic (BMP) mode. T108 OSD1 supports two threads menus and 1 graphic rendering simultaneously. So it will be easier to have menu control and Closed Caption. 2.6.1 OSD1 RAM Partition The OSD1 Font/Menus/BMP memory share the same built-in 8Kx16 SRAM. 16 《液 晶 之 家》 www.fpdclub.net T108 Release 2.6.2 OSD1 Register Map I/O Port Groups Index 00h 01h 02h 03h 04h 05h Global Setting 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Fh 10h Menu-1 Setting A0h – OSD1_Index A1h – OSD1_Data ROM Font 11h 12h 13h 14h 16h 17h 18h Menu-2 Setting 19h 1Ah 1Bh 1Ch 20h 21h 22h 23h 24h 25h BMP Setting 26h 27h 28h 29h 2Ah 2Bh 2Ch 2Dh OSD1 Enable/Blinking Register Font Size Char2BP Font Index Base Char4BP Font Index Base Char2BP Font Memory Base Address, LSB Char2BP Font Memory Base Address, MSB Char4BP Font Memory Base Address, LSB Char4BP Font Memory Base Address, MSB OSD1 Color LUT Address port OSD1 Color LUT Data Port OSD1 Window Shadow Global Alpha Blending Control Char1BP color high bits offset ROM Font Index Base Revision ID Menu-1 Enable Menu-1 Start Address, LSB Menu-1 Start Address, MSB Menu-1 End Address, LSB Menu-1 End Address, MSB ROM Font Memory Base Address, LSB ROM Font Memory Base Address, MSB Menu-2 Enable Menu-2 Start Address, LSB Menu-2 Start Address, MSB Menu-2 End Address, LSB Menu-2 End Address, MSB BMP Control Register BMP Start Address, LSB BMP Start Address, MSB BMP Alpha Blending Control BMP Horizontal Size, LSB BMP Horizontal Size, MSB BMP Vertical Size, LSB BMP Vertical Size, MSB BMP Position, Horizontal Start, LSB BMP Position, Horizontal Start, MSB BMP Position, Vertical Start, LSB BMP Position, Vertical Start, MSB BMP LUT Base Address BMP Background Color Copyright by Terawins, Inc. Description 17 《液 晶 之 家》 www.fpdclub.net T108 Release I/O Port Groups Index 40h 41h Block Write 42h 43h 44h 45h A2h – ORAM_A A3h – ORAM_D Block Write Data LSB Block Write Data MSB Block Write Starting Address LSB Block Write Starting Address MSB Block Write Count Block Write Control Copyright by Terawins, Inc. Description OSD1 RAM Address Port of Starting Access (LSB A[7:0] first, then MSB A[12:8]). OSD1 RAM Data Port (Low Byte first, then High Byte). After two Writes, the address will be increased by 1. 18 《液 晶 之 家》 www.fpdclub.net T108 Release 2.6.3 OSD1 Color Scheme Copyright by Terawins, Inc. For drawing a graphic menu, a colorful icon or logo, …., T108 OSD1 provides 1BPP (one bit per pixel) ~ 5BPP (5 bits per pixel) BMP coding. For n-BPP BMP, it has one background color and (2^n – 1) foreground colors. For character menus with pre-defined fonts, T108 OSD1 provides mono characters (Char1BP) and color characters (Char2BP, Char4BP), randomly mix-able. So that, simple icon can be implemented by color characters. The color mapping of character/menu is more complicate, please refer to the following drawing. The OSD1 main Color LUT is 256 entries SRAM, color in RGB565 format. 19 《液 晶 之 家》 www.fpdclub.net T108 Release 2.6.4 Character RAM Format Copyright by Terawins, Inc. T108 OSD1 character decoding supports 512 fonts. By setting FontROM, Char2BP and Char4BP Font Index Base, we could assign different percentage for those character fonts, depends on application, menu color requirement, memory size, fonts replacing, ... The character “MENU” in T108 OSD1 is combined with 1~n character “ROW”s, each ROW can have its own rendering behavior, such as alpha blending, position, zooming ratio, color groups, border/shadow modes, row length,…, these are defined as ROW Attributes (RAtt, current version supports 8 types). Or, few rows can share the same setting without redefining those RAtt. 2.6.4.1 Character Format Each character is 16-bits length, includes foreground/background color, blinking, font index. Bit [15:14] [13] [12:9] Symbol BG_Color[1:0] Blink FG_Color[3:0] Description Background Color, which combined with the RAtt_C to become 3 bit, selects 6 background remap colors. If both 0, then transparent background. Enable this Character display with blinking feature. Foreground (FG) Color, depends font index is Char1BP, Char2BP or Char4BP: 1. When Char1BP, these 4 bits as FG LSB 4 bits, combine with RAtt_A (as FG MSB 4 bits), total 8 bits for selecting color LUT as character FG color. If the value is set as 0000b, then there will be no foreground, i.e. transparent. (Char1BP only) 2. When Char2BP, these 4 bits select one of 16 Char2BP remap LUT. Each Char2BP remap LUT entry is 3*8 bits for 2BP font pixel value: 01b, 10b and 11b. For 2BP font pixel value = 00b, then it will render as transparent. 3. When Char4BP, these 4 bits as FG MSB, then combine with 4BP font pixel 4 bits value to become 8 bits for addressing LUT. For 4BP font pixel value = 0000b, then it will render as transparent. Character Address (Index), selects the character font (i.e., 0,1,2,.. A,B,C, a,b,c,$,%,…). If the value is number N, then it selects the Nth font, and that font starting address is (N x Font_Height ). The Font_Height is defined in OSD1_01h. [8:0] Char_Index[8:0] 2.6.4.2 Row Attribute Alpha-Blending Type Format (RAtt_A) Bit [15:12] [11:8] [7:6] [5:4] Symbol RAtt_ID = 1101b FGC_1BP[7:4] Reserved FG_aB_Mode[1:0] Description Must set value 1101b for RAtt_A Defines the MSB 4 bits for Char1BP FG color for current row or below in same thread menu. Defines the FG alpha-Blending mode (see OSD1 configuration register OSD1_0B for detail) for current row or below in same thread menu. [3:0] aB_Source_Percentage[3: Defines the alpha-Blending ratio (of source video/graphic) for current row or 0] below in same thread menu. 20 《液 晶 之 家》 www.fpdclub.net T108 Release 2.6.4.3 Row Attribute Character Type Format (RAtt_C) Copyright by Terawins, Inc. This RAtt_C is a must-have attribute for each menu row, and those content in OSD1 memory followed will be rendering as characters, not other row attributes except exceeding the row length (see Row_Length[5:0] below). Bit [15:13] [12] [11] [10] [9:8] [7:6] [5:0] Symbol RAtt_ID = 000b Skip_This Description Must set value 000b for RAtt_C When set to 1, the following one character row of current thread menu could be skipped, and continues the next row instead. End_After When set to 1, the following all character rows of current thread menu will be skipped. BG_RGB[2] Background color bit 2, combined with the BG_Color[1:0] in each character become 3 bits to select background remap color. CharHeight_Scale[1:0] Defines the enlarge ratio (x1, x2, x3, x4) of the character height of the menu rows following and after. CharWidth_Scale[1:0] Defines the enlarge ratio (x1, x2, x3, x4) of the character width of the menu rows following and after. Row_Length[5:0] Indicates the following character row length (how many characters), valid value range is 1 to 63. 2.6.4.4 Row Attribute Dummy Type Format (RAtt_D) This RAtt_D is a dummy attribute, it is used for replacing other non-RAtt_C type attributes when changing rendering behavior if need, also it is used when switch between rows with different BDS behavior, 4 lines will be inserted. Bit [15:0] Symbol RAtt_ID = E001h Must set value E001h for RAtt_D Description 2.6.4.5 Row Attribute Gap Type Format (RAtt_G) This RAtt_G is used to insert fix vertical null lines between menu rows. Bit [15:13] [12:11] [10:0] Symbol RAtt_ID = 001b Reserved Gap[10:0] Must set value 001b for RAtt_G Line number inserted before the following menu row. Description 2.6.4.6 Row Attribute Jump Menu Type Format (RAtt_J) This RAtt_J is used to redirect menu to other assigned new menu block in OSD1 memory. This is useful for controlling menu flows. Bit [15:14] [13] [12:0] Symbol RAtt_ID = 10b Jump_En Jump_MenuA[12:0] Description Must set value 10b for RAtt_J Set to 1 enables the menu jump to new assigned address in RAtt_J. When set to 0, this RAtt_J has no effect. Jump to the OSD1 RAM address, which should still point to a row attribute of menu. 21 《液 晶 之 家》 www.fpdclub.net T108 Release 2.6.4.7 Row Attribute Horizontal Position Type Format (RAtt_H) Bit [15:13] [12:11] [10:0] Symbol RAtt_ID = 011b Reserved HStart[10:0] Must set value 011b for RAtt_H Copyright by Terawins, Inc. Description Set the horizontal start position of the following menu rows. 2.6.4.8 Row Attribute Vertical Position Type Format (RAtt_V) Bit [15:13] [12:11] [10:0] Symbol RAtt_ID = 010b Reserved VStart[10:0] Must set value 010b for RAtt_V Set the vertical start position of the following menu rows. Description 22 《液 晶 之 家》 www.fpdclub.net T108 Release 2.6.5 OSD1 Configuration Registers Copyright by Terawins, Inc. 2.6.5.1 OSD1 Enable/Blinking Register Address Offset: Default Value: Bit [7] [6] [5:4] Access R/W R/W R/W OSD1_00h 0Ah Symbol Access: Size: Read/Write 8 bits Description [3:2] R/W [1:0] R/W OSD1_En Set to 1 for globally enabling OSD1 function. Color_1_Half Set to 1 for allowing shadow effect when color value is 1 CRAM_ByteAccess[1:0] Byte Access mode when programming character of menu: 0Xb: Word access (LSB first, then MSB byte) 10b: LSB only (not affect font index >= 256) 11b: MSB only (character BG/FG colors, Blinking, and Index bit 8) BlinkFreq[1:0] Blinking Frequency Select (internal 4x BCLK for Blinking State Machine). Set 00b for Refresh Rate /16; 01b for 1/32; 10b for 1/64; 11b for 1/128. BlinkDuty[1:0] For adjusting the blinking duty cycle, Set: 00b for Global Blink Off, i.e., 0% Background, 100% Pattern Fill. 01b for 25% Background, 75% Pattern Fill. 10b for 50% Background, 50% Pattern Fill. 11b for 75% Background, 25% Pattern Fill. 2.6.5.2 OSD1 Font Size Register Address Offset: Default Value: Bit [7] [6] [5] Access R/W R/W R/W OSD1_01h 12h Symbol vDE_from_VS hDE_from_HS FontW16 Access: Size: Read/Write 8 bits Description [4:0] R/W FontHeight[4:0] Shift OSD1 more up Shift OSD1 more left Set Font Width: 0b: Font Width = 12 1b: Font Width = 16 Font Height, valid value between 1 and 24 2.6.5.3 OSD1 Char2BP Font Index Base Register Address Offset: Default Value: Bit [7:0] Access R/W OSD1_02h 80h Symbol Font_Index_2BP[8:1] Access: Size: Read/Write 8 bits Description Defines the Char2BP font index base (offset). When character index small than this value*2 will be decoded as Char1BP (mono char). And if the character index greater than or equal to this value*2 will be decoded as Char2BP (= this value but less than Char2BP_IndexBase is mono character (Char1BP) ROM font segment. 2.6.5.15 OSD1 Revision ID Register Address Offset: Default Value: Bit [7:0] Access RO OSD1_0Fh 31h Symbol Revision_ID[7:0] Access: Size: Read Only 8 bits Description 25 《液 晶 之 家》 www.fpdclub.net T108 Release 2.6.5.16 OSD1 Menu-1 Enable Register Address Offset: Default Value: Bit [7] [6:0] Access R/W RO Copyright by Terawins, Inc. OSD1_10h 00h Symbol M1_En Reserved Access: Size: Read/Write 8 bits Description Set to 1 enable Menu-1 thread to display 2.6.5.17 OSD1 Menu-1 Start Address LSB Register Address Offset: Default Value: Bit [7:0] Access R/W OSD1_11h 00h Symbol M1_Menu_SA[7:0] Access: Size: st Read/Write 8 bits Description Point to the 1 row attribute of Menu-1 in OSD1 RAM. 2.6.5.18 OSD1 Menu-1 Start Address MSB Register Address Offset: Default Value: Bit [7:5] [4:0] Access RO R/W OSD1_12h 10h Symbol Reserved M1_Menu_SA[12:8] Access: Size: Read/Write 8 bits Description Point to the 1st row attribute of Menu-1 in OSD1 RAM. 2.6.5.19 OSD1 Menu-1 End Address LSB Register Address Offset: Default Value: Bit [7:0] Access R/W OSD1_13h 00h Symbol M1_Menu_EA[7:0] Access: Size: Read/Write 8 bits Description Point to the end of Menu-1 in OSD1 RAM. 2.6.5.20 OSD1 Menu-1 End Address MSB Register Address Offset: Default Value: Bit [7:5] [4:0] Access RO R/W OSD1_14h 14h Symbol Reserved M1_Menu_EA[12:8] Access: Size: Read/Write 8 bits Description Point to the end of Menu-1 in OSD1 RAM. 2.6.5.21 OSD1 FontROM Base Address LSB Register Address Offset: Default Value: Bit [7:0] Access R/W OSD1_16h 00h Symbol Access: Size: Read/Write 8 bits Description st Font_BaseA_ROM[7:0] Point to the start address in ROM, i.e., point to the 1 Font in ROM. 2.6.5.22 OSD1 FontROM Base Address MSB Register Address Offset: Default Value: Bit [7:5] [4:0] Access RO R/W OSD1_17h 00h Symbol Access: Size: Read/Write 8 bits Description Reserved st Font_BaseA_ROM[12:8] Point to the start address in ROM, i.e., point to the 1 Font in ROM. 26 《液 晶 之 家》 www.fpdclub.net T108 Release 2.6.5.23 OSD1 Menu-2 Enable Register Address Offset: Default Value: Bit [7] [6:0] Access R/W RO Copyright by Terawins, Inc. OSD1_18h 00h Symbol M2_En Reserved Access: Size: Read/Write 8 bits Description Set to 1 enable Menu-2 thread to display 2.6.5.24 OSD1 Menu-2 Start Address LSB Register Address Offset: Default Value: Bit [7:0] Access R/W OSD1_19h 00h Symbol M2_Menu_SA[7:0] Access: Size: st Read/Write 8 bits Description Point to the 1 row attribute of Menu-2 in OSD1 RAM. 2.6.5.25 OSD1 Menu-2 Start Address MSB Register Address Offset: Default Value: Bit [7:5] [4:0] Access RO R/W OSD1_1Ah 15h Symbol Reserved M2_Menu_SA[12:8] Access: Size: Read/Write 8 bits Description Point to the 1st row attribute of Menu-2 in OSD1 RAM. 2.6.5.26 OSD1 Menu-2 End Address LSB Register Address Offset: Default Value: Bit [7:0] Access R/W OSD1_1Bh 00h Symbol M2_Menu_EA[7:0] Access: Size: Read/Write 8 bits Description Point to the end of Menu-2 in OSD1 RAM. 2.6.5.27 OSD1 Menu-2 End Address MSB Register Address Offset: Default Value: Bit [7:5] [4:0] Access RO R/W OSD1_1Ch 16h Symbol Reserved M2_Menu_EA[12:8] Access: Size: Read/Write 8 bits Description Point to the end of Menu-2 in OSD1 RAM. 2.6.5.28 OSD1 BMP Control Register Address Offset: Default Value: Bit [7] [6:4] Access R/W R/W OSD1_20h 00h Symbol BMP_En BMP_Nbpp Access: Size: Read/Write 8 bits Description [3:2] [1:0] R/W R/W Set to 1 enable BMP to display Defines current BMP for displaying is N bits per pixel. 000b: Reserved 001b: 1 bit/pixel 010b: 2 bits/pixel 011b: 3 bits/pixel 100b: 4 bits/pixel 101b: 5 bits/pixel 11Xb: 5 bits/pixel BMP_Extra_Height[1:0] BMP enlarge ratio in vertical direction: x1, x2, x3, x4 lines BMP_Extra_Width[1:0] BMP enlarge ratio in horizontal direction: x1, x2, x3, x4 dots 27 《液 晶 之 家》 www.fpdclub.net T108 Release 2.6.5.29 OSD1 BMP Start Address LSB Register Address Offset: Default Value: Bit [7:0] Access R/W Copyright by Terawins, Inc. OSD1_21h 00h Symbol BMP_SA[7:0] Access: Size: Read/Write 8 bits Description Point to the top-left dot of BMP for displaying in OSD1 RAM. 2.6.5.30 OSD1 BMP Start Address MSB Register Address Offset: Default Value: Bit [7:5] [4:0] Access RO R/W OSD1_22h 0Bh Symbol Reserved BMP_SA[12:8] Access: Size: Read/Write 8 bits Description Point to the top-left dot of BMP for displaying in OSD1 RAM. 2.6.5.31 OSD1 BMP Alpha-Blending Control Register Address Offset: Default Value: Bit [7:6] [5:4] Access RO R/W OSD1_23h 1Ah Symbol Access: Size: Read/Write 8 bits Description [3:0] R/W Reserved BMP_FG_aB_Mode[1:0] Defines BMP alpha-blending for foreground when BG already alphaBlended: 00b: All FG need alpha-Blended if BG is alpha-Blended; 01b: All FG no need alpha-Blended; 10b: All FG no need alpha-Blended, except their color is LUT[1]; 11b: All FG no need alpha-Blended, except their color is LUT[1..3]; BMP_aB_SourcePercent[ Defines the percentage of source image/video for mixed with OSD1 3:0] BMP. 2.6.5.32 OSD1 BMP Horizontal Size LSB Register Address Offset: Default Value: Bit [7:0] Access R/W OSD1_24h 10h Symbol BMP_HSize[7:0] Access: Size: Read/Write 8 bits Description Defines the horizontal size of BMP for displaying in OSD1 RAM. Unit is how manys word (16-bits) count (before enlarged). 2.6.5.33 OSD1 BMP Horizontal Size MSB Register Address Offset: Default Value: Bit [7:3] [2:0] Access RO R/W OSD1_25h 00h Symbol Reserved BMP_HSize[10:8] Access: Size: Read/Write 8 bits Description Defines the horizontal size of BMP for displaying in OSD1 RAM. 2.6.5.34 OSD1 BMP Vertical Size LSB Register Address Offset: Default Value: Bit [7:0] Access R/W OSD1_26h 60h Symbol BMP_HSize[7:0] Access: Size: Read/Write 8 bits Description Defines the vertical size of BMP for displaying in OSD1 RAM. Unit is how many lines count (before enlarged). 28 《液 晶 之 家》 www.fpdclub.net T108 Release 2.6.5.35 OSD1 BMP Vertical Size MSB Register Address Offset: Default Value: Bit [7:3] [2:0] Access RO R/W Copyright by Terawins, Inc. OSD1_27h 00h Symbol Reserved BMP_HSize[10:8] Access: Size: Read/Write 8 bits Description Defines the vertical size of BMP for displaying in OSD1 RAM. 2.6.5.36 OSD1 BMP Horizontal Start Position LSB Register Address Offset: Default Value: Bit [7:0] Access R/W OSD1_28h 00h Symbol BMP_HStart[7:0] Access: Size: Read/Write 8 bits Description Defines the left boundary position of BMP for displaying, count in display clocks. 2.6.5.37 OSD1 BMP Horizontal Start Position MSB Register Address Offset: Default Value: Bit [7:3] [2:0] Access RO R/W OSD1_29h 03h Symbol Reserved BMP_HStart[10:8] Access: Size: Read/Write 8 bits Description Defines the left boundary position of BMP for displaying. 2.6.5.38 OSD1 BMP Vertical Start Position LSB Register Address Offset: Default Value: Bit [7:0] Access R/W OSD1_2Ah 80h Symbol BMP_VStart[7:0] Access: Size: Read/Write 8 bits Description Defines the top boundary position of BMP for displaying, count in lines. 2.6.5.39 OSD1 BMP Vertical Start Position MSB Register Address Offset: Default Value: Bit [7:3] [2:0] Access RO R/W OSD1_2Bh 02h Symbol Reserved BMP_VStart[10:8] Access: Size: Read/Write 8 bits Description Defines the top boundary position of BMP for displaying. 2.6.5.40 OSD1 BMP LUT Base Address Register Address Offset: Default Value: Bit [7:1] [0] Access R/W RO OSD1_2Ch 10h Symbol Access: Size: Read/Write 8 bits Description BMP_LUT_BaseA[7:1] Defines the LUT offset. For N-BPP BMP, its LUT segment starts with {BMP_LUT_BaseA[7:N], N’b0}; Reserved 2.6.5.41 OSD1 BMP Background Color Register Address Offset: Default Value: Bit [7:0] Access R/W OSD1_2Dh 00h Symbol BMP_BG_Color[7:0] Access: Size: Read/Write 8 bits Description Defines the address of one LUT as BMP background color. 29 《液 晶 之 家》 www.fpdclub.net T108 Release 2.6.5.42 OSD1 Block Write Data LSB Register Address Offset: Default Value: Bit [7:0] Access R/W Copyright by Terawins, Inc. OSD1_40h 00h Symbol Access: Size: Read/Write 8 bits Description OSD1_BlockWr_D[7:0] LSB Data to be block fill 2.6.5.43 OSD1 Block Write Data MSB Register Address Offset: Default Value: Bit [7:0] Access R/W OSD1_41h 00h Symbol Access: Size: Read/Write 8 bits Description OSD1_BlockWr_D[15:8] MSB Data to be block fill 2.6.5.44 OSD1 Block Write Starting Address LSB Register Address Offset: Default Value: Bit [7:0] Access R/W OSD1_42h 00h Symbol Access: Size: Read/Write 8 bits Description OSD1_BlockWr_SA[7:0] Starting Address of block fill 2.6.5.45 OSD1 Block Write Starting Address MSB Register Address Offset: Default Value: Bit [7:5] [4:0] Access RO R/W OSD1_43h 00h Symbol Access: Size: Read/Write 8 bits Description Reserved OSD1_BlockWr_SA[12:8] Starting Address of block fill 2.6.5.46 OSD1 Block Write Length Register Address Offset: Default Value: Bit [7:0] Access R/W OSD1_44h 10h Symbol Access: Size: Read/Write 8 bits Description OSD1_BlockWr_L[7:0] Block fill length (count) 2.6.5.47 OSD1 Block Write Control Register Address Offset: Default Value: Bit [7] [6] [5] [4:0] Access WO/ RO R/W RO R/W OSD1_45h 00h Symbol Access: Size: Read/Write 8 bits Description OSD1_BlockWr_Trig Set to 1 to trigger block fill operation OSD1_BlockWr_Done Get 1 means the block fill operation is done OSD1_BlockWr_mode Reserved OSD1_BlockWr_L[12:8] Block fill length (count) 30 《液 晶 之 家》 www.fpdclub.net T108 Release Copyright by Terawins, Inc. 2.7 Pattern Fill 2.7.1 Pattern Fill Register Map I/O Port Groups Index 00h 08h 09h 30h 31h 32h 33h 34h A8h – OSD1_Index A9h – OSD1_Data Pattern Fill 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch 3Dh 3Eh 3Fh Description OSD1 Pattern Fill Enable/Blinking Register OSD1 Pattern Fill Color LUT Address port OSD1 Pattern Fill Color LUT Data Port Pattern Fill Control Register Pattern Fill LUT Base Address Pattern Fill Horizontal Size Pattern Fill Vertical Size Pattern Fill Row Shift Pattern Fill Alpha Blending Control OSD1 BIST Result and Pattern Fill Enlarge Pattern Fill RAM Write Data Port Pattern Fill Horizontal Start, LSB Pattern Fill Horizontal Start, MSB Pattern Fill Vertical Start, LSB Pattern Fill Vertical Start, MSB Pattern Fill Horizontal End, LSB Pattern Fill Horizontal End, MSB Pattern Fill Vertical End, LSB Pattern Fill Vertical End, MSB 31 《液 晶 之 家》 www.fpdclub.net T108 Release 2.7.2 OSD1 Pattern Fill Color Scheme Copyright by Terawins, Inc. Pattern Fill can be implemented by Bitmap. The color mapping of Bitmap is more complicate, please refer to the following drawing. The OSD1 Pattern Fill main Color LUT is 256 entries SRAM, color in RGB565 format. 32 《液 晶 之 家》 www.fpdclub.net T108 Release 2.7.3 OSD1 Pattern Fill Configuration Registers Copyright by Terawins, Inc. 2.7.3.1 OSD1 Pattern_Fill Enable/Blinking Register Address Offset: Default Value: Bit [7] [6] [5:4] Access R/W R/W R/W OSD1PF_00h 0Ah Symbol Access: Size: Read/Write 8 bits Description [3:0] R/W OSD1PF_En Set to 1 for globally enabling OSD1 Pattern Fill function. Reserved CRAM_ByteAccess[1:0] Byte Access mode when programming character of menu: 0Xb: Word access (LSB first, then MSB byte) 10b: LSB only (not affect font index >= 256) 11b: MSB only (character BG/FG colors, Blinking, and Index bit 8) Reserved 2.7.3.2 OSD1 Pattern_Fill LUT Address Register Address Offset: Default Value: Bit [7:0] Access WO OSD1PF_08h 00h Symbol LUT_A[8:1] Access: Size: Write Only 8 bits Description Assign access pointer of Color LUT. When assigning, LUT_A[0] always = 0. LUT[0..255] are main color LUT (16-bits); LUT[256..271] are Char2BP remap LUT (24-bits); LUT[272..273]are BMP remap LUT (24-bits). 2.7.3.3 OSD1 Pattern_Fill LUT Data Port Register Address Offset: Default Value: Bit [7:0] Access WO OSD1 PF _09h 00h Symbol LUT_D[7:0] Access: Size: Write Only 8 bits Description Data written to this port will overwrite OSD2 LUT. 2.7.3.4 OSD1 Pattern_Fill Control Register Address Offset: Default Value: Bit [7] [6:4] Access R/W R/W OSD1 PF _30h 48h Symbol Patt_En Patt_ColorDepth[2:0] Access: Size: Read/Write 8 bits Description [3:2] R/W [1] [0] R/W WO Set to 1 enable Pattern_Fill to display Defines nBP color: 000b: 8BPP 001b: 1BPP 010b: 2BPP 011b: 3BPP 100b: 4BPP 101b: 5BPP 110b: 6BPP 111b: 7BPP Patt_RAM_Bit[1:0] Defines the usage in Pattern RAM: 00b: 1 bit/pixel 01b: 2 bits/pixel 10b: 4 bits/pixel 11b: 8 bits/pixel Patt_Independ_AB Set to 1 for independent Alpha-Blending setting for Pattern_Fill; set to 0 for by OSD1_0B Reset_PRAM_Pointer Write 1 to reset the Pattern RAM pointer for loading pattern data 33 《液 晶 之 家》 www.fpdclub.net T108 Release 2.7.3.5 OSD1 Pattern_Fill LUT Base Address Register Address Offset: Default Value: Bit [7:7] Access R/W Copyright by Terawins, Inc. OSD1 PF _31h 80h Symbol Patt_LUT_BaseA[7:0] Access: Size: Read/Write 8 bits Description Defines the MSB color in LUT for PatternFill color. Bit 0 is not used. 2.7.3.6 OSD1 Pattern_Fill Pattern Horizontal Size Register Address Offset: Default Value: Bit [7:0] Access R/W OSD1 PF _32h 10h Symbol Patt_HSize[7:0] Access: Size: Read/Write 8 bits Description For repeated pattern, this defines its width in the unit: Byte. 2.7.3.7 OSD1 Pattern_Fill Pattern Vertical Size Register Address Offset: Default Value: Bit [7:0] Access R/W OSD1 PF _33h 10h Symbol Patt_VSize[7:0] Access: Size: Read/Write 8 bits Description For repeated pattern, this defines its height in the unit: line. 2.7.3.8 OSD1 Pattern_Fill Pattern Row Shift Register Address Offset: Default Value: Bit [7:0] Access R/W OSD1 PF _34h 00h Symbol Patt_Row_Shift[7:0] Access: Size: Read/Write 8 bits Description For repeated pattern, this defines horizontal shift in the unit: Byte, to build a delta-type pattern. 2.7.3.9 OSD1 Pattern_Fill Color High Bits Register Address Offset: Default Value: Bit [7:4] [3:0] Access RO R/W OSD1 PF _35h 05h Symbol Reserved Patt_aB_ SourcePencent[3:0] Access: Size: Read/Write 8 bits Description Alpha Blending percentage (n/16) for Filled patterns only. If set 0000b, alpha blending is disabled (0/16 * Original Video Source + 8/8 * PatternFill display); If set 0001b, blending as 1/16 * Original Video Source + 15/16 * PatternFill display; ... If set N, blending as N/16 * Original Video Source + (16-N)/16 * PatternFill display; 2.7.3.10 OSD1 BIST Result and Pattern Enlarge Register Address Offset: Default Value: Bit [7] [6] [5:4] [3:2] [1:0] Access RO RO RO R/W R/W OSD1 PF _36h 00h Symbol Reserved OSD1_PRAM_Fail Reserved Patt_V_Enlarge[1:0] Patt_H_Enlarge[1:0] Access: Size: Read/Write 8 bits Description After OSD BIST done, get 1 in this bit shows the OSD1 PatternFill RAM is failed. For each repeated pattern, enlarge it in verical direction For each repeated pattern, enlarge it in horizontal direction 34 《液 晶 之 家》 www.fpdclub.net T108 Release 2.7.3.11 OSD1 Pattern_Fill Pattern RAM Write Port Register Address Offset: Default Value: Bit [7:0] Access WO Copyright by Terawins, Inc. OSD1 PF _37h 00h Symbol Access: Size: Read/Write 8 bits Description PRAM_WrD_Port[10:8] For building pattern, need to load via writing pattern to PRAM (Pattern RAM). After reset PRAM pointer, the PRAM pointer will increase after each burst write. 2.7.3.12 OSD1 Pattern_Fill Position, Horizontal Start LSB Register Address Offset: Default Value: Bit [7:0] Access R/W OSD1 PF _38h 00h Symbol Patt_HStart[7:0] Access: Size: Read/Write 8 bits Description Allowable pattern display region: horizontal start 2.7.3.13 OSD1 Pattern_Fill Position, Horizontal Start MSB Register Address Offset: Default Value: Bit [7:3] [2:0] Access RO R/W OSD1 PF _39h 00h Symbol Reserved Patt_HStart[10:8] Access: Size: Read/Write 8 bits Description Allowable pattern display region: horizontal start 2.7.3.14 OSD1 Pattern_Fill Position, Vertical Start LSB Register Address Offset: Default Value: Bit [7:0] Access R/W OSD1 PF _3Ah 00h Symbol Patt_VStart[7:0] Access: Size: Read/Write 8 bits Description Allowable pattern display region: vertical start 2.7.3.15 OSD1 Pattern_Fill Position, Vertical Start MSB Register Address Offset: Default Value: Bit [7:3] [2:0] Access RO R/W OSD1 PF _3Bh 00h Symbol Reserved Patt_VStart[10:8] Access: Size: Read/Write 8 bits Description Allowable pattern display region: vertical start 2.7.3.16 OSD1 Pattern_Fill Position, Horizontal End LSB Register Address Offset: Default Value: Bit [7:0] Access R/W OSD1 PF _3Ch 00h Symbol Patt_HEnd[7:0] Access: Size: Read/Write 8 bits Description Allowable pattern display region: horizontal End 2.7.3.17 OSD1 Pattern_Fill Position, Horizontal End MSB Register Address Offset: Default Value: Bit [7:3] [2:0] Access RO R/W OSD1 PF _3Dh 01h Symbol Reserved Patt_HEnd[10:8] Access: Size: Read/Write 8 bits Description Allowable pattern display region: horizontal End 35 《液 晶 之 家》 www.fpdclub.net T108 Release 2.7.3.18 OSD1 Pattern_Fill Position, Vertical End LSB Register Address Offset: Default Value: Bit [7:0] Access R/W Copyright by Terawins, Inc. OSD1 PF _3Eh 80h Symbol Patt_VEnd[7:0] Access: Size: Read/Write 8 bits Description Allowable pattern display region: vertical End 2.7.3.19 OSD1 Pattern_Fill Position, Vertical End MSB Register Address Offset: Default Value: Bit [7:3] [2:0] Access RO R/W OSD1 PF _3Fh 00h Symbol Reserved Patt_VEnd[10:8] Access: Size: Read/Write 8 bits Description Allowable pattern display region: vertical End 36 《液 晶 之 家》 www.fpdclub.net T108 Release Copyright by Terawins, Inc. 3 Register Description Serial Bus Register Set Page 0 3.1 ADC Register Set 3.1.1 Mid-level Clamp Voltage Register Address Offset: Default Value: Bit [7:6] [5:4] [3:2] [1:0] Access RO R/W R/W R/W 05h 00h Symbol Access: Size: Read/Write 8 bits Description Reserved B_Clamp_Volt_Sel[1:0] Blue channel Clamp voltage select G_Clamp_Volt_Sel[1:0] Green channel Clamp voltage select R_Clamp_Volt_Sel[1:0] Red channel Clamp voltage select 3.1.2 ADC Channel 0 Static Gain Address Offset: Default Value: Bit [7:0] Access R/W 07h FFh Symbol ADCRSG Access: Size: Read/Write 8 bits Description This register can set a fixed gain for ADC channel 0 when static gain control is enabled 3.1.3 ADC Channel 1 Static Gain Address Offset: Default Value: Bit [7:0] Access R/W 08h FFh Symbol ADCGSG Access: Size: Read/Write 8 bits Description This register can set a fixed gain for ADC channel 1 when static gain control is enabled 3.1.4 ADC Channel 2 Static Gain Address Offset: Default Value: Bit [7:0] Access R/W 09h FFh Symbol ADCBSG Access: Size: Read/Write 8 bits Description This register can set a fixed gain for ADC channel 2 when static gain control is enabled 3.1.5 ADC Channel 0 Offset Address Offset: Default Value: Bit [7:2] [1:0] Access R/W RO 0Ah 60h Symbol ADC_ROFF Reserved Access: Size: Read/Write 8 bits Description ADC Channel 0 DC Offset Control 37 《液 晶 之 家》 www.fpdclub.net T108 Release 3.1.6 ADC Channel 1 Offset Address Offset: Default Value: Bit [7:2] [1:0] Access R/W RO Copyright by Terawins, Inc. 0Bh 60h Symbol ADC_GOFF Reserved Access: Size: Read/Write 8 bits Description ADC Channel 1 DC Offset Control 3.1.7 ADC Channel 2 Offset Address Offset: Default Value: Bit [7:2] [1:0] Access R/W RO 0Ch 60h Symbol ADC_BOFF Reserved Access: Size: Read/Write 8 bits Description ADC Channel 2 DC Offset Control 3.1.8 ADC General Control Configuration Register Address Offset: Default Value: Bit [7] [6] Access RO R/W 0Dh 20h Symbol Reserved CLPMD Access: Size: Read/Write 8 bits Description Clamping mode Mode 0 1 [5] [4] [3] [2] [1] [0] R/W R/W R/W RO R/W R/W DCEN DCSEL Reserved DC_CAL_RDY DC_CALEN DC_CALMD DC Clamping Enable Clamping Source Selection Test only, vmode DC Calibration Ready DC Calibration Enable DC Calibration Mode Type Fixed window Locked Window Mode 0 1 Type minimum average 3.1.9 ADC Gain ReadBack Address Offset: Default Value: Bit [7:0] Access R 0Eh Symbol adc_auto_gain Access: Size: Read Only 6 bits Description ADC automatic gain control read back. 3.1.10 ADC Power Down Control Address Offset: Default Value: Bit [7] [6] [5] Access R/W R/W R/W 0Fh 00h Symbol PwDn_SOY PD2 (B) PD1 (G) Access: Size: Read/Write 8 bits Description 1 for Power down SOY slicer 1: Power down 0: Power up 1: Power down 0: Power up 38 《液 晶 之 家》 www.fpdclub.net T108 Release [4] [3:1] [0] R/W R/W RO PD0 (R) Reserved Reserved 1: Power down 0: Power up Copyright by Terawins, Inc. 3.1.11 ADC Polarity Control 10h E8h Symbol Address Offset: Default Value: Bit [7] [6] [5] [4] [3] [2] [1] [0] Access RO/WO RO/WO R/W R/W R/W R/W R/W R/W Access: Size: Read/Write 8 bits Description HSi_Polarity / HSi_Inv_ When Read: get input HSync polarity When writing, to invert (0) or non-invert (1) input HSync VSi_Polarity / VSi_Inv_ When Read: get input VSync polarity When writing, to invert (0) or non-invert (1) input VSync SOY_Inv_ For invert (0) or non-invert (1) input SOY Auto_Polarity Set to 1 for enabling auto-adjusting HSync/VSync polarity. Clamp_Polarity Set to 1 for controlling Clamp positive polarity. Clamp_Sel_GfbHS Set to 1 to use PLL feedback HSync as clamp reference Clamp_Leading Set to 1 to use leading edge of HSync as clamp reference point. Clamp_Sel_RGB Clamp control by: 1: RGB/SOY logic, 0: VD logic. 3.1.12 YPbPr Clamping Control Register 11h 98h Symbol SOY_Threshold SOY_Discharge BSCALE GSCALE RSCALE Address Offset: Default Value: Bit [7:5] [4:3] [2] [1] [0] Access R/W R/W R/W R/W R/W Access: Size: Read/Write 8 bits Description Voltage threshold for SOY slicing SOY Discharge option ADC Channel 2 Clamping Mode 0: Clamp to Ground; 1: Clamp to mid-scale ADC Channel 1 Clamping Mode 0: Clamp to Ground; 1: Clamp to mid-scale ADC Channel 0 Clamping Mode 0: Clamp to Ground; 1: Clamp to mid-scale 3.1.13 SOY Slice Control 12h 06h Symbol Address Offset: Default Value: Bit [7] [6:5] [4] [3:2] [1:0] Access Access: Size: Read/Write 8 bits Description RO/WO Done_ / En_Slicer_Status When read: get flag of Slicer status ready or not When write, to enable monitoring Slicer status RO Slicer_Status 0:Slicer always low, 1: always high, 2: almost low, 3: almost high R/W Reserved R/W SOY_ClampPlacement SOY Clamp Placement R/W SOY_ClampDuration SOY Clamp Duration. 39 《液 晶 之 家》 www.fpdclub.net T108 Release 3.1.14 VSync Separation Register 13h 08h Symbol CSync_Detect_Done Fs_TooFast En_CSync_Detect Reserved Reserved Reserved Div_To14[1:0] Copyright by Terawins, Inc. Address Offset: Default Value: Bit [7] [6] [5] [4] [3] [2] [1:0] Access RO RO R/W R/W R/W R/W R/W Access: Size: Read/Write 8 bits Description flag of whether CSync Detection is done or not Get 1 if CSync Detecting operation clock is too fast Set to 1 for enabling CSync Detection function Reserved for chip testing, should set 0 for normal operation Reserved for special case, set to 1 for normal conditions Reserved for special case, set to 0 for normal conditions 00b: power down or reset, 01b: XCLK/1, 10b:XCLK/2 (normal operation for XCLK=27MHz); 11b: XCLK/3 3.1.15 Sync Routine Control Address Offset: Default Value: Bit [7] [6] [5] [4] [3] [2] [1] [0] Access R/W R/W R/W R/W R/W R/W R/W R/W 14h D1h Symbol HS2PLL_Polarity Coast2PLL_Polarity ADC_is_RGB HSo_Sel_Fdbk HRef_Sel_SOY VS_Sel_Sep Coast_Sel_Sep Reserved Access: Size: Read/Write 8 bits Description HRef polarity Coast polarity ADC Color space select: Set 1 for RGB input, 0 for YPbPr input. ADC HSo source from PLL when set to 1 PLL HRef from: 1: SOY Slicer (SOY); 0: HS input pin (SS/CS) ADC VSo from: 1: VSync Detect (SOY/CS); 0: VS input pin (SS) PLL Coast from: 1: VSync Detect (SOY/CS); 0: Ground (SS) 3.1.16 Line Lock PLL Divider Register 1 Address Offset: Default Value: Bit [7:0] Access R/W 15h 5Ah Symbol APLL_Div[7:0] Access: Size: Read/Write 8 bits Description PLL divider LSB 3.1.17 Line Lock PLL Divider Register 2 Address Offset: Default Value: Bit [7] [6] [5] [4] [3:0] Access R/W R/W R/W RO R/W 16h C3h Symbol APLL_PowerDown APLL_Sel_HighFreq APLL_Reset ADC_Clock_From APLL_Div[11:8] Access: Size: Read/Write 8 bits Description 1: power down, 0: enable Reserved for testing, 1: high freq., 0: low freq. 1: Reset Line-lock PLL 0: normal operation for RGB and SOY inputs ADC clock source: 1: XCLK; 0:APLL output PLL divider MSB 40 《液 晶 之 家》 www.fpdclub.net T108 Release 3.1.18 VCO & Charge Pump Register Address Offset: Default Value: Bit [7:6] [5:3] [2] [1] [0] Access R/W R/W R/W R/W R/W Copyright by Terawins, Inc. 17h 48h Symbol ADC_VCO ADC_ChargePump AutoClampV_B AutoClampV_G AutoClampV_R Access: Size: Read/Write 8 bits Description Reserved for testing Reserved for testing Reserved for testing 3.1.19 Analog Source MUX Selection Address Offset: Default Value: Bit [7:6] [5:4] Access RO R/W 18h 00h Symbol Reserved AI2SEL (B) Access: Size: Read/Write 8 bits Description [3:2] R/W AI1SEL (G) [1:0] R/W AI0SEL (R) Analog mux selection for ADC channel 2 00: ACB1 01: ACB0 1x: ACB2 Analog mux selection for ADC channel 1 00: AY1 01: AY0 1x: AY2 Analog mux selection for ADC channel 0 00: ACR1 01: ACR0 1x: ACR2 3.1.20 Y/Cb/Cr Data Switching Control 19h 07h Symbol Reserved CBINSEL Address Offset: Default Value: Bit [7:6] [5:4] Access RO R/W Access: Size: Read/Write 8 bits Description [3:2] R/W YINSEL [1:0] R/W CRINSEL The digitaized CB or B data can be taken from one of 3 ADCs: 00: ADC Ch0 01: ADC Ch1 1X: ADC Ch2 The digitaized Y or Composite or G data can be taken from one of 3 ADCs: 00: ADC Ch0 01: ADC Ch1 1X: ADC Ch2 The digitaized CR or Chroma or R data can be taken from one of 3 ADCs: 00: ADC Ch0 01: ADC Ch1 1X: ADC Ch2 41 《液 晶 之 家》 www.fpdclub.net T108 Release 3.1.21 ADC Analog AGC Selection Address Offset: Default Value: Bit [7:6] Access R/W Copyright by Terawins, Inc. 1Ah 87h Symbol AGC_GAINMD Access: Size: Read/Write 8 bits Description Mode 0 1 2 3 If 0, refer to ADCBSG (P0_09h): 0: Static gain; 1: Dynamic gain If 0, refer to ADCGSG (P0_08h) 0: Static gain; 1: Dynamic gain If 0, refer to ADCRSG (P0_07h) 0: Static gain; 1: Dynamic gain Type Positive gain Positive gain 1x~2x Negative gain 1x~2x Negative gain [5:3] [2] [1] [0] RO R/W R/W R/W Reserved CB_AGC_SEL Y_AGC_SEL CR_AGC_SEL 3.1.22 Blank Sync Level Address Offset: Default Value: Bit [7:0] Access R/W 1Ch F0h Symbol BLANK_SL Access: Size: Read/Write 8 bits Description 3.1.23 ADC Phase Setting Register Address Offset: Default Value: Bit [7:3] [2] [1] [0] Access R/W R/W R/W R/W 20h 80h Symbol ADC_Phase[4:0] ADC_Clk_Div2 ADC_Clk_Dly ADC_Clk_Inv Access: Size: Read/Write 8 bits Description 32 phases per clock Clock divided by 2 if set to 1 Clock delay if set to 1 Clock inverted if set to 1 3.1.24 ADC Detection Register Address Offset: Default Value: Bit [7] [6:5] Access RO/WO R/W 21h 00h Symbol Done_ATK / En_ATK ATK_Channel[1:0] Access: Size: Read/Write 8 bits Description When read: get flag of Phases Tracking finish or not When write, to enable Phases Tracking Select which channel to perform ATK: 00: R+G+B 01: R 10: G 11: B When read: get flag of Checking ADC HS/VS finish or not When write, to enable Checking ADC HS/VS HSync input toggle when read 1 HSync input toggle when read 1 [4:3] [2] [1] [0] RO RO/WO RO RO Reserved Done_Exist_ADC / En_Exist_ADC Exist_HSync Exist_VSync 42 《液 晶 之 家》 www.fpdclub.net T108 Release 3.1.25 ADC Phase Tracking Register 1 Address Offset: Default Value: Bit [7:0] Access RO Copyright by Terawins, Inc. 22h XXh Symbol ATK_Accu[7:0] Access: Size: Read Only 8 bits Description Accumulated Phase Tracking Result 3.1.26 ADC Phase Tracking Register 2 Address Offset: Default Value: Bit [7:0] Access RO 23h XXh Symbol ATK_Accu[15:8] Access: Size: Read Only 8 bits Description Accumulated Phase Tracking Result 3.1.27 ADC Phase Tracking Register 3 Address Offset: Default Value: Bit [7:0] Access RO 24h XXh Symbol ATK_Accu[23:16] Access: Size: Read Only 8 bits Description Accumulated Phase Tracking Result 3.1.28 Boundary Control Register 26h 04h Symbol Done_Boundary / En_Boundary Boundary_hDE Address Offset: Default Value: Bit [7] [6] Access RO/WO R/W Access: Size: Read/Write 8 bits Description [5:3] [2:0] R/W R/W When read: get flag of Boundary Detection finish or not When write, to enable Boundary Detection Check boundary when: 0: in all range 1: in HDE window Boundary_Mask_HS_L Set the do not care range near HSync leading edge Boundary_Mask_HS_T Set the do not care range near HSync trailing edge 3.1.29 Boundary Control Register 27h 40h Symbol Boundary_Threshold Address Offset: Default Value: Bit [7:0] Access R/W Access: Size: Read/Write 8 bits Description Set the color threshold for boundary detection 3.1.30 Boundary Left LSB Register Address Offset: Default Value: Bit [7:0] Access RO 28h XXh Symbol Left_Bound[7:0] Access: Size: Read Only 8 bits Description Left Boundary Position 3.1.31 Boundary Left MSB Register Address Offset: Default Value: Bit [7:3] [2:0] Access RO RO 29h XXh Symbol Reserved Left_Bound[10:8] Access: Size: Read Only 8 bits Description Left Boundary Position 43 《液 晶 之 家》 www.fpdclub.net T108 Release 3.1.32 Boundary Right LSB Register Address Offset: Default Value: Bit [7:0] Access RO Copyright by Terawins, Inc. 2Ah XXh Symbol Right_Bound[7:0] Right Boundary Position Access: Size: Read Only 8 bits Description 3.1.33 Boundary Right MSB Register Address Offset: Default Value: Bit [7:3] [2:0] Access RO RO 2Bh XXh Symbol Reserved Right_Bound[10:8] Access: Size: Read Only 8 bits Description Right Boundary Position 3.1.34 Boundary Top LSB Register Address Offset: Default Value: Bit [7:0] Access RO 2Ch XXh Symbol Top_Bound[7:0] Access: Size: Read Only 8 bits Description Top Boundary Position 3.1.35 Boundary Top MSB Register Address Offset: Default Value: Bit [7:2] [1:0] Access RO RO 2Dh XXh Symbol Reserved Top_Bound[9:8] Access: Size: Read Only 8 bits Description Top Boundary Position 3.1.36 Boundary Bottom LSB Register Address Offset: Default Value: Bit [7:0] Access RO 2Eh XXh Symbol Bottom_Bound[7:0] Access: Size: Read Only 8 bits Description Bottom Boundary Position 3.1.37 Boundary Bottom MSB Register Address Offset: Default Value: Bit [7:2] [1:0] Access RO RO 2Fh XXh Symbol Reserved Bottom_Bound[9:8] Access: Size: Read Only 8 bits Description Bottom Boundary Position 44 《液 晶 之 家》 www.fpdclub.net T108 Release Copyright by Terawins, Inc. 3.2 Input Timing Register Set 3.2.1 De-Interlaced Process & Vertical Shadow Control Register Address Offset: Default Value: Bit [7:6] [5] Access RO R/W 30h 82h Symbol Reserved VST_CHGSEL Access: Size: Read/Write 8 bits Description [4] R/W INT_EDGE [3] R/W LB_SIZE_FIXED [2] [1] [0] R/W R/W R/W ENQKHS ITLCPRO ADC_Odd_in_HsVs 1:Vsync timing change determined by 8*# of XCLK 0:Vsync timing change determined by # of hsync (default) # can be assigned at Reg 0x3A Interrupt polarity 1: positive 0: negative (default) This bit control capture size for Scaler. 1: Hsize and Vsize are assigned by 54h ~57h 0: sizes assigned by input sources. (default) Reserved for chip teset only, set to 0 for normal operation Set 1 for interlaced video (default) Set 0 for non-interlaced video Set to 1 for enabling detecting Odd flag from HS/VS pins 3.2.2 Source Select Register Address Offset: Default Value: Bit [7] [6:4] Access RO R/W 31h 04h Symbol ITLCFLM VIP_Sel[2:0] Access: Size: Read/Write 8 bits Description [3:2] R/W InSource_Sel[1:0] Indicates incoming video signal is interlaced if get 1 Select the digital input source (VIP: Video Input): 000: A656 001: B656 010: L601_8bits 011: L601_16bits 100: Reserved 101: RGB565 110: RGB666 111: RGB888 Select the input source: 00: Digital VIP input 01: select VD input (CVBS, S-Video, YPbPr) 10: Select ADC RGB, SOY(YPbPr) 11: Reserved Current VBI field information [1] [0] RO RO Reserved VBI_Field 45 《液 晶 之 家》 www.fpdclub.net T108 Release 3.2.3 Interrupt Status Register Address Offset: Default Value: Bit [7:0] Access RO/W1C Copyright by Terawins, Inc. 32h 00h Symbol INTSTS Access: Size: Read-only / Write-1-to-clear 8 bits Description Read to get interrupt trigger source, Write 1 to clear it. [7]: IR packet received [6]: VBI packet is valid for processing [5]: Every VSync Leading Edge [4]: Timer time out [3]: HSync Timing Changed [2]: VSync Timing Changed [1]: Lost HSync [0]: Lost VSync 3.2.4 Interrupt Mask Register Address Offset: Default Value: Bit [7:0] Access R/W 33h FFh Symbol INTMASK Access: Size: Read/Write 8 bits Description Set to 1 for masking relative interrupt trigger source: [7]: IR packet received [6]: VBI packet is valid for processing [5]: Every VSync Leading Edge [4]: Timer time out [3]: HSync Timing Changed [2]: VSync Timing Changed [1]: Lost HSync [0]: Lost VSync 3.2.5 Interrupt Status/Mask 2 Register Address Offset: Default Value: Bit [7:5] [4] [3:1] [0] Access R/W R/W RO/W1C RO/W1C 34h 10h Symbol Reserved INTMASK_2 Reserved INTSTS_2 Access: Size: Read/Write 8 bits Description Set to 1 for masking relative interrupt trigger source: [4]: SAR1_Toggling Read to get interrupt trigger source, Write 1 to clear it. [0]: SAR1_Toggling 3.2.6 VD/656 Left Border Crop Register Address Offset: Default Value: Bit [7:6] [5:0] Access RO R/W 3Ch 00h Symbol Reserved CROP_LEFTB Access: Size: Read/Write 8 bits Description Remove noisy pixels appearing on left border. 1LSB =1 pixel 46 《液 晶 之 家》 www.fpdclub.net T108 Release 3.2.7 VD/656 VSync Offset Register Address Offset: Default Value: Bit [7] Access R/W Copyright by Terawins, Inc. 3Dh 00h Symbol VD_VsOfs_Mode Access: Size: Read/Write 8 bits Description VD/656 VSync Offset mode: 0: Crop Top Border 1: VSync Offset, delay lines Remove noisy pixels appearing on top border or re-shape VSync 1LSB =1 line, value 0 means disable. [6] [5:0] RO R/W Reserved VD_VsOffset 3.2.8 VD/656 Left Border Crop Register Address Offset: Default Value: Bit [7] [6] [5:0] Access R/W R/W R/W 3Eh 10h Symbol En_VD_VsOfs_P1 VD_VsOfs_on_Odd VD_VsBP Access: Size: Read/Write 8 bits Description Enable VSync Offset add 1 line for even or odd field on VD path Set to 1 for selecting VD VSync Offset delay 1 line on Odd field; Set to 0 for Even field. This bit works only when En_VD_VsOfs_P1=1. VD/656 VSync Back Proch (# lines) 3.2.9 Input Sync Signal Detection Register Address Offset: Default Value: Bit [7] [6] Access R/W R/W 3Fh 00h Symbol HSTLSPVS AUTOVSD6 Access: Size: Read/Write 8 bits Description 1:use trailing edge of hsync to sample 0:use leading edge of hsync to sample When the edges of vsync and hsync are too close, input detection circuit can delay vsync 6 cycle of XCLK to avoid unstable detection 1:Automatically delay 6 cycles of XCLK if CFSEEDGE is true. 0:Dealy 6 cycles of XCLK if FCVSD6 is true [5] [4] [3] [2] [1:0] R/W RO RO RO RO Reserved CFSEEDGE HS_Polarity VS_Polarity Reserved VS and HS edges are too close. Detected HSync polarity (for Analog RGB raw input) Detected VSync polarity (for Analog RGB raw input) 3.2.10 ADC Sync Offset Control Register Address Offset: Default Value: Bit [7] [6] [5] [4] [3:2] [1] [0] Access R/W R/W R/W R/W RO R/W R/W 40h D0h Symbol En_HsOffset En_VsOffset En_VsOfs_Evn_P1 SOY_Odd_Inv_ Reserved RGB_PowerDown_ HS_in_SyncSel Access: Size: Read/Write 8 bits Description Set to 1 for enabling ADC HSync Offset. Set to 1 for enabling ADC VSync Offset. Set to 1 for enabling ADC VSync Offset delay 1 line for even field. Set to 0 for inverting SOY Odd field flag. Set to 0 for power down RGB related logic. 1 for enabling RGB path. Select the sampling edge of HSync pin. 47 《液 晶 之 家》 www.fpdclub.net T108 Release 3.2.11 ADC HSync Offset LSB Register Address Offset: Default Value: Bit [7:0] Access R/W Copyright by Terawins, Inc. 41h 02h Symbol HsOffset[7:0] Delay ADC HSync by # dots. Access: Size: Read/Write 8 bits Description 3.2.12 ADC HSync Offset MSB Register Address Offset: Default Value: Bit [7:3] [2:0] Access RO R/W 42h 00h Symbol Reserved HsOffset[10:8] Access: Size: Read/Write 8 bits Description Delay ADC HSync by # dots. 3.2.13 ADC VSync Offset LSB Register Address Offset: Default Value: Bit [7:0] Access R/W 43h 01h Symbol VsOffset[7:0] Access: Size: Read/Write 8 bits Description Delay ADC VSync by # lines. 3.2.14 ADC VSync Offset MSB Register Address Offset: Default Value: Bit [7:2] [1:0] Access RO R/W 44h 00h Symbol Reserved VsOffset[9:8] Access: Size: Read/Write 8 bits Description Delay ADC VSync by # lines. 3.2.15 ADC HSync Offset Pulse Width Register Address Offset: Default Value: Bit [7:0] Access R/W 45h 10h Symbol HsPulseWidth[7:0] Access: Size: Read/Write 8 bits Description Pulse width of the regenerated ADC HSync (# dots). 3.2.16 ADC VSync Offset Pulse Width Register Address Offset: Default Value: Bit [7:4] [3:0] Access RO R/W 46h 01h Symbol Reserved VsPulseWidth[3:0] Access: Size: Read/Write 8 bits Description Pulse width of the regenerated ADC VSync (# lines). 48 《液 晶 之 家》 www.fpdclub.net T108 Release 3.2.17 ADC Capture Control Register Address Offset: Default Value: Bit [7] [6] [5] [4] [3:1] [0] Access R/W R/W R/W R/W RO R/W Copyright by Terawins, Inc. 47h 00h Symbol Mask_H_Left Mask_H_Right Mask_V_Top Mask_V_Bottom Reserved Reserved Access: Size: Read/Write 8 bits Description Set to 1 for mask left portion when wrap. Set to 1 for mask right portion when wrap. Set to 1 for mask top portion when wrap. Set to 1 for mask bottom portion when wrap. Reserved for chip test only 3.2.18 ADC Capture HSize LSB Register Address Offset: Default Value: Bit [7:0] Access R/W 48h 00h Symbol ADC_HSize[7:0] Access: Size: Read/Write 8 bits Description ADC Capture window: Horizontal Size (# dots). 3.2.19 ADC Capture HSize MSB Register Address Offset: Default Value: Bit [7:3] [2:0] Access RO R/W 49h 02h Symbol Reserved ADC_HSize[10:8] Access: Size: Read/Write 8 bits Description ADC Capture window: Horizontal Size (# dots). 3.2.20 ADC Capture VSize LSB Register Address Offset: Default Value: Bit [7:0] Access R/W 4Ah E0h Symbol ADC_VSize[7:0] Access: Size: Read/Write 8 bits Description ADC Capture window: Vertical Size (# lines). 3.2.21 ADC Capture VSize MSB Register Address Offset: Default Value: Bit [7:2] [1:0] Access RO R/W 4Bh 01h Symbol Reserved ADC_VSize[9:8] Access: Size: Read/Write 8 bits Description ADC Capture window: Vertical Size (# lines). 3.2.22 ADC Capture HSync Back Porch LSB Register Address Offset: Default Value: Bit [7:0] Access R/W 4Ch 10h Symbol ADC_HStart[7:0] Access: Size: Read/Write 8 bits Description ADC Capture window: HSync Start Point (# dots). 49 《液 晶 之 家》 www.fpdclub.net T108 Release 3.2.23 ADC Capture HSync Back Porch MSB Register Address Offset: Default Value: Bit [7:3] [2:0] Access RO R/W Copyright by Terawins, Inc. 4Dh 00h Symbol Reserved ADC_HStart[10:8] Access: Size: Read/Write 8 bits Description ADC Capture window: HSync Start Point (# dots). 3.2.24 ADC Capture VSync Back Porch LSB Register Address Offset: Default Value: Bit [7:0] Access R/W 4Eh 05h Symbol ADC_VStart[7:0] Access: Size: Read/Write 8 bits Description ADC Capture window: VSync Start Point (# linees). 3.2.25 ADC Capture VSync Back Porch MSB Register Address Offset: Default Value: Bit [7:2] [1:0] Access RO R/W 4Fh 00h Symbol Reserved ADC_VStart[9:8] Access: Size: Read/Write 8 bits Description ADC Capture window: VSync Start Point (# linees). 50 《液 晶 之 家》 www.fpdclub.net T108 Release Copyright by Terawins, Inc. 3.3 Picture Enhancement Register Set 3.3.1 DCTI Control Register Address Offset: Default Value: Bit [7:3] [2] [1] [0] Access RO R/W RO R/W 60h 00h Symbol Reserved DCTi_Dist_Sel Reserved DLTi_Dist_Sel Access: Size: Read/Write 8 bits Description DCTI distance selection: 1 for longer distance DLTI distance selection: 1 for longer distance 3.3.2 Peaking Register Address Offset: Default Value: Bit [7] [6] [5:0] Access R/W R/W R/W 61h 08h Symbol Peaking_En Peaking_LR_Disable Peaking_Coring Access: Size: 8 bits Description Enable Peaking function Peaking boundary mode 3.3.3 Peaking Band-Pass Coefficient Register Address Offset: Default Value: Bit [7:5] [4:0] Access RO R/W 62h 04h Symbol Reserved Peaking_BP_Coef Access: Size: 8 bits Description 3.3.4 Peaking High-Pass Coefficient Register Address Offset: Default Value: Bit [7:5] [4:0] Access RO R/W 63h 04h Symbol Reserved Peaking_HP_Coef Access: Size: 8 bits Description 3.3.5 Peaking Low-Pass Coefficient Register Address Offset: Default Value: Bit [7:3] [1:0] Access RO R/W 64h 02h Symbol Reserved Peaking_LP_Coef Access: Size: 8 bits Description 3.3.6 DCTI_0 Gain and Coring Register Address Offset: Default Value: Bit [7:5] [4:0] Access R/W R/W 65h 08h Symbol DCTI_GAIN_0 DCTI_CO_0 Access: Size: Read/Write 8 bits Description 51 《液 晶 之 家》 www.fpdclub.net T108 Release 3.3.7 DCTI_1 Gain and Coring Register Address Offset: Default Value: Bit [7:5] [4:0] Access R/W R/W Copyright by Terawins, Inc. 66h 08h Symbol DCTI_GAIN_1 DCTI_CO_1 Access: Size: Read/Write 8 bits Description 3.3.8 Cb/Cr Delay control Address Offset: Default Value: Bit [7] Access R/W 67h 1Eh Symbol U_delay Access: Size: Read/Write 8 bits Description [6:5] R/W V_delay [4:0] R/W DCTI_Threshold Cb signal delay control. 0: no delay (default) 1: 1 pixel delay Cr signal delay control. 00: no delay (default) 01: 1 pixel delay 10: 2 pixel delay 11: 3 pixel delay DCTI performing Threshold Limit 3.3.9 Contrast Adjust Register Address Offset: Default Value: Bit [7:0] Access R/W 68h 80h Symbol LumaCON Access: Size: Read/Write 8 bits Description 3.3.10 Brightness Adjust Register 69h 80h Symbol LumaBRI Address Offset: Default Value: Bit [7:0] Access R/W Access: Size: Read/Write 8 bits Description 3.3.11 Hue Sin Adjust Register 6Ah 00h Symbol HueSin Address Offset: Default Value: Bit [7:0] Access R/W Access: Size: Read/Write 8 bits Description 3.3.12 Hue Cos Adjust Register Address Offset: Default Value: Bit [7:0] Access R/W 6Bh 7Fh Symbol HueCos Access: Size: Read/Write 8 bits Description 52 《液 晶 之 家》 www.fpdclub.net T108 Release 3.3.13 Chroma Saturation Adjust Register 6Ch 80h Symbol ChomSat Copyright by Terawins, Inc. Access: Size: Read/Write 8 bits Description Address Offset: Default Value: Bit [7:0] Access R/W 3.3.14 Black Level Expansion Threshold Register Address Offset: Default Value: Bit [7:0] Access R/W 6Eh 10h Symbol BLE_TH Access: Size: Read/Write 8 bits Description 3.3.15 VIP Black level Expansion Gain / Offset Control Register 6Fh 00h Symbol BLE_GAIN Reserved BLE_OFFSET Address Offset: DefaultValue: Bit [7:4] [3:2] [1:0] Access R/W RO R/W Access: Size: Read/Write 8 bits Description 53 《液 晶 之 家》 www.fpdclub.net T108 Release Copyright by Terawins, Inc. 3.4 Scaling Register Set 3.4.1 Scaling General Control Register Address Offset: Default Value: Bit [7:6] [5] [4:3] [2:1] [0] Access R/W R/W R/W RO WO 70h 00h Symbol Reserved Inv_VideoF Reserved Reserved Coef_Pointer_Reset Access: Size: Read/Write 8 bits Description Inv_VideoF: Reverse input odd field control for intra-field scaling, only take action when ITLCPRO set to 1. Write 1 to reset pointer, must be performed before programming scaling coefficients. 3.4.2 Horizontal Scale Step LSB Register Address Offset: Default Value: Bit [7:0] Access R/W 72h 00h Symbol H_Scale_Step [7:0] Access: Size: Read/Write 8 bits Description 3.4.3 Horizontal Scale Step MSB Register Address Offset: Default Value: Bit [7:0] Access R/W 73h 80h Symbol H_Scale_Step [15:8] Access: Size: Read/Write 8 bits Description 3.4.4 Vertical Scale Step LSB Register Address Offset: Default Value: Bit [7:0] Access R/W 74h 00h Symbol V_Scale_Step [7:0] Access: Size: Read/Write 8 bits Description 3.4.5 Vertical Scale Step MSB Register Address Offset: Default Value: Bit [7:0] Access R/W 75h 80h Symbol V_Scale_Step [15:8] Access: Size: Read/Write 8 bits Description 3.4.6 Horizontal Aspect Ratio LSB Register Address Offset: Default Value: Bit [7:0] Access R/W 76h 00h Symbol H_Aspect[7:0] Access: Size: Read/Write 8 bits Description Horizontal Aspect Ratio [7:0] 54 《液 晶 之 家》 www.fpdclub.net T108 Release 3.4.7 Horizontal Aspect Ratio MSB Register Address Offset: Default Value: Bit [7] [6] Access R/W R/W Copyright by Terawins, Inc. 77h 00h Symbol Access: Size: Read/Write 8 bits Description [5:4] [3:0] RO R/W H_Aspect_En Horizontal Aspect Ratio Enable HASP_Center_Enlarge Horizontal Aspect adjusting effect: 0: Center portion shrink 1: Center portion enlarge Reserved H_Aspect[11:8] Horizontal Aspect Ratio [11:8] 3.4.8 Low Pass Filter Register Address Offset: Default Value: Bit [7] [6] [5:4] [3] [2] [1:0] Access R/W RO R/W R/W RO R/W 78h 00h Symbol En_Half_input Reserved LP_Average[1:0] LP_Boundary_Dup Reserved LP_ShiftDot[1:0] Access: Size: Read/Write 8 bits Description Enable Low pass Shift average level in Low Pass enabled Duplicate the first dot or not Shift dot count during Low Pass enabled 3.4.9 Frame Color (Luma-Y) in Scaler Register Address Offset: Default Value: Bit [7:0] Access R/W 7Dh 10h Symbol Scale_Frame_Y[7:0] Access: Size: Read/Write 8 bits Description Background (Frame) Y Color of Scaler. 3.4.10 Frame Color (Chroma-U) in Scaler Register Address Offset: Default Value: Bit [7:0] Access R/W 7Eh 80h Symbol Scale_Frame_U[7:0] Access: Size: Read/Write 8 bits Description Background (Frame) U Color of Scaler. 3.4.11 Frame Color (Chroma-V) in Scaler Register 7Fh 80h Symbol Scale_Frame_V[7:0] Address Offset: Default Value: Bit [7:0] Access R/W Access: Size: Read/Write 8 bits Description Background (Frame) V Color of Scaler. 3.4.12 Line Buffer Configuration LSB Register 84h 00h Symbol LBPRFL[7:0] Address Offset: Default Value: Bit [7:0] Access R/W Access: Size: Read/Write 8 bits Description LBPRFL can cause a time dealy in XCLK count between the leading edge of input Vsync and leading edge of output Vsync. 55 《液 晶 之 家》 www.fpdclub.net T108 Release 3.4.13 Line Buffer Configuration MSB Register 85h 01h Symbol LBPRFL[15:8] Copyright by Terawins, Inc. Access: Size: Read/Write 8 bits Description Address Offset: Default Value: Bit [7:0] Access R/W 3.4.14 Left Display Border Configuration LSB Register Address Offset: Default Value: Bit [7:0] Access R/W 88h 00h Symbol HLDSPLB[7:0] Access: Size: Read/Write 8 bits Description When Output pixel’s index is less than HRDSPLB, output pixel value is assigned as left display border with Frame color: {FMCLRRED, FMCLRGRN , FMCLRBLU} 3.4.15 Left Display Border Configuration MSB Register Address Offset: Default Value: Bit [7] Access R/W 89h 00h Symbol HDSPLB_INV Access: Size: Read/Write 8 bits Description [6] R/w VDSPLB_INV [5] R/W HDSPLB_STY [4] R/W VDSPLB_STY Horizontal border is on if HDSPLB_INV is set as follows 1: HLDSPLB < Horizontal border < HRDSPLB 0: Horizontal border < HLDSPLB or it > HRDSPLB Vertical border is on if VDSPLB_INV is set as follows 1: VTDSPLB < < VBDSPLB 0: Vertical border < VTDSPLB or it > VBDSPLB Horizontal Border style 1: mesh 0: solid Vertical Border style 1: mesh 0: solid [3] [2:0] RO R/W Reserved HLDSPLB[10:8] 3.4.16 Right Display Border Configuration LSB Register 8Ah 00h Symbol HRDSPLB[7:0] Address Offset: Default Value: Bit [7:0] Access R/W Access: Size: Read/Write 8 bits Description When Output pixel’s index is greater than HRDSPLB, output pixel value is assigned as right display border with Frame color 3.4.17 Right Display Border Configuration MSB Register 8Bh 00h Symbol Reserved HRDSPLB[10:8] Address Offset: Default Value: Bit [7:3] [2:0] Access RO R/W Access: Size: Read/Write 8 bits Description 56 《液 晶 之 家》 www.fpdclub.net T108 Release 3.4.18 Top Display Border Configuration LSB Register 8Ch 00h Symbol VTDSPLB[7:0] Copyright by Terawins, Inc. Access: Size: Read/Write 8 bits Description Address Offset: Default Value: Bit [7:0] Access R/W 3.4.19 Top Display Border Configuration MSB Register 8Dh 00h Symbol HDSPLB_GRID[1:0] H grip precision, 00b: 1 pixel 01b: 4 pixels 10b: 16 pixels 11b: 32 pixels V grip precision 00b: 1 line 01b: 4 lines 10b: 16 lines 11b: 32 lines Address Offset: Default Value: Bit [7:6] Access R/W Access: Size: Read/Write 8 bits Description [5:4] R/W VDSPLB_GRID[1:0] [3:2] [1:0] RO R/W Reserved VTDSPLB[9:8] 3.4.20 Bottom Display Border Configuration LSB Register 8Eh 00h Symbol VBDSPLB[7:0] Address Offset: Default Value: Bit [7:0] Access R/W Access: Size: Read/Write 8 bits Description 3.4.21 Bottom Display Border Configuration MSB Register 8Fh 00h Symbol Reserved VBDSPLB[9:8] Address Offset: Default Value: Bit [7:2] [1:0] Access RO R/W Access: Size: Read/Write 8 bits Description 57 《液 晶 之 家》 www.fpdclub.net T108 Release Copyright by Terawins, Inc. 3.5 Gamma and Pattern Gen. Register Set 3.5.1 Image Function Control Register Address Offset: Default Value: Bit [7:6] Access R/W 90h 04h Symbol GATS[1:0] Access: Size: Read/Write 8 bits Description [5] [4:2] [1] [0] R/W R/W R/W R/W Gamma_BIST_En Reserved EN_GAMMA EN_DITHER Gamma Table Select. Default=2’b00. 00b: All R/G/B Gamma tables 01b: B Gamma table 10b: G Gamma table 11b: R Gamma table Enable Gamma RAM BIST. Enable Gamma. Enable Dithering: 0: Disable Dithering, output full 8 bit 1: 6 bits Dithering 3.5.2 Built-in Pattern Generator Control Register Address Offset: Default Value: Bit [7] Access R/W 91h 04h Symbol EFMCLR Access: Size: Read/Write 8 bits Description Enable Frame background color Turn on this bit may disable Scaler’s color and show userdefined color on LCD panel. See 0x9D, 0x9E and 0x9F for user-defined frame color. [6] R/W ESLDSW This bit may enable pattern generator shows 9 patterns sequentially. EFMCLR, ESLDSW Output 2'b0X Normal Color 2'b10 Still pattern 2'b11 Motion patterns Enable Vertical Bar Patterns 1: indicate 8-bit patterns 0:indicate 6-bit patterns [5] [4] [3:0] R/W R/W R/W EVBAR PLBIT PTN Show nth pattern on LCD panel when EFMCLR is enabled When Both EFMCLR and ESLDSW are enabled, pattern generator may show 0, 1 ,2 ...up to PTNth. 3.5.3 GAMMA RAM BIST Result Register Address Offset: Default Value: Bit [7] [6:4] [3:0] Access RO RO RO 92h X0h Symbol Gamma_BIST_Done Gamma_R/G/B_Fail Reserved Access: Size: Read/Write 8 bits Description When Gamma RAM BIST finish, this bit will be set to 1, then the other P0_92 bits are valid. When Gamma RAM (R/G/B RAMs) BIST result: 0=pass, 1=fail. 58 《液 晶 之 家》 www.fpdclub.net T108 Release 3.5.4 GAMMA Table Address Port Register Address Offset: Default Value: Bit [7:0] Access R/W Copyright by Terawins, Inc. 93h 00h Symbol GAMMA_ADR Access: Size: Read/Write 8 bits Description Gamma coefficient table address. The Index range is 00h~FFh 3.5.5 GAMMA Table Write Data Port Register Address Offset: Default Value: Bit [7:0] Access WO 94h 00h Symbol GAMMA_WR_D Access: Size: Write Only 8 bits Description Gamma coefficient write data port. 3.5.6 Pattern Bar Width Register Address Offset: Default Value: Bit [7:0] Access R/W 96h 3Ch Symbol Pattern_Bar_Width Access: Size: Read/Write 8 bits Description This is for generated pattern vertical bar width (for patterns: Color Bar or Gray ramp) 3.5.7 Pattern Color Gradient & Dithering Mode Register Address Offset: Default Value: Bit [7:4] [3:0] Access R/W R/W 9Ch 00h Symbol CLRGRDT[3:0] Reserved Access: Size: Read/Write 8 bits Description When EFMCLR are enabled, CLRGRDT may set color gradient at pattern 2, 3 ,4, 5 3.5.8 Frame Color Red Configuration Register Address Offset: Default Value: Bit [7:0] Access R/W 9Dh 00h Symbol FMCLRRED Access: Size: Read/Write 8 bits Description 8 bits of red color depth for frame color. 3.5.9 Frame Color Green Configuration Register Address Offset: Default Value: Bit [7:0] Access R/W 9Eh 00h Symbol FMCLRGRN Access: Size: Read/Write 8 bits Description 8 bits of green color depth for frame color. 3.5.10 Frame Color Blue Configuration Register 9Fh 00h Symbol FMCLRBLU Address Offset: Default Value: Bit [7:0] Access R/W Access: Size: Read/Write 8 bits Description 8 bits of blue color depth for frame color. 59 《液 晶 之 家》 www.fpdclub.net T108 Release Copyright by Terawins, Inc. 3.6 OSD1 Register Set (For detail OSD1 description, please refer to section 2.6 OSD.) 3.6.1 OSD1 Configuration Index Port Register Address Offset: Default Value: Bit [7:0] Access W A0h 00h Symbol OSD1_CFG_INDEX Access: Size: Write Only 8 bits Description OSD1 Configuration Address Port 3.6.2 OSD1 Configuration Data Port Register Address Offset: Default Value: Bit [7:0] Access R/W A1h 00h Symbol OSD1_CFG_DATA Access: Size: Read/Write 8 bits Description OSD1 Configuration Data Port 3.6.3 OSD1 RAM Address Port Register Address Offset: Default Value: Bit [7:0] [1] [0] Access WO RO RO A2h 00h Symbol OSD1_RAM_A OSD1_RAM_Ready OSD1_Cfg_Ready Access: Size: Write Only 8 bits Description OSD1 RAM Address Port, LSB first, then MSB OSD1 RAM is ready for next programming OSD1 configuration is ready for next programming 3.6.4 OSD1 RAM Data Port Register Address Offset: Default Value: Bit [7:0] Access R/W A3h 00h Symbol OSD1_RAM_D Access: Size: Read/Write 8 bits Description OSD1 RAM Data Port 3.6.5 OSD1 Pattern Fill Configuration Index Port Register Address Offset: Default Value: Bit [7:0] Access WO A8h 00h Symbol Access: Size: Write Only 8 bits Description OSD1PF_CFG_INDEX OSD1 Pattern Fill Configuration Address Port 3.6.6 OSD1 Pattern Fill Configuration Data Port Register Address Offset: Default Value: Bit [7:0] Access R/W A9h 00h Symbol Access: Size: Read/Write 8 bits Description OSD1PF_CFG_DATA OSD1 Pattern Fill Configuration Data Port 60 《液 晶 之 家》 www.fpdclub.net T108 Release Copyright by Terawins, Inc. 3.7 LCD Output Control Register Set 3.7.1 Display Window Horizontal Start Register Address Offset: Default Value: Bit [7:0] Access R/W B0h 20h Symbol DWHS_L[7:0] Access: Size: Read/Write 8 bits Description Horizontal back porch. 3.7.2 Display Window Vertical Start Register Address Offset: Default Value: Bit [7:0] Access R/W B2h 10h Symbol DWVS[7:0] Access: Size: Read/Write 8 bits Description Vertical back porch 3.7.3 Display Window Horizontal Width LSB Register Address Offset: Default Value: Bit [7:0] Access R/W B4h E0h Symbol DWHSZ[7:0] Access: Size: Read/Write 8 bits Description Horizontal Active. 3.7.4 Display Window Horizontal Width MSB Register Address Offset: Default Value: Bit [7:3] [2:0] Access RO R/W B5h 01h Symbol Reserved DWHSZ[10:8] Access: Size: Read/Write 8 bits Description Horizontal Active. 3.7.5 Display Window Vertical Width LSB Register Address Offset: Default Value: Bit [7:0] Access R/W B6h EAh Symbol DWVSZ[7:0] Access: Size: Vertical Active. Read/Write 8 bits Description 3.7.6 Display Window Vertical Width MSB Register Address Offset: Default Value: Bit [7:2] [1:0] Access RO R/W B7h 00h Symbol Reserved DWVSZ[9:8] Access: Size: Read/Write 8 bits Description 3.7.7 Display Panel Horizontal Total Dots per Scan Line LSB Register Address Offset: Default Value: Bit [7:0] Access R/W B8h 80h Symbol PH_TOT[7:0] Access: Size: Read/Write 8 bits Description Output horizontal total dots 61 《液 晶 之 家》 www.fpdclub.net T108 Release 3.7.8 Address Offset: Default Value: Bit [7:3] [2:0] Access RO R/W Copyright by Terawins, Inc. B9h 03h Symbol Reserved PH_TOT[10:8] Display Panel Horizontal Total Dots per Scan Line MSB Register Access: Size: Read/Write 8 bits Description 3.7.9 Display Panel Vertical Total Lines per Frame LSB Register Address Offset: Default Value: Bit [7:0] Access R/W BAh 58h Symbol PV_TOT[7:0] Access: Size: Read/Write 8 bits Description Output vertical total lines 3.7.10 Display Panel Vertical Total Lines per Frame MSB Register BBh 02h Symbol Reserved PV_TOT[9:8] Address Offset: Default Value: Bit [7:2] [1:0] Access RO R/W Access: Size: Read/Write 8 bits Description 3.7.11 Display Panel HSYNC Width Register BCh 10h Symbol PH_PW[7:0] Address Offset: Default Value: Bit [7:0] Access R/W Access: Size: Read/Write 8 bits Description 3.7.12 Display Panel VSYNC Width Register BEh 02h Symbol Reserved PV_PW[4:0] Address Offset: Default Value: Bit [7:5] [4:0] Access RO R/W Access: Size: Read/Write 8 bits Description 62 《液 晶 之 家》 www.fpdclub.net T108 Release 3.7.13 Panel Output Signal Control 1 Register C0h 01h Symbol Reserved Reserved En_sPanel Copyright by Terawins, Inc. Address Offset: Default Value: Bit [7] [6] [5] Access R/W RO R/W Access: Size: Read/Write 8 bits Description Enable Serial RGB (sPanel) output. 0: for Analog panel (DAC output with TCON) 1: for Serial RGB panel (sD[7:0] + DCLKO + HS/VS/HDE) Reverse RGB output. 0: No reverse 1: RGB reverse. PHSYNC Polarity. Default=0. 0: Active Low 1: Active High PVSYNC Polarity. Default=0. 0: Active Low 1: Active High PDE polarity. Default=1. 0: Active Low 1: Active High [4] [3] R/W R/W Reserved Data_Neg [2] R/W PHSync_Polarity [1] R/W PVSync_Polarity [0] R/W PHDE_Polarity 3.7.14 Panel Output Signal Control 3 Register C1h 10h Symbol Reserved DCLK_INV Address Offset: Default Value: Bit [7:4] [3] Access R/W R/W Access: Size: Read/Write 8 bits Description CLKO Polarity. Default=0. 0: Non-Invert, CLKO rising aligns to Data transition 1: Inverted, CLKO falling aligns to Data transition Half CPHn frequency when set to 1. [2:1] [0] RO R/W Reserved Half_CPHn 3.7.15 Panel VSYNC Frame Delay Control Register Address Offset: Default Value: Bit [7] [6:5] [4] Access RO R/W R/W C2h 00h Symbol Reserved Reserved PSYNC_STR Access: Size: Read/Write 8 bits Description For Frame lock, input VSync (if exist) will trigger output VSync 0: Allow input vsync to trigger output vsync 1: Block input vsync triggering on output vsync [3] [2] [1] [0] R/W RO R/W WO Reserved Reserved IGNORE_VSYNC Reserved Ignore the input VSYNC. This can be used for output free run when input VSYN is not available For Chip Test only 63 《液 晶 之 家》 www.fpdclub.net T108 Release 3.7.16 Serial RGB HSync Delay Register Address Offset: Default Value: Bit [7:0] Access R/W Copyright by Terawins, Inc. C5h 60h Symbol Access: Size: Read/Write 8 bits Description sPanel_HS_Delay[7:0] Delay output HSync for sPanel. (count in 3x panel clock) Value must >= 02h. This register is used to shift sPanel_HS, and align correct RGB color in sequence, for some sPanel do not have HDE input. 3.7.17 Output RGB Reordering Register Address Offset: Default Value: Bit [7] [6:4] [3] Access RO R/W R/W C7h 00h Symbol Reserved Reserved BIGENDIANE Access: Size: Read/Write 8 bits Description [2:0] R/W RGBSWAPE Reverse bit [7:0] of RGB: 0: Non-Inverted, Little Endian. 1: Inverted, Big Endian. RGB Channel Swapping 3.7.18 Output PLL Divider 1 Register C8h 15h Symbol Reserved PLLDIV_F PLL feedback divider. Address Offset: Default Value: Bit [7] [6:0] Access RO R/W Access: Size: Read/Write 8 bits Description 3.7.19 Output PLL Divider 2 Register C9h 02h Symbol Address Offset: Default Value: Bit [7] [6:5] [4:0] Access R/W R/W R/W Access: Size: Read/Write 8 bits Description SS_Clock_En Enable Spread Spectrum clock output SS_Clock_Deviation[1:0] Spread Spectrum clock deviation selection PLLDIV_I PLL Input Divider. 3.7.20 Output PLL Divider 3 Register CAh 03h Symbol PLLMX PLL MUX Function Select Address Offset: Default Value: Bit [7:6] Access R/W Access: Size: Read/Write 8 bits Description PLLMX 2'b00 2'b01 2'b10 2'b11 [5] R/W PLLPD Mode PLLCLK Keep High Bypass PLL Bypass PLL [4] R/W PLL_Div2 Display PLL power down Control: 0: Display PLL power on 1: Display PLL power down Display PLL analog divider, set 1 to half frequency output 64 《液 晶 之 家》 www.fpdclub.net T108 Release [3:2] R/W PLL_OUT_SEL Copyright by Terawins, Inc. PLL additional divider 0: no divider 1: divided by 2 2: divided by 4 3: divided by 8 PLL Output Divider. Default=1. output_freq = 27Mhz * (F + 2) / (I+2) / (2^(O+1) ) [1:0] R/W PLLDIV_O 3.7.21 LLCKn Clock Register Address Offset: Default Value: Bit [7:4] [3:0] Access R/W R/W CBh 10h Symbol LLCK1_Phase[3:0] LLCK_DivideN[3:0] Access: Size: Read/Write 8 bits Description CPH1 (LLCK1) phase, 1